From 5d06d1d2136fd1d7b53cdb42230274f36de97e3d Mon Sep 17 00:00:00 2001 From: Jonatan Antoni Date: Tue, 24 Oct 2023 16:13:45 +0200 Subject: [PATCH] Add LLVM LIT/FileCheck tests for Core files --- .devcontainer/ubuntu-22.04/Dockerfile | 37 + .devcontainer/ubuntu-22.04/devcontainer.json | 13 + .../ubuntu-22.04/vcpkg-configuration.json | 23 + .github/workflows/core.yml | 91 +++ .gitignore | 7 +- CMSIS/Core/Test/apsr.c | 11 + CMSIS/Core/Test/basepri.c | 43 + CMSIS/Core/Test/bkpt.c | 10 + CMSIS/Core/Test/build.py | 88 ++ CMSIS/Core/Test/clrex.c | 12 + CMSIS/Core/Test/clz.c | 14 + CMSIS/Core/Test/control.c | 39 + CMSIS/Core/Test/dmb.c | 11 + CMSIS/Core/Test/dsb.c | 11 + CMSIS/Core/Test/fault_irq.c | 18 + CMSIS/Core/Test/faultmask.c | 36 + CMSIS/Core/Test/fpscr.c | 20 + CMSIS/Core/Test/fpscr_nofp.c | 21 + CMSIS/Core/Test/ipsr.c | 12 + CMSIS/Core/Test/irq.c | 17 + CMSIS/Core/Test/isb.c | 11 + CMSIS/Core/Test/lda.c | 29 + CMSIS/Core/Test/ldaex.c | 29 + CMSIS/Core/Test/ldrex.c | 29 + CMSIS/Core/Test/ldrt.c | 30 + CMSIS/Core/Test/lit.cfg.py | 770 ++++++++++++++++++ CMSIS/Core/Test/msp.c | 36 + CMSIS/Core/Test/msplim.c | 36 + CMSIS/Core/Test/nop.c | 10 + CMSIS/Core/Test/noreturn.c | 15 + CMSIS/Core/Test/primask.c | 36 + CMSIS/Core/Test/psp.c | 36 + CMSIS/Core/Test/psplim.c | 36 + CMSIS/Core/Test/psplim_baseline.c | 39 + CMSIS/Core/Test/rbit.c | 14 + CMSIS/Core/Test/requirements.txt | 6 + CMSIS/Core/Test/rev.c | 13 + CMSIS/Core/Test/rev16.c | 13 + CMSIS/Core/Test/revsh.c | 13 + CMSIS/Core/Test/ror.c | 15 + CMSIS/Core/Test/rrx.c | 13 + CMSIS/Core/Test/sat.c | 26 + CMSIS/Core/Test/sev.c | 11 + CMSIS/Core/Test/simd.c | 530 ++++++++++++ CMSIS/Core/Test/sp_ns.c | 22 + CMSIS/Core/Test/stl.c | 29 + CMSIS/Core/Test/stlex.c | 29 + CMSIS/Core/Test/strex.c | 29 + CMSIS/Core/Test/strt.c | 29 + CMSIS/Core/Test/systick.c | 17 + CMSIS/Core/Test/vcpkg-configuration.json | 20 + CMSIS/Core/Test/wfi.c | 10 + CMSIS/Core/Test/xpsr.c | 12 + 53 files changed, 2526 insertions(+), 1 deletion(-) create mode 100644 .devcontainer/ubuntu-22.04/Dockerfile create mode 100644 .devcontainer/ubuntu-22.04/devcontainer.json create mode 100644 .devcontainer/ubuntu-22.04/vcpkg-configuration.json create mode 100644 .github/workflows/core.yml create mode 100644 CMSIS/Core/Test/apsr.c create mode 100644 CMSIS/Core/Test/basepri.c create mode 100644 CMSIS/Core/Test/bkpt.c create mode 100755 CMSIS/Core/Test/build.py create mode 100644 CMSIS/Core/Test/clrex.c create mode 100644 CMSIS/Core/Test/clz.c create mode 100644 CMSIS/Core/Test/control.c create mode 100644 CMSIS/Core/Test/dmb.c create mode 100644 CMSIS/Core/Test/dsb.c create mode 100644 CMSIS/Core/Test/fault_irq.c create mode 100644 CMSIS/Core/Test/faultmask.c create mode 100644 CMSIS/Core/Test/fpscr.c create mode 100644 CMSIS/Core/Test/fpscr_nofp.c create mode 100644 CMSIS/Core/Test/ipsr.c create mode 100644 CMSIS/Core/Test/irq.c create mode 100644 CMSIS/Core/Test/isb.c create mode 100644 CMSIS/Core/Test/lda.c create mode 100644 CMSIS/Core/Test/ldaex.c create mode 100644 CMSIS/Core/Test/ldrex.c create mode 100644 CMSIS/Core/Test/ldrt.c create mode 100644 CMSIS/Core/Test/lit.cfg.py create mode 100644 CMSIS/Core/Test/msp.c create mode 100644 CMSIS/Core/Test/msplim.c create mode 100644 CMSIS/Core/Test/nop.c create mode 100644 CMSIS/Core/Test/noreturn.c create mode 100644 CMSIS/Core/Test/primask.c create mode 100644 CMSIS/Core/Test/psp.c create mode 100644 CMSIS/Core/Test/psplim.c create mode 100644 CMSIS/Core/Test/psplim_baseline.c create mode 100644 CMSIS/Core/Test/rbit.c create mode 100644 CMSIS/Core/Test/requirements.txt create mode 100644 CMSIS/Core/Test/rev.c create mode 100644 CMSIS/Core/Test/rev16.c create mode 100644 CMSIS/Core/Test/revsh.c create mode 100644 CMSIS/Core/Test/ror.c create mode 100644 CMSIS/Core/Test/rrx.c create mode 100644 CMSIS/Core/Test/sat.c create mode 100644 CMSIS/Core/Test/sev.c create mode 100644 CMSIS/Core/Test/simd.c create mode 100644 CMSIS/Core/Test/sp_ns.c create mode 100644 CMSIS/Core/Test/stl.c create mode 100644 CMSIS/Core/Test/stlex.c create mode 100644 CMSIS/Core/Test/strex.c create mode 100644 CMSIS/Core/Test/strt.c create mode 100644 CMSIS/Core/Test/systick.c create mode 100644 CMSIS/Core/Test/vcpkg-configuration.json create mode 100644 CMSIS/Core/Test/wfi.c create mode 100644 CMSIS/Core/Test/xpsr.c diff --git a/.devcontainer/ubuntu-22.04/Dockerfile b/.devcontainer/ubuntu-22.04/Dockerfile new file mode 100644 index 000000000..4acac2cd7 --- /dev/null +++ b/.devcontainer/ubuntu-22.04/Dockerfile @@ -0,0 +1,37 @@ +FROM --platform=linux/amd64 ubuntu:22.04 + +SHELL ["/bin/bash", "-c"] + +ARG DEBIAN_FRONTEND=noninteractive + +RUN apt-get update && \ + apt-get -y install \ + build-essential \ + curl \ + gdb \ + less \ + python3 \ + python3-pip \ + python-is-python3 \ + git \ + libtinfo5 \ + llvm-15-tools \ + unzip && \ + ln -s /usr/bin/FileCheck-15 /usr/bin/FileCheck + +RUN pip install \ + lit \ + python-matrix-runner + +RUN bash -c "$(curl -fsSL https://raw.githubusercontent.com/ohmybash/oh-my-bash/master/tools/install.sh)" && \ + sed -i 's/OSH_THEME="font"/OSH_THEME="powerline"/' ~/.bashrc + +ADD vcpkg-configuration.json /root/ + +RUN pushd /root && \ + . <(curl https://aka.ms/vcpkg-init.sh -L) && \ + echo "\n# Initialize vcpkg\n. /root/.vcpkg/vcpkg-init" >> .bashrc && \ + vcpkg x-update-registry --all && \ + vcpkg activate + +CMD ["/bin/bash"] diff --git a/.devcontainer/ubuntu-22.04/devcontainer.json b/.devcontainer/ubuntu-22.04/devcontainer.json new file mode 100644 index 000000000..f437b911b --- /dev/null +++ b/.devcontainer/ubuntu-22.04/devcontainer.json @@ -0,0 +1,13 @@ +{ + "name": "Ubuntu-22.04", + "build": { "dockerfile": "Dockerfile" }, + + "customizations": { + "vscode": { + "extensions": [ + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack" + ] + } + } + } diff --git a/.devcontainer/ubuntu-22.04/vcpkg-configuration.json b/.devcontainer/ubuntu-22.04/vcpkg-configuration.json new file mode 100644 index 000000000..2c96be693 --- /dev/null +++ b/.devcontainer/ubuntu-22.04/vcpkg-configuration.json @@ -0,0 +1,23 @@ +{ + "registries": [ + { + "kind": "artifact", + "location": "https://aka.ms/vcpkg-ce-default", + "name": "microsoft" + }, + { + "kind": "artifact", + "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip", + "name": "arm" + } + ], + "requires": { + "microsoft:ninja": "^1.10.2", + "arm:compilers/arm/armclang":"^6.20.0", + "arm:compilers/arm/arm-none-eabi-gcc": "^12.2.1-0", + "arm:compilers/arm/llvm-embedded": "^17.0.1-0", + "arm:tools/open-cmsis-pack/cmsis-toolbox": "^2.1.0-0", + "arm:models/arm/avh": "^11.21.15" + } + } + \ No newline at end of file diff --git a/.github/workflows/core.yml b/.github/workflows/core.yml new file mode 100644 index 000000000..a8babd18a --- /dev/null +++ b/.github/workflows/core.yml @@ -0,0 +1,91 @@ +name: Core Checks +on: + workflow_dispatch: + pull_request: + push: + branches: [main] + +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + +jobs: + lit: + runs-on: ubuntu-latest + + env: + ARM_UBL_ACTIVATION_CODE: ${{ secrets.ARM_UBL_ACTIVATION_CODE }} + + steps: + - uses: actions/checkout@v3 + + - uses: actions/setup-python@v4 + with: + python-version: '3.10' + cache: 'pip' + + - name: Python requirements + run: | + pip install -r ./CMSIS/Core/Test/requirements.txt + + - name: Cache vcpkg + uses: actions/cache@v3 + with: + key: vcpkg-${{ runner.os }}-${{ runner.arch }}-${{ github.run_id }}-${{ matrix.compiler }} + restore-keys: | + vcpkg-${{ runner.os }}-${{ runner.arch }}- + path: /home/runner/.vcpkg + + - name: Install LLVM dependencies and tools + working-directory: /home/runner + run: | + sudo apt-get update + sudo apt-get install libtinfo5 llvm-15-tools + sudo ln -s /usr/bin/FileCheck-15 /usr/bin/FileCheck + + - name: Prepare vcpkg env + working-directory: ./CMSIS/Core/Test + run: | + . <(curl https://aka.ms/vcpkg-init.sh -L) + vcpkg x-update-registry --all + vcpkg activate + + - name: Activate Arm tool license + working-directory: ./CMSIS/Core/Test + run: | + . /home/runner/.vcpkg/vcpkg-init + vcpkg activate + if [[ -n "${{ env.ARM_UBL_ACTIVATION_CODE }}" ]]; then + armlm activate --code ${{ env.ARM_UBL_ACTIVATION_CODE }} + else + armlm activate --server https://mdk-preview.keil.arm.com --product KEMDK-COM0 + fi + + - uses: ammaraskar/gcc-problem-matcher@master + + - name: Run LIT + working-directory: ./CMSIS/Core/Test + run: | + . /home/runner/.vcpkg/vcpkg-init + vcpkg activate + + ./build.py lit + + - name: Deactivate Arm tool license + if: always() + working-directory: ./CMSIS/Core/Test + run: | + . /home/runner/.vcpkg/vcpkg-init + vcpkg activate + if [[ -n "${{ env.ARM_UBL_ACTIVATION_CODE }}" ]]; then + armlm deactivate --code ${{ env.ARM_UBL_ACTIVATION_CODE }} + else + armlm deactivate --product KEMDK-COM0 + fi + + - name: Publish Test Results + if: ${{ !cancelled() && env.ARM_UBL_ACTIVATION_CODE }} + uses: EnricoMi/publish-unit-test-result-action@v2 + with: + report_individual_runs: true + files: ./CMSIS/Core/Test/*.xunit diff --git a/.gitignore b/.gitignore index dd0fa26b3..6c60f34ad 100644 --- a/.gitignore +++ b/.gitignore @@ -2,6 +2,9 @@ **/__pycache__ CMSIS/Documentation/ CMSIS/DoxyGen/**/*.dxy +CMSIS/Core/Test/*.o +CMSIS/Core/Test/*.xunit +CMSIS/Core/Test/.lit_test_times.txt CMSIS/CoreValidation/Project/*.zip CMSIS/CoreValidation/Project/*.junit CMSIS/CoreValidation/Project/*.clangd @@ -9,6 +12,7 @@ CMSIS/CoreValidation/Project/Validation.*/ CMSIS/CoreValidation/Project/Bootloader.*/ CMSIS/CoreValidation/Project/build CMSIS/CoreValidation/Project/RTE/_**/* +*.cbuild-idx.yml *.uvguix.* *.uvmpw.uvgui.* *.zip @@ -16,4 +20,5 @@ CMSIS/CoreValidation/Project/RTE/_**/* build output linkchecker-out.csv -.DS_STORE \ No newline at end of file +.DS_STORE +*.tmp diff --git a/CMSIS/Core/Test/apsr.c b/CMSIS/Core/Test/apsr.c new file mode 100644 index 000000000..7c1683074 --- /dev/null +++ b/CMSIS/Core/Test/apsr.c @@ -0,0 +1,11 @@ +// REQUIRES: thumbv6m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_apsr() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, apsr + volatile uint32_t result = __get_APSR(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/basepri.c b/CMSIS/Core/Test/basepri.c new file mode 100644 index 000000000..174ceea7a --- /dev/null +++ b/CMSIS/Core/Test/basepri.c @@ -0,0 +1,43 @@ +// REQUIRES: thumb-2, thumbv7m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_basepri() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, basepri + volatile uint32_t result = __get_BASEPRI(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void get_basepri_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: mrs {{r[0-9]+}}, basepri_ns + volatile uint32_t result = __TZ_get_BASEPRI_NS(); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_basepri() { + // CHECK-LABEL: : + // CHECK: msr basepri, {{r[0-9]+}} + __set_BASEPRI(0x0815u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_basepri_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: msr basepri_ns, {{r[0-9]+}} + __TZ_set_BASEPRI_NS(0x0815u); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_basepri_max() { + // CHECK-LABEL: : + // CHECK: msr basepri_max, {{r[0-9]+}} + __set_BASEPRI_MAX(0x0815u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/bkpt.c b/CMSIS/Core/Test/bkpt.c new file mode 100644 index 000000000..a0682e110 --- /dev/null +++ b/CMSIS/Core/Test/bkpt.c @@ -0,0 +1,10 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void bkpt() { + // CHECK-LABEL: : + // CHECK: bkpt {{#0x15|#21}} + __BKPT(0x15); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/build.py b/CMSIS/Core/Test/build.py new file mode 100755 index 000000000..cac4aa1c5 --- /dev/null +++ b/CMSIS/Core/Test/build.py @@ -0,0 +1,88 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- + +import logging + +from datetime import datetime +from enum import Enum + +from matrix_runner import main, matrix_axis, matrix_action, matrix_command, matrix_filter, \ + FileReport, JUnitReport + + +@matrix_axis("device", "d", "Device(s) to be considered.") +class DeviceAxis(Enum): + CM0 = ('Cortex-M0', 'CM0') + CM0plus = ('Cortex-M0plus', 'CM0plus') + CM3 = ('Cortex-M3', 'CM3') + CM4 = ('Cortex-M4', 'CM4') + CM4FP = ('Cortex-M4FP', 'CM4FP') + CM7 = ('Cortex-M7', 'CM7') + CM7SP = ('Cortex-M7SP', 'CM7SP') + CM7DP = ('Cortex-M7DP', 'CM7DP') + CM23 = ('Cortex-M23', 'CM23') + CM23S = ('Cortex-M23S', 'CM23S') + CM23NS = ('Cortex-M23NS', 'CM23NS') + CM33 = ('Cortex-M33', 'CM33') + CM33S = ('Cortex-M33S', 'CM33S') + CM33NS = ('Cortex-M33NS', 'CM33NS') + CM35P = ('Cortex-M35P', 'CM35P') + CM35PS = ('Cortex-M35PS', 'CM35PS') + CM35PNS = ('Cortex-M35PNS', 'CM35PNS') + CM55 = ('Cortex-M55', 'CM55') + CM55S = ('Cortex-M55S', 'CM55S') + CM55NS = ('Cortex-M55NS', 'CM55NS') + CM85 = ('Cortex-M85', 'CM85') + CM85S = ('Cortex-M85S', 'CM85S') + CM85NS = ('Cortex-M85NS', 'CM85NS') + CA5 = ('Cortex-A5', 'CA5') + CA7 = ('Cortex-A7', 'CA7') + CA9 = ('Cortex-A9', 'CA9') + CA5NEON = ('Cortex-A5neon', 'CA5neon') + CA7NEON = ('Cortex-A7neon', 'CA7neon') + CA9NEON = ('Cortex-A9neon', 'CA9neon') + + +@matrix_axis("compiler", "c", "Compiler(s) to be considered.") +class CompilerAxis(Enum): + AC6 = ('AC6') + GCC = ('GCC') + IAR = ('IAR') + CLANG = ('Clang') + +@matrix_axis("optimize", "o", "Optimization level(s) to be considered.") +class OptimizationAxis(Enum): + NONE = ('none') + BALANCED = ('balanced') + SPEED = ('speed') + SIZE = ('size') + + +@matrix_action +def lit(config): + """Run tests for the selected configurations using llvm's lit.""" + yield run_lit(config.compiler[0], config.device[1], config.optimize[0]) + + +def timestamp(): + return datetime.now().strftime('%Y%m%d%H%M%S') + +@matrix_command() +def run_lit(toolchain, device, optimize): + return ["lit", "--xunit-xml-output", f"lit-{toolchain}-{optimize}-{device}.xunit", "-D", f"toolchain={toolchain}", "-D", f"device={device}", "-D", f"optimize={optimize}", "." ] + +@matrix_filter +def filter_iar(config): + return config.compiler == CompilerAxis.IAR + +@matrix_filter +def filter_gcc_cm85(config): + return config.compiler == CompilerAxis.GCC and config.device.match('CM85*') + +#@matrix_filter +#def filter_clang_cortex_a(config): +# return config.compiler == CompilerAxis.CLANG and config.device.match('CA*') + + +if __name__ == "__main__": + main() diff --git a/CMSIS/Core/Test/clrex.c b/CMSIS/Core/Test/clrex.c new file mode 100644 index 000000000..d46091025 --- /dev/null +++ b/CMSIS/Core/Test/clrex.c @@ -0,0 +1,12 @@ +// REQUIRES: ldrex +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void clrex() { + // CHECK-LABEL: : + // CHECK: clrex + __CLREX(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/clz.c b/CMSIS/Core/Test/clz.c new file mode 100644 index 000000000..698e5b8bd --- /dev/null +++ b/CMSIS/Core/Test/clz.c @@ -0,0 +1,14 @@ +// REQUIRES: clz +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint32_t a = 10u; + +void clz() { + // CHECK-LABEL: : + // CHECK: clz {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t c = __CLZ(a); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/control.c b/CMSIS/Core/Test/control.c new file mode 100644 index 000000000..c4cc6f925 --- /dev/null +++ b/CMSIS/Core/Test/control.c @@ -0,0 +1,39 @@ +// REQUIRES: thumbv6m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_control() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, control + volatile uint32_t result = __get_CONTROL(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void get_control_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: mrs {{r[0-9]+}}, control_ns + volatile uint32_t result = __TZ_get_CONTROL_NS(); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +volatile uint32_t v32 = 0x4711u; + +void set_control() { + // CHECK-LABEL: : + // CHECK: msr control, {{r[0-9]+}} + __set_CONTROL(v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_control_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: msr control_ns, {{r[0-9]+}} + __TZ_set_CONTROL_NS(v32); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/dmb.c b/CMSIS/Core/Test/dmb.c new file mode 100644 index 000000000..19167de9f --- /dev/null +++ b/CMSIS/Core/Test/dmb.c @@ -0,0 +1,11 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void dmb() { + // CHECK-LABEL: : + // CHECK: dmb sy + __DMB(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/dsb.c b/CMSIS/Core/Test/dsb.c new file mode 100644 index 000000000..df8ca7403 --- /dev/null +++ b/CMSIS/Core/Test/dsb.c @@ -0,0 +1,11 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void dsb() { + // CHECK-LABEL: : + // CHECK: dsb sy + __DSB(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/fault_irq.c b/CMSIS/Core/Test/fault_irq.c new file mode 100644 index 000000000..a0812d3bd --- /dev/null +++ b/CMSIS/Core/Test/fault_irq.c @@ -0,0 +1,18 @@ +// REQUIRES: thumb-2 +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void enable_fault_irq() { + // CHECK-LABEL: : + // CHECK: cpsie f + __enable_fault_irq(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void disable_fault_irq() { + // CHECK-LABEL: : + // CHECK: cpsid f + __disable_fault_irq(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/faultmask.c b/CMSIS/Core/Test/faultmask.c new file mode 100644 index 000000000..6c4523738 --- /dev/null +++ b/CMSIS/Core/Test/faultmask.c @@ -0,0 +1,36 @@ +// REQUIRES: thumb-2, thumbv7m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_faultmask() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, faultmask + volatile uint32_t result = __get_FAULTMASK(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void get_faultmask_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: mrs {{r[0-9]+}}, faultmask_ns + volatile uint32_t result = __TZ_get_FAULTMASK_NS(); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_faultmask() { + // CHECK-LABEL: : + // CHECK: msr faultmask, {{r[0-9]+}} + __set_FAULTMASK(0x0815u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_faultmask_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: msr faultmask_ns, {{r[0-9]+}} + __TZ_set_FAULTMASK_NS(0x0815u); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/fpscr.c b/CMSIS/Core/Test/fpscr.c new file mode 100644 index 000000000..5b262fa9c --- /dev/null +++ b/CMSIS/Core/Test/fpscr.c @@ -0,0 +1,20 @@ +// REQUIRES: fpu +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_fpscr() { + // CHECK-LABEL: : + // CHECK: vmrs {{r[0-9]+}}, fpscr + volatile uint32_t result = __get_FPSCR(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +volatile uint32_t v32 = 0x4711u; + +void set_fpscr() { + // CHECK-LABEL: : + // CHECK: vmsr fpscr, {{r[0-9]+}} + __set_FPSCR(v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/fpscr_nofp.c b/CMSIS/Core/Test/fpscr_nofp.c new file mode 100644 index 000000000..4ceb4cd1f --- /dev/null +++ b/CMSIS/Core/Test/fpscr_nofp.c @@ -0,0 +1,21 @@ +// UNSUPPORTED: fpu +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_fpscr() { + // CHECK-LABEL: : + // CHECK-NOT: vmrs {{r[0-9]+}}, fpscr + // CHECK: mov{{s?}} {{r[0-9]+}}, #0 + volatile uint32_t result = __get_FPSCR(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +volatile uint32_t v32 = 0x4711u; + +void set_fpscr() { + // CHECK-LABEL: : + // CHECK-NOT: vmsr fpscr, {{r[0-9]+}} + __set_FPSCR(v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/ipsr.c b/CMSIS/Core/Test/ipsr.c new file mode 100644 index 000000000..3e6d9da73 --- /dev/null +++ b/CMSIS/Core/Test/ipsr.c @@ -0,0 +1,12 @@ + +// REQUIRES: thumbv6m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_ipsr() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, ipsr + volatile uint32_t result = __get_IPSR(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/irq.c b/CMSIS/Core/Test/irq.c new file mode 100644 index 000000000..e5b79ef37 --- /dev/null +++ b/CMSIS/Core/Test/irq.c @@ -0,0 +1,17 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void enable_irq() { + // CHECK-LABEL: : + // CHECK: cpsie i + __enable_irq(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void disable_irq() { + // CHECK-LABEL: : + // CHECK: cpsid i + __disable_irq(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/isb.c b/CMSIS/Core/Test/isb.c new file mode 100644 index 000000000..ebae9d839 --- /dev/null +++ b/CMSIS/Core/Test/isb.c @@ -0,0 +1,11 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void isb() { + // CHECK-LABEL: : + // CHECK: isb sy + __ISB(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/lda.c b/CMSIS/Core/Test/lda.c new file mode 100644 index 000000000..0b83047ea --- /dev/null +++ b/CMSIS/Core/Test/lda.c @@ -0,0 +1,29 @@ +// REQUIRES: armv8m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint8_t v8 = 0x7u; +static volatile uint16_t v16 = 0x7u; +static volatile uint32_t v32 = 0x7u; + +void ldab() { + // CHECK-LABEL: : + // CHECK: ldab {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint8_t result = __LDAB(&v8); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void ldah() { + // CHECK-LABEL: : + // CHECK: ldah {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint16_t result = __LDAH(&v16); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void lda() { + // CHECK-LABEL: : + // CHECK: lda {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint32_t result = __LDA(&v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/ldaex.c b/CMSIS/Core/Test/ldaex.c new file mode 100644 index 000000000..77ab4345d --- /dev/null +++ b/CMSIS/Core/Test/ldaex.c @@ -0,0 +1,29 @@ +// REQUIRES: armv8m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint8_t v8 = 0x7u; +static volatile uint16_t v16 = 0x7u; +static volatile uint32_t v32 = 0x7u; + +void ldaexb() { + // CHECK-LABEL: : + // CHECK: ldaexb {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint8_t result = __LDAEXB(&v8); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void ldaexh() { + // CHECK-LABEL: : + // CHECK: ldaexh {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint16_t result = __LDAEXH(&v16); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void ldaex() { + // CHECK-LABEL: : + // CHECK: ldaex {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint32_t result = __LDAEX(&v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/ldrex.c b/CMSIS/Core/Test/ldrex.c new file mode 100644 index 000000000..52d203bea --- /dev/null +++ b/CMSIS/Core/Test/ldrex.c @@ -0,0 +1,29 @@ +// REQUIRES: ldrex +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint8_t v8 = 0x7u; +static volatile uint16_t v16 = 0x7u; +static volatile uint32_t v32 = 0x7u; + +void ldrexb() { + // CHECK-LABEL: : + // CHECK: ldrexb {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint8_t result = __LDREXB(&v8); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void ldrexh() { + // CHECK-LABEL: : + // CHECK: ldrexh {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint16_t result = __LDREXH(&v16); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void ldrexw() { + // CHECK-LABEL: : + // CHECK: ldrex {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint32_t result = __LDREXW(&v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/ldrt.c b/CMSIS/Core/Test/ldrt.c new file mode 100644 index 000000000..48dffaeb4 --- /dev/null +++ b/CMSIS/Core/Test/ldrt.c @@ -0,0 +1,30 @@ + +// REQUIRES: thumb-2 +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint8_t v8 = 0x7u; +static volatile uint16_t v16 = 0x7u; +static volatile uint32_t v32 = 0x7u; + +void ldrbt() { + // CHECK-LABEL: : + // CHECK: ldrbt {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint8_t result = __LDRBT(&v8); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void ldrht() { + // CHECK-LABEL: : + // CHECK: ldrht {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint16_t result = __LDRHT(&v16); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void ldrt() { + // CHECK-LABEL: : + // CHECK: ldrt {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint32_t result = __LDRT(&v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/lit.cfg.py b/CMSIS/Core/Test/lit.cfg.py new file mode 100644 index 000000000..19c16b257 --- /dev/null +++ b/CMSIS/Core/Test/lit.cfg.py @@ -0,0 +1,770 @@ +# -*- Python -*- + +import os + +import lit.formats +import lit.util + +DEVICES = { + 'CM0': { + 'arch': 'thumbv6m', + 'triple': 'thumbv6m', + 'abi': 'eabi', + 'mcpu': 'cortex-m0', + 'mfpu': 'none', + 'mpu': False, + 'features': ['thumbv6m'], + 'header': 'core_cm0.h', + 'defines': { + '__CM0_REV': '0x0000U', + '__NVIC_PRIO_BITS': '2U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM0plus': { + 'arch': 'thumbv6m', + 'triple': 'thumbv6m', + 'abi': 'eabi', + 'mcpu': 'cortex-m0plus', + 'mfpu': 'none', + 'mpu': True, + 'features': ['thumbv6m'], + 'header': 'core_cm0plus.h', + 'defines': { + '__CM0PLUS_REV': '0x0000U', + '__MPU_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '2U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM3': { + 'arch': 'thumbv7m', + 'triple': 'thumbv7-m', + 'abi': 'eabi', + 'mcpu': 'cortex-m3', + 'mfpu': 'none', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm3.h', + 'defines': { + '__CM3_REV': '0x0000U', + '__MPU_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM4': { + 'arch': 'thumbv7em', + 'triple': 'thumbv7-em', + 'abi': 'eabi', + 'mcpu': 'cortex-m4', + 'mfpu': 'none', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm4.h', + 'defines': { + '__CM4_REV': '0x0000U', + '__FPU_PRESENT': '0U', + '__MPU_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM4FP': { + 'arch': 'thumbv7em', + 'triple': 'thumbv7-em', + 'abi': 'eabihf', + 'mcpu': 'cortex-m4', + 'mfpu': 'fpv4-sp-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm4.h', + 'defines': { + '__CM4_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__MPU_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM7': { + 'arch': 'thumbv7em', + 'triple': 'thumbv7-em', + 'abi': 'eabi', + 'mcpu': 'cortex-m7', + 'mfpu': 'none', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm7.h', + 'defines': { + '__CM7_REV': '0x0000U', + '__FPU_PRESENT': '0U', + '__MPU_PRESENT': '1U', + '__ICACHE_PRESENT': '1U', + '__DCACHE_PRESENT': '1U', + '__DTCM_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM7SP': { + 'arch': 'thumbv7em', + 'triple': 'thumbv7-em', + 'abi': 'eabi', + 'mcpu': 'cortex-m7', + 'mfpu': 'fpv4-sp-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm7.h', + 'defines': { + '__CM7_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__MPU_PRESENT': '1U', + '__ICACHE_PRESENT': '1U', + '__DCACHE_PRESENT': '1U', + '__DTCM_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM7DP': { + 'arch': 'thumbv7em', + 'triple': 'thumbv7-em', + 'abi': 'eabihf', + 'mcpu': 'cortex-m7', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm7.h', + 'defines': { + '__CM7_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__MPU_PRESENT': '1U', + '__ICACHE_PRESENT': '1U', + '__DCACHE_PRESENT': '1U', + '__DTCM_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM23': { + 'arch': 'thumbv8m.base', + 'triple': 'thumbv8m', + 'abi': 'eabi', + 'mcpu': 'cortex-m23', + 'mfpu': 'none', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'thumbv8m.base', 'ldrex'], + 'header': 'core_cm23.h', + 'defines': { + '__CM23_REV': '0x0000U', + '__FPU_PRESENT': '0U', + '__MPU_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM23S': { + 'arch': 'thumbv8m.base', + 'triple': 'thumbv8m', + 'abi': 'eabi', + 'mcpu': 'cortex-m23', + 'mfpu': 'none', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'thumbv8m.base', 'ldrex'], + 'header': 'core_cm23.h', + 'defines': { + '__CM23_REV': '0x0000U', + '__FPU_PRESENT': '0U', + '__MPU_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM23NS': { + 'arch': 'thumbv8m.base', + 'triple': 'thumbv8m', + 'abi': 'eabi', + 'mcpu': 'cortex-m23', + 'mfpu': 'none', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'thumbv8m.base', 'ldrex'], + 'header': 'core_cm23.h', + 'defines': { + '__CM23_REV': '0x0000U', + '__FPU_PRESENT': '0U', + '__MPU_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM33': { + 'arch': 'thumbv8m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m33', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm33.h', + 'defines': { + '__CM33_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__MPU_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM33S': { + 'arch': 'thumbv8m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m33', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm33.h', + 'defines': { + '__CM33_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__MPU_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM33NS': { + 'arch': 'thumbv8m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m33', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm33.h', + 'defines': { + '__CM33_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__MPU_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM35P': { + 'arch': 'thumbv8m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m35p', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm35p.h', + 'defines': { + '__CM35P_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__MPU_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM35PS': { + 'arch': 'thumbv8m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m35p', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm35p.h', + 'defines': { + '__CM35P_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__MPU_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM35PNS': { + 'arch': 'thumbv8m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m35p', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm35p.h', + 'defines': { + '__CM35P_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__MPU_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__VTOR_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM55': { + 'arch': 'thumbv8.1m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m55', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm55.h', + 'defines': { + '__CM55_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__FPU_DP': '1U', + '__MPU_PRESENT': '1U', + '__ICACHE_PRESENT': '1U', + '__DCACHE_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__DSP_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__PMU_PRESENT': '1U', + '__PMU_NUM_EVENTCNT': '8U', + '__DSP_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM55S': { + 'arch': 'thumbv8.1m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m55', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm55.h', + 'defines': { + '__CM55_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__FPU_DP': '1U', + '__MPU_PRESENT': '1U', + '__ICACHE_PRESENT': '1U', + '__DCACHE_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__DSP_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__PMU_PRESENT': '1U', + '__PMU_NUM_EVENTCNT': '8U', + '__DSP_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM55NS': { + 'arch': 'thumbv8.1m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m55', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm55.h', + 'defines': { + '__CM55_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__FPU_DP': '1U', + '__MPU_PRESENT': '1U', + '__ICACHE_PRESENT': '1U', + '__DCACHE_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__DSP_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__PMU_PRESENT': '1U', + '__PMU_NUM_EVENTCNT': '8U', + '__DSP_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM85': { + 'arch': 'thumbv8.1m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m85', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm85.h', + 'defines': { + '__CM85_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__FPU_DP': '1U', + '__MPU_PRESENT': '1U', + '__ICACHE_PRESENT': '1U', + '__DCACHE_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__DSP_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__PMU_PRESENT': '1U', + '__PMU_NUM_EVENTCNT': '8U', + '__DSP_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM85S': { + 'arch': 'thumbv8.1m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m85', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm85.h', + 'defines': { + '__CM85_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__FPU_DP': '1U', + '__MPU_PRESENT': '1U', + '__ICACHE_PRESENT': '1U', + '__DCACHE_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__DSP_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__PMU_PRESENT': '1U', + '__PMU_NUM_EVENTCNT': '8U', + '__DSP_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CM85NS': { + 'arch': 'thumbv8.1m.main', + 'triple': 'thumbv8m', + 'abi': 'eabihf', + 'mcpu': 'cortex-m85', + 'mfpu': 'fpv5-d16', + 'mpu': True, + 'features': ['thumbv6m', 'thumbv7m', 'dsp', 'thumbv8m.base', 'thumbv8m.main', 'thumbv8.1m.main', 'thumb-2', 'sat', 'ldrex', 'clz'], + 'header': 'core_cm85.h', + 'defines': { + '__CM85_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__FPU_DP': '1U', + '__MPU_PRESENT': '1U', + '__ICACHE_PRESENT': '1U', + '__DCACHE_PRESENT': '1U', + '__SAUREGION_PRESENT': '8U', + '__DSP_PRESENT': '1U', + '__VTOR_PRESENT': '1U', + '__PMU_PRESENT': '1U', + '__PMU_NUM_EVENTCNT': '8U', + '__DSP_PRESENT': '1U', + '__NVIC_PRIO_BITS': '3U', + '__Vendor_SysTickConfig': '0U' + } + }, + 'CA5': { + 'arch': 'armv7a', + 'triple': 'armv7-a', + 'abi': 'eabi', + 'mcpu': 'cortex-a5', + 'mfpu': 'none', + 'mpu': True, + 'features': ['armv7a', 'thumb-2', 'sat', 'clz'], + 'header': 'core_ca.h', + 'defines': { + '__CA_REV': '0x0000U', + '__FPU_PRESENT': '0U', + '__GIC_PRESENT': '1U', + '__TIM_PRESENT': '1U', + '__L2C_PRESENT': '1U' + } + }, + 'CA5neon': { + 'arch': 'armv7a', + 'triple': 'armv7-a', + 'abi': 'eabihf', + 'mcpu': 'cortex-a5', + 'mfpu': 'neon-vfpv4', + 'mpu': True, + 'features': ['armv7a', 'thumb-2', 'sat', 'dsp', 'clz'], + 'header': 'core_ca.h', + 'defines': { + '__CA_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__GIC_PRESENT': '1U', + '__TIM_PRESENT': '1U', + '__L2C_PRESENT': '1U' + } + }, + 'CA7': { + 'arch': 'armv7a', + 'triple': 'armv7-a', + 'abi': 'eabi', + 'mcpu': 'cortex-a7', + 'mfpu': 'none', + 'mpu': True, + 'features': ['armv7a', 'thumb-2', 'sat', 'clz'], + 'header': 'core_ca.h', + 'defines': { + '__CA_REV': '0x0000U', + '__FPU_PRESENT': '0U', + '__GIC_PRESENT': '1U', + '__TIM_PRESENT': '1U', + '__L2C_PRESENT': '1U' + } + }, + 'CA7neon': { + 'arch': 'armv7a', + 'triple': 'armv7-a', + 'abi': 'eabihf', + 'mcpu': 'cortex-a7', + 'mfpu': 'neon-vfpv4', + 'mpu': True, + 'features': ['armv7a', 'thumb-2', 'sat', 'dsp', 'clz'], + 'header': 'core_ca.h', + 'defines': { + '__CA_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__GIC_PRESENT': '1U', + '__TIM_PRESENT': '1U', + '__L2C_PRESENT': '1U' + } + }, + 'CA9': { + 'arch': 'armv7a', + 'triple': 'armv7-a', + 'abi': 'eabi', + 'mcpu': 'cortex-a9', + 'mfpu': 'none', + 'mpu': True, + 'features': ['armv7a', 'thumb-2', 'sat', 'clz'], + 'header': 'core_ca.h', + 'defines': { + '__CA_REV': '0x0000U', + '__FPU_PRESENT': '0U', + '__GIC_PRESENT': '1U', + '__TIM_PRESENT': '1U', + '__L2C_PRESENT': '1U' + } + }, + 'CA9neon': { + 'arch': 'armv7a', + 'triple': 'armv7-a', + 'abi': 'eabihf', + 'mcpu': 'cortex-a9', + 'mfpu': 'neon-vfpv3', + 'mpu': True, + 'features': ['armv7a', 'thumb-2', 'sat', 'dsp', 'ldrex', 'clz'], + 'header': 'core_ca.h', + 'defines': { + '__CA_REV': '0x0000U', + '__FPU_PRESENT': '1U', + '__GIC_PRESENT': '1U', + '__TIM_PRESENT': '1U', + '__L2C_PRESENT': '1U' + } + } +} + +# Configuration file for the 'lit' test runner. + +# name: The name of this test suite. +config.name = "CMSIS-Core" + +# testFormat: The test format to use to interpret tests. +# +# For now we require '&&' between commands, until they get globally killed and +# the test runner updated. +config.test_format = lit.formats.ShTest() + +# suffixes: A list of file extensions to treat as test files. +config.suffixes = [ + ".c" +] + +# test_source_root: The root path where tests are located. +config.test_source_root = os.path.dirname(__file__) + + +# clang_path = get_toolchain_from_env('CLANG') + +toolchain = lit_config.params.get("toolchain", "AC6") +device = lit_config.params.get("device", "ARMCM3") +optimize = lit_config.params.get("optimize", "none") + +class Toolchain: + def __init__(self, toolchain, device, optimize): + self._toolchain = toolchain + self.device = device + self.optimize = optimize + + def get_root_from_env(self): + keys = sorted((k for k in os.environ.keys() if k.startswith(f'{self._toolchain}_TOOLCHAIN_')), reverse=True) + if not keys: + print(f"Toolchain '{self._toolchain}' not registered!") + return None + return os.environ.get(keys[0]) + + def get_root(self): + return self.get_root_from_env() + + +class Toolchain_AC6(Toolchain): + OPTIMIZE = { + 'none': '-O1', + 'balanced': '-O3', + 'speed': '-Os', + 'size': '-Oz' + } + + def __init__(self, **args): + super().__init__('AC6', **args) + + def get_cc(self): + return os.path.join(self.get_root(), 'armclang') + + def get_ccflags(self): + ccflags = [ + '--target=arm-arm-none-eabi', f'-mcpu={DEVICES[self.device]["mcpu"]}', f'-mfpu={DEVICES[self.device]["mfpu"]}', + self.OPTIMIZE[self.optimize], '-I', '../Include', '-c', '-D', f'CORE_HEADER=\\"{DEVICES[device]["header"]}\\"'] + if device.endswith('S') and not device.endswith('NS'): + ccflags += ["-mcmse"] + ccflags += list(sum([('-D', f'{define}={value}') for (define, value) in DEVICES[self.device]['defines'].items()], ())) + return ccflags + + +class Toolchain_GCC(Toolchain): + OPTIMIZE = { + 'none': '-O1', + 'balanced': '-O3', + 'speed': '-Os', + 'size': '-Oz' + } + + def __init__(self, **args): + super().__init__('GCC', **args) + + def get_cc(self): + return os.path.join(self.get_root(), 'arm-none-eabi-gcc') + + def get_ccflags(self): + floatabi='soft' + if DEVICES[self.device]["mfpu"] != 'none': + floatabi='hard' + ccflags = [ + f'-mcpu={DEVICES[self.device]["mcpu"]}', f'-mfloat-abi={floatabi}', + self.OPTIMIZE[self.optimize], '-I', '../Include', + '-D', f'CORE_HEADER=\\"{DEVICES[device]["header"]}\\"', '-c'] + if DEVICES[self.device]["mfpu"] != "none": + ccflags += [f'-mfpu={DEVICES[self.device]["mfpu"]}'] + if device.endswith('S') and not device.endswith('NS'): + ccflags += ["-mcmse"] + ccflags += list(sum([('-D', f'{define}={value}') for (define, value) in DEVICES[self.device]['defines'].items()], ())) + return ccflags + +class Toolchain_Clang(Toolchain): + TARGET = { + 'CM0': 'thumbv6m-none-unknown-eabi', + 'CM0plus': 'thumbv6m-none-unknown-eabi', + 'CM3': 'thumbv7m-none-unknown-eabi', + 'CM4': 'thumbv7em-none-unknown-eabi', + 'CM4FP': 'thumbv7em-none-unknown-eabihf', + 'CM7': 'thumbv7em-none-unknown-eabi', + 'CM7SP': 'thumbv7em-none-unknown-eabihf', + 'CM7DP': 'thumbv7em-none-unknown-eabihf', + 'CM23': 'thumbv8m.base-none-unknown-eabi', + 'CM23S': 'thumbv8m.base-none-unknown-eabi', + 'CM23NS': 'thumbv8m.base-none-unknown-eabi', + 'CM33': 'thumbv8m.main-none-unknown-eabihf', + 'CM33S': 'thumbv8m.main-none-unknown-eabihf', + 'CM33NS': 'thumbv8m.main-none-unknown-eabihf', + 'CM35P': 'thumbv8m.main-none-unknown-eabihf', + 'CM35PS': 'thumbv8m.main-none-unknown-eabihf', + 'CM35PNS': 'thumbv8m.main-none-unknown-eabihf', + 'CM55': 'thumbv8.1m.main-none-unknown-eabihf', + 'CM55S': 'thumbv8.1m.main-none-unknown-eabihf', + 'CM55NS': 'thumbv8.1m.main-none-unknown-eabihf', + 'CM85': 'thumbv8.1m.main-none-unknown-eabihf', + 'CM85S': 'thumbv8.1m.main-none-unknown-eabihf', + 'CM85NS': 'thumbv8.1m.main-none-unknown-eabihf', + 'CA5': 'armv7-none-unknown-eabi', + 'CA5neon': 'armv7-none-unknown-eabihf', + 'CA7': 'armv7-none-unknown-eabi', + 'CA7neon': 'armv7-none-unknown-eabihf', + 'CA9': 'armv7-none-unknown-eabi', + 'CA9neon': 'armv7-none-unknown-eabihf' + } + OPTIMIZE = { + 'none': '-O1', + 'balanced': '-O3', + 'speed': '-Os', + 'size': '-Oz' + } + def __init__(self, **args): + super().__init__('CLANG', **args) + + def get_cc(self): + return os.path.join(self.get_root(), 'clang') + + def get_ccflags(self): + ccflags = [ + f'--target={self.TARGET[self.device]}', self.OPTIMIZE[self.optimize], + f'-mcpu={DEVICES[self.device]["mcpu"]}', f'-mfpu={DEVICES[self.device]["mfpu"]}', + '-I', '../Include', '-c', '-D', f'CORE_HEADER=\\"{DEVICES[device]["header"]}\\"'] + if device.endswith('S') and not device.endswith('NS'): + ccflags += ["-mcmse"] + ccflags += list(sum([('-D', f'{define}={value}') for (define, value) in DEVICES[self.device]['defines'].items()], ())) + + return ccflags + +tc = None +if toolchain == 'AC6': + tc = Toolchain_AC6(device=device, optimize=optimize) +elif toolchain == 'GCC': + tc = Toolchain_GCC(device=device, optimize=optimize) +elif toolchain == 'Clang': + tc = Toolchain_Clang(device=device, optimize=optimize) + +prefixes = ['CHECK'] +if device.endswith('NS'): + prefixes += ['CHECK-NS'] +elif device.endswith('S'): + prefixes += ['CHECK-S'] +if DEVICES[device]['arch'].startswith('thumb'): + prefixes += ['CHECK-THUMB'] +elif DEVICES[device]['arch'].startswith('arm'): + prefixes += ['CHECK-ARM'] + +if DEVICES[device]["mfpu"] != 'none': + config.available_features.add('fpu') +for feature in DEVICES[device]['features']: + config.available_features.add(feature) + +objdump = os.path.join(Toolchain("CLANG", "none", "none").get_root(), 'llvm-objdump') +config.substitutions.append(("llvm-objdump", objdump)) + +config.substitutions.append(("%ccout%", "-o")) +config.substitutions.append(("%cc%", tc.get_cc())) +config.substitutions.append(("%ccflags%", ' '.join(tc.get_ccflags()))) +config.substitutions.append(("%prefixes%", ','.join(prefixes))) +config.substitutions.append(("%triple%", DEVICES[device]['triple'])) +config.substitutions.append(("%mcpu%", DEVICES[device]['mcpu'])) diff --git a/CMSIS/Core/Test/msp.c b/CMSIS/Core/Test/msp.c new file mode 100644 index 000000000..0be59ef4a --- /dev/null +++ b/CMSIS/Core/Test/msp.c @@ -0,0 +1,36 @@ +// REQUIRES: thumbv6m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_msp() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, msp + volatile uint32_t result = __get_MSP(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void get_msp_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: mrs {{r[0-9]+}}, msp_ns + volatile uint32_t result = __TZ_get_MSP_NS(); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_msp() { + // CHECK-LABEL: : + // CHECK: msr msp, {{r[0-9]+}} + __set_MSP(0x0815u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_msp_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: msr msp_ns, {{r[0-9]+}} + __TZ_set_MSP_NS(0x0815u); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/msplim.c b/CMSIS/Core/Test/msplim.c new file mode 100644 index 000000000..9d9678ef7 --- /dev/null +++ b/CMSIS/Core/Test/msplim.c @@ -0,0 +1,36 @@ +// REQUIRES: thumbv8m.main +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_msplim() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, msplim + volatile uint32_t result = __get_MSPLIM(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void get_msplim_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: mrs {{r[0-9]+}}, msplim_ns + volatile uint32_t result = __TZ_get_MSPLIM_NS(); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_msplim() { + // CHECK-LABEL: : + // CHECK: msr msplim, {{r[0-9]+}} + __set_MSPLIM(0x0815u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_msplim_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: msr msplim_ns, {{r[0-9]+}} + __TZ_set_MSPLIM_NS(0x0815u); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/nop.c b/CMSIS/Core/Test/nop.c new file mode 100644 index 000000000..33a30efc4 --- /dev/null +++ b/CMSIS/Core/Test/nop.c @@ -0,0 +1,10 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void nop() { + // CHECK-LABEL: : + // CHECK: {{(nop|mov r8, r8)}} + __NOP(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/noreturn.c b/CMSIS/Core/Test/noreturn.c new file mode 100644 index 000000000..c073eb861 --- /dev/null +++ b/CMSIS/Core/Test/noreturn.c @@ -0,0 +1,15 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +__NO_RETURN +static void func() { + while(1); +} + +void noreturn() { + // CHECK-LABEL: : + // CHECK: b 0x0 + func(); + // CHECK-NOT: bx lr +} diff --git a/CMSIS/Core/Test/primask.c b/CMSIS/Core/Test/primask.c new file mode 100644 index 000000000..bbad3256d --- /dev/null +++ b/CMSIS/Core/Test/primask.c @@ -0,0 +1,36 @@ +// REQUIRES: thumbv6m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_primask() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, primask + volatile uint32_t result = __get_PRIMASK(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void get_primask_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: mrs {{r[0-9]+}}, primask_ns + volatile uint32_t result = __TZ_get_PRIMASK_NS(); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_primask() { + // CHECK-LABEL: : + // CHECK: msr primask, {{r[0-9]+}} + __set_PRIMASK(0x0815u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_primask_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: msr primask_ns, {{r[0-9]+}} + __TZ_set_PRIMASK_NS(0x0815u); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/psp.c b/CMSIS/Core/Test/psp.c new file mode 100644 index 000000000..b6bf34214 --- /dev/null +++ b/CMSIS/Core/Test/psp.c @@ -0,0 +1,36 @@ +// REQUIRES: thumbv6m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_psp() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, psp + volatile uint32_t result = __get_PSP(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void get_psp_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: mrs {{r[0-9]+}}, psp_ns + volatile uint32_t result = __TZ_get_PSP_NS(); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_psp() { + // CHECK-LABEL: : + // CHECK: msr psp, {{r[0-9]+}} + __set_PSP(0x0815u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_psp_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: msr psp_ns, {{r[0-9]+}} + __TZ_set_PSP_NS(0x0815u); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/psplim.c b/CMSIS/Core/Test/psplim.c new file mode 100644 index 000000000..e1c2a7f99 --- /dev/null +++ b/CMSIS/Core/Test/psplim.c @@ -0,0 +1,36 @@ +// REQUIRES: thumbv8m.main +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_psplim() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, psplim + volatile uint32_t result = __get_PSPLIM(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void get_psplim_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: mrs {{r[0-9]+}}, psplim_ns + volatile uint32_t result = __TZ_get_PSPLIM_NS(); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_psplim() { + // CHECK-LABEL: : + // CHECK: msr psplim, {{r[0-9]+}} + __set_PSPLIM(0x0815u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_psplim_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: msr psplim_ns, {{r[0-9]+}} + __TZ_set_PSPLIM_NS(0x0815u); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/psplim_baseline.c b/CMSIS/Core/Test/psplim_baseline.c new file mode 100644 index 000000000..4da007c03 --- /dev/null +++ b/CMSIS/Core/Test/psplim_baseline.c @@ -0,0 +1,39 @@ +// REQUIRES: thumbv8m.base +// UNSUPPORTED: thumbv8m.main +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_psplim() { + // CHECK-LABEL: : + // CHECK-S: mrs {{r[0-9]+}}, psplim + // CHECK-NS-NOT: mrs {{r[0-9]+}}, psplim + volatile uint32_t result = __get_PSPLIM(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void get_psplim_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S-NOT: mrs {{r[0-9]+}}, psplim_ns + volatile uint32_t result = __TZ_get_PSPLIM_NS(); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_psplim() { + // CHECK-LABEL: : + // CHECK-S: msr psplim, {{r[0-9]+}} + // CHECK-NS-NOT: msr psplim, {{r[0-9]+}} + __set_PSPLIM(0x0815u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_psplim_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S-NOT: msr psplim_ns, {{r[0-9]+}} + __TZ_set_PSPLIM_NS(0x0815u); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/rbit.c b/CMSIS/Core/Test/rbit.c new file mode 100644 index 000000000..d0a1648e8 --- /dev/null +++ b/CMSIS/Core/Test/rbit.c @@ -0,0 +1,14 @@ +// REQUIRES: thumb-2 +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint32_t a = 10u; + +void rbit() { + // CHECK-LABEL: : + // CHECK: rbit {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t c = __RBIT(a); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/requirements.txt b/CMSIS/Core/Test/requirements.txt new file mode 100644 index 000000000..447c147b8 --- /dev/null +++ b/CMSIS/Core/Test/requirements.txt @@ -0,0 +1,6 @@ +# -*- coding: utf-8 -*- +# +# Python requirements for build.py script +# +python-matrix-runner~=1.0 +lit~=17.0 diff --git a/CMSIS/Core/Test/rev.c b/CMSIS/Core/Test/rev.c new file mode 100644 index 000000000..5515f3cda --- /dev/null +++ b/CMSIS/Core/Test/rev.c @@ -0,0 +1,13 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint32_t a = 10u; + +void rev() { + // CHECK-LABEL: : + // CHECK: rev {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t c = __REV(a); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/rev16.c b/CMSIS/Core/Test/rev16.c new file mode 100644 index 000000000..59d2b53ba --- /dev/null +++ b/CMSIS/Core/Test/rev16.c @@ -0,0 +1,13 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint32_t a = 10u; + +void rev16() { + // CHECK-LABEL: : + // CHECK: rev16 {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t c = __REV16(a); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/revsh.c b/CMSIS/Core/Test/revsh.c new file mode 100644 index 000000000..d4c8187ef --- /dev/null +++ b/CMSIS/Core/Test/revsh.c @@ -0,0 +1,13 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint32_t a = 10u; + +void revsh() { + // CHECK-LABEL: : + // CHECK: revsh {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t c = __REVSH(a); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/ror.c b/CMSIS/Core/Test/ror.c new file mode 100644 index 000000000..b16ddb6be --- /dev/null +++ b/CMSIS/Core/Test/ror.c @@ -0,0 +1,15 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint32_t a = 10u; +static volatile uint32_t b = 2u; + +void ror() { + // CHECK-LABEL: : + // CHECK-THUMB: ror{{s|.w}} {{r[0-9]+}}, {{r[0-9]+}} + // CHECK-ARM: ror {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t c = __ROR(a, b); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/rrx.c b/CMSIS/Core/Test/rrx.c new file mode 100644 index 000000000..fd4991b8c --- /dev/null +++ b/CMSIS/Core/Test/rrx.c @@ -0,0 +1,13 @@ +// REQUIRES: thumb-2 +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint32_t a = 10u; + +void rrx() { + // CHECK-LABEL: : + // CHECK: rrx {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t c = __RRX(a); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/sat.c b/CMSIS/Core/Test/sat.c new file mode 100644 index 000000000..be9f5226a --- /dev/null +++ b/CMSIS/Core/Test/sat.c @@ -0,0 +1,26 @@ +// REQUIRES: sat +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint32_t s32 = 10; +static volatile uint32_t u32 = 10U; + +void ssat() { + // CHECK-LABEL: : + // CHECK: ssat {{r[0-9]+}}, #0x2, {{r[0-9]+}} + volatile uint32_t c = __SSAT(s32, 2u); + // CHECK: ssat {{r[0-9]+}}, #0x5, {{r[0-9]+}} + volatile uint32_t d = __SSAT(s32, 5u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void usat() { + // CHECK-LABEL: : + // CHECK: usat {{r[0-9]+}}, #0x2, {{r[0-9]+}} + volatile uint32_t c = __USAT(u32, 2u); + // CHECK: usat {{r[0-9]+}}, #0x5, {{r[0-9]+}} + volatile uint32_t d = __USAT(u32, 5u); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/sev.c b/CMSIS/Core/Test/sev.c new file mode 100644 index 000000000..f77f48009 --- /dev/null +++ b/CMSIS/Core/Test/sev.c @@ -0,0 +1,11 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void sev() { + // CHECK-LABEL: : + // CHECK: sev + __SEV(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + diff --git a/CMSIS/Core/Test/simd.c b/CMSIS/Core/Test/simd.c new file mode 100644 index 000000000..17641aea5 --- /dev/null +++ b/CMSIS/Core/Test/simd.c @@ -0,0 +1,530 @@ +// REQUIRES: dsp +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +volatile static int32_t s32_1 = 0x47; +volatile static int32_t s32_2 = 0x11; +volatile static int32_t s32_3 = 0x15; +volatile static uint8_t u8 = 5u; + +/* ADD8 */ + +void sadd8() { + // CHECK-LABEL: : + // CHECK: sadd8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SADD8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void qadd8() { + // CHECK-LABEL: : + // CHECK: qadd8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __QADD8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void shadd8() { + // CHECK-LABEL: : + // CHECK: shadd8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SHADD8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uadd8() { + // CHECK-LABEL: : + // CHECK: uadd8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UADD8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uqadd8() { + // CHECK-LABEL: : + // CHECK: uqadd8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UQADD8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uhadd8() { + // CHECK-LABEL: : + // CHECK: uhadd8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UHADD8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +/* SUB8 */ + +void ssub8() { + // CHECK-LABEL: : + // CHECK: ssub8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SSUB8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void qsub8() { + // CHECK-LABEL: : + // CHECK: qsub8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __QSUB8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void shsub8() { + // CHECK-LABEL: : + // CHECK: shsub8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SHSUB8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void usub8() { + // CHECK-LABEL: : + // CHECK: usub8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __USUB8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uqsub8() { + // CHECK-LABEL: : + // CHECK: uqsub8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UQSUB8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uhsub8() { + // CHECK-LABEL: : + // CHECK: uhsub8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UHSUB8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +/* ADD16 */ + +void sadd16() { + // CHECK-LABEL: : + // CHECK: sadd16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SADD16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void qadd16() { + // CHECK-LABEL: : + // CHECK: qadd16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __QADD16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void shadd16() { + // CHECK-LABEL: : + // CHECK: shadd16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SHADD16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uadd16() { + // CHECK-LABEL: : + // CHECK: uadd16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UADD16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uqadd16() { + // CHECK-LABEL: : + // CHECK: uqadd16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UQADD16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uhadd16() { + // CHECK-LABEL: : + // CHECK: uhadd16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UHADD16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +/* SUB16 */ + +void ssub16() { + // CHECK-LABEL: : + // CHECK: ssub16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SSUB16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void qsub16() { + // CHECK-LABEL: : + // CHECK: qsub16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __QSUB16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void shsub16() { + // CHECK-LABEL: : + // CHECK: shsub16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SHSUB16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void usub16() { + // CHECK-LABEL: : + // CHECK: usub16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __USUB16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uqsub16() { + // CHECK-LABEL: : + // CHECK: uqsub16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UQSUB16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uhsub16() { + // CHECK-LABEL: : + // CHECK: uhsub16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UHSUB16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +/* ASX */ + +void sasx() { + // CHECK-LABEL: : + // CHECK: sasx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SASX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void qasx() { + // CHECK-LABEL: : + // CHECK: qasx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __QASX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void shasx() { + // CHECK-LABEL: : + // CHECK: shasx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SHASX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uasx() { + // CHECK-LABEL: : + // CHECK: uasx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UASX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uqasx() { + // CHECK-LABEL: : + // CHECK: uqasx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UQASX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uhasx() { + // CHECK-LABEL: : + // CHECK: uhasx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UHASX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +/* SAX */ + +void ssax() { + // CHECK-LABEL: : + // CHECK: ssax {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SSAX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void qsax() { + // CHECK-LABEL: : + // CHECK: qsax {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __QSAX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void shsax() { + // CHECK-LABEL: : + // CHECK: shsax {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SHSAX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void usax() { + // CHECK-LABEL: : + // CHECK: usax {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __USAX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uqsax() { + // CHECK-LABEL: : + // CHECK: uqsax {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UQSAX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uhsax() { + // CHECK-LABEL: : + // CHECK: uhsax {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UHSAX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +/* SAT */ + +void usad8() { + // CHECK-LABEL: : + // CHECK: usad8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __USAD8(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void usada8() { + // CHECK-LABEL: : + // CHECK: usada8 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __USADA8(s32_1, s32_2, s32_3); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void ssat16() { + // CHECK-LABEL: : + // CHECK: ssat16 {{r[0-9]+}}, #0x5, {{r[0-9]+}} + volatile uint32_t result = __SSAT16(s32_1, 0x05); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void usat16() { + // CHECK-LABEL: : + // CHECK: usat16 {{r[0-9]+}}, #0x5, {{r[0-9]+}} + volatile uint32_t result = __USAT16(s32_1, 0x05); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uxtb16() { + // CHECK-LABEL: : + // CHECK: uxtb16 {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UXTB16(s32_1); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void uxtab16() { + // CHECK-LABEL: : + // CHECK: uxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __UXTAB16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void sxtb16() { + // CHECK-LABEL: : + // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SXTB16(s32_1); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void sxtab16() { + // CHECK-LABEL: : + // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SXTAB16(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +/* MUL */ + +void smuad() { + // CHECK-LABEL: : + // CHECK: smuad {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMUAD(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smuadx() { + // CHECK-LABEL: : + // CHECK: smuadx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMUADX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smlad() { + // CHECK-LABEL: : + // CHECK: smlad {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMLAD(s32_1, s32_2, s32_3); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smladx() { + // CHECK-LABEL: : + // CHECK: smladx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMLADX(s32_1, s32_2, s32_3); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smlald() { + // CHECK-LABEL: : + // CHECK: smlald {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMLALD(s32_1, s32_2, s32_3); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smlaldx() { + // CHECK-LABEL: : + // CHECK: smlaldx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMLALDX(s32_1, s32_2, s32_3); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smusd() { + // CHECK-LABEL: : + // CHECK: smusd {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMUSD(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smusdx() { + // CHECK-LABEL: : + // CHECK: smusdx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMUSDX(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smlsd() { + // CHECK-LABEL: : + // CHECK: smlsd {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMLSD(s32_1, s32_2, s32_3); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smlsdx() { + // CHECK-LABEL: : + // CHECK: smlsdx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMLSDX(s32_1, s32_2, s32_3); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smlsld() { + // CHECK-LABEL: : + // CHECK: smlsld {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMLSLD(s32_1, s32_2, s32_3); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smlsldx() { + // CHECK-LABEL: : + // CHECK: smlsldx {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SMLSLDX(s32_1, s32_2, s32_3); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void sel() { + // CHECK-LABEL: : + // CHECK: sel {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __SEL(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void qadd() { + // CHECK-LABEL: : + // CHECK: qadd {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __QADD(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void qsub() { + // CHECK-LABEL: : + // CHECK: qsub {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile uint32_t result = __QSUB(s32_1, s32_2); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void pkhbt0() { + // CHECK-LABEL: : + // CHECK: {{pkhtb|pkhbt}} {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + // CHECK-NOT: , lsl + // CHECK-NOT: , asr + volatile uint32_t result = __PKHBT(s32_1, s32_2, 0); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void pkhbt() { + // CHECK-LABEL: : + // CHECK: pkhbt {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, lsl #11 + volatile uint32_t result = __PKHBT(s32_1, s32_2, 11); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void pkhtb0() { + // CHECK-LABEL: : + // CHECK: {{pkhtb|pkhbt}} {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + // CHECK-NOT: , lsl + // CHECK-NOT: , asr + volatile uint32_t result = __PKHTB(s32_1, s32_2, 0); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void pkhtb() { + // CHECK-LABEL: : + // CHECK: pkhtb {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, asr #11 + volatile uint32_t result = __PKHTB(s32_1, s32_2, 11); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void sxtb16_ror() { + // CHECK-LABEL: : + // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #8 + volatile uint32_t result = __SXTB16_RORn(s32_1, 8); + + // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #16 + result = __SXTB16_RORn(s32_1, 16); + + // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}}, ror #24 + result = __SXTB16_RORn(s32_1, 24); + + // CHECK-THUMB: ror.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}} + // CHECK-ARM: ror [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}} + // CHECK: sxtb16 {{r[0-9]+}}, [[REG]] + // CHECK-NOT: , ror + result = __SXTB16_RORn(s32_1, 5); + + // CHECK-THUMB: ror{{.w|ne|s}} {{r[0-9]+}}, {{r[0-9]+}} + // CHECK-ARM: ror{{(ne)?}} {{r[0-9]+}}, {{r[0-9]+}} + // CHECK: sxtb16 {{r[0-9]+}}, {{r[0-9]+}} + // CHECK-NOT: , ror + result = __SXTB16_RORn(s32_1, u8); + + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void sxtab16_ror() { + // CHECK-LABEL: : + + // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #8 + volatile uint32_t result = __SXTAB16_RORn(s32_1, s32_2, 8); + + // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #16 + result = __SXTAB16_RORn(s32_1, s32_2, 16); + + // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, ror #24 + result = __SXTAB16_RORn(s32_1, s32_2, 24); + + // CHECK-THUMB: ror.w [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}} + // CHECK-ARM: ror [[REG:r[0-9]+]], {{r[0-9]+}}, {{#5|#0x5}} + // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, [[REG]] + // CHECK-NOT: , ror + result = __SXTAB16_RORn(s32_1, s32_2, 5); + + // CHECK-THUMB: ror{{.w|ne|s}} {{r[0-9]+}}, {{r[0-9]+}} + // CHECK-ARM: ror{{(ne)?}} {{r[0-9]+}}, {{r[0-9]+}} + // CHECK: sxtab16 {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + // CHECK-NOT: , ror + result = __SXTAB16_RORn(s32_1, s32_2, u8); + + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void smmla() { + // CHECK-LABEL: : + // CHECK: smmla {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}}, {{r[0-9]+}} + volatile int32_t result = __SMMLA(s32_1, s32_2, s32_3); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/sp_ns.c b/CMSIS/Core/Test/sp_ns.c new file mode 100644 index 000000000..83e1a2c05 --- /dev/null +++ b/CMSIS/Core/Test/sp_ns.c @@ -0,0 +1,22 @@ +// REQUIRES: thumbv8m.base +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_sp_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: mrs {{r[0-9]+}}, sp_ns + volatile uint32_t result = __TZ_get_SP_NS(); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void set_sp_ns() { + // CHECK-LABEL: : +#if __ARM_FEATURE_CMSE == 3 + // CHECK-S: msr sp_ns, {{r[0-9]+}} + __TZ_set_SP_NS(0x0815u); +#endif + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/stl.c b/CMSIS/Core/Test/stl.c new file mode 100644 index 000000000..ab8386c22 --- /dev/null +++ b/CMSIS/Core/Test/stl.c @@ -0,0 +1,29 @@ +// REQUIRES: armv8m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint8_t v8; +static volatile uint16_t v16; +static volatile uint32_t v32; + +void stlb() { + // CHECK-LABEL: : + // CHECK: stlb {{r[0-9]+}}, [{{r[0-9]+}}] + __STLB(0x7u, &v8); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void stlh() { + // CHECK-LABEL: : + // CHECK: stlh {{r[0-9]+}}, [{{r[0-9]+}}] + __STLH(0x7u, &v16); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void stl() { + // CHECK-LABEL: : + // CHECK: stl {{r[0-9]+}}, [{{r[0-9]+}}] + __STL(0x7u, &v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/stlex.c b/CMSIS/Core/Test/stlex.c new file mode 100644 index 000000000..fc67ca124 --- /dev/null +++ b/CMSIS/Core/Test/stlex.c @@ -0,0 +1,29 @@ +// REQUIRES: armv8m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint8_t v8; +static volatile uint16_t v16; +static volatile uint32_t v32; + +void stlexb() { + // CHECK-LABEL: : + // CHECK: stlexb {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint32_t result = __STLEXB(0x7u, &v8); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void stlexh() { + // CHECK-LABEL: : + // CHECK: stlexh {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint32_t result = __STLEXH(0x7u, &v16); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void stlex() { + // CHECK-LABEL: : + // CHECK: stlex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint32_t result = __STLEX(0x7u, &v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/strex.c b/CMSIS/Core/Test/strex.c new file mode 100644 index 000000000..063090751 --- /dev/null +++ b/CMSIS/Core/Test/strex.c @@ -0,0 +1,29 @@ +// REQUIRES: ldrex +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint8_t v8; +static volatile uint16_t v16; +static volatile uint32_t v32; + +void strexb() { + // CHECK-LABEL: : + // CHECK: strexb {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint32_t result = __STREXB(0x7u, &v8); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void strexh() { + // CHECK-LABEL: : + // CHECK: strexh {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint32_t result = __STREXH(0x7u, &v16); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void strexw() { + // CHECK-LABEL: : + // CHECK: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}] + volatile uint32_t result = __STREXW(0x7u, &v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/strt.c b/CMSIS/Core/Test/strt.c new file mode 100644 index 000000000..3eda0ae3c --- /dev/null +++ b/CMSIS/Core/Test/strt.c @@ -0,0 +1,29 @@ +// REQUIRES: thumb-2 +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +static volatile uint8_t v8; +static volatile uint16_t v16; +static volatile uint32_t v32; + +void strbt() { + // CHECK-LABEL: : + // CHECK: strbt {{r[0-9]+}}, [{{r[0-9]+}}] + __STRBT(0x7u, &v8); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void strht() { + // CHECK-LABEL: : + // CHECK: strht {{r[0-9]+}}, [{{r[0-9]+}}] + __STRHT(0x7u, &v16); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} + +void strt() { + // CHECK-LABEL: : + // CHECK: strt {{r[0-9]+}}, [{{r[0-9]+}}] + __STRT(0x7u, &v32); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/systick.c b/CMSIS/Core/Test/systick.c new file mode 100644 index 000000000..4f262156f --- /dev/null +++ b/CMSIS/Core/Test/systick.c @@ -0,0 +1,17 @@ +// REQUIRES: unsupported +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include + +typedef uint32_t IRQn_Type; +uint32_t SysTick_IRQn; + +#include CORE_HEADER + +void systick_type_ctrl() { + // CHECK-LABEL: : + // CHECK: mov.w [[REG:r[0-9]+]], #0xe000e000 + // CHECK: ldr {{r[0-9]+}}, [[[REG]], #0x10] + uint32_t ctrl = SysTick->CTRL; + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/vcpkg-configuration.json b/CMSIS/Core/Test/vcpkg-configuration.json new file mode 100644 index 000000000..4baf75d45 --- /dev/null +++ b/CMSIS/Core/Test/vcpkg-configuration.json @@ -0,0 +1,20 @@ +{ + "registries": [ + { + "kind": "artifact", + "location": "https://aka.ms/vcpkg-ce-default", + "name": "microsoft" + }, + { + "kind": "artifact", + "location": "https://artifacts.keil.arm.com/vcpkg-ce-registry/registry.zip", + "name": "arm" + } + ], + "requires": { + "arm:compilers/arm/armclang":"^6.20.0", + "arm:compilers/arm/arm-none-eabi-gcc": "^12.2.1-0", + "arm:compilers/arm/llvm-embedded": "^17.0.1-0" + } + } + \ No newline at end of file diff --git a/CMSIS/Core/Test/wfi.c b/CMSIS/Core/Test/wfi.c new file mode 100644 index 000000000..aef8a5fba --- /dev/null +++ b/CMSIS/Core/Test/wfi.c @@ -0,0 +1,10 @@ +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void wfi() { + // CHECK-LABEL: : + // CHECK: wfi + __WFI(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +} diff --git a/CMSIS/Core/Test/xpsr.c b/CMSIS/Core/Test/xpsr.c new file mode 100644 index 000000000..18116ff22 --- /dev/null +++ b/CMSIS/Core/Test/xpsr.c @@ -0,0 +1,12 @@ + +// REQUIRES: thumbv6m +// RUN: %cc% %ccflags% %ccout% %s.o %s; llvm-objdump --mcpu=%mcpu% -d %s.o | FileCheck --allow-unused-prefixes --check-prefixes %prefixes% %s + +#include "cmsis_compiler.h" + +void get_xpsr() { + // CHECK-LABEL: : + // CHECK: mrs {{r[0-9]+}}, xpsr + volatile uint32_t result = __get_xPSR(); + // CHECK: {{(bx lr)|(pop {.*pc})}} +}