From e14c9007b9a99caec363b6c02d270445dd7ba4e3 Mon Sep 17 00:00:00 2001 From: Sudhir Sreedharan Date: Tue, 9 Jul 2024 19:39:14 +0530 Subject: [PATCH] CMSIS-Core(M): M55/M85 : add CPPWR SU10/11 defines FP & MVE requires the SU10 to be modified while transitioning to low power state. Signed-off-by: Sudhir Sreedharan --- CMSIS/Core/Include/core_cm55.h | 13 +++++++++++++ CMSIS/Core/Include/core_cm85.h | 13 +++++++++++++ 2 files changed, 26 insertions(+) diff --git a/CMSIS/Core/Include/core_cm55.h b/CMSIS/Core/Include/core_cm55.h index a7c9f743..06ac9d8c 100644 --- a/CMSIS/Core/Include/core_cm55.h +++ b/CMSIS/Core/Include/core_cm55.h @@ -1023,6 +1023,19 @@ typedef struct __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } ICB_Type; +/** \brief ICB Coprocessor Power Control Register Definitions */ +#define ICB_CPPWR_SUS11_Pos 23U /*!< CPPWR: SUS11 Position */ +#define ICB_CPPWR_SUS11_Msk (1UL << ICB_CPPWR_SUS11_Pos) /*!< CPPWR: SUS11 Mask */ + +#define ICB_CPPWR_SU11_Pos 22U /*!< CPPWR: SU11 Position */ +#define ICB_CPPWR_SU11_Msk (1UL << ICB_CPPWR_SU11_Pos) /*!< CPPWR: SU11 Mask */ + +#define ICB_CPPWR_SUS10_Pos 21U /*!< CPPWR: SUS10 Position */ +#define ICB_CPPWR_SUS10_Msk (1UL << ICB_CPPWR_SUS10_Pos) /*!< CPPWR: SUS10 Mask */ + +#define ICB_CPPWR_SU10_Pos 20U /*!< CPPWR: SU10 Position */ +#define ICB_CPPWR_SU10_Msk (1UL << ICB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */ + /** \brief ICB Auxiliary Control Register Definitions */ #define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ #define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ diff --git a/CMSIS/Core/Include/core_cm85.h b/CMSIS/Core/Include/core_cm85.h index 8a8b8954..8d587214 100644 --- a/CMSIS/Core/Include/core_cm85.h +++ b/CMSIS/Core/Include/core_cm85.h @@ -1044,6 +1044,19 @@ typedef struct __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ } ICB_Type; +/** \brief ICB Coprocessor Power Control Register Definitions */ +#define ICB_CPPWR_SUS11_Pos 23U /*!< CPPWR: SUS11 Position */ +#define ICB_CPPWR_SUS11_Msk (1UL << ICB_CPPWR_SUS11_Pos) /*!< CPPWR: SUS11 Mask */ + +#define ICB_CPPWR_SU11_Pos 22U /*!< CPPWR: SU11 Position */ +#define ICB_CPPWR_SU11_Msk (1UL << ICB_CPPWR_SU11_Pos) /*!< CPPWR: SU11 Mask */ + +#define ICB_CPPWR_SUS10_Pos 21U /*!< CPPWR: SUS10 Position */ +#define ICB_CPPWR_SUS10_Msk (1UL << ICB_CPPWR_SUS10_Pos) /*!< CPPWR: SUS10 Mask */ + +#define ICB_CPPWR_SU10_Pos 20U /*!< CPPWR: SU10 Position */ +#define ICB_CPPWR_SU10_Msk (1UL << ICB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */ + /** \brief ICB Auxiliary Control Register Definitions */ #define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ #define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */