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B_PE_01 Fail -- The values of PMCEID0_EL0, PMCR_EL0 are different on cores with different architectures in DynamIQ SoC #253
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The first rule in the BSA specification states that: "RB_PE_01 All PEs are architecturally symmetric except for the permitted exceptions listed in Section A." Section A has table 18, which shows the permitted differences for systems composed of heterogeneous PEs, such as big.LITTLE. These variations are not expected to be perceived as architectural differences by a general purpose OS. PMCEID0_E0 and PMCR_EL0 are not in that list, which explains the failure. |
Thanks for the reply.
I'm just curious if this heterogeneous PEs like cortex-a720+cortex-x4 are not BSA compliant? |
@magicse7en |
The main difference is that the PMCR_EL0 bit[15:11] (indicate the number of event counters implemented), the number of event counters of cortex-a720 and cortex-x4 are diffferent. |
Thanks, @magicse7en According to the TRMs for a720 and x5 (the links below), PMCR_EL0 bit[15:11] are reserved and the reset values for both a720 and x5 PMCR_EL0 bit[15:10] are the same (all 0s). Could you confirm that the difference is in [15:11]? It looks like the difference could only occur in bits [9][7][5]. |
Hi @sunnywang-arm,
The A720 PMCR_EL0 value: 0xA0E0 |
Yes, you're right. Thanks for pointing that out, @magicse7en. We'll also check this. |
On RK3588 (A76 + A55) registers also differ on PE 4-7:
PE 0-3 are A55, 4-7 are A76 |
Since the SoC is DynamIQ architecture(e.g., cortex-a720 + cortex-x4), the values of PMCEID0_E0 and PMCR_EL0 differ between cortex-a720 and cortex-x4, causing the B_PE_01 test to fail.
Reg compare failed for PE index=4 for Register: PMCEID0_EL0
Current PE value = 0xF0F1A7F7BFF7F3F Other PE value = 0xF0F1A7F7FFF6F3F
Failed on PE - 4
B_PE_01
Checkpoint -- 1 : Result: FAIL
END
Any ideas?
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