From d5598241dd095edf7a5ec228bf83d2d97f822eb3 Mon Sep 17 00:00:00 2001 From: Douglas Wilson Date: Sat, 11 Jan 2025 15:56:17 +0000 Subject: [PATCH] better sum --- hugr-llvm/Cargo.toml | 1 + hugr-llvm/src/custom/types.rs | 9 +- hugr-llvm/src/emit/ops.rs | 4 +- ...ps__cfg__test__diverse_outputs@llvm14.snap | 51 +- ...t__diverse_outputs@pre-mem2reg@llvm14.snap | 69 +- ...__emit__ops__cfg__test__nested@llvm14.snap | 98 ++- ..._cfg__test__nested@pre-mem2reg@llvm14.snap | 264 ++++--- ...test_fns__diverse_cfg_children@llvm14.snap | 21 +- ...verse_cfg_children@pre-mem2reg@llvm14.snap | 71 +- ...test_fns__diverse_dfg_children@llvm14.snap | 14 +- ...verse_dfg_children@pre-mem2reg@llvm14.snap | 44 +- ...test__test_fns__emit_hugr_call@llvm14.snap | 24 +- ...ns__emit_hugr_call@pre-mem2reg@llvm14.snap | 78 +- ...t_fns__emit_hugr_call_indirect@llvm14.snap | 24 +- ...hugr_call_indirect@pre-mem2reg@llvm14.snap | 90 +-- ...est_fns__emit_hugr_conditional@llvm14.snap | 46 +- ...t_hugr_conditional@pre-mem2reg@llvm14.snap | 180 +++-- ..._test__test_fns__emit_hugr_dfg@llvm14.snap | 8 +- ...fns__emit_hugr_dfg@pre-mem2reg@llvm14.snap | 32 +- ...t_fns__emit_hugr_load_constant@llvm14.snap | 8 +- ...hugr_load_constant@pre-mem2reg@llvm14.snap | 20 +- ..._test__test_fns__emit_hugr_tag@llvm14.snap | 8 +- ...fns__emit_hugr_tag@pre-mem2reg@llvm14.snap | 20 +- ...mit__test__test_fns__tail_loop@llvm14.snap | 46 +- ...est_fns__tail_loop@pre-mem2reg@llvm14.snap | 80 +-- ...st__test_fns__tail_loop_simple@llvm14.snap | 28 +- ...__tail_loop_simple@pre-mem2reg@llvm14.snap | 50 +- hugr-llvm/src/emit/test.rs | 2 +- hugr-llvm/src/extension/collections/array.rs | 34 +- hugr-llvm/src/extension/collections/list.rs | 2 +- ...ons__array__test__emit_all_ops@llvm14.snap | 310 ++++---- ...test__emit_all_ops@pre-mem2reg@llvm14.snap | 365 +++++----- ...ections__array__test__emit_get@llvm14.snap | 11 +- ...ay__test__emit_get@pre-mem2reg@llvm14.snap | 21 +- ...__collections__list__test__get@llvm14.snap | 9 +- ...s__list__test__get@pre-mem2reg@llvm14.snap | 21 +- ...ollections__list__test__insert@llvm14.snap | 13 +- ...list__test__insert@pre-mem2reg@llvm14.snap | 25 +- ...__collections__list__test__pop@llvm14.snap | 13 +- ...s__list__test__pop@pre-mem2reg@llvm14.snap | 25 +- ...__collections__list__test__set@llvm14.snap | 16 +- ...s__list__test__set@pre-mem2reg@llvm14.snap | 28 +- hugr-llvm/src/extension/conversions.rs | 2 +- hugr-llvm/src/extension/prelude.rs | 2 +- ...__conversions__test__ifrombool@llvm14.snap | 9 +- ...s__test__ifrombool@pre-mem2reg@llvm14.snap | 15 +- ...on__conversions__test__itobool@llvm14.snap | 6 +- ...ons__test__itobool@pre-mem2reg@llvm14.snap | 18 +- ...on__conversions__test__trunc_s@llvm14.snap | 9 +- ...ons__test__trunc_s@pre-mem2reg@llvm14.snap | 21 +- ...on__conversions__test__trunc_u@llvm14.snap | 9 +- ...ons__test__trunc_u@pre-mem2reg@llvm14.snap | 21 +- ...m__extension__float__test__feq@llvm14.snap | 8 +- ...__float__test__feq@pre-mem2reg@llvm14.snap | 20 +- ...m__extension__float__test__fge@llvm14.snap | 8 +- ...__float__test__fge@pre-mem2reg@llvm14.snap | 20 +- ...m__extension__float__test__fgt@llvm14.snap | 8 +- ...__float__test__fgt@pre-mem2reg@llvm14.snap | 20 +- ...m__extension__float__test__fle@llvm14.snap | 8 +- ...__float__test__fle@pre-mem2reg@llvm14.snap | 20 +- ...m__extension__float__test__flt@llvm14.snap | 8 +- ...__float__test__flt@pre-mem2reg@llvm14.snap | 20 +- ...m__extension__float__test__fne@llvm14.snap | 8 +- ...__float__test__fne@pre-mem2reg@llvm14.snap | 20 +- ...lvm__extension__int__test__ieq@llvm14.snap | 8 +- ...on__int__test__ieq@pre-mem2reg@llvm14.snap | 20 +- ...m__extension__int__test__ilt_s@llvm14.snap | 8 +- ...__int__test__ilt_s@pre-mem2reg@llvm14.snap | 20 +- ...m__extension__logic__test__and@llvm14.snap | 13 +- ...__logic__test__and@pre-mem2reg@llvm14.snap | 37 +- ...vm__extension__logic__test__eq@llvm14.snap | 12 +- ...n__logic__test__eq@pre-mem2reg@llvm14.snap | 36 +- ...m__extension__logic__test__not@llvm14.snap | 10 +- ...__logic__test__not@pre-mem2reg@llvm14.snap | 28 +- ...vm__extension__logic__test__or@llvm14.snap | 13 +- ...n__logic__test__or@pre-mem2reg@llvm14.snap | 37 +- ..._prelude_const_external_symbol@llvm14.snap | 14 +- ...st_external_symbol@pre-mem2reg@llvm14.snap | 26 +- ...lude__test__prelude_make_tuple@llvm14.snap | 11 +- ...prelude_make_tuple@pre-mem2reg@llvm14.snap | 35 +- ...de__test__prelude_unpack_tuple@llvm14.snap | 15 +- ...elude_unpack_tuple@pre-mem2reg@llvm14.snap | 45 +- ...pes__test__func_type_to_llvm@llvm14_0.snap | 6 +- ...pes__test__func_type_to_llvm@llvm14_1.snap | 6 +- ...pes__test__func_type_to_llvm@llvm14_2.snap | 6 +- ...ypes__test__sum_type_to_llvm@llvm14_1.snap | 6 +- ...ypes__test__sum_type_to_llvm@llvm14_2.snap | 6 +- ...ypes__test__sum_type_to_llvm@llvm14_3.snap | 6 +- ...m__types__test__type_to_llvm@llvm14_5.snap | 6 +- ...m__types__test__type_to_llvm@llvm14_6.snap | 6 +- ...m__types__test__type_to_llvm@llvm14_7.snap | 6 +- hugr-llvm/src/sum.rs | 680 ++++++++++++++---- hugr-llvm/src/sum/layout.rs | 216 ++++++ hugr-llvm/src/types.rs | 4 +- 94 files changed, 2190 insertions(+), 1715 deletions(-) create mode 100644 hugr-llvm/src/sum/layout.rs diff --git a/hugr-llvm/Cargo.toml b/hugr-llvm/Cargo.toml index a161aed3a..3628ee241 100644 --- a/hugr-llvm/Cargo.toml +++ b/hugr-llvm/Cargo.toml @@ -47,6 +47,7 @@ pathsearch = { workspace = true, optional = true } serde_json = { workspace = true, optional = true } serde = { workspace = true, optional = true } typetag = { workspace = true, optional = true } +derive_more = { workspace = true, features = ["debug"] } [dev-dependencies] hugr-llvm = { "path" = ".", features = ["test-utils"] } diff --git a/hugr-llvm/src/custom/types.rs b/hugr-llvm/src/custom/types.rs index ee77b8cc5..392684330 100644 --- a/hugr-llvm/src/custom/types.rs +++ b/hugr-llvm/src/custom/types.rs @@ -49,15 +49,14 @@ impl<'a> TypeMapping for LLVMTypeMapping<'a> { fn map_sum_type<'c>( &self, - sum_type: &HugrSumType, + _sum_type: &HugrSumType, context: TypingSession<'c, 'a>, variants: impl IntoIterator>>, ) -> Result> { - LLVMSumType::try_new2( + Ok(LLVMSumType::new( context.iw_context(), - variants.into_iter().collect(), - sum_type.clone(), - ) + variants.into_iter().collect_vec(), + )) } fn map_function_type<'c>( diff --git a/hugr-llvm/src/emit/ops.rs b/hugr-llvm/src/emit/ops.rs index dad6b1094..aebed16f6 100644 --- a/hugr-llvm/src/emit/ops.rs +++ b/hugr-llvm/src/emit/ops.rs @@ -135,7 +135,7 @@ pub fn emit_value<'c, H: HugrView>( .iter() .map(|x| emit_value(context, x)) .collect::>>()?; - llvm_st.build_tag(context.builder(), *tag, vs) + Ok(llvm_st.build_tag(context.builder(), *tag, vs)?.into()) } } } @@ -160,7 +160,7 @@ fn emit_tag<'c, H: HugrView>( let builder = context.builder(); args.outputs.finish( builder, - [st.build_tag(builder, args.node.tag, args.inputs)?], + [st.build_tag(builder, args.node.tag, args.inputs)?.into()], ) } diff --git a/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@llvm14.snap b/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@llvm14.snap index 3e74fd960..9ab7670b9 100644 --- a/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@llvm14.snap +++ b/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@llvm14.snap @@ -1,6 +1,6 @@ --- -source: src/emit/ops/cfg.rs -expression: module.to_string() +source: hugr-llvm/src/emit/ops/cfg.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" @@ -12,38 +12,33 @@ alloca_block: entry_block: ; preds = %alloca_block br label %2 -2: ; preds = %14, %entry_block - %"7_0.0" = phi i8 [ %0, %entry_block ], [ %16, %14 ] - %"7_1.0" = phi i8 [ %1, %entry_block ], [ %9, %14 ] - %3 = insertvalue { i8, i8 } undef, i8 %"7_0.0", 0 +2: ; preds = %11, %entry_block + %"7_0.0" = phi i8 [ %0, %entry_block ], [ %12, %11 ] + %"7_1.0" = phi i8 [ %1, %entry_block ], [ %7, %11 ] + %3 = insertvalue { i8, i8 } poison, i8 %"7_0.0", 0 %4 = insertvalue { i8, i8 } %3, i8 %"7_1.0", 1 - %5 = insertvalue { { i8, i8 } } poison, { i8, i8 } %4, 0 - switch i32 0, label %6 [ + switch i1 false, label %5 [ ] -6: ; preds = %2 - %7 = extractvalue { { i8, i8 } } %5, 0 - %8 = extractvalue { i8, i8 } %7, 0 - %9 = extractvalue { i8, i8 } %7, 1 - br label %10 - -10: ; preds = %6 - %11 = insertvalue { i8 } undef, i8 %8, 0 - %12 = insertvalue { i32, { i8 }, {} } { i32 0, { i8 } poison, {} poison }, { i8 } %11, 1 - %13 = extractvalue { i32, { i8 }, {} } %12, 0 - switch i32 %13, label %14 [ - i32 1, label %17 +5: ; preds = %2 + %6 = extractvalue { i8, i8 } %4, 0 + %7 = extractvalue { i8, i8 } %4, 1 + br label %8 + +8: ; preds = %5 + %9 = insertvalue { i1, i8 } { i1 false, i8 poison }, i8 %6, 1 + %10 = extractvalue { i1, i8 } %9, 0 + switch i1 %10, label %11 [ + i1 true, label %13 ] -14: ; preds = %10 - %15 = extractvalue { i32, { i8 }, {} } %12, 1 - %16 = extractvalue { i8 } %15, 0 +11: ; preds = %8 + %12 = extractvalue { i1, i8 } %9, 1 br label %2 -17: ; preds = %10 - %18 = extractvalue { i32, { i8 }, {} } %12, 2 - br label %19 +13: ; preds = %8 + br label %14 -19: ; preds = %17 - ret i8 %9 +14: ; preds = %13 + ret i8 %7 } diff --git a/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@pre-mem2reg@llvm14.snap index a17ad4f85..b0b14601d 100644 --- a/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@pre-mem2reg@llvm14.snap @@ -1,6 +1,6 @@ --- -source: src/emit/ops/cfg.rs -expression: module.to_string() +source: hugr-llvm/src/emit/ops/cfg.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" @@ -16,8 +16,8 @@ alloca_block: %"03" = alloca i8, align 1 %"11_0" = alloca i8, align 1 %"11_1" = alloca i8, align 1 - %"9_0" = alloca { { i8, i8 } }, align 8 - %"13_0" = alloca { i32, { i8 }, {} }, align 8 + %"9_0" = alloca { i8, i8 }, align 8 + %"13_0" = alloca { i1, i8 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block @@ -29,64 +29,59 @@ entry_block: ; preds = %alloca_block store i8 %"2_12", i8* %"7_1", align 1 br label %2 -2: ; preds = %14, %entry_block +2: ; preds = %11, %entry_block %"7_04" = load i8, i8* %"7_0", align 1 %"7_15" = load i8, i8* %"7_1", align 1 store i8 %"7_04", i8* %"7_0", align 1 store i8 %"7_15", i8* %"7_1", align 1 %"7_06" = load i8, i8* %"7_0", align 1 %"7_17" = load i8, i8* %"7_1", align 1 - %3 = insertvalue { i8, i8 } undef, i8 %"7_06", 0 + %3 = insertvalue { i8, i8 } poison, i8 %"7_06", 0 %4 = insertvalue { i8, i8 } %3, i8 %"7_17", 1 - %5 = insertvalue { { i8, i8 } } poison, { i8, i8 } %4, 0 - store { { i8, i8 } } %5, { { i8, i8 } }* %"9_0", align 1 - %"9_08" = load { { i8, i8 } }, { { i8, i8 } }* %"9_0", align 1 - store { { i8, i8 } } %"9_08", { { i8, i8 } }* %"9_0", align 1 - %"9_09" = load { { i8, i8 } }, { { i8, i8 } }* %"9_0", align 1 - switch i32 0, label %6 [ + store { i8, i8 } %4, { i8, i8 }* %"9_0", align 1 + %"9_08" = load { i8, i8 }, { i8, i8 }* %"9_0", align 1 + store { i8, i8 } %"9_08", { i8, i8 }* %"9_0", align 1 + %"9_09" = load { i8, i8 }, { i8, i8 }* %"9_0", align 1 + switch i1 false, label %5 [ ] -6: ; preds = %2 - %7 = extractvalue { { i8, i8 } } %"9_09", 0 - %8 = extractvalue { i8, i8 } %7, 0 - %9 = extractvalue { i8, i8 } %7, 1 - store i8 %8, i8* %"11_0", align 1 - store i8 %9, i8* %"11_1", align 1 - br label %10 +5: ; preds = %2 + %6 = extractvalue { i8, i8 } %"9_09", 0 + %7 = extractvalue { i8, i8 } %"9_09", 1 + store i8 %6, i8* %"11_0", align 1 + store i8 %7, i8* %"11_1", align 1 + br label %8 -10: ; preds = %6 +8: ; preds = %5 %"11_011" = load i8, i8* %"11_0", align 1 %"11_112" = load i8, i8* %"11_1", align 1 store i8 %"11_011", i8* %"11_0", align 1 store i8 %"11_112", i8* %"11_1", align 1 %"11_013" = load i8, i8* %"11_0", align 1 - %11 = insertvalue { i8 } undef, i8 %"11_013", 0 - %12 = insertvalue { i32, { i8 }, {} } { i32 0, { i8 } poison, {} poison }, { i8 } %11, 1 - store { i32, { i8 }, {} } %12, { i32, { i8 }, {} }* %"13_0", align 4 - %"13_014" = load { i32, { i8 }, {} }, { i32, { i8 }, {} }* %"13_0", align 4 + %9 = insertvalue { i1, i8 } { i1 false, i8 poison }, i8 %"11_013", 1 + store { i1, i8 } %9, { i1, i8 }* %"13_0", align 1 + %"13_014" = load { i1, i8 }, { i1, i8 }* %"13_0", align 1 %"11_115" = load i8, i8* %"11_1", align 1 - store { i32, { i8 }, {} } %"13_014", { i32, { i8 }, {} }* %"13_0", align 4 + store { i1, i8 } %"13_014", { i1, i8 }* %"13_0", align 1 store i8 %"11_115", i8* %"11_1", align 1 - %"13_016" = load { i32, { i8 }, {} }, { i32, { i8 }, {} }* %"13_0", align 4 + %"13_016" = load { i1, i8 }, { i1, i8 }* %"13_0", align 1 %"11_117" = load i8, i8* %"11_1", align 1 - %13 = extractvalue { i32, { i8 }, {} } %"13_016", 0 - switch i32 %13, label %14 [ - i32 1, label %17 + %10 = extractvalue { i1, i8 } %"13_016", 0 + switch i1 %10, label %11 [ + i1 true, label %13 ] -14: ; preds = %10 - %15 = extractvalue { i32, { i8 }, {} } %"13_016", 1 - %16 = extractvalue { i8 } %15, 0 - store i8 %16, i8* %"7_0", align 1 +11: ; preds = %8 + %12 = extractvalue { i1, i8 } %"13_016", 1 + store i8 %12, i8* %"7_0", align 1 store i8 %"11_117", i8* %"7_1", align 1 br label %2 -17: ; preds = %10 - %18 = extractvalue { i32, { i8 }, {} } %"13_016", 2 +13: ; preds = %8 store i8 %"11_117", i8* %"03", align 1 - br label %19 + br label %14 -19: ; preds = %17 +14: ; preds = %13 %"010" = load i8, i8* %"03", align 1 store i8 %"010", i8* %"4_0", align 1 %"4_018" = load i8, i8* %"4_0", align 1 diff --git a/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@llvm14.snap b/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@llvm14.snap index f125648dc..52d8aca1b 100644 --- a/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@llvm14.snap +++ b/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@llvm14.snap @@ -1,11 +1,11 @@ --- -source: src/emit/ops/cfg.rs -expression: module.to_string() +source: hugr-llvm/src/emit/ops/cfg.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1({ i32, {}, {}, {} } %0, { i32, {}, {} } %1) { +define i1 @_hl.main.1(i2 %0, i1 %1) { alloca_block: br label %entry_block @@ -13,83 +13,71 @@ entry_block: ; preds = %alloca_block br label %2 2: ; preds = %entry_block - br label %10 + br label %8 -3: ; preds = %29 - switch i32 0, label %4 [ +3: ; preds = %19 + switch i1 false, label %4 [ ] 4: ; preds = %3 - %5 = extractvalue { {} } undef, 0 - br label %9 + br label %7 -6: ; preds = %31 - switch i32 0, label %7 [ +5: ; preds = %20 + switch i1 false, label %6 [ ] -7: ; preds = %6 - %8 = extractvalue { {} } undef, 0 - br label %9 +6: ; preds = %5 + br label %7 -9: ; preds = %7, %4 - %"03.0" = phi { i32, {}, {} } [ { i32 1, {} poison, {} undef }, %4 ], [ { i32 0, {} undef, {} poison }, %7 ] - ret { i32, {}, {} } %"03.0" +7: ; preds = %6, %4 + %"03.0" = phi i1 [ true, %4 ], [ false, %6 ] + ret i1 %"03.0" -10: ; preds = %2 - %11 = extractvalue { i32, {}, {}, {} } %0, 0 - switch i32 %11, label %12 [ - i32 1, label %14 - i32 2, label %16 +8: ; preds = %2 + switch i2 %0, label %9 [ + i2 1, label %10 + i2 -2, label %11 ] -12: ; preds = %10 - %13 = extractvalue { i32, {}, {}, {} } %0, 1 - br label %18 +9: ; preds = %8 + br label %12 -14: ; preds = %10 - %15 = extractvalue { i32, {}, {}, {} } %0, 2 - br label %21 +10: ; preds = %8 + br label %14 -16: ; preds = %10 - %17 = extractvalue { i32, {}, {}, {} } %0, 3 - br label %24 +11: ; preds = %8 + br label %16 -18: ; preds = %12 - switch i32 0, label %19 [ +12: ; preds = %9 + switch i1 false, label %13 [ ] -19: ; preds = %18 - %20 = extractvalue { {} } undef, 0 - br label %27 +13: ; preds = %12 + br label %18 -21: ; preds = %14 - switch i32 0, label %22 [ +14: ; preds = %10 + switch i1 false, label %15 [ ] -22: ; preds = %21 - %23 = extractvalue { {} } undef, 0 - br label %27 +15: ; preds = %14 + br label %18 -24: ; preds = %16 - switch i32 0, label %25 [ +16: ; preds = %11 + switch i1 false, label %17 [ ] -25: ; preds = %24 - %26 = extractvalue { {} } undef, 0 - br label %27 +17: ; preds = %16 + br label %18 -27: ; preds = %25, %22, %19 - %"06.0" = phi { i32, {}, {} } [ { i32 1, {} poison, {} undef }, %19 ], [ %1, %25 ], [ { i32 0, {} undef, {} poison }, %22 ] - %28 = extractvalue { i32, {}, {} } %"06.0", 0 - switch i32 %28, label %29 [ - i32 1, label %31 +18: ; preds = %17, %15, %13 + %"06.0" = phi i1 [ true, %13 ], [ %1, %17 ], [ false, %15 ] + switch i1 %"06.0", label %19 [ + i1 true, label %20 ] -29: ; preds = %27 - %30 = extractvalue { i32, {}, {} } %"06.0", 1 +19: ; preds = %18 br label %3 -31: ; preds = %27 - %32 = extractvalue { i32, {}, {} } %"06.0", 2 - br label %6 +20: ; preds = %18 + br label %5 } diff --git a/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@pre-mem2reg@llvm14.snap index 8b3df5bbc..8fbf629ae 100644 --- a/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@pre-mem2reg@llvm14.snap @@ -1,170 +1,158 @@ --- -source: src/emit/ops/cfg.rs -expression: module.to_string() +source: hugr-llvm/src/emit/ops/cfg.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1({ i32, {}, {}, {} } %0, { i32, {}, {} } %1) { +define i1 @_hl.main.1(i2 %0, i1 %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"5_0" = alloca { {} }, align 8 - %"2_0" = alloca { i32, {}, {}, {} }, align 8 - %"2_1" = alloca { i32, {}, {} }, align 8 - %"6_0" = alloca { i32, {}, {} }, align 8 - %"9_0" = alloca { i32, {}, {}, {} }, align 8 - %"9_1" = alloca { i32, {}, {} }, align 8 - %"03" = alloca { i32, {}, {} }, align 8 - %"11_0" = alloca { i32, {}, {} }, align 8 - %"06" = alloca { i32, {}, {} }, align 8 - %"20_0" = alloca { i32, {}, {} }, align 8 - %"25_0" = alloca { i32, {}, {} }, align 8 - %"39_0" = alloca { i32, {}, {} }, align 8 - %"44_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"5_0" = alloca {}, align 8 + %"2_0" = alloca i2, align 1 + %"2_1" = alloca i1, align 1 + %"6_0" = alloca i1, align 1 + %"9_0" = alloca i2, align 1 + %"9_1" = alloca i1, align 1 + %"03" = alloca i1, align 1 + %"11_0" = alloca i1, align 1 + %"06" = alloca i1, align 1 + %"20_0" = alloca i1, align 1 + %"25_0" = alloca i1, align 1 + %"39_0" = alloca i1, align 1 + %"44_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { {} } undef, { {} }* %"5_0", align 1 - store { i32, {}, {}, {} } %0, { i32, {}, {}, {} }* %"2_0", align 4 - store { i32, {}, {} } %1, { i32, {}, {} }* %"2_1", align 4 - %"2_01" = load { i32, {}, {}, {} }, { i32, {}, {}, {} }* %"2_0", align 4 - %"2_12" = load { i32, {}, {} }, { i32, {}, {} }* %"2_1", align 4 - store { i32, {}, {}, {} } %"2_01", { i32, {}, {}, {} }* %"9_0", align 4 - store { i32, {}, {} } %"2_12", { i32, {}, {} }* %"9_1", align 4 + store {} undef, {}* %"5_0", align 1 + store i2 %0, i2* %"2_0", align 1 + store i1 %1, i1* %"2_1", align 1 + %"2_01" = load i2, i2* %"2_0", align 1 + %"2_12" = load i1, i1* %"2_1", align 1 + store i2 %"2_01", i2* %"9_0", align 1 + store i1 %"2_12", i1* %"9_1", align 1 br label %2 2: ; preds = %entry_block - %"9_04" = load { i32, {}, {}, {} }, { i32, {}, {}, {} }* %"9_0", align 4 - %"9_15" = load { i32, {}, {} }, { i32, {}, {} }* %"9_1", align 4 - store { i32, {}, {}, {} } %"9_04", { i32, {}, {}, {} }* %"9_0", align 4 - store { i32, {}, {} } %"9_15", { i32, {}, {} }* %"9_1", align 4 - br label %10 - -3: ; preds = %29 - store { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} }* %"39_0", align 4 - %"5_025" = load { {} }, { {} }* %"5_0", align 1 - %"39_026" = load { i32, {}, {} }, { i32, {}, {} }* %"39_0", align 4 - store { {} } %"5_025", { {} }* %"5_0", align 1 - store { i32, {}, {} } %"39_026", { i32, {}, {} }* %"39_0", align 4 - %"5_027" = load { {} }, { {} }* %"5_0", align 1 - %"39_028" = load { i32, {}, {} }, { i32, {}, {} }* %"39_0", align 4 - switch i32 0, label %4 [ + %"9_04" = load i2, i2* %"9_0", align 1 + %"9_15" = load i1, i1* %"9_1", align 1 + store i2 %"9_04", i2* %"9_0", align 1 + store i1 %"9_15", i1* %"9_1", align 1 + br label %8 + +3: ; preds = %19 + store i1 true, i1* %"39_0", align 1 + %"5_025" = load {}, {}* %"5_0", align 1 + %"39_026" = load i1, i1* %"39_0", align 1 + store {} %"5_025", {}* %"5_0", align 1 + store i1 %"39_026", i1* %"39_0", align 1 + %"5_027" = load {}, {}* %"5_0", align 1 + %"39_028" = load i1, i1* %"39_0", align 1 + switch i1 false, label %4 [ ] 4: ; preds = %3 - %5 = extractvalue { {} } %"5_027", 0 - store { i32, {}, {} } %"39_028", { i32, {}, {} }* %"03", align 4 - br label %9 - -6: ; preds = %31 - store { i32, {}, {} } { i32 0, {} undef, {} poison }, { i32, {}, {} }* %"44_0", align 4 - %"5_029" = load { {} }, { {} }* %"5_0", align 1 - %"44_030" = load { i32, {}, {} }, { i32, {}, {} }* %"44_0", align 4 - store { {} } %"5_029", { {} }* %"5_0", align 1 - store { i32, {}, {} } %"44_030", { i32, {}, {} }* %"44_0", align 4 - %"5_031" = load { {} }, { {} }* %"5_0", align 1 - %"44_032" = load { i32, {}, {} }, { i32, {}, {} }* %"44_0", align 4 - switch i32 0, label %7 [ + store i1 %"39_028", i1* %"03", align 1 + br label %7 + +5: ; preds = %20 + store i1 false, i1* %"44_0", align 1 + %"5_029" = load {}, {}* %"5_0", align 1 + %"44_030" = load i1, i1* %"44_0", align 1 + store {} %"5_029", {}* %"5_0", align 1 + store i1 %"44_030", i1* %"44_0", align 1 + %"5_031" = load {}, {}* %"5_0", align 1 + %"44_032" = load i1, i1* %"44_0", align 1 + switch i1 false, label %6 [ ] -7: ; preds = %6 - %8 = extractvalue { {} } %"5_031", 0 - store { i32, {}, {} } %"44_032", { i32, {}, {} }* %"03", align 4 - br label %9 - -9: ; preds = %7, %4 - %"024" = load { i32, {}, {} }, { i32, {}, {} }* %"03", align 4 - store { i32, {}, {} } %"024", { i32, {}, {} }* %"6_0", align 4 - %"6_033" = load { i32, {}, {} }, { i32, {}, {} }* %"6_0", align 4 - store { i32, {}, {} } %"6_033", { i32, {}, {} }* %"0", align 4 - %"034" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"034" - -10: ; preds = %2 - %"9_07" = load { i32, {}, {}, {} }, { i32, {}, {}, {} }* %"9_0", align 4 - store { i32, {}, {}, {} } %"9_07", { i32, {}, {}, {} }* %"9_0", align 4 - %"9_08" = load { i32, {}, {}, {} }, { i32, {}, {}, {} }* %"9_0", align 4 - %11 = extractvalue { i32, {}, {}, {} } %"9_08", 0 - switch i32 %11, label %12 [ - i32 1, label %14 - i32 2, label %16 +6: ; preds = %5 + store i1 %"44_032", i1* %"03", align 1 + br label %7 + +7: ; preds = %6, %4 + %"024" = load i1, i1* %"03", align 1 + store i1 %"024", i1* %"6_0", align 1 + %"6_033" = load i1, i1* %"6_0", align 1 + store i1 %"6_033", i1* %"0", align 1 + %"034" = load i1, i1* %"0", align 1 + ret i1 %"034" + +8: ; preds = %2 + %"9_07" = load i2, i2* %"9_0", align 1 + store i2 %"9_07", i2* %"9_0", align 1 + %"9_08" = load i2, i2* %"9_0", align 1 + switch i2 %"9_08", label %9 [ + i2 1, label %10 + i2 -2, label %11 ] -12: ; preds = %10 - %13 = extractvalue { i32, {}, {}, {} } %"9_08", 1 +9: ; preds = %8 + br label %12 + +10: ; preds = %8 + br label %14 + +11: ; preds = %8 + br label %16 + +12: ; preds = %9 + store i1 true, i1* %"20_0", align 1 + %"5_010" = load {}, {}* %"5_0", align 1 + %"20_011" = load i1, i1* %"20_0", align 1 + store {} %"5_010", {}* %"5_0", align 1 + store i1 %"20_011", i1* %"20_0", align 1 + %"5_012" = load {}, {}* %"5_0", align 1 + %"20_013" = load i1, i1* %"20_0", align 1 + switch i1 false, label %13 [ + ] + +13: ; preds = %12 + store i1 %"20_013", i1* %"06", align 1 br label %18 14: ; preds = %10 - %15 = extractvalue { i32, {}, {}, {} } %"9_08", 2 - br label %21 - -16: ; preds = %10 - %17 = extractvalue { i32, {}, {}, {} } %"9_08", 3 - br label %24 - -18: ; preds = %12 - store { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} }* %"20_0", align 4 - %"5_010" = load { {} }, { {} }* %"5_0", align 1 - %"20_011" = load { i32, {}, {} }, { i32, {}, {} }* %"20_0", align 4 - store { {} } %"5_010", { {} }* %"5_0", align 1 - store { i32, {}, {} } %"20_011", { i32, {}, {} }* %"20_0", align 4 - %"5_012" = load { {} }, { {} }* %"5_0", align 1 - %"20_013" = load { i32, {}, {} }, { i32, {}, {} }* %"20_0", align 4 - switch i32 0, label %19 [ + store i1 false, i1* %"25_0", align 1 + %"5_014" = load {}, {}* %"5_0", align 1 + %"25_015" = load i1, i1* %"25_0", align 1 + store {} %"5_014", {}* %"5_0", align 1 + store i1 %"25_015", i1* %"25_0", align 1 + %"5_016" = load {}, {}* %"5_0", align 1 + %"25_017" = load i1, i1* %"25_0", align 1 + switch i1 false, label %15 [ ] -19: ; preds = %18 - %20 = extractvalue { {} } %"5_012", 0 - store { i32, {}, {} } %"20_013", { i32, {}, {} }* %"06", align 4 - br label %27 - -21: ; preds = %14 - store { i32, {}, {} } { i32 0, {} undef, {} poison }, { i32, {}, {} }* %"25_0", align 4 - %"5_014" = load { {} }, { {} }* %"5_0", align 1 - %"25_015" = load { i32, {}, {} }, { i32, {}, {} }* %"25_0", align 4 - store { {} } %"5_014", { {} }* %"5_0", align 1 - store { i32, {}, {} } %"25_015", { i32, {}, {} }* %"25_0", align 4 - %"5_016" = load { {} }, { {} }* %"5_0", align 1 - %"25_017" = load { i32, {}, {} }, { i32, {}, {} }* %"25_0", align 4 - switch i32 0, label %22 [ - ] +15: ; preds = %14 + store i1 %"25_017", i1* %"06", align 1 + br label %18 -22: ; preds = %21 - %23 = extractvalue { {} } %"5_016", 0 - store { i32, {}, {} } %"25_017", { i32, {}, {} }* %"06", align 4 - br label %27 - -24: ; preds = %16 - %"5_018" = load { {} }, { {} }* %"5_0", align 1 - %"9_119" = load { i32, {}, {} }, { i32, {}, {} }* %"9_1", align 4 - store { {} } %"5_018", { {} }* %"5_0", align 1 - store { i32, {}, {} } %"9_119", { i32, {}, {} }* %"9_1", align 4 - %"5_020" = load { {} }, { {} }* %"5_0", align 1 - %"9_121" = load { i32, {}, {} }, { i32, {}, {} }* %"9_1", align 4 - switch i32 0, label %25 [ +16: ; preds = %11 + %"5_018" = load {}, {}* %"5_0", align 1 + %"9_119" = load i1, i1* %"9_1", align 1 + store {} %"5_018", {}* %"5_0", align 1 + store i1 %"9_119", i1* %"9_1", align 1 + %"5_020" = load {}, {}* %"5_0", align 1 + %"9_121" = load i1, i1* %"9_1", align 1 + switch i1 false, label %17 [ ] -25: ; preds = %24 - %26 = extractvalue { {} } %"5_020", 0 - store { i32, {}, {} } %"9_121", { i32, {}, {} }* %"06", align 4 - br label %27 - -27: ; preds = %25, %22, %19 - %"09" = load { i32, {}, {} }, { i32, {}, {} }* %"06", align 4 - store { i32, {}, {} } %"09", { i32, {}, {} }* %"11_0", align 4 - %"11_022" = load { i32, {}, {} }, { i32, {}, {} }* %"11_0", align 4 - store { i32, {}, {} } %"11_022", { i32, {}, {} }* %"11_0", align 4 - %"11_023" = load { i32, {}, {} }, { i32, {}, {} }* %"11_0", align 4 - %28 = extractvalue { i32, {}, {} } %"11_023", 0 - switch i32 %28, label %29 [ - i32 1, label %31 +17: ; preds = %16 + store i1 %"9_121", i1* %"06", align 1 + br label %18 + +18: ; preds = %17, %15, %13 + %"09" = load i1, i1* %"06", align 1 + store i1 %"09", i1* %"11_0", align 1 + %"11_022" = load i1, i1* %"11_0", align 1 + store i1 %"11_022", i1* %"11_0", align 1 + %"11_023" = load i1, i1* %"11_0", align 1 + switch i1 %"11_023", label %19 [ + i1 true, label %20 ] -29: ; preds = %27 - %30 = extractvalue { i32, {}, {} } %"11_023", 1 +19: ; preds = %18 br label %3 -31: ; preds = %27 - %32 = extractvalue { i32, {}, {} } %"11_023", 2 - br label %6 +20: ; preds = %18 + br label %5 } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_cfg_children@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_cfg_children@llvm14.snap index 6c403f689..9ea0d09e8 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_cfg_children@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_cfg_children@llvm14.snap @@ -1,11 +1,11 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1() { +define i1 @_hl.main.1() { alloca_block: br label %entry_block @@ -13,22 +13,21 @@ entry_block: ; preds = %alloca_block br label %0 0: ; preds = %entry_block - %1 = call { i32, {}, {} } @_hl.scoped_func.7() - switch i32 0, label %2 [ + %1 = call i1 @_hl.scoped_func.7() + switch i1 false, label %2 [ ] 2: ; preds = %0 - %3 = extractvalue { {} } undef, 0 - br label %4 + br label %3 -4: ; preds = %2 - ret { i32, {}, {} } %1 +3: ; preds = %2 + ret i1 %1 } -define { i32, {}, {} } @_hl.scoped_func.7() { +define i1 @_hl.scoped_func.7() { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - ret { i32, {}, {} } { i32 0, {} undef, {} poison } + ret i1 false } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_cfg_children@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_cfg_children@pre-mem2reg@llvm14.snap index 7a2443ce6..c38ac33f4 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_cfg_children@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_cfg_children@pre-mem2reg@llvm14.snap @@ -1,59 +1,58 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1() { +define i1 @_hl.main.1() { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 - %"01" = alloca { i32, {}, {} }, align 8 - %"15_0" = alloca { {} }, align 8 - %"16_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"4_0" = alloca i1, align 1 + %"01" = alloca i1, align 1 + %"15_0" = alloca {}, align 8 + %"16_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block br label %0 0: ; preds = %entry_block - %1 = call { i32, {}, {} } @_hl.scoped_func.7() - store { i32, {}, {} } %1, { i32, {}, {} }* %"16_0", align 4 - store { {} } undef, { {} }* %"15_0", align 1 - %"15_02" = load { {} }, { {} }* %"15_0", align 1 - %"16_03" = load { i32, {}, {} }, { i32, {}, {} }* %"16_0", align 4 - store { {} } %"15_02", { {} }* %"15_0", align 1 - store { i32, {}, {} } %"16_03", { i32, {}, {} }* %"16_0", align 4 - %"15_04" = load { {} }, { {} }* %"15_0", align 1 - %"16_05" = load { i32, {}, {} }, { i32, {}, {} }* %"16_0", align 4 - switch i32 0, label %2 [ + %1 = call i1 @_hl.scoped_func.7() + store i1 %1, i1* %"16_0", align 1 + store {} undef, {}* %"15_0", align 1 + %"15_02" = load {}, {}* %"15_0", align 1 + %"16_03" = load i1, i1* %"16_0", align 1 + store {} %"15_02", {}* %"15_0", align 1 + store i1 %"16_03", i1* %"16_0", align 1 + %"15_04" = load {}, {}* %"15_0", align 1 + %"16_05" = load i1, i1* %"16_0", align 1 + switch i1 false, label %2 [ ] 2: ; preds = %0 - %3 = extractvalue { {} } %"15_04", 0 - store { i32, {}, {} } %"16_05", { i32, {}, {} }* %"01", align 4 - br label %4 + store i1 %"16_05", i1* %"01", align 1 + br label %3 -4: ; preds = %2 - %"06" = load { i32, {}, {} }, { i32, {}, {} }* %"01", align 4 - store { i32, {}, {} } %"06", { i32, {}, {} }* %"4_0", align 4 - %"4_07" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_07", { i32, {}, {} }* %"0", align 4 - %"08" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"08" +3: ; preds = %2 + %"06" = load i1, i1* %"01", align 1 + store i1 %"06", i1* %"4_0", align 1 + %"4_07" = load i1, i1* %"4_0", align 1 + store i1 %"4_07", i1* %"0", align 1 + %"08" = load i1, i1* %"0", align 1 + ret i1 %"08" } -define { i32, {}, {} } @_hl.scoped_func.7() { +define i1 @_hl.scoped_func.7() { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"10_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"10_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } { i32 0, {} undef, {} poison }, { i32, {}, {} }* %"10_0", align 4 - %"10_01" = load { i32, {}, {} }, { i32, {}, {} }* %"10_0", align 4 - store { i32, {}, {} } %"10_01", { i32, {}, {} }* %"0", align 4 - %"02" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"02" + store i1 false, i1* %"10_0", align 1 + %"10_01" = load i1, i1* %"10_0", align 1 + store i1 %"10_01", i1* %"0", align 1 + %"02" = load i1, i1* %"0", align 1 + ret i1 %"02" } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_dfg_children@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_dfg_children@llvm14.snap index ebea354fb..ea9074b87 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_dfg_children@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_dfg_children@llvm14.snap @@ -1,23 +1,23 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1() { +define i1 @_hl.main.1() { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %0 = call { i32, {}, {} } @_hl.scoped_func.8() - ret { i32, {}, {} } %0 + %0 = call i1 @_hl.scoped_func.8() + ret i1 %0 } -define { i32, {}, {} } @_hl.scoped_func.8() { +define i1 @_hl.scoped_func.8() { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - ret { i32, {}, {} } { i32 0, {} undef, {} poison } + ret i1 false } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_dfg_children@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_dfg_children@pre-mem2reg@llvm14.snap index 435634b69..f990db641 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_dfg_children@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_dfg_children@pre-mem2reg@llvm14.snap @@ -1,38 +1,38 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1() { +define i1 @_hl.main.1() { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 - %"12_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"4_0" = alloca i1, align 1 + %"12_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - %0 = call { i32, {}, {} } @_hl.scoped_func.8() - store { i32, {}, {} } %0, { i32, {}, {} }* %"12_0", align 4 - %"12_01" = load { i32, {}, {} }, { i32, {}, {} }* %"12_0", align 4 - store { i32, {}, {} } %"12_01", { i32, {}, {} }* %"4_0", align 4 - %"4_02" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_02", { i32, {}, {} }* %"0", align 4 - %"03" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"03" + %0 = call i1 @_hl.scoped_func.8() + store i1 %0, i1* %"12_0", align 1 + %"12_01" = load i1, i1* %"12_0", align 1 + store i1 %"12_01", i1* %"4_0", align 1 + %"4_02" = load i1, i1* %"4_0", align 1 + store i1 %"4_02", i1* %"0", align 1 + %"03" = load i1, i1* %"0", align 1 + ret i1 %"03" } -define { i32, {}, {} } @_hl.scoped_func.8() { +define i1 @_hl.scoped_func.8() { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"11_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"11_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } { i32 0, {} undef, {} poison }, { i32, {}, {} }* %"11_0", align 4 - %"11_01" = load { i32, {}, {} }, { i32, {}, {} }* %"11_0", align 4 - store { i32, {}, {} } %"11_01", { i32, {}, {} }* %"0", align 4 - %"02" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"02" + store i1 false, i1* %"11_0", align 1 + %"11_01" = load i1, i1* %"11_0", align 1 + store i1 %"11_01", i1* %"0", align 1 + %"02" = load i1, i1* %"0", align 1 + ret i1 %"02" } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call@llvm14.snap index 7d3eebb6b..a47dd8f02 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call@llvm14.snap @@ -1,6 +1,6 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" @@ -14,24 +14,24 @@ entry_block: ; preds = %alloca_block ret void } -define { i32, {}, {} } @_hl.main_unary.5({ i32, {}, {} } %0) { +define i1 @_hl.main_unary.5(i1 %0) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %1 = call { i32, {}, {} } @_hl.main_unary.5({ i32, {}, {} } %0) - ret { i32, {}, {} } %1 + %1 = call i1 @_hl.main_unary.5(i1 %0) + ret i1 %1 } -define { { i32, {}, {} }, { i32, {}, {} } } @_hl.main_binary.9({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define { i1, i1 } @_hl.main_binary.9(i1 %0, i1 %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %2 = call { { i32, {}, {} }, { i32, {}, {} } } @_hl.main_binary.9({ i32, {}, {} } %0, { i32, {}, {} } %1) - %3 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %2, 0 - %4 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %2, 1 - %mrv = insertvalue { { i32, {}, {} }, { i32, {}, {} } } undef, { i32, {}, {} } %3, 0 - %mrv7 = insertvalue { { i32, {}, {} }, { i32, {}, {} } } %mrv, { i32, {}, {} } %4, 1 - ret { { i32, {}, {} }, { i32, {}, {} } } %mrv7 + %2 = call { i1, i1 } @_hl.main_binary.9(i1 %0, i1 %1) + %3 = extractvalue { i1, i1 } %2, 0 + %4 = extractvalue { i1, i1 } %2, 1 + %mrv = insertvalue { i1, i1 } undef, i1 %3, 0 + %mrv7 = insertvalue { i1, i1 } %mrv, i1 %4, 1 + ret { i1, i1 } %mrv7 } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call@pre-mem2reg@llvm14.snap index 7cd0aa2a0..268166f27 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call@pre-mem2reg@llvm14.snap @@ -1,6 +1,6 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" @@ -14,51 +14,51 @@ entry_block: ; preds = %alloca_block ret void } -define { i32, {}, {} } @_hl.main_unary.5({ i32, {}, {} } %0) { +define i1 @_hl.main_unary.5(i1 %0) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"6_0" = alloca { i32, {}, {} }, align 8 - %"8_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"6_0" = alloca i1, align 1 + %"8_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } %0, { i32, {}, {} }* %"6_0", align 4 - %"6_01" = load { i32, {}, {} }, { i32, {}, {} }* %"6_0", align 4 - %1 = call { i32, {}, {} } @_hl.main_unary.5({ i32, {}, {} } %"6_01") - store { i32, {}, {} } %1, { i32, {}, {} }* %"8_0", align 4 - %"8_02" = load { i32, {}, {} }, { i32, {}, {} }* %"8_0", align 4 - store { i32, {}, {} } %"8_02", { i32, {}, {} }* %"0", align 4 - %"03" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"03" + store i1 %0, i1* %"6_0", align 1 + %"6_01" = load i1, i1* %"6_0", align 1 + %1 = call i1 @_hl.main_unary.5(i1 %"6_01") + store i1 %1, i1* %"8_0", align 1 + %"8_02" = load i1, i1* %"8_0", align 1 + store i1 %"8_02", i1* %"0", align 1 + %"03" = load i1, i1* %"0", align 1 + ret i1 %"03" } -define { { i32, {}, {} }, { i32, {}, {} } } @_hl.main_binary.9({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define { i1, i1 } @_hl.main_binary.9(i1 %0, i1 %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"1" = alloca { i32, {}, {} }, align 8 - %"10_0" = alloca { i32, {}, {} }, align 8 - %"10_1" = alloca { i32, {}, {} }, align 8 - %"12_0" = alloca { i32, {}, {} }, align 8 - %"12_1" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"1" = alloca i1, align 1 + %"10_0" = alloca i1, align 1 + %"10_1" = alloca i1, align 1 + %"12_0" = alloca i1, align 1 + %"12_1" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } %0, { i32, {}, {} }* %"10_0", align 4 - store { i32, {}, {} } %1, { i32, {}, {} }* %"10_1", align 4 - %"10_01" = load { i32, {}, {} }, { i32, {}, {} }* %"10_0", align 4 - %"10_12" = load { i32, {}, {} }, { i32, {}, {} }* %"10_1", align 4 - %2 = call { { i32, {}, {} }, { i32, {}, {} } } @_hl.main_binary.9({ i32, {}, {} } %"10_01", { i32, {}, {} } %"10_12") - %3 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %2, 0 - %4 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %2, 1 - store { i32, {}, {} } %3, { i32, {}, {} }* %"12_0", align 4 - store { i32, {}, {} } %4, { i32, {}, {} }* %"12_1", align 4 - %"12_03" = load { i32, {}, {} }, { i32, {}, {} }* %"12_0", align 4 - %"12_14" = load { i32, {}, {} }, { i32, {}, {} }* %"12_1", align 4 - store { i32, {}, {} } %"12_03", { i32, {}, {} }* %"0", align 4 - store { i32, {}, {} } %"12_14", { i32, {}, {} }* %"1", align 4 - %"05" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - %"16" = load { i32, {}, {} }, { i32, {}, {} }* %"1", align 4 - %mrv = insertvalue { { i32, {}, {} }, { i32, {}, {} } } undef, { i32, {}, {} } %"05", 0 - %mrv7 = insertvalue { { i32, {}, {} }, { i32, {}, {} } } %mrv, { i32, {}, {} } %"16", 1 - ret { { i32, {}, {} }, { i32, {}, {} } } %mrv7 + store i1 %0, i1* %"10_0", align 1 + store i1 %1, i1* %"10_1", align 1 + %"10_01" = load i1, i1* %"10_0", align 1 + %"10_12" = load i1, i1* %"10_1", align 1 + %2 = call { i1, i1 } @_hl.main_binary.9(i1 %"10_01", i1 %"10_12") + %3 = extractvalue { i1, i1 } %2, 0 + %4 = extractvalue { i1, i1 } %2, 1 + store i1 %3, i1* %"12_0", align 1 + store i1 %4, i1* %"12_1", align 1 + %"12_03" = load i1, i1* %"12_0", align 1 + %"12_14" = load i1, i1* %"12_1", align 1 + store i1 %"12_03", i1* %"0", align 1 + store i1 %"12_14", i1* %"1", align 1 + %"05" = load i1, i1* %"0", align 1 + %"16" = load i1, i1* %"1", align 1 + %mrv = insertvalue { i1, i1 } undef, i1 %"05", 0 + %mrv7 = insertvalue { i1, i1 } %mrv, i1 %"16", 1 + ret { i1, i1 } %mrv7 } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call_indirect@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call_indirect@llvm14.snap index af9f3cb74..21e50610d 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call_indirect@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call_indirect@llvm14.snap @@ -1,6 +1,6 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" @@ -14,24 +14,24 @@ entry_block: ; preds = %alloca_block ret void } -define { i32, {}, {} } @_hl.main_unary.6({ i32, {}, {} } %0) { +define i1 @_hl.main_unary.6(i1 %0) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %1 = call { i32, {}, {} } @_hl.main_unary.6({ i32, {}, {} } %0) - ret { i32, {}, {} } %1 + %1 = call i1 @_hl.main_unary.6(i1 %0) + ret i1 %1 } -define { { i32, {}, {} }, { i32, {}, {} } } @_hl.main_binary.11({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define { i1, i1 } @_hl.main_binary.11(i1 %0, i1 %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %2 = call { { i32, {}, {} }, { i32, {}, {} } } @_hl.main_binary.11({ i32, {}, {} } %0, { i32, {}, {} } %1) - %3 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %2, 0 - %4 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %2, 1 - %mrv = insertvalue { { i32, {}, {} }, { i32, {}, {} } } undef, { i32, {}, {} } %3, 0 - %mrv8 = insertvalue { { i32, {}, {} }, { i32, {}, {} } } %mrv, { i32, {}, {} } %4, 1 - ret { { i32, {}, {} }, { i32, {}, {} } } %mrv8 + %2 = call { i1, i1 } @_hl.main_binary.11(i1 %0, i1 %1) + %3 = extractvalue { i1, i1 } %2, 0 + %4 = extractvalue { i1, i1 } %2, 1 + %mrv = insertvalue { i1, i1 } undef, i1 %3, 0 + %mrv8 = insertvalue { i1, i1 } %mrv, i1 %4, 1 + ret { i1, i1 } %mrv8 } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call_indirect@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call_indirect@pre-mem2reg@llvm14.snap index 59765560a..b3283ee1b 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call_indirect@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_call_indirect@pre-mem2reg@llvm14.snap @@ -1,6 +1,6 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" @@ -17,57 +17,57 @@ entry_block: ; preds = %alloca_block ret void } -define { i32, {}, {} } @_hl.main_unary.6({ i32, {}, {} } %0) { +define i1 @_hl.main_unary.6(i1 %0) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"7_0" = alloca { i32, {}, {} }, align 8 - %"9_0" = alloca { i32, {}, {} } ({ i32, {}, {} })*, align 8 - %"10_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"7_0" = alloca i1, align 1 + %"9_0" = alloca i1 (i1)*, align 8 + %"10_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } %0, { i32, {}, {} }* %"7_0", align 4 - store { i32, {}, {} } ({ i32, {}, {} })* @_hl.main_unary.6, { i32, {}, {} } ({ i32, {}, {} })** %"9_0", align 8 - %"9_01" = load { i32, {}, {} } ({ i32, {}, {} })*, { i32, {}, {} } ({ i32, {}, {} })** %"9_0", align 8 - %"7_02" = load { i32, {}, {} }, { i32, {}, {} }* %"7_0", align 4 - %1 = call { i32, {}, {} } %"9_01"({ i32, {}, {} } %"7_02") - store { i32, {}, {} } %1, { i32, {}, {} }* %"10_0", align 4 - %"10_03" = load { i32, {}, {} }, { i32, {}, {} }* %"10_0", align 4 - store { i32, {}, {} } %"10_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + store i1 %0, i1* %"7_0", align 1 + store i1 (i1)* @_hl.main_unary.6, i1 (i1)** %"9_0", align 8 + %"9_01" = load i1 (i1)*, i1 (i1)** %"9_0", align 8 + %"7_02" = load i1, i1* %"7_0", align 1 + %1 = call i1 %"9_01"(i1 %"7_02") + store i1 %1, i1* %"10_0", align 1 + %"10_03" = load i1, i1* %"10_0", align 1 + store i1 %"10_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } -define { { i32, {}, {} }, { i32, {}, {} } } @_hl.main_binary.11({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define { i1, i1 } @_hl.main_binary.11(i1 %0, i1 %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"1" = alloca { i32, {}, {} }, align 8 - %"12_0" = alloca { i32, {}, {} }, align 8 - %"12_1" = alloca { i32, {}, {} }, align 8 - %"14_0" = alloca { { i32, {}, {} }, { i32, {}, {} } } ({ i32, {}, {} }, { i32, {}, {} })*, align 8 - %"15_0" = alloca { i32, {}, {} }, align 8 - %"15_1" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"1" = alloca i1, align 1 + %"12_0" = alloca i1, align 1 + %"12_1" = alloca i1, align 1 + %"14_0" = alloca { i1, i1 } (i1, i1)*, align 8 + %"15_0" = alloca i1, align 1 + %"15_1" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } %0, { i32, {}, {} }* %"12_0", align 4 - store { i32, {}, {} } %1, { i32, {}, {} }* %"12_1", align 4 - store { { i32, {}, {} }, { i32, {}, {} } } ({ i32, {}, {} }, { i32, {}, {} })* @_hl.main_binary.11, { { i32, {}, {} }, { i32, {}, {} } } ({ i32, {}, {} }, { i32, {}, {} })** %"14_0", align 8 - %"14_01" = load { { i32, {}, {} }, { i32, {}, {} } } ({ i32, {}, {} }, { i32, {}, {} })*, { { i32, {}, {} }, { i32, {}, {} } } ({ i32, {}, {} }, { i32, {}, {} })** %"14_0", align 8 - %"12_02" = load { i32, {}, {} }, { i32, {}, {} }* %"12_0", align 4 - %"12_13" = load { i32, {}, {} }, { i32, {}, {} }* %"12_1", align 4 - %2 = call { { i32, {}, {} }, { i32, {}, {} } } %"14_01"({ i32, {}, {} } %"12_02", { i32, {}, {} } %"12_13") - %3 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %2, 0 - %4 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %2, 1 - store { i32, {}, {} } %3, { i32, {}, {} }* %"15_0", align 4 - store { i32, {}, {} } %4, { i32, {}, {} }* %"15_1", align 4 - %"15_04" = load { i32, {}, {} }, { i32, {}, {} }* %"15_0", align 4 - %"15_15" = load { i32, {}, {} }, { i32, {}, {} }* %"15_1", align 4 - store { i32, {}, {} } %"15_04", { i32, {}, {} }* %"0", align 4 - store { i32, {}, {} } %"15_15", { i32, {}, {} }* %"1", align 4 - %"06" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - %"17" = load { i32, {}, {} }, { i32, {}, {} }* %"1", align 4 - %mrv = insertvalue { { i32, {}, {} }, { i32, {}, {} } } undef, { i32, {}, {} } %"06", 0 - %mrv8 = insertvalue { { i32, {}, {} }, { i32, {}, {} } } %mrv, { i32, {}, {} } %"17", 1 - ret { { i32, {}, {} }, { i32, {}, {} } } %mrv8 + store i1 %0, i1* %"12_0", align 1 + store i1 %1, i1* %"12_1", align 1 + store { i1, i1 } (i1, i1)* @_hl.main_binary.11, { i1, i1 } (i1, i1)** %"14_0", align 8 + %"14_01" = load { i1, i1 } (i1, i1)*, { i1, i1 } (i1, i1)** %"14_0", align 8 + %"12_02" = load i1, i1* %"12_0", align 1 + %"12_13" = load i1, i1* %"12_1", align 1 + %2 = call { i1, i1 } %"14_01"(i1 %"12_02", i1 %"12_13") + %3 = extractvalue { i1, i1 } %2, 0 + %4 = extractvalue { i1, i1 } %2, 1 + store i1 %3, i1* %"15_0", align 1 + store i1 %4, i1* %"15_1", align 1 + %"15_04" = load i1, i1* %"15_0", align 1 + %"15_15" = load i1, i1* %"15_1", align 1 + store i1 %"15_04", i1* %"0", align 1 + store i1 %"15_15", i1* %"1", align 1 + %"06" = load i1, i1* %"0", align 1 + %"17" = load i1, i1* %"1", align 1 + %mrv = insertvalue { i1, i1 } undef, i1 %"06", 0 + %mrv8 = insertvalue { i1, i1 } %mrv, i1 %"17", 1 + ret { i1, i1 } %mrv8 } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_conditional@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_conditional@llvm14.snap index 2a6ab1381..f12ea5a52 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_conditional@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_conditional@llvm14.snap @@ -1,54 +1,46 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { {} } } @_hl.main.1({ i32, { {} }, { { {} } }, { { i32, {}, {} } } } %0, { {} } %1) { +define { { i2, i2, i1 }, {} } @_hl.main.1({ i2, i2, i1 } %0, {} %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %2 = extractvalue { i32, { {} }, { { {} } }, { { i32, {}, {} } } } %0, 0 - switch i32 %2, label %3 [ - i32 1, label %6 - i32 2, label %9 + %2 = extractvalue { i2, i2, i1 } %0, 0 + switch i2 %2, label %3 [ + i2 1, label %4 + i2 -2, label %6 ] 3: ; preds = %entry_block - %4 = extractvalue { i32, { {} }, { { {} } }, { { i32, {}, {} } } } %0, 1 - %5 = extractvalue { {} } %4, 0 br label %cond_4_case_0 -6: ; preds = %entry_block - %7 = extractvalue { i32, { {} }, { { {} } }, { { i32, {}, {} } } } %0, 2 - %8 = extractvalue { { {} } } %7, 0 +4: ; preds = %entry_block + %5 = extractvalue { i2, i2, i1 } %0, 2 br label %cond_4_case_1 -9: ; preds = %entry_block - %10 = extractvalue { i32, { {} }, { { {} } }, { { i32, {}, {} } } } %0, 3 - %11 = extractvalue { { i32, {}, {} } } %10, 0 +6: ; preds = %entry_block + %7 = extractvalue { i2, i2, i1 } %0, 1 br label %cond_4_case_2 cond_4_case_0: ; preds = %3 - %12 = insertvalue { {} } undef, {} %5, 0 - %13 = insertvalue { i32, { { i32, {}, {} } }, { { {} } }, { {} } } { i32 2, { { i32, {}, {} } } poison, { { {} } } poison, { {} } poison }, { {} } %12, 3 br label %cond_exit_4 -cond_4_case_1: ; preds = %6 - %14 = insertvalue { { {} } } undef, { {} } %8, 0 - %15 = insertvalue { i32, { { i32, {}, {} } }, { { {} } }, { {} } } { i32 1, { { i32, {}, {} } } poison, { { {} } } poison, { {} } poison }, { { {} } } %14, 2 +cond_4_case_1: ; preds = %4 + %8 = insertvalue { i2, i2, i1 } { i2 1, i2 poison, i1 poison }, i1 %5, 2 br label %cond_exit_4 -cond_4_case_2: ; preds = %9 - %16 = insertvalue { { i32, {}, {} } } undef, { i32, {}, {} } %11, 0 - %17 = insertvalue { i32, { { i32, {}, {} } }, { { {} } }, { {} } } { i32 0, { { i32, {}, {} } } poison, { { {} } } poison, { {} } poison }, { { i32, {}, {} } } %16, 1 +cond_4_case_2: ; preds = %6 + %9 = insertvalue { i2, i2, i1 } { i2 0, i2 poison, i1 poison }, i2 %7, 1 br label %cond_exit_4 cond_exit_4: ; preds = %cond_4_case_2, %cond_4_case_1, %cond_4_case_0 - %"03.0" = phi { i32, { { i32, {}, {} } }, { { {} } }, { {} } } [ %13, %cond_4_case_0 ], [ %17, %cond_4_case_2 ], [ %15, %cond_4_case_1 ] - %mrv = insertvalue { { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { {} } } undef, { i32, { { i32, {}, {} } }, { { {} } }, { {} } } %"03.0", 0 - %mrv32 = insertvalue { { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { {} } } %mrv, { {} } %1, 1 - ret { { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { {} } } %mrv32 + %"03.0" = phi { i2, i2, i1 } [ { i2 -2, i2 poison, i1 poison }, %cond_4_case_0 ], [ %9, %cond_4_case_2 ], [ %8, %cond_4_case_1 ] + %mrv = insertvalue { { i2, i2, i1 }, {} } undef, { i2, i2, i1 } %"03.0", 0 + %mrv32 = insertvalue { { i2, i2, i1 }, {} } %mrv, {} %1, 1 + ret { { i2, i2, i1 }, {} } %mrv32 } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_conditional@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_conditional@pre-mem2reg@llvm14.snap index a09e1b2b8..c2d28d64b 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_conditional@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_conditional@pre-mem2reg@llvm14.snap @@ -1,126 +1,118 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { {} } } @_hl.main.1({ i32, { {} }, { { {} } }, { { i32, {}, {} } } } %0, { {} } %1) { +define { { i2, i2, i1 }, {} } @_hl.main.1({ i2, i2, i1 } %0, {} %1) { alloca_block: - %"0" = alloca { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, align 8 - %"1" = alloca { {} }, align 8 - %"2_0" = alloca { i32, { {} }, { { {} } }, { { i32, {}, {} } } }, align 8 - %"2_1" = alloca { {} }, align 8 - %"4_0" = alloca { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, align 8 - %"4_1" = alloca { {} }, align 8 - %"03" = alloca { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, align 8 - %"14" = alloca { {} }, align 8 + %"0" = alloca { i2, i2, i1 }, align 8 + %"1" = alloca {}, align 8 + %"2_0" = alloca { i2, i2, i1 }, align 8 + %"2_1" = alloca {}, align 8 + %"4_0" = alloca { i2, i2, i1 }, align 8 + %"4_1" = alloca {}, align 8 + %"03" = alloca { i2, i2, i1 }, align 8 + %"14" = alloca {}, align 8 %"07" = alloca {}, align 8 - %"18" = alloca { {} }, align 8 + %"18" = alloca {}, align 8 %"6_0" = alloca {}, align 8 - %"6_1" = alloca { {} }, align 8 - %"8_0" = alloca { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, align 8 - %"014" = alloca { {} }, align 8 - %"115" = alloca { {} }, align 8 - %"10_0" = alloca { {} }, align 8 - %"10_1" = alloca { {} }, align 8 - %"12_0" = alloca { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, align 8 - %"021" = alloca { i32, {}, {} }, align 8 - %"122" = alloca { {} }, align 8 - %"14_0" = alloca { i32, {}, {} }, align 8 - %"14_1" = alloca { {} }, align 8 - %"16_0" = alloca { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, align 8 + %"6_1" = alloca {}, align 8 + %"8_0" = alloca { i2, i2, i1 }, align 8 + %"014" = alloca i1, align 1 + %"115" = alloca {}, align 8 + %"10_0" = alloca i1, align 1 + %"10_1" = alloca {}, align 8 + %"12_0" = alloca { i2, i2, i1 }, align 8 + %"021" = alloca i2, align 1 + %"122" = alloca {}, align 8 + %"14_0" = alloca i2, align 1 + %"14_1" = alloca {}, align 8 + %"16_0" = alloca { i2, i2, i1 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, { {} }, { { {} } }, { { i32, {}, {} } } } %0, { i32, { {} }, { { {} } }, { { i32, {}, {} } } }* %"2_0", align 4 - store { {} } %1, { {} }* %"2_1", align 1 - %"2_01" = load { i32, { {} }, { { {} } }, { { i32, {}, {} } } }, { i32, { {} }, { { {} } }, { { i32, {}, {} } } }* %"2_0", align 4 - %"2_12" = load { {} }, { {} }* %"2_1", align 1 - %2 = extractvalue { i32, { {} }, { { {} } }, { { i32, {}, {} } } } %"2_01", 0 - switch i32 %2, label %3 [ - i32 1, label %6 - i32 2, label %9 + store { i2, i2, i1 } %0, { i2, i2, i1 }* %"2_0", align 1 + store {} %1, {}* %"2_1", align 1 + %"2_01" = load { i2, i2, i1 }, { i2, i2, i1 }* %"2_0", align 1 + %"2_12" = load {}, {}* %"2_1", align 1 + %2 = extractvalue { i2, i2, i1 } %"2_01", 0 + switch i2 %2, label %3 [ + i2 1, label %4 + i2 -2, label %6 ] 3: ; preds = %entry_block - %4 = extractvalue { i32, { {} }, { { {} } }, { { i32, {}, {} } } } %"2_01", 1 - %5 = extractvalue { {} } %4, 0 - store {} %5, {}* %"07", align 1 - store { {} } %"2_12", { {} }* %"18", align 1 + store {} undef, {}* %"07", align 1 + store {} %"2_12", {}* %"18", align 1 br label %cond_4_case_0 -6: ; preds = %entry_block - %7 = extractvalue { i32, { {} }, { { {} } }, { { i32, {}, {} } } } %"2_01", 2 - %8 = extractvalue { { {} } } %7, 0 - store { {} } %8, { {} }* %"014", align 1 - store { {} } %"2_12", { {} }* %"115", align 1 +4: ; preds = %entry_block + %5 = extractvalue { i2, i2, i1 } %"2_01", 2 + store i1 %5, i1* %"014", align 1 + store {} %"2_12", {}* %"115", align 1 br label %cond_4_case_1 -9: ; preds = %entry_block - %10 = extractvalue { i32, { {} }, { { {} } }, { { i32, {}, {} } } } %"2_01", 3 - %11 = extractvalue { { i32, {}, {} } } %10, 0 - store { i32, {}, {} } %11, { i32, {}, {} }* %"021", align 4 - store { {} } %"2_12", { {} }* %"122", align 1 +6: ; preds = %entry_block + %7 = extractvalue { i2, i2, i1 } %"2_01", 1 + store i2 %7, i2* %"021", align 1 + store {} %"2_12", {}* %"122", align 1 br label %cond_4_case_2 cond_4_case_0: ; preds = %3 %"09" = load {}, {}* %"07", align 1 - %"110" = load { {} }, { {} }* %"18", align 1 + %"110" = load {}, {}* %"18", align 1 store {} %"09", {}* %"6_0", align 1 - store { {} } %"110", { {} }* %"6_1", align 1 + store {} %"110", {}* %"6_1", align 1 %"6_011" = load {}, {}* %"6_0", align 1 - %12 = insertvalue { {} } undef, {} %"6_011", 0 - %13 = insertvalue { i32, { { i32, {}, {} } }, { { {} } }, { {} } } { i32 2, { { i32, {}, {} } } poison, { { {} } } poison, { {} } poison }, { {} } %12, 3 - store { i32, { { i32, {}, {} } }, { { {} } }, { {} } } %13, { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"8_0", align 4 - %"8_012" = load { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"8_0", align 4 - %"6_113" = load { {} }, { {} }* %"6_1", align 1 - store { i32, { { i32, {}, {} } }, { { {} } }, { {} } } %"8_012", { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"03", align 4 - store { {} } %"6_113", { {} }* %"14", align 1 + store { i2, i2, i1 } { i2 -2, i2 poison, i1 poison }, { i2, i2, i1 }* %"8_0", align 1 + %"8_012" = load { i2, i2, i1 }, { i2, i2, i1 }* %"8_0", align 1 + %"6_113" = load {}, {}* %"6_1", align 1 + store { i2, i2, i1 } %"8_012", { i2, i2, i1 }* %"03", align 1 + store {} %"6_113", {}* %"14", align 1 br label %cond_exit_4 -cond_4_case_1: ; preds = %6 - %"016" = load { {} }, { {} }* %"014", align 1 - %"117" = load { {} }, { {} }* %"115", align 1 - store { {} } %"016", { {} }* %"10_0", align 1 - store { {} } %"117", { {} }* %"10_1", align 1 - %"10_018" = load { {} }, { {} }* %"10_0", align 1 - %14 = insertvalue { { {} } } undef, { {} } %"10_018", 0 - %15 = insertvalue { i32, { { i32, {}, {} } }, { { {} } }, { {} } } { i32 1, { { i32, {}, {} } } poison, { { {} } } poison, { {} } poison }, { { {} } } %14, 2 - store { i32, { { i32, {}, {} } }, { { {} } }, { {} } } %15, { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"12_0", align 4 - %"12_019" = load { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"12_0", align 4 - %"10_120" = load { {} }, { {} }* %"10_1", align 1 - store { i32, { { i32, {}, {} } }, { { {} } }, { {} } } %"12_019", { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"03", align 4 - store { {} } %"10_120", { {} }* %"14", align 1 +cond_4_case_1: ; preds = %4 + %"016" = load i1, i1* %"014", align 1 + %"117" = load {}, {}* %"115", align 1 + store i1 %"016", i1* %"10_0", align 1 + store {} %"117", {}* %"10_1", align 1 + %"10_018" = load i1, i1* %"10_0", align 1 + %8 = insertvalue { i2, i2, i1 } { i2 1, i2 poison, i1 poison }, i1 %"10_018", 2 + store { i2, i2, i1 } %8, { i2, i2, i1 }* %"12_0", align 1 + %"12_019" = load { i2, i2, i1 }, { i2, i2, i1 }* %"12_0", align 1 + %"10_120" = load {}, {}* %"10_1", align 1 + store { i2, i2, i1 } %"12_019", { i2, i2, i1 }* %"03", align 1 + store {} %"10_120", {}* %"14", align 1 br label %cond_exit_4 -cond_4_case_2: ; preds = %9 - %"023" = load { i32, {}, {} }, { i32, {}, {} }* %"021", align 4 - %"124" = load { {} }, { {} }* %"122", align 1 - store { i32, {}, {} } %"023", { i32, {}, {} }* %"14_0", align 4 - store { {} } %"124", { {} }* %"14_1", align 1 - %"14_025" = load { i32, {}, {} }, { i32, {}, {} }* %"14_0", align 4 - %16 = insertvalue { { i32, {}, {} } } undef, { i32, {}, {} } %"14_025", 0 - %17 = insertvalue { i32, { { i32, {}, {} } }, { { {} } }, { {} } } { i32 0, { { i32, {}, {} } } poison, { { {} } } poison, { {} } poison }, { { i32, {}, {} } } %16, 1 - store { i32, { { i32, {}, {} } }, { { {} } }, { {} } } %17, { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"16_0", align 4 - %"16_026" = load { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"16_0", align 4 - %"14_127" = load { {} }, { {} }* %"14_1", align 1 - store { i32, { { i32, {}, {} } }, { { {} } }, { {} } } %"16_026", { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"03", align 4 - store { {} } %"14_127", { {} }* %"14", align 1 +cond_4_case_2: ; preds = %6 + %"023" = load i2, i2* %"021", align 1 + %"124" = load {}, {}* %"122", align 1 + store i2 %"023", i2* %"14_0", align 1 + store {} %"124", {}* %"14_1", align 1 + %"14_025" = load i2, i2* %"14_0", align 1 + %9 = insertvalue { i2, i2, i1 } { i2 0, i2 poison, i1 poison }, i2 %"14_025", 1 + store { i2, i2, i1 } %9, { i2, i2, i1 }* %"16_0", align 1 + %"16_026" = load { i2, i2, i1 }, { i2, i2, i1 }* %"16_0", align 1 + %"14_127" = load {}, {}* %"14_1", align 1 + store { i2, i2, i1 } %"16_026", { i2, i2, i1 }* %"03", align 1 + store {} %"14_127", {}* %"14", align 1 br label %cond_exit_4 cond_exit_4: ; preds = %cond_4_case_2, %cond_4_case_1, %cond_4_case_0 - %"05" = load { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"03", align 4 - %"16" = load { {} }, { {} }* %"14", align 1 - store { i32, { { i32, {}, {} } }, { { {} } }, { {} } } %"05", { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"4_0", align 4 - store { {} } %"16", { {} }* %"4_1", align 1 - %"4_028" = load { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"4_0", align 4 - %"4_129" = load { {} }, { {} }* %"4_1", align 1 - store { i32, { { i32, {}, {} } }, { { {} } }, { {} } } %"4_028", { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"0", align 4 - store { {} } %"4_129", { {} }* %"1", align 1 - %"030" = load { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { i32, { { i32, {}, {} } }, { { {} } }, { {} } }* %"0", align 4 - %"131" = load { {} }, { {} }* %"1", align 1 - %mrv = insertvalue { { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { {} } } undef, { i32, { { i32, {}, {} } }, { { {} } }, { {} } } %"030", 0 - %mrv32 = insertvalue { { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { {} } } %mrv, { {} } %"131", 1 - ret { { i32, { { i32, {}, {} } }, { { {} } }, { {} } }, { {} } } %mrv32 + %"05" = load { i2, i2, i1 }, { i2, i2, i1 }* %"03", align 1 + %"16" = load {}, {}* %"14", align 1 + store { i2, i2, i1 } %"05", { i2, i2, i1 }* %"4_0", align 1 + store {} %"16", {}* %"4_1", align 1 + %"4_028" = load { i2, i2, i1 }, { i2, i2, i1 }* %"4_0", align 1 + %"4_129" = load {}, {}* %"4_1", align 1 + store { i2, i2, i1 } %"4_028", { i2, i2, i1 }* %"0", align 1 + store {} %"4_129", {}* %"1", align 1 + %"030" = load { i2, i2, i1 }, { i2, i2, i1 }* %"0", align 1 + %"131" = load {}, {}* %"1", align 1 + %mrv = insertvalue { { i2, i2, i1 }, {} } undef, { i2, i2, i1 } %"030", 0 + %mrv32 = insertvalue { { i2, i2, i1 }, {} } %mrv, {} %"131", 1 + ret { { i2, i2, i1 }, {} } %mrv32 } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_dfg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_dfg@llvm14.snap index 8ca5d2602..ae72186e2 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_dfg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_dfg@llvm14.snap @@ -1,14 +1,14 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { {} } @_hl.main.1({ {} } %0) { +define {} @_hl.main.1({} %0) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - ret { {} } %0 + ret {} %0 } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_dfg@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_dfg@pre-mem2reg@llvm14.snap index 04f627a9f..28ba006ac 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_dfg@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_dfg@pre-mem2reg@llvm14.snap @@ -1,26 +1,26 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { {} } @_hl.main.1({ {} } %0) { +define {} @_hl.main.1({} %0) { alloca_block: - %"0" = alloca { {} }, align 8 - %"2_0" = alloca { {} }, align 8 - %"4_0" = alloca { {} }, align 8 - %"5_0" = alloca { {} }, align 8 + %"0" = alloca {}, align 8 + %"2_0" = alloca {}, align 8 + %"4_0" = alloca {}, align 8 + %"5_0" = alloca {}, align 8 br label %entry_block entry_block: ; preds = %alloca_block - store { {} } %0, { {} }* %"2_0", align 1 - %"2_01" = load { {} }, { {} }* %"2_0", align 1 - store { {} } %"2_01", { {} }* %"5_0", align 1 - %"5_02" = load { {} }, { {} }* %"5_0", align 1 - store { {} } %"5_02", { {} }* %"4_0", align 1 - %"4_03" = load { {} }, { {} }* %"4_0", align 1 - store { {} } %"4_03", { {} }* %"0", align 1 - %"04" = load { {} }, { {} }* %"0", align 1 - ret { {} } %"04" + store {} %0, {}* %"2_0", align 1 + %"2_01" = load {}, {}* %"2_0", align 1 + store {} %"2_01", {}* %"5_0", align 1 + %"5_02" = load {}, {}* %"5_0", align 1 + store {} %"5_02", {}* %"4_0", align 1 + %"4_03" = load {}, {}* %"4_0", align 1 + store {} %"4_03", {}* %"0", align 1 + %"04" = load {}, {}* %"0", align 1 + ret {} %"04" } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_load_constant@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_load_constant@llvm14.snap index df80ecc00..e7dc941c5 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_load_constant@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_load_constant@llvm14.snap @@ -1,14 +1,14 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { { { i32, {}, {}, {}, {} }, i16 } } @_hl.main.1() { +define { i2, i16 } @_hl.main.1() { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - ret { { { i32, {}, {}, {}, {} }, i16 } } { { { i32, {}, {}, {}, {} }, i16 } { { i32, {}, {}, {}, {} } { i32 2, {} poison, {} poison, {} undef, {} poison }, i16 -24 } } + ret { i2, i16 } { i2 -2, i16 -24 } } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_load_constant@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_load_constant@pre-mem2reg@llvm14.snap index e8424cf40..33612b2c2 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_load_constant@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_load_constant@pre-mem2reg@llvm14.snap @@ -1,20 +1,20 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { { { i32, {}, {}, {}, {} }, i16 } } @_hl.main.1() { +define { i2, i16 } @_hl.main.1() { alloca_block: - %"0" = alloca { { { i32, {}, {}, {}, {} }, i16 } }, align 8 - %"5_0" = alloca { { { i32, {}, {}, {}, {} }, i16 } }, align 8 + %"0" = alloca { i2, i16 }, align 8 + %"5_0" = alloca { i2, i16 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block - store { { { i32, {}, {}, {}, {} }, i16 } } { { { i32, {}, {}, {}, {} }, i16 } { { i32, {}, {}, {}, {} } { i32 2, {} poison, {} poison, {} undef, {} poison }, i16 -24 } }, { { { i32, {}, {}, {}, {} }, i16 } }* %"5_0", align 4 - %"5_01" = load { { { i32, {}, {}, {}, {} }, i16 } }, { { { i32, {}, {}, {}, {} }, i16 } }* %"5_0", align 4 - store { { { i32, {}, {}, {}, {} }, i16 } } %"5_01", { { { i32, {}, {}, {}, {} }, i16 } }* %"0", align 4 - %"02" = load { { { i32, {}, {}, {}, {} }, i16 } }, { { { i32, {}, {}, {}, {} }, i16 } }* %"0", align 4 - ret { { { i32, {}, {}, {}, {} }, i16 } } %"02" + store { i2, i16 } { i2 -2, i16 -24 }, { i2, i16 }* %"5_0", align 2 + %"5_01" = load { i2, i16 }, { i2, i16 }* %"5_0", align 2 + store { i2, i16 } %"5_01", { i2, i16 }* %"0", align 2 + %"02" = load { i2, i16 }, { i2, i16 }* %"0", align 2 + ret { i2, i16 } %"02" } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_tag@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_tag@llvm14.snap index 10a6b337f..89a4c44b4 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_tag@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_tag@llvm14.snap @@ -1,14 +1,14 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {}, {} } @_hl.main.1() { +define i2 @_hl.main.1() { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - ret { i32, {}, {}, {} } { i32 1, {} poison, {} undef, {} poison } + ret i2 1 } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_tag@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_tag@pre-mem2reg@llvm14.snap index 3dbc925d5..dca6775cd 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_tag@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_tag@pre-mem2reg@llvm14.snap @@ -1,20 +1,20 @@ --- -source: src/emit/test.rs -expression: module.to_string() +source: hugr-llvm/src/emit/test.rs +expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {}, {} } @_hl.main.1() { +define i2 @_hl.main.1() { alloca_block: - %"0" = alloca { i32, {}, {}, {} }, align 8 - %"4_0" = alloca { i32, {}, {}, {} }, align 8 + %"0" = alloca i2, align 1 + %"4_0" = alloca i2, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {}, {} } { i32 1, {} poison, {} undef, {} poison }, { i32, {}, {}, {} }* %"4_0", align 4 - %"4_01" = load { i32, {}, {}, {} }, { i32, {}, {}, {} }* %"4_0", align 4 - store { i32, {}, {}, {} } %"4_01", { i32, {}, {}, {} }* %"0", align 4 - %"02" = load { i32, {}, {}, {} }, { i32, {}, {}, {} }* %"0", align 4 - ret { i32, {}, {}, {} } %"02" + store i2 1, i2* %"4_0", align 1 + %"4_01" = load i2, i2* %"4_0", align 1 + store i2 %"4_01", i2* %"0", align 1 + %"02" = load i2, i2* %"0", align 1 + ret i2 %"02" } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop@llvm14.snap index 7765ae0a2..7c88f9b48 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop@llvm14.snap @@ -12,50 +12,44 @@ alloca_block: entry_block: ; preds = %alloca_block br label %loop_body -loop_body: ; preds = %12, %entry_block - %"9_0.0" = phi i64 [ 3, %entry_block ], [ %14, %12 ] - %"9_1.0" = phi i64 [ 7, %entry_block ], [ %0, %12 ] +loop_body: ; preds = %8, %entry_block + %"9_0.0" = phi i64 [ 3, %entry_block ], [ %9, %8 ] + %"9_1.0" = phi i64 [ 7, %entry_block ], [ %0, %8 ] %0 = mul i64 %"9_1.0", 2 %1 = icmp eq i64 %"9_0.0", 0 - %2 = select i1 %1, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - %3 = extractvalue { i32, {}, {} } %2, 0 - switch i32 %3, label %4 [ - i32 1, label %6 + %2 = select i1 %1, i1 true, i1 false + switch i1 %2, label %3 [ + i1 true, label %4 ] -4: ; preds = %loop_body - %5 = extractvalue { i32, {}, {} } %2, 1 +3: ; preds = %loop_body br label %cond_17_case_0 -6: ; preds = %loop_body - %7 = extractvalue { i32, {}, {} } %2, 2 +4: ; preds = %loop_body br label %cond_17_case_1 -loop_out: ; preds = %15 +loop_out: ; preds = %10 ret i64 %0 -cond_17_case_0: ; preds = %4 - %8 = sub i64 %"9_0.0", 1 - %9 = insertvalue { i64 } undef, i64 %8, 0 - %10 = insertvalue { i32, { i64 }, {} } { i32 0, { i64 } poison, {} poison }, { i64 } %9, 1 +cond_17_case_0: ; preds = %3 + %5 = sub i64 %"9_0.0", 1 + %6 = insertvalue { i1, i64 } { i1 false, i64 poison }, i64 %5, 1 br label %cond_exit_17 -cond_17_case_1: ; preds = %6 +cond_17_case_1: ; preds = %4 br label %cond_exit_17 cond_exit_17: ; preds = %cond_17_case_1, %cond_17_case_0 - %"011.0" = phi { i32, { i64 }, {} } [ %10, %cond_17_case_0 ], [ { i32 1, { i64 } poison, {} undef }, %cond_17_case_1 ] - %11 = extractvalue { i32, { i64 }, {} } %"011.0", 0 - switch i32 %11, label %12 [ - i32 1, label %15 + %"011.0" = phi { i1, i64 } [ %6, %cond_17_case_0 ], [ { i1 true, i64 poison }, %cond_17_case_1 ] + %7 = extractvalue { i1, i64 } %"011.0", 0 + switch i1 %7, label %8 [ + i1 true, label %10 ] -12: ; preds = %cond_exit_17 - %13 = extractvalue { i32, { i64 }, {} } %"011.0", 1 - %14 = extractvalue { i64 } %13, 0 +8: ; preds = %cond_exit_17 + %9 = extractvalue { i1, i64 } %"011.0", 1 br label %loop_body -15: ; preds = %cond_exit_17 - %16 = extractvalue { i32, { i64 }, {} } %"011.0", 2 +10: ; preds = %cond_exit_17 br label %loop_out } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop@pre-mem2reg@llvm14.snap index 6f9d1cb13..2a6ef7a36 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop@pre-mem2reg@llvm14.snap @@ -13,19 +13,19 @@ alloca_block: %"8_0" = alloca i64, align 8 %"9_0" = alloca i64, align 8 %"9_1" = alloca i64, align 8 - %"17_0" = alloca { i32, { i64 }, {} }, align 8 + %"17_0" = alloca { i1, i64 }, align 8 %"16_0" = alloca i64, align 8 %"15_0" = alloca i64, align 8 %"12_0" = alloca i64, align 8 - %"13_0" = alloca { i32, {}, {} }, align 8 - %"011" = alloca { i32, { i64 }, {} }, align 8 + %"13_0" = alloca i1, align 1 + %"011" = alloca { i1, i64 }, align 8 %"013" = alloca i64, align 8 %"23_0" = alloca i64, align 8 %"20_0" = alloca i64, align 8 %"24_0" = alloca i64, align 8 - %"25_0" = alloca { i32, { i64 }, {} }, align 8 + %"25_0" = alloca { i1, i64 }, align 8 %"019" = alloca i64, align 8 - %"29_0" = alloca { i32, { i64 }, {} }, align 8 + %"29_0" = alloca { i1, i64 }, align 8 %"27_0" = alloca i64, align 8 br label %entry_block @@ -38,7 +38,7 @@ entry_block: ; preds = %alloca_block store i64 %"7_02", i64* %"9_1", align 4 br label %loop_body -loop_body: ; preds = %12, %entry_block +loop_body: ; preds = %8, %entry_block %"9_03" = load i64, i64* %"9_0", align 4 %"9_14" = load i64, i64* %"9_1", align 4 store i64 2, i64* %"15_0", align 4 @@ -52,78 +52,72 @@ loop_body: ; preds = %12, %entry_block %"9_07" = load i64, i64* %"9_0", align 4 %"12_08" = load i64, i64* %"12_0", align 4 %1 = icmp eq i64 %"9_07", %"12_08" - %2 = select i1 %1, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %2, { i32, {}, {} }* %"13_0", align 4 - %"13_09" = load { i32, {}, {} }, { i32, {}, {} }* %"13_0", align 4 + %2 = select i1 %1, i1 true, i1 false + store i1 %2, i1* %"13_0", align 1 + %"13_09" = load i1, i1* %"13_0", align 1 %"9_010" = load i64, i64* %"9_0", align 4 - %3 = extractvalue { i32, {}, {} } %"13_09", 0 - switch i32 %3, label %4 [ - i32 1, label %6 + switch i1 %"13_09", label %3 [ + i1 true, label %4 ] -4: ; preds = %loop_body - %5 = extractvalue { i32, {}, {} } %"13_09", 1 +3: ; preds = %loop_body store i64 %"9_010", i64* %"013", align 4 br label %cond_17_case_0 -6: ; preds = %loop_body - %7 = extractvalue { i32, {}, {} } %"13_09", 2 +4: ; preds = %loop_body store i64 %"9_010", i64* %"019", align 4 br label %cond_17_case_1 -loop_out: ; preds = %15 +loop_out: ; preds = %10 %"8_026" = load i64, i64* %"8_0", align 4 store i64 %"8_026", i64* %"0", align 4 %"027" = load i64, i64* %"0", align 4 ret i64 %"027" -cond_17_case_0: ; preds = %4 +cond_17_case_0: ; preds = %3 %"014" = load i64, i64* %"013", align 4 store i64 1, i64* %"23_0", align 4 store i64 %"014", i64* %"20_0", align 4 %"20_015" = load i64, i64* %"20_0", align 4 %"23_016" = load i64, i64* %"23_0", align 4 - %8 = sub i64 %"20_015", %"23_016" - store i64 %8, i64* %"24_0", align 4 + %5 = sub i64 %"20_015", %"23_016" + store i64 %5, i64* %"24_0", align 4 %"24_017" = load i64, i64* %"24_0", align 4 - %9 = insertvalue { i64 } undef, i64 %"24_017", 0 - %10 = insertvalue { i32, { i64 }, {} } { i32 0, { i64 } poison, {} poison }, { i64 } %9, 1 - store { i32, { i64 }, {} } %10, { i32, { i64 }, {} }* %"25_0", align 4 - %"25_018" = load { i32, { i64 }, {} }, { i32, { i64 }, {} }* %"25_0", align 4 - store { i32, { i64 }, {} } %"25_018", { i32, { i64 }, {} }* %"011", align 4 + %6 = insertvalue { i1, i64 } { i1 false, i64 poison }, i64 %"24_017", 1 + store { i1, i64 } %6, { i1, i64 }* %"25_0", align 4 + %"25_018" = load { i1, i64 }, { i1, i64 }* %"25_0", align 4 + store { i1, i64 } %"25_018", { i1, i64 }* %"011", align 4 br label %cond_exit_17 -cond_17_case_1: ; preds = %6 +cond_17_case_1: ; preds = %4 %"020" = load i64, i64* %"019", align 4 - store { i32, { i64 }, {} } { i32 1, { i64 } poison, {} undef }, { i32, { i64 }, {} }* %"29_0", align 4 - %"29_021" = load { i32, { i64 }, {} }, { i32, { i64 }, {} }* %"29_0", align 4 - store { i32, { i64 }, {} } %"29_021", { i32, { i64 }, {} }* %"011", align 4 + store { i1, i64 } { i1 true, i64 poison }, { i1, i64 }* %"29_0", align 4 + %"29_021" = load { i1, i64 }, { i1, i64 }* %"29_0", align 4 + store { i1, i64 } %"29_021", { i1, i64 }* %"011", align 4 store i64 %"020", i64* %"27_0", align 4 br label %cond_exit_17 cond_exit_17: ; preds = %cond_17_case_1, %cond_17_case_0 - %"012" = load { i32, { i64 }, {} }, { i32, { i64 }, {} }* %"011", align 4 - store { i32, { i64 }, {} } %"012", { i32, { i64 }, {} }* %"17_0", align 4 - %"17_022" = load { i32, { i64 }, {} }, { i32, { i64 }, {} }* %"17_0", align 4 + %"012" = load { i1, i64 }, { i1, i64 }* %"011", align 4 + store { i1, i64 } %"012", { i1, i64 }* %"17_0", align 4 + %"17_022" = load { i1, i64 }, { i1, i64 }* %"17_0", align 4 %"16_023" = load i64, i64* %"16_0", align 4 - store { i32, { i64 }, {} } %"17_022", { i32, { i64 }, {} }* %"17_0", align 4 + store { i1, i64 } %"17_022", { i1, i64 }* %"17_0", align 4 store i64 %"16_023", i64* %"16_0", align 4 - %"17_024" = load { i32, { i64 }, {} }, { i32, { i64 }, {} }* %"17_0", align 4 + %"17_024" = load { i1, i64 }, { i1, i64 }* %"17_0", align 4 %"16_025" = load i64, i64* %"16_0", align 4 - %11 = extractvalue { i32, { i64 }, {} } %"17_024", 0 - switch i32 %11, label %12 [ - i32 1, label %15 + %7 = extractvalue { i1, i64 } %"17_024", 0 + switch i1 %7, label %8 [ + i1 true, label %10 ] -12: ; preds = %cond_exit_17 - %13 = extractvalue { i32, { i64 }, {} } %"17_024", 1 - %14 = extractvalue { i64 } %13, 0 - store i64 %14, i64* %"9_0", align 4 +8: ; preds = %cond_exit_17 + %9 = extractvalue { i1, i64 } %"17_024", 1 + store i64 %9, i64* %"9_0", align 4 store i64 %"16_025", i64* %"9_1", align 4 br label %loop_body -15: ; preds = %cond_exit_17 - %16 = extractvalue { i32, { i64 }, {} } %"17_024", 2 +10: ; preds = %cond_exit_17 store i64 %"16_025", i64* %"8_0", align 4 br label %loop_out } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop_simple@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop_simple@llvm14.snap index 408f61aeb..3f53e26e0 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop_simple@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop_simple@llvm14.snap @@ -5,32 +5,28 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { {} } @_hl.main.1(i64 %0) { +define {} @_hl.main.1(i64 %0) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block br label %loop_body -loop_body: ; preds = %4, %entry_block - %"5_0.0" = phi i64 [ %0, %entry_block ], [ %6, %4 ] - %1 = insertvalue { i64 } undef, i64 %"5_0.0", 0 - %2 = insertvalue { i32, { i64 }, { { {} } } } { i32 0, { i64 } poison, { { {} } } poison }, { i64 } %1, 1 - %3 = extractvalue { i32, { i64 }, { { {} } } } %2, 0 - switch i32 %3, label %4 [ - i32 1, label %7 +loop_body: ; preds = %3, %entry_block + %"5_0.0" = phi i64 [ %0, %entry_block ], [ %4, %3 ] + %1 = insertvalue { i1, i64 } { i1 false, i64 poison }, i64 %"5_0.0", 1 + %2 = extractvalue { i1, i64 } %1, 0 + switch i1 %2, label %3 [ + i1 true, label %5 ] -4: ; preds = %loop_body - %5 = extractvalue { i32, { i64 }, { { {} } } } %2, 1 - %6 = extractvalue { i64 } %5, 0 +3: ; preds = %loop_body + %4 = extractvalue { i1, i64 } %1, 1 br label %loop_body -7: ; preds = %loop_body - %8 = extractvalue { i32, { i64 }, { { {} } } } %2, 2 - %9 = extractvalue { { {} } } %8, 0 +5: ; preds = %loop_body br label %loop_out -loop_out: ; preds = %7 - ret { {} } %9 +loop_out: ; preds = %5 + ret {} undef } diff --git a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop_simple@pre-mem2reg@llvm14.snap b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop_simple@pre-mem2reg@llvm14.snap index 7c1a36ea0..35ca1c42a 100644 --- a/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop_simple@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__tail_loop_simple@pre-mem2reg@llvm14.snap @@ -5,13 +5,13 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { {} } @_hl.main.1(i64 %0) { +define {} @_hl.main.1(i64 %0) { alloca_block: - %"0" = alloca { {} }, align 8 + %"0" = alloca {}, align 8 %"2_0" = alloca i64, align 8 - %"4_0" = alloca { {} }, align 8 + %"4_0" = alloca {}, align 8 %"5_0" = alloca i64, align 8 - %"7_0" = alloca { i32, { i64 }, { { {} } } }, align 8 + %"7_0" = alloca { i1, i64 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block @@ -20,36 +20,32 @@ entry_block: ; preds = %alloca_block store i64 %"2_01", i64* %"5_0", align 4 br label %loop_body -loop_body: ; preds = %4, %entry_block +loop_body: ; preds = %3, %entry_block %"5_02" = load i64, i64* %"5_0", align 4 store i64 %"5_02", i64* %"5_0", align 4 %"5_03" = load i64, i64* %"5_0", align 4 - %1 = insertvalue { i64 } undef, i64 %"5_03", 0 - %2 = insertvalue { i32, { i64 }, { { {} } } } { i32 0, { i64 } poison, { { {} } } poison }, { i64 } %1, 1 - store { i32, { i64 }, { { {} } } } %2, { i32, { i64 }, { { {} } } }* %"7_0", align 4 - %"7_04" = load { i32, { i64 }, { { {} } } }, { i32, { i64 }, { { {} } } }* %"7_0", align 4 - store { i32, { i64 }, { { {} } } } %"7_04", { i32, { i64 }, { { {} } } }* %"7_0", align 4 - %"7_05" = load { i32, { i64 }, { { {} } } }, { i32, { i64 }, { { {} } } }* %"7_0", align 4 - %3 = extractvalue { i32, { i64 }, { { {} } } } %"7_05", 0 - switch i32 %3, label %4 [ - i32 1, label %7 + %1 = insertvalue { i1, i64 } { i1 false, i64 poison }, i64 %"5_03", 1 + store { i1, i64 } %1, { i1, i64 }* %"7_0", align 4 + %"7_04" = load { i1, i64 }, { i1, i64 }* %"7_0", align 4 + store { i1, i64 } %"7_04", { i1, i64 }* %"7_0", align 4 + %"7_05" = load { i1, i64 }, { i1, i64 }* %"7_0", align 4 + %2 = extractvalue { i1, i64 } %"7_05", 0 + switch i1 %2, label %3 [ + i1 true, label %5 ] -4: ; preds = %loop_body - %5 = extractvalue { i32, { i64 }, { { {} } } } %"7_05", 1 - %6 = extractvalue { i64 } %5, 0 - store i64 %6, i64* %"5_0", align 4 +3: ; preds = %loop_body + %4 = extractvalue { i1, i64 } %"7_05", 1 + store i64 %4, i64* %"5_0", align 4 br label %loop_body -7: ; preds = %loop_body - %8 = extractvalue { i32, { i64 }, { { {} } } } %"7_05", 2 - %9 = extractvalue { { {} } } %8, 0 - store { {} } %9, { {} }* %"4_0", align 1 +5: ; preds = %loop_body + store {} undef, {}* %"4_0", align 1 br label %loop_out -loop_out: ; preds = %7 - %"4_06" = load { {} }, { {} }* %"4_0", align 1 - store { {} } %"4_06", { {} }* %"0", align 1 - %"07" = load { {} }, { {} }* %"0", align 1 - ret { {} } %"07" +loop_out: ; preds = %5 + %"4_06" = load {}, {}* %"4_0", align 1 + store {} %"4_06", {}* %"0", align 1 + %"07" = load {}, {}* %"0", align 1 + ret {} %"07" } diff --git a/hugr-llvm/src/emit/test.rs b/hugr-llvm/src/emit/test.rs index 4a2627a69..5aafed0c7 100644 --- a/hugr-llvm/src/emit/test.rs +++ b/hugr-llvm/src/emit/test.rs @@ -313,7 +313,7 @@ mod test_fns { fn emit_hugr_conditional(llvm_ctx: TestContext) { let hugr = { let input_v_rows: Vec = - (0..3).map(Type::new_unit_sum).map_into().collect_vec(); + (1..4).map(Type::new_unit_sum).map_into().collect_vec(); let output_v_rows = { let mut r = input_v_rows.clone(); r.reverse(); diff --git a/hugr-llvm/src/extension/collections/array.rs b/hugr-llvm/src/extension/collections/array.rs index 0cf530e9f..66aa27f0b 100644 --- a/hugr-llvm/src/extension/collections/array.rs +++ b/hugr-llvm/src/extension/collections/array.rs @@ -21,7 +21,6 @@ use itertools::Itertools; use crate::emit::emit_value; use crate::{ emit::{deaggregate_call_result, EmitFuncContext, RowPromise}, - sum::LLVMSumType, types::{HugrType, TypingSession}, }; use crate::{CodegenExtension, CodegenExtsBuilder}; @@ -332,7 +331,7 @@ pub fn emit_array_op<'c, H: HugrView>( let TypeEnum::Sum(st) = res_hugr_ty.as_type_enum() else { Err(anyhow!("ArrayOp::get output is not a sum type"))? }; - LLVMSumType::try_new(&ts, st.clone())? + ts.llvm_sum_type(st.clone())? }; let exit_rmb = ctx.new_row_mail_box([res_hugr_ty], "")?; @@ -353,7 +352,7 @@ pub fn emit_array_op<'c, H: HugrView>( builder.build_load(elem_addr, "") })?; let success_v = res_sum_ty.build_tag(builder, 1, vec![elem_v])?; - exit_rmb.write(ctx.builder(), [success_v])?; + exit_rmb.write(ctx.builder(), [success_v.into()])?; builder.build_unconditional_branch(exit_block)?; Ok(bb) })?; @@ -362,7 +361,7 @@ pub fn emit_array_op<'c, H: HugrView>( ctx.build_positioned_new_block("", Some(success_block), |ctx, bb| { let builder = ctx.builder(); let failure_v = res_sum_ty.build_tag(builder, 0, vec![])?; - exit_rmb.write(ctx.builder(), [failure_v])?; + exit_rmb.write(ctx.builder(), [failure_v.into()])?; builder.build_unconditional_branch(exit_block)?; Ok(bb) })?; @@ -395,7 +394,7 @@ pub fn emit_array_op<'c, H: HugrView>( let TypeEnum::Sum(st) = res_hugr_ty.as_type_enum() else { Err(anyhow!("ArrayOp::set output is not a sum type"))? }; - LLVMSumType::try_new(&ts, st.clone())? + ts.llvm_sum_type(st.clone())? }; let exit_rmb = ctx.new_row_mail_box([res_hugr_ty], "")?; @@ -426,7 +425,7 @@ pub fn emit_array_op<'c, H: HugrView>( Ok((elem_v, array_v)) })?; let success_v = res_sum_ty.build_tag(builder, 1, vec![elem_v, array_v])?; - exit_rmb.write(ctx.builder(), [success_v])?; + exit_rmb.write(ctx.builder(), [success_v.into()])?; builder.build_unconditional_branch(exit_block)?; Ok(bb) })?; @@ -436,7 +435,7 @@ pub fn emit_array_op<'c, H: HugrView>( let builder = ctx.builder(); let failure_v = res_sum_ty.build_tag(builder, 0, vec![value_v, array_v.into()])?; - exit_rmb.write(ctx.builder(), [failure_v])?; + exit_rmb.write(ctx.builder(), [failure_v.into()])?; builder.build_unconditional_branch(exit_block)?; Ok(bb) })?; @@ -469,7 +468,7 @@ pub fn emit_array_op<'c, H: HugrView>( let TypeEnum::Sum(st) = res_hugr_ty.as_type_enum() else { Err(anyhow!("ArrayOp::swap output is not a sum type"))? }; - LLVMSumType::try_new(&ts, st.clone())? + ts.llvm_sum_type(st.clone())? }; let exit_rmb = ctx.new_row_mail_box([res_hugr_ty], "")?; @@ -510,7 +509,7 @@ pub fn emit_array_op<'c, H: HugrView>( builder.build_load(ptr, "") })?; let success_v = res_sum_ty.build_tag(builder, 1, vec![array_v])?; - exit_rmb.write(ctx.builder(), [success_v])?; + exit_rmb.write(ctx.builder(), [success_v.into()])?; builder.build_unconditional_branch(exit_block)?; Ok(bb) })?; @@ -519,7 +518,7 @@ pub fn emit_array_op<'c, H: HugrView>( ctx.build_positioned_new_block("", Some(success_block), |ctx, bb| { let builder = ctx.builder(); let failure_v = res_sum_ty.build_tag(builder, 0, vec![array_v.into()])?; - exit_rmb.write(ctx.builder(), [failure_v])?; + exit_rmb.write(ctx.builder(), [failure_v.into()])?; builder.build_unconditional_branch(exit_block)?; Ok(bb) })?; @@ -586,15 +585,12 @@ fn emit_pop_op<'c>( array_v: ArrayValue<'c>, pop_left: bool, ) -> Result> { - let ret_ty = LLVMSumType::try_new( - ts, - option_type(vec![ - elem_ty.clone(), - array_type(size.saturating_add_signed(-1), elem_ty), - ]), - )?; + let ret_ty = ts.llvm_sum_type(option_type(vec![ + elem_ty.clone(), + array_type(size.saturating_add_signed(-1), elem_ty), + ]))?; if size == 0 { - return ret_ty.build_tag(builder, 0, vec![]); + return Ok(ret_ty.build_tag(builder, 0, vec![])?.into()); } let ctx = builder.get_insert_block().unwrap().get_context(); let (elem_v, array_v) = with_array_alloca(builder, array_v, |ptr| { @@ -621,7 +617,7 @@ fn emit_pop_op<'c>( let array_v = builder.build_load(ptr, "")?; Ok((elem_v, array_v)) })?; - ret_ty.build_tag(builder, 1, vec![elem_v, array_v]) + Ok(ret_ty.build_tag(builder, 1, vec![elem_v, array_v])?.into()) } /// Emits an [ArrayRepeat] op. diff --git a/hugr-llvm/src/extension/collections/list.rs b/hugr-llvm/src/extension/collections/list.rs index 004209445..b19468ae0 100644 --- a/hugr-llvm/src/extension/collections/list.rs +++ b/hugr-llvm/src/extension/collections/list.rs @@ -268,7 +268,7 @@ fn emit_list_op<'c, H: HugrView>( let unit = ctx.llvm_sum_type(SumType::new_unary(1))? .build_tag(ctx.builder(), 0, vec![])?; - let ok_or = build_ok_or_else(ctx, ok, unit, Type::UNIT, elem, hugr_elem_ty)?; + let ok_or = build_ok_or_else(ctx, ok, unit.into(), Type::UNIT, elem, hugr_elem_ty)?; args.outputs.finish(ctx.builder(), vec![list, ok_or])?; } ListOp::length => { diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_all_ops@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_all_ops@llvm14.snap index 9572d943f..bc9aa19c6 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_all_ops@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_all_ops@llvm14.snap @@ -26,233 +26,213 @@ entry_block: ; preds = %alloca_block %2 = icmp ult i64 0, 2 %3 = icmp ult i64 1, 2 %4 = and i1 %2, %3 - br i1 %4, label %8, label %5 + br i1 %4, label %7, label %5 5: ; preds = %entry_block - %6 = insertvalue { [2 x i64] } undef, [2 x i64] %1, 0 - %7 = insertvalue { i32, { [2 x i64] }, { [2 x i64] } } { i32 0, { [2 x i64] } poison, { [2 x i64] } poison }, { [2 x i64] } %6, 1 - br label %19 - -8: ; preds = %entry_block - %9 = alloca i64, i32 2, align 8 - %10 = bitcast i64* %9 to [2 x i64]* - store [2 x i64] %1, [2 x i64]* %10, align 4 - %11 = getelementptr inbounds i64, i64* %9, i64 0 - %12 = load i64, i64* %11, align 4 - %13 = getelementptr inbounds i64, i64* %9, i64 1 - %14 = load i64, i64* %13, align 4 - store i64 %14, i64* %11, align 4 - store i64 %12, i64* %13, align 4 - %15 = bitcast i64* %9 to [2 x i64]* - %16 = load [2 x i64], [2 x i64]* %15, align 4 - %17 = insertvalue { [2 x i64] } undef, [2 x i64] %16, 0 - %18 = insertvalue { i32, { [2 x i64] }, { [2 x i64] } } { i32 1, { [2 x i64] } poison, { [2 x i64] } poison }, { [2 x i64] } %17, 2 - br label %19 - -19: ; preds = %5, %8 - %"0.0" = phi { i32, { [2 x i64] }, { [2 x i64] } } [ %18, %8 ], [ %7, %5 ] - %20 = extractvalue { i32, { [2 x i64] }, { [2 x i64] } } %"0.0", 0 - switch i32 %20, label %21 [ - i32 1, label %24 + %6 = insertvalue { i1, [2 x i64] } { i1 false, [2 x i64] poison }, [2 x i64] %1, 1 + br label %17 + +7: ; preds = %entry_block + %8 = alloca i64, i32 2, align 8 + %9 = bitcast i64* %8 to [2 x i64]* + store [2 x i64] %1, [2 x i64]* %9, align 4 + %10 = getelementptr inbounds i64, i64* %8, i64 0 + %11 = load i64, i64* %10, align 4 + %12 = getelementptr inbounds i64, i64* %8, i64 1 + %13 = load i64, i64* %12, align 4 + store i64 %13, i64* %10, align 4 + store i64 %11, i64* %12, align 4 + %14 = bitcast i64* %8 to [2 x i64]* + %15 = load [2 x i64], [2 x i64]* %14, align 4 + %16 = insertvalue { i1, [2 x i64] } { i1 true, [2 x i64] poison }, [2 x i64] %15, 1 + br label %17 + +17: ; preds = %5, %7 + %"0.0" = phi { i1, [2 x i64] } [ %16, %7 ], [ %6, %5 ] + %18 = extractvalue { i1, [2 x i64] } %"0.0", 0 + switch i1 %18, label %19 [ + i1 true, label %21 ] -21: ; preds = %19 - %22 = extractvalue { i32, { [2 x i64] }, { [2 x i64] } } %"0.0", 1 - %23 = extractvalue { [2 x i64] } %22, 0 +19: ; preds = %17 + %20 = extractvalue { i1, [2 x i64] } %"0.0", 1 br label %cond_16_case_0 -24: ; preds = %19 - %25 = extractvalue { i32, { [2 x i64] }, { [2 x i64] } } %"0.0", 2 - %26 = extractvalue { [2 x i64] } %25, 0 +21: ; preds = %17 + %22 = extractvalue { i1, [2 x i64] } %"0.0", 1 br label %cond_16_case_1 -cond_16_case_0: ; preds = %21 - %27 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @0, i32 0, i32 0) }, 0 - %28 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @0, i32 0, i32 0) }, 1 - %29 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template, i32 0, i32 0), i32 %27, i8* %28) +cond_16_case_0: ; preds = %19 + %23 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @0, i32 0, i32 0) }, 0 + %24 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @0, i32 0, i32 0) }, 1 + %25 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template, i32 0, i32 0), i32 %23, i8* %24) call void @abort() br label %cond_exit_16 -cond_16_case_1: ; preds = %24 +cond_16_case_1: ; preds = %21 br label %cond_exit_16 cond_exit_16: ; preds = %cond_16_case_1, %cond_16_case_0 - %"08.0" = phi [2 x i64] [ zeroinitializer, %cond_16_case_0 ], [ %26, %cond_16_case_1 ] - %30 = icmp ult i64 0, 2 - br i1 %30, label %32, label %31 - -31: ; preds = %cond_exit_16 - br label %39 - -32: ; preds = %cond_exit_16 - %33 = alloca i64, i32 2, align 8 - %34 = bitcast i64* %33 to [2 x i64]* - store [2 x i64] %"08.0", [2 x i64]* %34, align 4 - %35 = getelementptr inbounds i64, i64* %33, i64 0 - %36 = load i64, i64* %35, align 4 - %37 = insertvalue { i64 } undef, i64 %36, 0 - %38 = insertvalue { i32, {}, { i64 } } { i32 1, {} poison, { i64 } poison }, { i64 } %37, 2 - br label %39 - -39: ; preds = %31, %32 - %"020.0" = phi { i32, {}, { i64 } } [ %38, %32 ], [ { i32 0, {} undef, { i64 } poison }, %31 ] - %40 = extractvalue { i32, {}, { i64 } } %"020.0", 0 - switch i32 %40, label %41 [ - i32 1, label %43 + %"08.0" = phi [2 x i64] [ zeroinitializer, %cond_16_case_0 ], [ %22, %cond_16_case_1 ] + %26 = icmp ult i64 0, 2 + br i1 %26, label %28, label %27 + +27: ; preds = %cond_exit_16 + br label %34 + +28: ; preds = %cond_exit_16 + %29 = alloca i64, i32 2, align 8 + %30 = bitcast i64* %29 to [2 x i64]* + store [2 x i64] %"08.0", [2 x i64]* %30, align 4 + %31 = getelementptr inbounds i64, i64* %29, i64 0 + %32 = load i64, i64* %31, align 4 + %33 = insertvalue { i1, i64 } { i1 true, i64 poison }, i64 %32, 1 + br label %34 + +34: ; preds = %27, %28 + %"020.0" = phi { i1, i64 } [ %33, %28 ], [ { i1 false, i64 poison }, %27 ] + %35 = extractvalue { i1, i64 } %"020.0", 0 + switch i1 %35, label %36 [ + i1 true, label %37 ] -41: ; preds = %39 - %42 = extractvalue { i32, {}, { i64 } } %"020.0", 1 +36: ; preds = %34 br label %cond_28_case_0 -43: ; preds = %39 - %44 = extractvalue { i32, {}, { i64 } } %"020.0", 2 - %45 = extractvalue { i64 } %44, 0 +37: ; preds = %34 + %38 = extractvalue { i1, i64 } %"020.0", 1 br label %cond_28_case_1 -cond_28_case_0: ; preds = %41 - %46 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @1, i32 0, i32 0) }, 0 - %47 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @1, i32 0, i32 0) }, 1 - %48 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.1, i32 0, i32 0), i32 %46, i8* %47) +cond_28_case_0: ; preds = %36 + %39 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @1, i32 0, i32 0) }, 0 + %40 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @1, i32 0, i32 0) }, 1 + %41 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.1, i32 0, i32 0), i32 %39, i8* %40) call void @abort() br label %cond_exit_28 -cond_28_case_1: ; preds = %43 +cond_28_case_1: ; preds = %37 br label %cond_exit_28 cond_exit_28: ; preds = %cond_28_case_1, %cond_28_case_0 - %"023.0" = phi i64 [ 0, %cond_28_case_0 ], [ %45, %cond_28_case_1 ] - %49 = icmp ult i64 1, 2 - br i1 %49, label %54, label %50 - -50: ; preds = %cond_exit_28 - %51 = insertvalue { i64, [2 x i64] } undef, i64 %"023.0", 0 - %52 = insertvalue { i64, [2 x i64] } %51, [2 x i64] %"08.0", 1 - %53 = insertvalue { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } { i32 0, { i64, [2 x i64] } poison, { i64, [2 x i64] } poison }, { i64, [2 x i64] } %52, 1 - br label %64 - -54: ; preds = %cond_exit_28 - %55 = alloca i64, i32 2, align 8 - %56 = bitcast i64* %55 to [2 x i64]* - store [2 x i64] %"08.0", [2 x i64]* %56, align 4 - %57 = getelementptr inbounds i64, i64* %55, i64 1 - %58 = load i64, i64* %57, align 4 - store i64 %"023.0", i64* %57, align 4 - %59 = bitcast i64* %55 to [2 x i64]* - %60 = load [2 x i64], [2 x i64]* %59, align 4 - %61 = insertvalue { i64, [2 x i64] } undef, i64 %58, 0 - %62 = insertvalue { i64, [2 x i64] } %61, [2 x i64] %60, 1 - %63 = insertvalue { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } { i32 1, { i64, [2 x i64] } poison, { i64, [2 x i64] } poison }, { i64, [2 x i64] } %62, 2 - br label %64 - -64: ; preds = %50, %54 - %"033.0" = phi { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } [ %63, %54 ], [ %53, %50 ] - %65 = extractvalue { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } %"033.0", 0 - switch i32 %65, label %66 [ - i32 1, label %70 + %"023.0" = phi i64 [ 0, %cond_28_case_0 ], [ %38, %cond_28_case_1 ] + %42 = icmp ult i64 1, 2 + br i1 %42, label %46, label %43 + +43: ; preds = %cond_exit_28 + %44 = insertvalue { i1, i64, [2 x i64] } { i1 false, i64 poison, [2 x i64] poison }, i64 %"023.0", 1 + %45 = insertvalue { i1, i64, [2 x i64] } %44, [2 x i64] %"08.0", 2 + br label %55 + +46: ; preds = %cond_exit_28 + %47 = alloca i64, i32 2, align 8 + %48 = bitcast i64* %47 to [2 x i64]* + store [2 x i64] %"08.0", [2 x i64]* %48, align 4 + %49 = getelementptr inbounds i64, i64* %47, i64 1 + %50 = load i64, i64* %49, align 4 + store i64 %"023.0", i64* %49, align 4 + %51 = bitcast i64* %47 to [2 x i64]* + %52 = load [2 x i64], [2 x i64]* %51, align 4 + %53 = insertvalue { i1, i64, [2 x i64] } { i1 true, i64 poison, [2 x i64] poison }, i64 %50, 1 + %54 = insertvalue { i1, i64, [2 x i64] } %53, [2 x i64] %52, 2 + br label %55 + +55: ; preds = %43, %46 + %"033.0" = phi { i1, i64, [2 x i64] } [ %54, %46 ], [ %45, %43 ] + %56 = extractvalue { i1, i64, [2 x i64] } %"033.0", 0 + switch i1 %56, label %57 [ + i1 true, label %60 ] -66: ; preds = %64 - %67 = extractvalue { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } %"033.0", 1 - %68 = extractvalue { i64, [2 x i64] } %67, 0 - %69 = extractvalue { i64, [2 x i64] } %67, 1 +57: ; preds = %55 + %58 = extractvalue { i1, i64, [2 x i64] } %"033.0", 1 + %59 = extractvalue { i1, i64, [2 x i64] } %"033.0", 2 br label %cond_40_case_0 -70: ; preds = %64 - %71 = extractvalue { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } %"033.0", 2 - %72 = extractvalue { i64, [2 x i64] } %71, 0 - %73 = extractvalue { i64, [2 x i64] } %71, 1 +60: ; preds = %55 + %61 = extractvalue { i1, i64, [2 x i64] } %"033.0", 1 + %62 = extractvalue { i1, i64, [2 x i64] } %"033.0", 2 br label %cond_40_case_1 -cond_40_case_0: ; preds = %66 - %74 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @2, i32 0, i32 0) }, 0 - %75 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @2, i32 0, i32 0) }, 1 - %76 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.2, i32 0, i32 0), i32 %74, i8* %75) +cond_40_case_0: ; preds = %57 + %63 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @2, i32 0, i32 0) }, 0 + %64 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @2, i32 0, i32 0) }, 1 + %65 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.2, i32 0, i32 0), i32 %63, i8* %64) call void @abort() br label %cond_exit_40 -cond_40_case_1: ; preds = %70 +cond_40_case_1: ; preds = %60 br label %cond_exit_40 cond_exit_40: ; preds = %cond_40_case_1, %cond_40_case_0 - %"036.0" = phi i64 [ 0, %cond_40_case_0 ], [ %72, %cond_40_case_1 ] - %"1.0" = phi [2 x i64] [ zeroinitializer, %cond_40_case_0 ], [ %73, %cond_40_case_1 ] - %77 = alloca i64, i32 2, align 8 - %78 = bitcast i64* %77 to [2 x i64]* - store [2 x i64] %"1.0", [2 x i64]* %78, align 4 - %79 = getelementptr i64, i64* %77, i32 1 - %80 = load i64, i64* %77, align 4 - %81 = bitcast i64* %79 to [1 x i64]* - %82 = load [1 x i64], [1 x i64]* %81, align 4 - %83 = insertvalue { i64, [1 x i64] } undef, i64 %80, 0 - %84 = insertvalue { i64, [1 x i64] } %83, [1 x i64] %82, 1 - %85 = insertvalue { i32, {}, { i64, [1 x i64] } } { i32 1, {} poison, { i64, [1 x i64] } poison }, { i64, [1 x i64] } %84, 2 - %86 = extractvalue { i32, {}, { i64, [1 x i64] } } %85, 0 - switch i32 %86, label %87 [ - i32 1, label %89 + %"036.0" = phi i64 [ 0, %cond_40_case_0 ], [ %61, %cond_40_case_1 ] + %"1.0" = phi [2 x i64] [ zeroinitializer, %cond_40_case_0 ], [ %62, %cond_40_case_1 ] + %66 = alloca i64, i32 2, align 8 + %67 = bitcast i64* %66 to [2 x i64]* + store [2 x i64] %"1.0", [2 x i64]* %67, align 4 + %68 = getelementptr i64, i64* %66, i32 1 + %69 = load i64, i64* %66, align 4 + %70 = bitcast i64* %68 to [1 x i64]* + %71 = load [1 x i64], [1 x i64]* %70, align 4 + %72 = insertvalue { i1, i64, [1 x i64] } { i1 true, i64 poison, [1 x i64] poison }, i64 %69, 1 + %73 = insertvalue { i1, i64, [1 x i64] } %72, [1 x i64] %71, 2 + %74 = extractvalue { i1, i64, [1 x i64] } %73, 0 + switch i1 %74, label %75 [ + i1 true, label %76 ] -87: ; preds = %cond_exit_40 - %88 = extractvalue { i32, {}, { i64, [1 x i64] } } %85, 1 +75: ; preds = %cond_exit_40 br label %cond_51_case_0 -89: ; preds = %cond_exit_40 - %90 = extractvalue { i32, {}, { i64, [1 x i64] } } %85, 2 - %91 = extractvalue { i64, [1 x i64] } %90, 0 - %92 = extractvalue { i64, [1 x i64] } %90, 1 +76: ; preds = %cond_exit_40 + %77 = extractvalue { i1, i64, [1 x i64] } %73, 1 + %78 = extractvalue { i1, i64, [1 x i64] } %73, 2 br label %cond_51_case_1 -cond_51_case_0: ; preds = %87 - %93 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @3, i32 0, i32 0) }, 0 - %94 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @3, i32 0, i32 0) }, 1 - %95 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.3, i32 0, i32 0), i32 %93, i8* %94) +cond_51_case_0: ; preds = %75 + %79 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @3, i32 0, i32 0) }, 0 + %80 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @3, i32 0, i32 0) }, 1 + %81 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.3, i32 0, i32 0), i32 %79, i8* %80) call void @abort() br label %cond_exit_51 -cond_51_case_1: ; preds = %89 +cond_51_case_1: ; preds = %76 br label %cond_exit_51 cond_exit_51: ; preds = %cond_51_case_1, %cond_51_case_0 - %"056.0" = phi i64 [ 0, %cond_51_case_0 ], [ %91, %cond_51_case_1 ] - %"157.0" = phi [1 x i64] [ zeroinitializer, %cond_51_case_0 ], [ %92, %cond_51_case_1 ] - %96 = alloca i64, align 8 - %97 = bitcast i64* %96 to [1 x i64]* - store [1 x i64] %"157.0", [1 x i64]* %97, align 4 - %98 = getelementptr i64, i64* %96, i32 0 - %99 = load i64, i64* %98, align 4 - %100 = bitcast i64* %96 to [0 x i64]* - %101 = load [0 x i64], [0 x i64]* %100, align 4 - %102 = insertvalue { i64, [0 x i64] } undef, i64 %99, 0 - %103 = insertvalue { i64, [0 x i64] } %102, [0 x i64] %101, 1 - %104 = insertvalue { i32, {}, { i64, [0 x i64] } } { i32 1, {} poison, { i64, [0 x i64] } poison }, { i64, [0 x i64] } %103, 2 - %105 = extractvalue { i32, {}, { i64, [0 x i64] } } %104, 0 - switch i32 %105, label %106 [ - i32 1, label %108 + %"056.0" = phi i64 [ 0, %cond_51_case_0 ], [ %77, %cond_51_case_1 ] + %"157.0" = phi [1 x i64] [ zeroinitializer, %cond_51_case_0 ], [ %78, %cond_51_case_1 ] + %82 = alloca i64, align 8 + %83 = bitcast i64* %82 to [1 x i64]* + store [1 x i64] %"157.0", [1 x i64]* %83, align 4 + %84 = getelementptr i64, i64* %82, i32 0 + %85 = load i64, i64* %84, align 4 + %86 = bitcast i64* %82 to [0 x i64]* + %87 = load [0 x i64], [0 x i64]* %86, align 4 + %88 = insertvalue { i1, i64 } { i1 true, i64 poison }, i64 %85, 1 + %89 = extractvalue { i1, i64 } %88, 0 + switch i1 %89, label %90 [ + i1 true, label %91 ] -106: ; preds = %cond_exit_51 - %107 = extractvalue { i32, {}, { i64, [0 x i64] } } %104, 1 +90: ; preds = %cond_exit_51 br label %cond_62_case_0 -108: ; preds = %cond_exit_51 - %109 = extractvalue { i32, {}, { i64, [0 x i64] } } %104, 2 - %110 = extractvalue { i64, [0 x i64] } %109, 0 - %111 = extractvalue { i64, [0 x i64] } %109, 1 +91: ; preds = %cond_exit_51 + %92 = extractvalue { i1, i64 } %88, 1 br label %cond_62_case_1 -cond_62_case_0: ; preds = %106 - %112 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @4, i32 0, i32 0) }, 0 - %113 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @4, i32 0, i32 0) }, 1 - %114 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.4, i32 0, i32 0), i32 %112, i8* %113) +cond_62_case_0: ; preds = %90 + %93 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @4, i32 0, i32 0) }, 0 + %94 = extractvalue { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @4, i32 0, i32 0) }, 1 + %95 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.4, i32 0, i32 0), i32 %93, i8* %94) call void @abort() br label %cond_exit_62 -cond_62_case_1: ; preds = %108 +cond_62_case_1: ; preds = %91 br label %cond_exit_62 cond_exit_62: ; preds = %cond_62_case_1, %cond_62_case_0 - %"071.0" = phi i64 [ 0, %cond_62_case_0 ], [ %110, %cond_62_case_1 ] - %"172.0" = phi [0 x i64] [ zeroinitializer, %cond_62_case_0 ], [ %111, %cond_62_case_1 ] + %"071.0" = phi i64 [ 0, %cond_62_case_0 ], [ %92, %cond_62_case_1 ] ret void } diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_all_ops@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_all_ops@pre-mem2reg@llvm14.snap index b883f160a..9b294486d 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_all_ops@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_all_ops@pre-mem2reg@llvm14.snap @@ -22,8 +22,8 @@ alloca_block: %"10_0" = alloca i64, align 8 %"13_0" = alloca [2 x i64], align 8 %"8_0" = alloca i64, align 8 - %"14_0" = alloca { i32, { [2 x i64] }, { [2 x i64] } }, align 8 - %"0" = alloca { i32, { [2 x i64] }, { [2 x i64] } }, align 8 + %"14_0" = alloca { i1, [2 x i64] }, align 8 + %"0" = alloca { i1, [2 x i64] }, align 8 %"16_0" = alloca [2 x i64], align 8 %"08" = alloca [2 x i64], align 8 %"010" = alloca [2 x i64], align 8 @@ -32,16 +32,16 @@ alloca_block: %"22_0" = alloca [2 x i64], align 8 %"015" = alloca [2 x i64], align 8 %"24_0" = alloca [2 x i64], align 8 - %"26_0" = alloca { i32, {}, { i64 } }, align 8 - %"020" = alloca { i32, {}, { i64 } }, align 8 + %"26_0" = alloca { i1, i64 }, align 8 + %"020" = alloca { i1, i64 }, align 8 %"28_0" = alloca i64, align 8 %"023" = alloca i64, align 8 %"33_0" = alloca { i32, i8* }, align 8 %"34_0" = alloca i64, align 8 %"027" = alloca i64, align 8 %"36_0" = alloca i64, align 8 - %"38_0" = alloca { i32, { i64, [2 x i64] }, { i64, [2 x i64] } }, align 8 - %"033" = alloca { i32, { i64, [2 x i64] }, { i64, [2 x i64] } }, align 8 + %"38_0" = alloca { i1, i64, [2 x i64] }, align 8 + %"033" = alloca { i1, i64, [2 x i64] }, align 8 %"40_0" = alloca i64, align 8 %"40_1" = alloca [2 x i64], align 8 %"036" = alloca i64, align 8 @@ -57,7 +57,7 @@ alloca_block: %"149" = alloca [2 x i64], align 8 %"48_0" = alloca i64, align 8 %"48_1" = alloca [2 x i64], align 8 - %"50_0" = alloca { i32, {}, { i64, [1 x i64] } }, align 8 + %"50_0" = alloca { i1, i64, [1 x i64] }, align 8 %"51_0" = alloca i64, align 8 %"51_1" = alloca [1 x i64], align 8 %"056" = alloca i64, align 8 @@ -69,7 +69,7 @@ alloca_block: %"164" = alloca [1 x i64], align 8 %"59_0" = alloca i64, align 8 %"59_1" = alloca [1 x i64], align 8 - %"61_0" = alloca { i32, {}, { i64, [0 x i64] } }, align 8 + %"61_0" = alloca { i1, i64 }, align 8 %"62_0" = alloca i64, align 8 %"62_1" = alloca [0 x i64], align 8 %"071" = alloca i64, align 8 @@ -98,68 +98,64 @@ entry_block: ; preds = %alloca_block %2 = icmp ult i64 %"8_04", 2 %3 = icmp ult i64 %"10_05", 2 %4 = and i1 %2, %3 - br i1 %4, label %8, label %5 + br i1 %4, label %7, label %5 5: ; preds = %entry_block - %6 = insertvalue { [2 x i64] } undef, [2 x i64] %"13_03", 0 - %7 = insertvalue { i32, { [2 x i64] }, { [2 x i64] } } { i32 0, { [2 x i64] } poison, { [2 x i64] } poison }, { [2 x i64] } %6, 1 - store { i32, { [2 x i64] }, { [2 x i64] } } %7, { i32, { [2 x i64] }, { [2 x i64] } }* %"0", align 4 - br label %19 - -8: ; preds = %entry_block - %9 = alloca i64, i32 2, align 8 - %10 = bitcast i64* %9 to [2 x i64]* - store [2 x i64] %"13_03", [2 x i64]* %10, align 4 - %11 = getelementptr inbounds i64, i64* %9, i64 %"8_04" - %12 = load i64, i64* %11, align 4 - %13 = getelementptr inbounds i64, i64* %9, i64 %"10_05" - %14 = load i64, i64* %13, align 4 - store i64 %14, i64* %11, align 4 - store i64 %12, i64* %13, align 4 - %15 = bitcast i64* %9 to [2 x i64]* - %16 = load [2 x i64], [2 x i64]* %15, align 4 - %17 = insertvalue { [2 x i64] } undef, [2 x i64] %16, 0 - %18 = insertvalue { i32, { [2 x i64] }, { [2 x i64] } } { i32 1, { [2 x i64] } poison, { [2 x i64] } poison }, { [2 x i64] } %17, 2 - store { i32, { [2 x i64] }, { [2 x i64] } } %18, { i32, { [2 x i64] }, { [2 x i64] } }* %"0", align 4 - br label %19 - -19: ; preds = %5, %8 - %"06" = load { i32, { [2 x i64] }, { [2 x i64] } }, { i32, { [2 x i64] }, { [2 x i64] } }* %"0", align 4 - store { i32, { [2 x i64] }, { [2 x i64] } } %"06", { i32, { [2 x i64] }, { [2 x i64] } }* %"14_0", align 4 - %"14_07" = load { i32, { [2 x i64] }, { [2 x i64] } }, { i32, { [2 x i64] }, { [2 x i64] } }* %"14_0", align 4 - %20 = extractvalue { i32, { [2 x i64] }, { [2 x i64] } } %"14_07", 0 - switch i32 %20, label %21 [ - i32 1, label %24 + %6 = insertvalue { i1, [2 x i64] } { i1 false, [2 x i64] poison }, [2 x i64] %"13_03", 1 + store { i1, [2 x i64] } %6, { i1, [2 x i64] }* %"0", align 4 + br label %17 + +7: ; preds = %entry_block + %8 = alloca i64, i32 2, align 8 + %9 = bitcast i64* %8 to [2 x i64]* + store [2 x i64] %"13_03", [2 x i64]* %9, align 4 + %10 = getelementptr inbounds i64, i64* %8, i64 %"8_04" + %11 = load i64, i64* %10, align 4 + %12 = getelementptr inbounds i64, i64* %8, i64 %"10_05" + %13 = load i64, i64* %12, align 4 + store i64 %13, i64* %10, align 4 + store i64 %11, i64* %12, align 4 + %14 = bitcast i64* %8 to [2 x i64]* + %15 = load [2 x i64], [2 x i64]* %14, align 4 + %16 = insertvalue { i1, [2 x i64] } { i1 true, [2 x i64] poison }, [2 x i64] %15, 1 + store { i1, [2 x i64] } %16, { i1, [2 x i64] }* %"0", align 4 + br label %17 + +17: ; preds = %5, %7 + %"06" = load { i1, [2 x i64] }, { i1, [2 x i64] }* %"0", align 4 + store { i1, [2 x i64] } %"06", { i1, [2 x i64] }* %"14_0", align 4 + %"14_07" = load { i1, [2 x i64] }, { i1, [2 x i64] }* %"14_0", align 4 + %18 = extractvalue { i1, [2 x i64] } %"14_07", 0 + switch i1 %18, label %19 [ + i1 true, label %21 ] -21: ; preds = %19 - %22 = extractvalue { i32, { [2 x i64] }, { [2 x i64] } } %"14_07", 1 - %23 = extractvalue { [2 x i64] } %22, 0 - store [2 x i64] %23, [2 x i64]* %"010", align 4 +19: ; preds = %17 + %20 = extractvalue { i1, [2 x i64] } %"14_07", 1 + store [2 x i64] %20, [2 x i64]* %"010", align 4 br label %cond_16_case_0 -24: ; preds = %19 - %25 = extractvalue { i32, { [2 x i64] }, { [2 x i64] } } %"14_07", 2 - %26 = extractvalue { [2 x i64] } %25, 0 - store [2 x i64] %26, [2 x i64]* %"015", align 4 +21: ; preds = %17 + %22 = extractvalue { i1, [2 x i64] } %"14_07", 1 + store [2 x i64] %22, [2 x i64]* %"015", align 4 br label %cond_16_case_1 -cond_16_case_0: ; preds = %21 +cond_16_case_0: ; preds = %19 %"011" = load [2 x i64], [2 x i64]* %"010", align 4 store { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @0, i32 0, i32 0) }, { i32, i8* }* %"21_0", align 8 store [2 x i64] %"011", [2 x i64]* %"18_0", align 4 %"21_012" = load { i32, i8* }, { i32, i8* }* %"21_0", align 8 %"18_013" = load [2 x i64], [2 x i64]* %"18_0", align 4 - %27 = extractvalue { i32, i8* } %"21_012", 0 - %28 = extractvalue { i32, i8* } %"21_012", 1 - %29 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template, i32 0, i32 0), i32 %27, i8* %28) + %23 = extractvalue { i32, i8* } %"21_012", 0 + %24 = extractvalue { i32, i8* } %"21_012", 1 + %25 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template, i32 0, i32 0), i32 %23, i8* %24) call void @abort() store [2 x i64] zeroinitializer, [2 x i64]* %"22_0", align 4 %"22_014" = load [2 x i64], [2 x i64]* %"22_0", align 4 store [2 x i64] %"22_014", [2 x i64]* %"08", align 4 br label %cond_exit_16 -cond_16_case_1: ; preds = %24 +cond_16_case_1: ; preds = %21 %"016" = load [2 x i64], [2 x i64]* %"015", align 4 store [2 x i64] %"016", [2 x i64]* %"24_0", align 4 %"24_017" = load [2 x i64], [2 x i64]* %"24_0", align 4 @@ -171,56 +167,53 @@ cond_exit_16: ; preds = %cond_16_case_1, %co store [2 x i64] %"09", [2 x i64]* %"16_0", align 4 %"16_018" = load [2 x i64], [2 x i64]* %"16_0", align 4 %"8_019" = load i64, i64* %"8_0", align 4 - %30 = icmp ult i64 %"8_019", 2 - br i1 %30, label %32, label %31 - -31: ; preds = %cond_exit_16 - store { i32, {}, { i64 } } { i32 0, {} undef, { i64 } poison }, { i32, {}, { i64 } }* %"020", align 4 - br label %39 - -32: ; preds = %cond_exit_16 - %33 = alloca i64, i32 2, align 8 - %34 = bitcast i64* %33 to [2 x i64]* - store [2 x i64] %"16_018", [2 x i64]* %34, align 4 - %35 = getelementptr inbounds i64, i64* %33, i64 %"8_019" - %36 = load i64, i64* %35, align 4 - %37 = insertvalue { i64 } undef, i64 %36, 0 - %38 = insertvalue { i32, {}, { i64 } } { i32 1, {} poison, { i64 } poison }, { i64 } %37, 2 - store { i32, {}, { i64 } } %38, { i32, {}, { i64 } }* %"020", align 4 - br label %39 - -39: ; preds = %31, %32 - %"021" = load { i32, {}, { i64 } }, { i32, {}, { i64 } }* %"020", align 4 - store { i32, {}, { i64 } } %"021", { i32, {}, { i64 } }* %"26_0", align 4 - %"26_022" = load { i32, {}, { i64 } }, { i32, {}, { i64 } }* %"26_0", align 4 - %40 = extractvalue { i32, {}, { i64 } } %"26_022", 0 - switch i32 %40, label %41 [ - i32 1, label %43 + %26 = icmp ult i64 %"8_019", 2 + br i1 %26, label %28, label %27 + +27: ; preds = %cond_exit_16 + store { i1, i64 } { i1 false, i64 poison }, { i1, i64 }* %"020", align 4 + br label %34 + +28: ; preds = %cond_exit_16 + %29 = alloca i64, i32 2, align 8 + %30 = bitcast i64* %29 to [2 x i64]* + store [2 x i64] %"16_018", [2 x i64]* %30, align 4 + %31 = getelementptr inbounds i64, i64* %29, i64 %"8_019" + %32 = load i64, i64* %31, align 4 + %33 = insertvalue { i1, i64 } { i1 true, i64 poison }, i64 %32, 1 + store { i1, i64 } %33, { i1, i64 }* %"020", align 4 + br label %34 + +34: ; preds = %27, %28 + %"021" = load { i1, i64 }, { i1, i64 }* %"020", align 4 + store { i1, i64 } %"021", { i1, i64 }* %"26_0", align 4 + %"26_022" = load { i1, i64 }, { i1, i64 }* %"26_0", align 4 + %35 = extractvalue { i1, i64 } %"26_022", 0 + switch i1 %35, label %36 [ + i1 true, label %37 ] -41: ; preds = %39 - %42 = extractvalue { i32, {}, { i64 } } %"26_022", 1 +36: ; preds = %34 br label %cond_28_case_0 -43: ; preds = %39 - %44 = extractvalue { i32, {}, { i64 } } %"26_022", 2 - %45 = extractvalue { i64 } %44, 0 - store i64 %45, i64* %"027", align 4 +37: ; preds = %34 + %38 = extractvalue { i1, i64 } %"26_022", 1 + store i64 %38, i64* %"027", align 4 br label %cond_28_case_1 -cond_28_case_0: ; preds = %41 +cond_28_case_0: ; preds = %36 store { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @1, i32 0, i32 0) }, { i32, i8* }* %"33_0", align 8 %"33_025" = load { i32, i8* }, { i32, i8* }* %"33_0", align 8 - %46 = extractvalue { i32, i8* } %"33_025", 0 - %47 = extractvalue { i32, i8* } %"33_025", 1 - %48 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.1, i32 0, i32 0), i32 %46, i8* %47) + %39 = extractvalue { i32, i8* } %"33_025", 0 + %40 = extractvalue { i32, i8* } %"33_025", 1 + %41 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.1, i32 0, i32 0), i32 %39, i8* %40) call void @abort() store i64 0, i64* %"34_0", align 4 %"34_026" = load i64, i64* %"34_0", align 4 store i64 %"34_026", i64* %"023", align 4 br label %cond_exit_28 -cond_28_case_1: ; preds = %43 +cond_28_case_1: ; preds = %37 %"028" = load i64, i64* %"027", align 4 store i64 %"028", i64* %"36_0", align 4 %"36_029" = load i64, i64* %"36_0", align 4 @@ -233,57 +226,53 @@ cond_exit_28: ; preds = %cond_28_case_1, %co %"16_030" = load [2 x i64], [2 x i64]* %"16_0", align 4 %"10_031" = load i64, i64* %"10_0", align 4 %"28_032" = load i64, i64* %"28_0", align 4 - %49 = icmp ult i64 %"10_031", 2 - br i1 %49, label %54, label %50 - -50: ; preds = %cond_exit_28 - %51 = insertvalue { i64, [2 x i64] } undef, i64 %"28_032", 0 - %52 = insertvalue { i64, [2 x i64] } %51, [2 x i64] %"16_030", 1 - %53 = insertvalue { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } { i32 0, { i64, [2 x i64] } poison, { i64, [2 x i64] } poison }, { i64, [2 x i64] } %52, 1 - store { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } %53, { i32, { i64, [2 x i64] }, { i64, [2 x i64] } }* %"033", align 4 - br label %64 - -54: ; preds = %cond_exit_28 - %55 = alloca i64, i32 2, align 8 - %56 = bitcast i64* %55 to [2 x i64]* - store [2 x i64] %"16_030", [2 x i64]* %56, align 4 - %57 = getelementptr inbounds i64, i64* %55, i64 %"10_031" - %58 = load i64, i64* %57, align 4 - store i64 %"28_032", i64* %57, align 4 - %59 = bitcast i64* %55 to [2 x i64]* - %60 = load [2 x i64], [2 x i64]* %59, align 4 - %61 = insertvalue { i64, [2 x i64] } undef, i64 %58, 0 - %62 = insertvalue { i64, [2 x i64] } %61, [2 x i64] %60, 1 - %63 = insertvalue { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } { i32 1, { i64, [2 x i64] } poison, { i64, [2 x i64] } poison }, { i64, [2 x i64] } %62, 2 - store { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } %63, { i32, { i64, [2 x i64] }, { i64, [2 x i64] } }* %"033", align 4 - br label %64 - -64: ; preds = %50, %54 - %"034" = load { i32, { i64, [2 x i64] }, { i64, [2 x i64] } }, { i32, { i64, [2 x i64] }, { i64, [2 x i64] } }* %"033", align 4 - store { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } %"034", { i32, { i64, [2 x i64] }, { i64, [2 x i64] } }* %"38_0", align 4 - %"38_035" = load { i32, { i64, [2 x i64] }, { i64, [2 x i64] } }, { i32, { i64, [2 x i64] }, { i64, [2 x i64] } }* %"38_0", align 4 - %65 = extractvalue { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } %"38_035", 0 - switch i32 %65, label %66 [ - i32 1, label %70 + %42 = icmp ult i64 %"10_031", 2 + br i1 %42, label %46, label %43 + +43: ; preds = %cond_exit_28 + %44 = insertvalue { i1, i64, [2 x i64] } { i1 false, i64 poison, [2 x i64] poison }, i64 %"28_032", 1 + %45 = insertvalue { i1, i64, [2 x i64] } %44, [2 x i64] %"16_030", 2 + store { i1, i64, [2 x i64] } %45, { i1, i64, [2 x i64] }* %"033", align 4 + br label %55 + +46: ; preds = %cond_exit_28 + %47 = alloca i64, i32 2, align 8 + %48 = bitcast i64* %47 to [2 x i64]* + store [2 x i64] %"16_030", [2 x i64]* %48, align 4 + %49 = getelementptr inbounds i64, i64* %47, i64 %"10_031" + %50 = load i64, i64* %49, align 4 + store i64 %"28_032", i64* %49, align 4 + %51 = bitcast i64* %47 to [2 x i64]* + %52 = load [2 x i64], [2 x i64]* %51, align 4 + %53 = insertvalue { i1, i64, [2 x i64] } { i1 true, i64 poison, [2 x i64] poison }, i64 %50, 1 + %54 = insertvalue { i1, i64, [2 x i64] } %53, [2 x i64] %52, 2 + store { i1, i64, [2 x i64] } %54, { i1, i64, [2 x i64] }* %"033", align 4 + br label %55 + +55: ; preds = %43, %46 + %"034" = load { i1, i64, [2 x i64] }, { i1, i64, [2 x i64] }* %"033", align 4 + store { i1, i64, [2 x i64] } %"034", { i1, i64, [2 x i64] }* %"38_0", align 4 + %"38_035" = load { i1, i64, [2 x i64] }, { i1, i64, [2 x i64] }* %"38_0", align 4 + %56 = extractvalue { i1, i64, [2 x i64] } %"38_035", 0 + switch i1 %56, label %57 [ + i1 true, label %60 ] -66: ; preds = %64 - %67 = extractvalue { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } %"38_035", 1 - %68 = extractvalue { i64, [2 x i64] } %67, 0 - %69 = extractvalue { i64, [2 x i64] } %67, 1 - store i64 %68, i64* %"039", align 4 - store [2 x i64] %69, [2 x i64]* %"140", align 4 +57: ; preds = %55 + %58 = extractvalue { i1, i64, [2 x i64] } %"38_035", 1 + %59 = extractvalue { i1, i64, [2 x i64] } %"38_035", 2 + store i64 %58, i64* %"039", align 4 + store [2 x i64] %59, [2 x i64]* %"140", align 4 br label %cond_40_case_0 -70: ; preds = %64 - %71 = extractvalue { i32, { i64, [2 x i64] }, { i64, [2 x i64] } } %"38_035", 2 - %72 = extractvalue { i64, [2 x i64] } %71, 0 - %73 = extractvalue { i64, [2 x i64] } %71, 1 - store i64 %72, i64* %"048", align 4 - store [2 x i64] %73, [2 x i64]* %"149", align 4 +60: ; preds = %55 + %61 = extractvalue { i1, i64, [2 x i64] } %"38_035", 1 + %62 = extractvalue { i1, i64, [2 x i64] } %"38_035", 2 + store i64 %61, i64* %"048", align 4 + store [2 x i64] %62, [2 x i64]* %"149", align 4 br label %cond_40_case_1 -cond_40_case_0: ; preds = %66 +cond_40_case_0: ; preds = %57 %"041" = load i64, i64* %"039", align 4 %"142" = load [2 x i64], [2 x i64]* %"140", align 4 store { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @2, i32 0, i32 0) }, { i32, i8* }* %"45_0", align 8 @@ -292,9 +281,9 @@ cond_40_case_0: ; preds = %66 %"45_043" = load { i32, i8* }, { i32, i8* }* %"45_0", align 8 %"42_044" = load i64, i64* %"42_0", align 4 %"42_145" = load [2 x i64], [2 x i64]* %"42_1", align 4 - %74 = extractvalue { i32, i8* } %"45_043", 0 - %75 = extractvalue { i32, i8* } %"45_043", 1 - %76 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.2, i32 0, i32 0), i32 %74, i8* %75) + %63 = extractvalue { i32, i8* } %"45_043", 0 + %64 = extractvalue { i32, i8* } %"45_043", 1 + %65 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.2, i32 0, i32 0), i32 %63, i8* %64) call void @abort() store i64 0, i64* %"46_0", align 4 store [2 x i64] zeroinitializer, [2 x i64]* %"46_1", align 4 @@ -304,7 +293,7 @@ cond_40_case_0: ; preds = %66 store [2 x i64] %"46_147", [2 x i64]* %"1", align 4 br label %cond_exit_40 -cond_40_case_1: ; preds = %70 +cond_40_case_1: ; preds = %60 %"050" = load i64, i64* %"048", align 4 %"151" = load [2 x i64], [2 x i64]* %"149", align 4 store i64 %"050", i64* %"48_0", align 4 @@ -321,41 +310,38 @@ cond_exit_40: ; preds = %cond_40_case_1, %co store i64 %"037", i64* %"40_0", align 4 store [2 x i64] %"138", [2 x i64]* %"40_1", align 4 %"40_154" = load [2 x i64], [2 x i64]* %"40_1", align 4 - %77 = alloca i64, i32 2, align 8 - %78 = bitcast i64* %77 to [2 x i64]* - store [2 x i64] %"40_154", [2 x i64]* %78, align 4 - %79 = getelementptr i64, i64* %77, i32 1 - %80 = load i64, i64* %77, align 4 - %81 = bitcast i64* %79 to [1 x i64]* - %82 = load [1 x i64], [1 x i64]* %81, align 4 - %83 = insertvalue { i64, [1 x i64] } undef, i64 %80, 0 - %84 = insertvalue { i64, [1 x i64] } %83, [1 x i64] %82, 1 - %85 = insertvalue { i32, {}, { i64, [1 x i64] } } { i32 1, {} poison, { i64, [1 x i64] } poison }, { i64, [1 x i64] } %84, 2 - store { i32, {}, { i64, [1 x i64] } } %85, { i32, {}, { i64, [1 x i64] } }* %"50_0", align 4 - %"50_055" = load { i32, {}, { i64, [1 x i64] } }, { i32, {}, { i64, [1 x i64] } }* %"50_0", align 4 - %86 = extractvalue { i32, {}, { i64, [1 x i64] } } %"50_055", 0 - switch i32 %86, label %87 [ - i32 1, label %89 + %66 = alloca i64, i32 2, align 8 + %67 = bitcast i64* %66 to [2 x i64]* + store [2 x i64] %"40_154", [2 x i64]* %67, align 4 + %68 = getelementptr i64, i64* %66, i32 1 + %69 = load i64, i64* %66, align 4 + %70 = bitcast i64* %68 to [1 x i64]* + %71 = load [1 x i64], [1 x i64]* %70, align 4 + %72 = insertvalue { i1, i64, [1 x i64] } { i1 true, i64 poison, [1 x i64] poison }, i64 %69, 1 + %73 = insertvalue { i1, i64, [1 x i64] } %72, [1 x i64] %71, 2 + store { i1, i64, [1 x i64] } %73, { i1, i64, [1 x i64] }* %"50_0", align 4 + %"50_055" = load { i1, i64, [1 x i64] }, { i1, i64, [1 x i64] }* %"50_0", align 4 + %74 = extractvalue { i1, i64, [1 x i64] } %"50_055", 0 + switch i1 %74, label %75 [ + i1 true, label %76 ] -87: ; preds = %cond_exit_40 - %88 = extractvalue { i32, {}, { i64, [1 x i64] } } %"50_055", 1 +75: ; preds = %cond_exit_40 br label %cond_51_case_0 -89: ; preds = %cond_exit_40 - %90 = extractvalue { i32, {}, { i64, [1 x i64] } } %"50_055", 2 - %91 = extractvalue { i64, [1 x i64] } %90, 0 - %92 = extractvalue { i64, [1 x i64] } %90, 1 - store i64 %91, i64* %"063", align 4 - store [1 x i64] %92, [1 x i64]* %"164", align 4 +76: ; preds = %cond_exit_40 + %77 = extractvalue { i1, i64, [1 x i64] } %"50_055", 1 + %78 = extractvalue { i1, i64, [1 x i64] } %"50_055", 2 + store i64 %77, i64* %"063", align 4 + store [1 x i64] %78, [1 x i64]* %"164", align 4 br label %cond_51_case_1 -cond_51_case_0: ; preds = %87 +cond_51_case_0: ; preds = %75 store { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @3, i32 0, i32 0) }, { i32, i8* }* %"56_0", align 8 %"56_060" = load { i32, i8* }, { i32, i8* }* %"56_0", align 8 - %93 = extractvalue { i32, i8* } %"56_060", 0 - %94 = extractvalue { i32, i8* } %"56_060", 1 - %95 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.3, i32 0, i32 0), i32 %93, i8* %94) + %79 = extractvalue { i32, i8* } %"56_060", 0 + %80 = extractvalue { i32, i8* } %"56_060", 1 + %81 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.3, i32 0, i32 0), i32 %79, i8* %80) call void @abort() store i64 0, i64* %"57_0", align 4 store [1 x i64] zeroinitializer, [1 x i64]* %"57_1", align 4 @@ -365,7 +351,7 @@ cond_51_case_0: ; preds = %87 store [1 x i64] %"57_162", [1 x i64]* %"157", align 4 br label %cond_exit_51 -cond_51_case_1: ; preds = %89 +cond_51_case_1: ; preds = %76 %"065" = load i64, i64* %"063", align 4 %"166" = load [1 x i64], [1 x i64]* %"164", align 4 store i64 %"065", i64* %"59_0", align 4 @@ -382,41 +368,36 @@ cond_exit_51: ; preds = %cond_51_case_1, %co store i64 %"058", i64* %"51_0", align 4 store [1 x i64] %"159", [1 x i64]* %"51_1", align 4 %"51_169" = load [1 x i64], [1 x i64]* %"51_1", align 4 - %96 = alloca i64, align 8 - %97 = bitcast i64* %96 to [1 x i64]* - store [1 x i64] %"51_169", [1 x i64]* %97, align 4 - %98 = getelementptr i64, i64* %96, i32 0 - %99 = load i64, i64* %98, align 4 - %100 = bitcast i64* %96 to [0 x i64]* - %101 = load [0 x i64], [0 x i64]* %100, align 4 - %102 = insertvalue { i64, [0 x i64] } undef, i64 %99, 0 - %103 = insertvalue { i64, [0 x i64] } %102, [0 x i64] %101, 1 - %104 = insertvalue { i32, {}, { i64, [0 x i64] } } { i32 1, {} poison, { i64, [0 x i64] } poison }, { i64, [0 x i64] } %103, 2 - store { i32, {}, { i64, [0 x i64] } } %104, { i32, {}, { i64, [0 x i64] } }* %"61_0", align 4 - %"61_070" = load { i32, {}, { i64, [0 x i64] } }, { i32, {}, { i64, [0 x i64] } }* %"61_0", align 4 - %105 = extractvalue { i32, {}, { i64, [0 x i64] } } %"61_070", 0 - switch i32 %105, label %106 [ - i32 1, label %108 + %82 = alloca i64, align 8 + %83 = bitcast i64* %82 to [1 x i64]* + store [1 x i64] %"51_169", [1 x i64]* %83, align 4 + %84 = getelementptr i64, i64* %82, i32 0 + %85 = load i64, i64* %84, align 4 + %86 = bitcast i64* %82 to [0 x i64]* + %87 = load [0 x i64], [0 x i64]* %86, align 4 + %88 = insertvalue { i1, i64 } { i1 true, i64 poison }, i64 %85, 1 + store { i1, i64 } %88, { i1, i64 }* %"61_0", align 4 + %"61_070" = load { i1, i64 }, { i1, i64 }* %"61_0", align 4 + %89 = extractvalue { i1, i64 } %"61_070", 0 + switch i1 %89, label %90 [ + i1 true, label %91 ] -106: ; preds = %cond_exit_51 - %107 = extractvalue { i32, {}, { i64, [0 x i64] } } %"61_070", 1 +90: ; preds = %cond_exit_51 br label %cond_62_case_0 -108: ; preds = %cond_exit_51 - %109 = extractvalue { i32, {}, { i64, [0 x i64] } } %"61_070", 2 - %110 = extractvalue { i64, [0 x i64] } %109, 0 - %111 = extractvalue { i64, [0 x i64] } %109, 1 - store i64 %110, i64* %"078", align 4 - store [0 x i64] %111, [0 x i64]* %"179", align 4 +91: ; preds = %cond_exit_51 + %92 = extractvalue { i1, i64 } %"61_070", 1 + store i64 %92, i64* %"078", align 4 + store [0 x i64] undef, [0 x i64]* %"179", align 4 br label %cond_62_case_1 -cond_62_case_0: ; preds = %106 +cond_62_case_0: ; preds = %90 store { i32, i8* } { i32 1, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @4, i32 0, i32 0) }, { i32, i8* }* %"67_0", align 8 %"67_075" = load { i32, i8* }, { i32, i8* }* %"67_0", align 8 - %112 = extractvalue { i32, i8* } %"67_075", 0 - %113 = extractvalue { i32, i8* } %"67_075", 1 - %114 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.4, i32 0, i32 0), i32 %112, i8* %113) + %93 = extractvalue { i32, i8* } %"67_075", 0 + %94 = extractvalue { i32, i8* } %"67_075", 1 + %95 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([34 x i8], [34 x i8]* @prelude.panic_template.4, i32 0, i32 0), i32 %93, i8* %94) call void @abort() store i64 0, i64* %"68_0", align 4 store [0 x i64] zeroinitializer, [0 x i64]* %"68_1", align 4 @@ -426,7 +407,7 @@ cond_62_case_0: ; preds = %106 store [0 x i64] %"68_177", [0 x i64]* %"172", align 4 br label %cond_exit_62 -cond_62_case_1: ; preds = %108 +cond_62_case_1: ; preds = %91 %"080" = load i64, i64* %"078", align 4 %"181" = load [0 x i64], [0 x i64]* %"179", align 4 store i64 %"080", i64* %"70_0", align 4 diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_get@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_get@llvm14.snap index d693fcac6..1c638784d 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_get@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_get@llvm14.snap @@ -16,7 +16,7 @@ entry_block: ; preds = %alloca_block br i1 %2, label %4, label %3 3: ; preds = %entry_block - br label %11 + br label %10 4: ; preds = %entry_block %5 = alloca i64, i32 2, align 8 @@ -24,11 +24,10 @@ entry_block: ; preds = %alloca_block store [2 x i64] %1, [2 x i64]* %6, align 4 %7 = getelementptr inbounds i64, i64* %5, i64 1 %8 = load i64, i64* %7, align 4 - %9 = insertvalue { i64 } undef, i64 %8, 0 - %10 = insertvalue { i32, {}, { i64 } } { i32 1, {} poison, { i64 } poison }, { i64 } %9, 2 - br label %11 + %9 = insertvalue { i1, i64 } { i1 true, i64 poison }, i64 %8, 1 + br label %10 -11: ; preds = %3, %4 - %"0.0" = phi { i32, {}, { i64 } } [ %10, %4 ], [ { i32 0, {} undef, { i64 } poison }, %3 ] +10: ; preds = %3, %4 + %"0.0" = phi { i1, i64 } [ %9, %4 ], [ { i1 false, i64 poison }, %3 ] ret void } diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_get@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_get@pre-mem2reg@llvm14.snap index 47a1b009a..15902b579 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_get@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__array__test__emit_get@pre-mem2reg@llvm14.snap @@ -10,8 +10,8 @@ alloca_block: %"7_0" = alloca i64, align 8 %"5_0" = alloca i64, align 8 %"8_0" = alloca [2 x i64], align 8 - %"9_0" = alloca { i32, {}, { i64 } }, align 8 - %"0" = alloca { i32, {}, { i64 } }, align 8 + %"9_0" = alloca { i1, i64 }, align 8 + %"0" = alloca { i1, i64 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block @@ -28,8 +28,8 @@ entry_block: ; preds = %alloca_block br i1 %2, label %4, label %3 3: ; preds = %entry_block - store { i32, {}, { i64 } } { i32 0, {} undef, { i64 } poison }, { i32, {}, { i64 } }* %"0", align 4 - br label %11 + store { i1, i64 } { i1 false, i64 poison }, { i1, i64 }* %"0", align 4 + br label %10 4: ; preds = %entry_block %5 = alloca i64, i32 2, align 8 @@ -37,13 +37,12 @@ entry_block: ; preds = %alloca_block store [2 x i64] %"8_03", [2 x i64]* %6, align 4 %7 = getelementptr inbounds i64, i64* %5, i64 %"5_04" %8 = load i64, i64* %7, align 4 - %9 = insertvalue { i64 } undef, i64 %8, 0 - %10 = insertvalue { i32, {}, { i64 } } { i32 1, {} poison, { i64 } poison }, { i64 } %9, 2 - store { i32, {}, { i64 } } %10, { i32, {}, { i64 } }* %"0", align 4 - br label %11 + %9 = insertvalue { i1, i64 } { i1 true, i64 poison }, i64 %8, 1 + store { i1, i64 } %9, { i1, i64 }* %"0", align 4 + br label %10 -11: ; preds = %3, %4 - %"05" = load { i32, {}, { i64 } }, { i32, {}, { i64 } }* %"0", align 4 - store { i32, {}, { i64 } } %"05", { i32, {}, { i64 } }* %"9_0", align 4 +10: ; preds = %3, %4 + %"05" = load { i1, i64 }, { i1, i64 }* %"0", align 4 + store { i1, i64 } %"05", { i1, i64 }* %"9_0", align 4 ret void } diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__get@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__get@llvm14.snap index 6f6b0bdf0..1fe825e8d 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__get@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__get@llvm14.snap @@ -5,7 +5,7 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, { i16 } } @_hl.main.1(i8* %0, i64 %1) { +define { i1, i16 } @_hl.main.1(i8* %0, i64 %1) { alloca_block: br label %entry_block @@ -15,10 +15,9 @@ entry_block: ; preds = %alloca_block %4 = call i1 @__rt__list__get(i8* %0, i64 %1, i8* %3) %5 = bitcast i8* %3 to i16* %6 = load i16, i16* %5, align 2 - %7 = insertvalue { i16 } undef, i16 %6, 0 - %8 = insertvalue { i32, {}, { i16 } } { i32 1, {} poison, { i16 } poison }, { i16 } %7, 2 - %9 = select i1 %4, { i32, {}, { i16 } } %8, { i32, {}, { i16 } } { i32 0, {} undef, { i16 } poison } - ret { i32, {}, { i16 } } %9 + %7 = insertvalue { i1, i16 } { i1 true, i16 poison }, i16 %6, 1 + %8 = select i1 %4, { i1, i16 } %7, { i1, i16 } { i1 false, i16 poison } + ret { i1, i16 } %8 } declare i1 @__rt__list__get(i8*, i64, i8*) diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__get@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__get@pre-mem2reg@llvm14.snap index 4a7165e96..de1117ffd 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__get@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__get@pre-mem2reg@llvm14.snap @@ -5,12 +5,12 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, { i16 } } @_hl.main.1(i8* %0, i64 %1) { +define { i1, i16 } @_hl.main.1(i8* %0, i64 %1) { alloca_block: - %"0" = alloca { i32, {}, { i16 } }, align 8 + %"0" = alloca { i1, i16 }, align 8 %"2_0" = alloca i8*, align 8 %"2_1" = alloca i64, align 8 - %"4_0" = alloca { i32, {}, { i16 } }, align 8 + %"4_0" = alloca { i1, i16 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block @@ -23,14 +23,13 @@ entry_block: ; preds = %alloca_block %4 = call i1 @__rt__list__get(i8* %"2_01", i64 %"2_12", i8* %3) %5 = bitcast i8* %3 to i16* %6 = load i16, i16* %5, align 2 - %7 = insertvalue { i16 } undef, i16 %6, 0 - %8 = insertvalue { i32, {}, { i16 } } { i32 1, {} poison, { i16 } poison }, { i16 } %7, 2 - %9 = select i1 %4, { i32, {}, { i16 } } %8, { i32, {}, { i16 } } { i32 0, {} undef, { i16 } poison } - store { i32, {}, { i16 } } %9, { i32, {}, { i16 } }* %"4_0", align 4 - %"4_03" = load { i32, {}, { i16 } }, { i32, {}, { i16 } }* %"4_0", align 4 - store { i32, {}, { i16 } } %"4_03", { i32, {}, { i16 } }* %"0", align 4 - %"04" = load { i32, {}, { i16 } }, { i32, {}, { i16 } }* %"0", align 4 - ret { i32, {}, { i16 } } %"04" + %7 = insertvalue { i1, i16 } { i1 true, i16 poison }, i16 %6, 1 + %8 = select i1 %4, { i1, i16 } %7, { i1, i16 } { i1 false, i16 poison } + store { i1, i16 } %8, { i1, i16 }* %"4_0", align 2 + %"4_03" = load { i1, i16 }, { i1, i16 }* %"4_0", align 2 + store { i1, i16 } %"4_03", { i1, i16 }* %"0", align 2 + %"04" = load { i1, i16 }, { i1, i16 }* %"0", align 2 + ret { i1, i16 } %"04" } declare i1 @__rt__list__get(i8*, i64, i8*) diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__insert@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__insert@llvm14.snap index 1c2dcfb5c..2ebc2fe20 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__insert@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__insert@llvm14.snap @@ -5,7 +5,7 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i8*, { i32, { i16 }, { { {} } } } } @_hl.main.1(i8* %0, i64 %1, i16 %2) { +define { i8*, { i1, i16 } } @_hl.main.1(i8* %0, i64 %1, i16 %2) { alloca_block: br label %entry_block @@ -14,12 +14,11 @@ entry_block: ; preds = %alloca_block store i16 %2, i16* %3, align 2 %4 = bitcast i16* %3 to i8* %5 = call i1 @__rt__list__insert(i8* %0, i64 %1, i8* %4) - %6 = insertvalue { i16 } undef, i16 %2, 0 - %7 = insertvalue { i32, { i16 }, { { {} } } } { i32 0, { i16 } poison, { { {} } } poison }, { i16 } %6, 1 - %8 = select i1 %5, { i32, { i16 }, { { {} } } } { i32 1, { i16 } poison, { { {} } } undef }, { i32, { i16 }, { { {} } } } %7 - %mrv = insertvalue { i8*, { i32, { i16 }, { { {} } } } } undef, i8* %0, 0 - %mrv8 = insertvalue { i8*, { i32, { i16 }, { { {} } } } } %mrv, { i32, { i16 }, { { {} } } } %8, 1 - ret { i8*, { i32, { i16 }, { { {} } } } } %mrv8 + %6 = insertvalue { i1, i16 } { i1 false, i16 poison }, i16 %2, 1 + %7 = select i1 %5, { i1, i16 } { i1 true, i16 poison }, { i1, i16 } %6 + %mrv = insertvalue { i8*, { i1, i16 } } undef, i8* %0, 0 + %mrv8 = insertvalue { i8*, { i1, i16 } } %mrv, { i1, i16 } %7, 1 + ret { i8*, { i1, i16 } } %mrv8 } declare i1 @__rt__list__insert(i8*, i64, i8*) diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__insert@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__insert@pre-mem2reg@llvm14.snap index 1657af5f2..3332a4f86 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__insert@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__insert@pre-mem2reg@llvm14.snap @@ -5,15 +5,15 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i8*, { i32, { i16 }, { { {} } } } } @_hl.main.1(i8* %0, i64 %1, i16 %2) { +define { i8*, { i1, i16 } } @_hl.main.1(i8* %0, i64 %1, i16 %2) { alloca_block: %"0" = alloca i8*, align 8 - %"1" = alloca { i32, { i16 }, { { {} } } }, align 8 + %"1" = alloca { i1, i16 }, align 8 %"2_0" = alloca i8*, align 8 %"2_1" = alloca i64, align 8 %"2_2" = alloca i16, align 2 %"4_0" = alloca i8*, align 8 - %"4_1" = alloca { i32, { i16 }, { { {} } } }, align 8 + %"4_1" = alloca { i1, i16 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block @@ -27,20 +27,19 @@ entry_block: ; preds = %alloca_block store i16 %"2_23", i16* %3, align 2 %4 = bitcast i16* %3 to i8* %5 = call i1 @__rt__list__insert(i8* %"2_01", i64 %"2_12", i8* %4) - %6 = insertvalue { i16 } undef, i16 %"2_23", 0 - %7 = insertvalue { i32, { i16 }, { { {} } } } { i32 0, { i16 } poison, { { {} } } poison }, { i16 } %6, 1 - %8 = select i1 %5, { i32, { i16 }, { { {} } } } { i32 1, { i16 } poison, { { {} } } undef }, { i32, { i16 }, { { {} } } } %7 + %6 = insertvalue { i1, i16 } { i1 false, i16 poison }, i16 %"2_23", 1 + %7 = select i1 %5, { i1, i16 } { i1 true, i16 poison }, { i1, i16 } %6 store i8* %"2_01", i8** %"4_0", align 8 - store { i32, { i16 }, { { {} } } } %8, { i32, { i16 }, { { {} } } }* %"4_1", align 4 + store { i1, i16 } %7, { i1, i16 }* %"4_1", align 2 %"4_04" = load i8*, i8** %"4_0", align 8 - %"4_15" = load { i32, { i16 }, { { {} } } }, { i32, { i16 }, { { {} } } }* %"4_1", align 4 + %"4_15" = load { i1, i16 }, { i1, i16 }* %"4_1", align 2 store i8* %"4_04", i8** %"0", align 8 - store { i32, { i16 }, { { {} } } } %"4_15", { i32, { i16 }, { { {} } } }* %"1", align 4 + store { i1, i16 } %"4_15", { i1, i16 }* %"1", align 2 %"06" = load i8*, i8** %"0", align 8 - %"17" = load { i32, { i16 }, { { {} } } }, { i32, { i16 }, { { {} } } }* %"1", align 4 - %mrv = insertvalue { i8*, { i32, { i16 }, { { {} } } } } undef, i8* %"06", 0 - %mrv8 = insertvalue { i8*, { i32, { i16 }, { { {} } } } } %mrv, { i32, { i16 }, { { {} } } } %"17", 1 - ret { i8*, { i32, { i16 }, { { {} } } } } %mrv8 + %"17" = load { i1, i16 }, { i1, i16 }* %"1", align 2 + %mrv = insertvalue { i8*, { i1, i16 } } undef, i8* %"06", 0 + %mrv8 = insertvalue { i8*, { i1, i16 } } %mrv, { i1, i16 } %"17", 1 + ret { i8*, { i1, i16 } } %mrv8 } declare i1 @__rt__list__insert(i8*, i64, i8*) diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__pop@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__pop@llvm14.snap index 27e680a03..8529684b5 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__pop@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__pop@llvm14.snap @@ -5,7 +5,7 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i8*, { i32, {}, { i16 } } } @_hl.main.1(i8* %0) { +define { i8*, { i1, i16 } } @_hl.main.1(i8* %0) { alloca_block: br label %entry_block @@ -15,12 +15,11 @@ entry_block: ; preds = %alloca_block %3 = call i1 @__rt__list__pop(i8* %0, i8* %2) %4 = bitcast i8* %2 to i16* %5 = load i16, i16* %4, align 2 - %6 = insertvalue { i16 } undef, i16 %5, 0 - %7 = insertvalue { i32, {}, { i16 } } { i32 1, {} poison, { i16 } poison }, { i16 } %6, 2 - %8 = select i1 %3, { i32, {}, { i16 } } %7, { i32, {}, { i16 } } { i32 0, {} undef, { i16 } poison } - %mrv = insertvalue { i8*, { i32, {}, { i16 } } } undef, i8* %0, 0 - %mrv6 = insertvalue { i8*, { i32, {}, { i16 } } } %mrv, { i32, {}, { i16 } } %8, 1 - ret { i8*, { i32, {}, { i16 } } } %mrv6 + %6 = insertvalue { i1, i16 } { i1 true, i16 poison }, i16 %5, 1 + %7 = select i1 %3, { i1, i16 } %6, { i1, i16 } { i1 false, i16 poison } + %mrv = insertvalue { i8*, { i1, i16 } } undef, i8* %0, 0 + %mrv6 = insertvalue { i8*, { i1, i16 } } %mrv, { i1, i16 } %7, 1 + ret { i8*, { i1, i16 } } %mrv6 } declare i1 @__rt__list__pop(i8*, i8*) diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__pop@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__pop@pre-mem2reg@llvm14.snap index fbc37e239..30238aff3 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__pop@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__pop@pre-mem2reg@llvm14.snap @@ -5,13 +5,13 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i8*, { i32, {}, { i16 } } } @_hl.main.1(i8* %0) { +define { i8*, { i1, i16 } } @_hl.main.1(i8* %0) { alloca_block: %"0" = alloca i8*, align 8 - %"1" = alloca { i32, {}, { i16 } }, align 8 + %"1" = alloca { i1, i16 }, align 8 %"2_0" = alloca i8*, align 8 %"4_0" = alloca i8*, align 8 - %"4_1" = alloca { i32, {}, { i16 } }, align 8 + %"4_1" = alloca { i1, i16 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block @@ -22,20 +22,19 @@ entry_block: ; preds = %alloca_block %3 = call i1 @__rt__list__pop(i8* %"2_01", i8* %2) %4 = bitcast i8* %2 to i16* %5 = load i16, i16* %4, align 2 - %6 = insertvalue { i16 } undef, i16 %5, 0 - %7 = insertvalue { i32, {}, { i16 } } { i32 1, {} poison, { i16 } poison }, { i16 } %6, 2 - %8 = select i1 %3, { i32, {}, { i16 } } %7, { i32, {}, { i16 } } { i32 0, {} undef, { i16 } poison } + %6 = insertvalue { i1, i16 } { i1 true, i16 poison }, i16 %5, 1 + %7 = select i1 %3, { i1, i16 } %6, { i1, i16 } { i1 false, i16 poison } store i8* %"2_01", i8** %"4_0", align 8 - store { i32, {}, { i16 } } %8, { i32, {}, { i16 } }* %"4_1", align 4 + store { i1, i16 } %7, { i1, i16 }* %"4_1", align 2 %"4_02" = load i8*, i8** %"4_0", align 8 - %"4_13" = load { i32, {}, { i16 } }, { i32, {}, { i16 } }* %"4_1", align 4 + %"4_13" = load { i1, i16 }, { i1, i16 }* %"4_1", align 2 store i8* %"4_02", i8** %"0", align 8 - store { i32, {}, { i16 } } %"4_13", { i32, {}, { i16 } }* %"1", align 4 + store { i1, i16 } %"4_13", { i1, i16 }* %"1", align 2 %"04" = load i8*, i8** %"0", align 8 - %"15" = load { i32, {}, { i16 } }, { i32, {}, { i16 } }* %"1", align 4 - %mrv = insertvalue { i8*, { i32, {}, { i16 } } } undef, i8* %"04", 0 - %mrv6 = insertvalue { i8*, { i32, {}, { i16 } } } %mrv, { i32, {}, { i16 } } %"15", 1 - ret { i8*, { i32, {}, { i16 } } } %mrv6 + %"15" = load { i1, i16 }, { i1, i16 }* %"1", align 2 + %mrv = insertvalue { i8*, { i1, i16 } } undef, i8* %"04", 0 + %mrv6 = insertvalue { i8*, { i1, i16 } } %mrv, { i1, i16 } %"15", 1 + ret { i8*, { i1, i16 } } %mrv6 } declare i1 @__rt__list__pop(i8*, i8*) diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__set@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__set@llvm14.snap index 6c94a7ac7..a5ec03c5e 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__set@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__set@llvm14.snap @@ -5,7 +5,7 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i8*, { i32, { i16 }, { i16 } } } @_hl.main.1(i8* %0, i64 %1, i16 %2) { +define { i8*, { i1, i16 } } @_hl.main.1(i8* %0, i64 %1, i16 %2) { alloca_block: br label %entry_block @@ -16,14 +16,12 @@ entry_block: ; preds = %alloca_block %5 = call i1 @__rt__list__set(i8* %0, i64 %1, i8* %4) %6 = bitcast i8* %4 to i16* %7 = load i16, i16* %6, align 2 - %8 = insertvalue { i16 } undef, i16 %7, 0 - %9 = insertvalue { i32, { i16 }, { i16 } } { i32 0, { i16 } poison, { i16 } poison }, { i16 } %8, 1 - %10 = insertvalue { i16 } undef, i16 %2, 0 - %11 = insertvalue { i32, { i16 }, { i16 } } { i32 1, { i16 } poison, { i16 } poison }, { i16 } %10, 2 - %12 = select i1 %5, { i32, { i16 }, { i16 } } %11, { i32, { i16 }, { i16 } } %9 - %mrv = insertvalue { i8*, { i32, { i16 }, { i16 } } } undef, i8* %0, 0 - %mrv8 = insertvalue { i8*, { i32, { i16 }, { i16 } } } %mrv, { i32, { i16 }, { i16 } } %12, 1 - ret { i8*, { i32, { i16 }, { i16 } } } %mrv8 + %8 = insertvalue { i1, i16 } { i1 false, i16 poison }, i16 %7, 1 + %9 = insertvalue { i1, i16 } { i1 true, i16 poison }, i16 %2, 1 + %10 = select i1 %5, { i1, i16 } %9, { i1, i16 } %8 + %mrv = insertvalue { i8*, { i1, i16 } } undef, i8* %0, 0 + %mrv8 = insertvalue { i8*, { i1, i16 } } %mrv, { i1, i16 } %10, 1 + ret { i8*, { i1, i16 } } %mrv8 } declare i1 @__rt__list__set(i8*, i64, i8*) diff --git a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__set@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__set@pre-mem2reg@llvm14.snap index f191ed87e..2189b5603 100644 --- a/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__set@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/collections/snapshots/hugr_llvm__extension__collections__list__test__set@pre-mem2reg@llvm14.snap @@ -5,15 +5,15 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i8*, { i32, { i16 }, { i16 } } } @_hl.main.1(i8* %0, i64 %1, i16 %2) { +define { i8*, { i1, i16 } } @_hl.main.1(i8* %0, i64 %1, i16 %2) { alloca_block: %"0" = alloca i8*, align 8 - %"1" = alloca { i32, { i16 }, { i16 } }, align 8 + %"1" = alloca { i1, i16 }, align 8 %"2_0" = alloca i8*, align 8 %"2_1" = alloca i64, align 8 %"2_2" = alloca i16, align 2 %"4_0" = alloca i8*, align 8 - %"4_1" = alloca { i32, { i16 }, { i16 } }, align 8 + %"4_1" = alloca { i1, i16 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block @@ -29,22 +29,20 @@ entry_block: ; preds = %alloca_block %5 = call i1 @__rt__list__set(i8* %"2_01", i64 %"2_12", i8* %4) %6 = bitcast i8* %4 to i16* %7 = load i16, i16* %6, align 2 - %8 = insertvalue { i16 } undef, i16 %7, 0 - %9 = insertvalue { i32, { i16 }, { i16 } } { i32 0, { i16 } poison, { i16 } poison }, { i16 } %8, 1 - %10 = insertvalue { i16 } undef, i16 %"2_23", 0 - %11 = insertvalue { i32, { i16 }, { i16 } } { i32 1, { i16 } poison, { i16 } poison }, { i16 } %10, 2 - %12 = select i1 %5, { i32, { i16 }, { i16 } } %11, { i32, { i16 }, { i16 } } %9 + %8 = insertvalue { i1, i16 } { i1 false, i16 poison }, i16 %7, 1 + %9 = insertvalue { i1, i16 } { i1 true, i16 poison }, i16 %"2_23", 1 + %10 = select i1 %5, { i1, i16 } %9, { i1, i16 } %8 store i8* %"2_01", i8** %"4_0", align 8 - store { i32, { i16 }, { i16 } } %12, { i32, { i16 }, { i16 } }* %"4_1", align 4 + store { i1, i16 } %10, { i1, i16 }* %"4_1", align 2 %"4_04" = load i8*, i8** %"4_0", align 8 - %"4_15" = load { i32, { i16 }, { i16 } }, { i32, { i16 }, { i16 } }* %"4_1", align 4 + %"4_15" = load { i1, i16 }, { i1, i16 }* %"4_1", align 2 store i8* %"4_04", i8** %"0", align 8 - store { i32, { i16 }, { i16 } } %"4_15", { i32, { i16 }, { i16 } }* %"1", align 4 + store { i1, i16 } %"4_15", { i1, i16 }* %"1", align 2 %"06" = load i8*, i8** %"0", align 8 - %"17" = load { i32, { i16 }, { i16 } }, { i32, { i16 }, { i16 } }* %"1", align 4 - %mrv = insertvalue { i8*, { i32, { i16 }, { i16 } } } undef, i8* %"06", 0 - %mrv8 = insertvalue { i8*, { i32, { i16 }, { i16 } } } %mrv, { i32, { i16 }, { i16 } } %"17", 1 - ret { i8*, { i32, { i16 }, { i16 } } } %mrv8 + %"17" = load { i1, i16 }, { i1, i16 }* %"1", align 2 + %mrv = insertvalue { i8*, { i1, i16 } } undef, i8* %"06", 0 + %mrv8 = insertvalue { i8*, { i1, i16 } } %mrv, { i1, i16 } %"17", 1 + ret { i8*, { i1, i16 } } %mrv8 } declare i1 @__rt__list__set(i8*, i64, i8*) diff --git a/hugr-llvm/src/extension/conversions.rs b/hugr-llvm/src/extension/conversions.rs index a3de97d68..71810228a 100644 --- a/hugr-llvm/src/extension/conversions.rs +++ b/hugr-llvm/src/extension/conversions.rs @@ -196,7 +196,7 @@ fn emit_conversion_op<'c, H: HugrView>( let sum_t = sum_ty.build_tag(ctx.builder(), 1, vec![])?; ctx.builder().build_select(is1, sum_t, sum_f, "")? } else { - let tag_ty = sum_ty.get_tag_type(); + let tag_ty = sum_ty.tag_type(); let tag = LLVMSumValue::try_new(arg, sum_ty)?.build_get_tag(ctx.builder())?; let is_true = ctx.builder().build_int_compare( IntPredicate::EQ, diff --git a/hugr-llvm/src/extension/prelude.rs b/hugr-llvm/src/extension/prelude.rs index 69a1050aa..69fd65362 100644 --- a/hugr-llvm/src/extension/prelude.rs +++ b/hugr-llvm/src/extension/prelude.rs @@ -261,7 +261,7 @@ fn add_prelude_extensions<'a, H: HugrView + 'a>( let make_tuple = MakeTuple::from_extension_op(args.node().as_ref())?; let llvm_sum_type = context.llvm_sum_type(SumType::new([make_tuple.0]))?; let r = llvm_sum_type.build_tag(context.builder(), 0, args.inputs)?; - args.outputs.finish(context.builder(), [r]) + args.outputs.finish(context.builder(), [r.into()]) } _ => Err(anyhow!("Unsupported TupleOpDef")), }) diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__ifrombool@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__ifrombool@llvm14.snap index 72fe903ff..2bcfc18b9 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__ifrombool@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__ifrombool@llvm14.snap @@ -5,13 +5,12 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define i8 @_hl.main.1({ i32, {}, {} } %0) { +define i8 @_hl.main.1(i1 %0) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %1 = extractvalue { i32, {}, {} } %0, 0 - %2 = icmp eq i32 %1, 1 - %3 = select i1 %2, i8 1, i8 0 - ret i8 %3 + %1 = icmp eq i1 %0, true + %2 = select i1 %1, i8 1, i8 0 + ret i8 %2 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__ifrombool@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__ifrombool@pre-mem2reg@llvm14.snap index ab30823d3..376cf693a 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__ifrombool@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__ifrombool@pre-mem2reg@llvm14.snap @@ -5,20 +5,19 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define i8 @_hl.main.1({ i32, {}, {} } %0) { +define i8 @_hl.main.1(i1 %0) { alloca_block: %"0" = alloca i8, align 1 - %"2_0" = alloca { i32, {}, {} }, align 8 + %"2_0" = alloca i1, align 1 %"4_0" = alloca i8, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } %0, { i32, {}, {} }* %"2_0", align 4 - %"2_01" = load { i32, {}, {} }, { i32, {}, {} }* %"2_0", align 4 - %1 = extractvalue { i32, {}, {} } %"2_01", 0 - %2 = icmp eq i32 %1, 1 - %3 = select i1 %2, i8 1, i8 0 - store i8 %3, i8* %"4_0", align 1 + store i1 %0, i1* %"2_0", align 1 + %"2_01" = load i1, i1* %"2_0", align 1 + %1 = icmp eq i1 %"2_01", true + %2 = select i1 %1, i8 1, i8 0 + store i8 %2, i8* %"4_0", align 1 %"4_02" = load i8, i8* %"4_0", align 1 store i8 %"4_02", i8* %"0", align 1 %"03" = load i8, i8* %"0", align 1 diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__itobool@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__itobool@llvm14.snap index 6ccc2bae1..e4583927c 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__itobool@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__itobool@llvm14.snap @@ -5,12 +5,12 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(i8 %0) { +define i1 @_hl.main.1(i8 %0) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block %eq1 = icmp eq i8 %0, 1 - %1 = select i1 %eq1, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %1 + %1 = select i1 %eq1, i1 true, i1 false + ret i1 %1 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__itobool@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__itobool@pre-mem2reg@llvm14.snap index d2b288d5a..567d9fa3a 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__itobool@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__itobool@pre-mem2reg@llvm14.snap @@ -5,21 +5,21 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(i8 %0) { +define i1 @_hl.main.1(i8 %0) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 %"2_0" = alloca i8, align 1 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block store i8 %0, i8* %"2_0", align 1 %"2_01" = load i8, i8* %"2_0", align 1 %eq1 = icmp eq i8 %"2_01", 1 - %1 = select i1 %eq1, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %1, { i32, {}, {} }* %"4_0", align 4 - %"4_02" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_02", { i32, {}, {} }* %"0", align 4 - %"03" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"03" + %1 = select i1 %eq1, i1 true, i1 false + store i1 %1, i1* %"4_0", align 1 + %"4_02" = load i1, i1* %"4_0", align 1 + store i1 %"4_02", i1* %"0", align 1 + %"03" = load i1, i1* %"0", align 1 + ret i1 %"03" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_s@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_s@llvm14.snap index 120329411..fe1e22d4c 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_s@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_s@llvm14.snap @@ -7,7 +7,7 @@ source_filename = "test_context" @0 = private unnamed_addr constant [58 x i8] c"Float value too big to convert to int of given width (32)\00", align 1 -define { i32, { { i32, i8* } }, { i32 } } @_hl.main.1(double %0) { +define { i1, { i32, i8* }, i32 } @_hl.main.1(double %0) { alloca_block: br label %entry_block @@ -16,8 +16,7 @@ entry_block: ; preds = %alloca_block %within_lower_bound = fcmp ole double 0xC1E0000000000000, %0 %success = and i1 %within_upper_bound, %within_lower_bound %trunc_result = fptosi double %0 to i32 - %1 = insertvalue { i32 } undef, i32 %trunc_result, 0 - %2 = insertvalue { i32, { { i32, i8* } }, { i32 } } { i32 1, { { i32, i8* } } poison, { i32 } poison }, { i32 } %1, 2 - %3 = select i1 %success, { i32, { { i32, i8* } }, { i32 } } %2, { i32, { { i32, i8* } }, { i32 } } { i32 0, { { i32, i8* } } { { i32, i8* } { i32 2, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @0, i32 0, i32 0) } }, { i32 } poison } - ret { i32, { { i32, i8* } }, { i32 } } %3 + %1 = insertvalue { i1, { i32, i8* }, i32 } { i1 true, { i32, i8* } poison, i32 poison }, i32 %trunc_result, 2 + %2 = select i1 %success, { i1, { i32, i8* }, i32 } %1, { i1, { i32, i8* }, i32 } { i1 false, { i32, i8* } { i32 2, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @0, i32 0, i32 0) }, i32 poison } + ret { i1, { i32, i8* }, i32 } %2 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_s@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_s@pre-mem2reg@llvm14.snap index 1bc847c2d..9d984c0b2 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_s@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_s@pre-mem2reg@llvm14.snap @@ -7,11 +7,11 @@ source_filename = "test_context" @0 = private unnamed_addr constant [58 x i8] c"Float value too big to convert to int of given width (32)\00", align 1 -define { i32, { { i32, i8* } }, { i32 } } @_hl.main.1(double %0) { +define { i1, { i32, i8* }, i32 } @_hl.main.1(double %0) { alloca_block: - %"0" = alloca { i32, { { i32, i8* } }, { i32 } }, align 8 + %"0" = alloca { i1, { i32, i8* }, i32 }, align 8 %"2_0" = alloca double, align 8 - %"4_0" = alloca { i32, { { i32, i8* } }, { i32 } }, align 8 + %"4_0" = alloca { i1, { i32, i8* }, i32 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block @@ -21,12 +21,11 @@ entry_block: ; preds = %alloca_block %within_lower_bound = fcmp ole double 0xC1E0000000000000, %"2_01" %success = and i1 %within_upper_bound, %within_lower_bound %trunc_result = fptosi double %"2_01" to i32 - %1 = insertvalue { i32 } undef, i32 %trunc_result, 0 - %2 = insertvalue { i32, { { i32, i8* } }, { i32 } } { i32 1, { { i32, i8* } } poison, { i32 } poison }, { i32 } %1, 2 - %3 = select i1 %success, { i32, { { i32, i8* } }, { i32 } } %2, { i32, { { i32, i8* } }, { i32 } } { i32 0, { { i32, i8* } } { { i32, i8* } { i32 2, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @0, i32 0, i32 0) } }, { i32 } poison } - store { i32, { { i32, i8* } }, { i32 } } %3, { i32, { { i32, i8* } }, { i32 } }* %"4_0", align 8 - %"4_02" = load { i32, { { i32, i8* } }, { i32 } }, { i32, { { i32, i8* } }, { i32 } }* %"4_0", align 8 - store { i32, { { i32, i8* } }, { i32 } } %"4_02", { i32, { { i32, i8* } }, { i32 } }* %"0", align 8 - %"03" = load { i32, { { i32, i8* } }, { i32 } }, { i32, { { i32, i8* } }, { i32 } }* %"0", align 8 - ret { i32, { { i32, i8* } }, { i32 } } %"03" + %1 = insertvalue { i1, { i32, i8* }, i32 } { i1 true, { i32, i8* } poison, i32 poison }, i32 %trunc_result, 2 + %2 = select i1 %success, { i1, { i32, i8* }, i32 } %1, { i1, { i32, i8* }, i32 } { i1 false, { i32, i8* } { i32 2, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @0, i32 0, i32 0) }, i32 poison } + store { i1, { i32, i8* }, i32 } %2, { i1, { i32, i8* }, i32 }* %"4_0", align 8 + %"4_02" = load { i1, { i32, i8* }, i32 }, { i1, { i32, i8* }, i32 }* %"4_0", align 8 + store { i1, { i32, i8* }, i32 } %"4_02", { i1, { i32, i8* }, i32 }* %"0", align 8 + %"03" = load { i1, { i32, i8* }, i32 }, { i1, { i32, i8* }, i32 }* %"0", align 8 + ret { i1, { i32, i8* }, i32 } %"03" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_u@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_u@llvm14.snap index 51dc2a4a1..83b4e1622 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_u@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_u@llvm14.snap @@ -7,7 +7,7 @@ source_filename = "test_context" @0 = private unnamed_addr constant [58 x i8] c"Float value too big to convert to int of given width (64)\00", align 1 -define { i32, { { i32, i8* } }, { i64 } } @_hl.main.1(double %0) { +define { i1, { i32, i8* }, i64 } @_hl.main.1(double %0) { alloca_block: br label %entry_block @@ -16,8 +16,7 @@ entry_block: ; preds = %alloca_block %within_lower_bound = fcmp ole double 0.000000e+00, %0 %success = and i1 %within_upper_bound, %within_lower_bound %trunc_result = fptoui double %0 to i64 - %1 = insertvalue { i64 } undef, i64 %trunc_result, 0 - %2 = insertvalue { i32, { { i32, i8* } }, { i64 } } { i32 1, { { i32, i8* } } poison, { i64 } poison }, { i64 } %1, 2 - %3 = select i1 %success, { i32, { { i32, i8* } }, { i64 } } %2, { i32, { { i32, i8* } }, { i64 } } { i32 0, { { i32, i8* } } { { i32, i8* } { i32 2, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @0, i32 0, i32 0) } }, { i64 } poison } - ret { i32, { { i32, i8* } }, { i64 } } %3 + %1 = insertvalue { i1, { i32, i8* }, i64 } { i1 true, { i32, i8* } poison, i64 poison }, i64 %trunc_result, 2 + %2 = select i1 %success, { i1, { i32, i8* }, i64 } %1, { i1, { i32, i8* }, i64 } { i1 false, { i32, i8* } { i32 2, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @0, i32 0, i32 0) }, i64 poison } + ret { i1, { i32, i8* }, i64 } %2 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_u@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_u@pre-mem2reg@llvm14.snap index ecd0899b6..07db760ae 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_u@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__conversions__test__trunc_u@pre-mem2reg@llvm14.snap @@ -7,11 +7,11 @@ source_filename = "test_context" @0 = private unnamed_addr constant [58 x i8] c"Float value too big to convert to int of given width (64)\00", align 1 -define { i32, { { i32, i8* } }, { i64 } } @_hl.main.1(double %0) { +define { i1, { i32, i8* }, i64 } @_hl.main.1(double %0) { alloca_block: - %"0" = alloca { i32, { { i32, i8* } }, { i64 } }, align 8 + %"0" = alloca { i1, { i32, i8* }, i64 }, align 8 %"2_0" = alloca double, align 8 - %"4_0" = alloca { i32, { { i32, i8* } }, { i64 } }, align 8 + %"4_0" = alloca { i1, { i32, i8* }, i64 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block @@ -21,12 +21,11 @@ entry_block: ; preds = %alloca_block %within_lower_bound = fcmp ole double 0.000000e+00, %"2_01" %success = and i1 %within_upper_bound, %within_lower_bound %trunc_result = fptoui double %"2_01" to i64 - %1 = insertvalue { i64 } undef, i64 %trunc_result, 0 - %2 = insertvalue { i32, { { i32, i8* } }, { i64 } } { i32 1, { { i32, i8* } } poison, { i64 } poison }, { i64 } %1, 2 - %3 = select i1 %success, { i32, { { i32, i8* } }, { i64 } } %2, { i32, { { i32, i8* } }, { i64 } } { i32 0, { { i32, i8* } } { { i32, i8* } { i32 2, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @0, i32 0, i32 0) } }, { i64 } poison } - store { i32, { { i32, i8* } }, { i64 } } %3, { i32, { { i32, i8* } }, { i64 } }* %"4_0", align 8 - %"4_02" = load { i32, { { i32, i8* } }, { i64 } }, { i32, { { i32, i8* } }, { i64 } }* %"4_0", align 8 - store { i32, { { i32, i8* } }, { i64 } } %"4_02", { i32, { { i32, i8* } }, { i64 } }* %"0", align 8 - %"03" = load { i32, { { i32, i8* } }, { i64 } }, { i32, { { i32, i8* } }, { i64 } }* %"0", align 8 - ret { i32, { { i32, i8* } }, { i64 } } %"03" + %1 = insertvalue { i1, { i32, i8* }, i64 } { i1 true, { i32, i8* } poison, i64 poison }, i64 %trunc_result, 2 + %2 = select i1 %success, { i1, { i32, i8* }, i64 } %1, { i1, { i32, i8* }, i64 } { i1 false, { i32, i8* } { i32 2, i8* getelementptr inbounds ([58 x i8], [58 x i8]* @0, i32 0, i32 0) }, i64 poison } + store { i1, { i32, i8* }, i64 } %2, { i1, { i32, i8* }, i64 }* %"4_0", align 8 + %"4_02" = load { i1, { i32, i8* }, i64 }, { i1, { i32, i8* }, i64 }* %"4_0", align 8 + store { i1, { i32, i8* }, i64 } %"4_02", { i1, { i32, i8* }, i64 }* %"0", align 8 + %"03" = load { i1, { i32, i8* }, i64 }, { i1, { i32, i8* }, i64 }* %"0", align 8 + ret { i1, { i32, i8* }, i64 } %"03" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__feq@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__feq@llvm14.snap index efc3b14b3..0701369c8 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__feq@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__feq@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block %2 = fcmp oeq double %0, %1 - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %3 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__feq@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__feq@pre-mem2reg@llvm14.snap index b362265fe..20cfb6c04 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__feq@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__feq@pre-mem2reg@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 %"2_0" = alloca double, align 8 %"2_1" = alloca double, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block @@ -19,10 +19,10 @@ entry_block: ; preds = %alloca_block %"2_01" = load double, double* %"2_0", align 8 %"2_12" = load double, double* %"2_1", align 8 %2 = fcmp oeq double %"2_01", %"2_12" - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %3, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fge@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fge@llvm14.snap index 0f370c6f6..71e1f8007 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fge@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fge@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block %2 = fcmp oge double %0, %1 - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %3 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fge@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fge@pre-mem2reg@llvm14.snap index 9aaf26b0b..5a2bf43d1 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fge@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fge@pre-mem2reg@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 %"2_0" = alloca double, align 8 %"2_1" = alloca double, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block @@ -19,10 +19,10 @@ entry_block: ; preds = %alloca_block %"2_01" = load double, double* %"2_0", align 8 %"2_12" = load double, double* %"2_1", align 8 %2 = fcmp oge double %"2_01", %"2_12" - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %3, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fgt@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fgt@llvm14.snap index 3e7f6ae3b..35969a73d 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fgt@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fgt@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block %2 = fcmp ogt double %0, %1 - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %3 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fgt@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fgt@pre-mem2reg@llvm14.snap index 4ce7c785a..7ed459dac 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fgt@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fgt@pre-mem2reg@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 %"2_0" = alloca double, align 8 %"2_1" = alloca double, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block @@ -19,10 +19,10 @@ entry_block: ; preds = %alloca_block %"2_01" = load double, double* %"2_0", align 8 %"2_12" = load double, double* %"2_1", align 8 %2 = fcmp ogt double %"2_01", %"2_12" - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %3, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fle@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fle@llvm14.snap index d990ebb36..186909f18 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fle@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fle@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block %2 = fcmp ole double %0, %1 - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %3 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fle@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fle@pre-mem2reg@llvm14.snap index 93f1e6fce..454c69dcf 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fle@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fle@pre-mem2reg@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 %"2_0" = alloca double, align 8 %"2_1" = alloca double, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block @@ -19,10 +19,10 @@ entry_block: ; preds = %alloca_block %"2_01" = load double, double* %"2_0", align 8 %"2_12" = load double, double* %"2_1", align 8 %2 = fcmp ole double %"2_01", %"2_12" - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %3, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__flt@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__flt@llvm14.snap index a459fdfa5..a9c2f1678 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__flt@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__flt@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block %2 = fcmp olt double %0, %1 - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %3 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__flt@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__flt@pre-mem2reg@llvm14.snap index 17f23de54..785cb59da 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__flt@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__flt@pre-mem2reg@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 %"2_0" = alloca double, align 8 %"2_1" = alloca double, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block @@ -19,10 +19,10 @@ entry_block: ; preds = %alloca_block %"2_01" = load double, double* %"2_0", align 8 %"2_12" = load double, double* %"2_1", align 8 %2 = fcmp olt double %"2_01", %"2_12" - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %3, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fne@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fne@llvm14.snap index fe58c2849..4c4ce19a6 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fne@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fne@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block %2 = fcmp one double %0, %1 - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %3 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fne@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fne@pre-mem2reg@llvm14.snap index dc8aa88ea..0dc0e8c8c 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fne@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__float__test__fne@pre-mem2reg@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/float.rs +source: hugr-llvm/src/extension/float.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(double %0, double %1) { +define i1 @_hl.main.1(double %0, double %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 %"2_0" = alloca double, align 8 %"2_1" = alloca double, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block @@ -19,10 +19,10 @@ entry_block: ; preds = %alloca_block %"2_01" = load double, double* %"2_0", align 8 %"2_12" = load double, double* %"2_1", align 8 %2 = fcmp one double %"2_01", %"2_12" - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %3, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ieq@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ieq@llvm14.snap index 5595ef5d6..4a86953d4 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ieq@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ieq@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/int.rs +source: hugr-llvm/src/extension/int.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(i8 %0, i8 %1) { +define i1 @_hl.main.1(i8 %0, i8 %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block %2 = icmp eq i8 %0, %1 - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %3 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ieq@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ieq@pre-mem2reg@llvm14.snap index 6d453e14b..0ca058a26 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ieq@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ieq@pre-mem2reg@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/int.rs +source: hugr-llvm/src/extension/int.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(i8 %0, i8 %1) { +define i1 @_hl.main.1(i8 %0, i8 %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 %"2_0" = alloca i8, align 1 %"2_1" = alloca i8, align 1 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block @@ -19,10 +19,10 @@ entry_block: ; preds = %alloca_block %"2_01" = load i8, i8* %"2_0", align 1 %"2_12" = load i8, i8* %"2_1", align 1 %2 = icmp eq i8 %"2_01", %"2_12" - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %3, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ilt_s@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ilt_s@llvm14.snap index 6a88510b6..dfbbeb5ac 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ilt_s@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ilt_s@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/int.rs +source: hugr-llvm/src/extension/int.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(i8 %0, i8 %1) { +define i1 @_hl.main.1(i8 %0, i8 %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block %2 = icmp slt i8 %0, %1 - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %3 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ilt_s@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ilt_s@pre-mem2reg@llvm14.snap index 36b528a34..9487469db 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ilt_s@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__int__test__ilt_s@pre-mem2reg@llvm14.snap @@ -1,16 +1,16 @@ --- -source: src/extension/int.rs +source: hugr-llvm/src/extension/int.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1(i8 %0, i8 %1) { +define i1 @_hl.main.1(i8 %0, i8 %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 %"2_0" = alloca i8, align 1 %"2_1" = alloca i8, align 1 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block @@ -19,10 +19,10 @@ entry_block: ; preds = %alloca_block %"2_01" = load i8, i8* %"2_0", align 1 %"2_12" = load i8, i8* %"2_1", align 1 %2 = icmp slt i8 %"2_01", %"2_12" - %3 = select i1 %2, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %3, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__and@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__and@llvm14.snap index 71f38b3bc..4bf6656c6 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__and@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__and@llvm14.snap @@ -1,19 +1,16 @@ --- -source: src/extension/logic.rs +source: hugr-llvm/src/extension/logic.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define i1 @_hl.main.1(i1 %0, i1 %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %2 = extractvalue { i32, {}, {} } %0, 0 - %3 = extractvalue { i32, {}, {} } %1, 0 - %4 = and i32 %2, %3 - %5 = trunc i32 %4 to i1 - %6 = select i1 %5, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %6 + %2 = and i1 %0, %1 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__and@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__and@pre-mem2reg@llvm14.snap index 70130dce9..d91355597 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__and@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__and@pre-mem2reg@llvm14.snap @@ -1,31 +1,28 @@ --- -source: src/extension/logic.rs +source: hugr-llvm/src/extension/logic.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define i1 @_hl.main.1(i1 %0, i1 %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"2_0" = alloca { i32, {}, {} }, align 8 - %"2_1" = alloca { i32, {}, {} }, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"2_0" = alloca i1, align 1 + %"2_1" = alloca i1, align 1 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } %0, { i32, {}, {} }* %"2_0", align 4 - store { i32, {}, {} } %1, { i32, {}, {} }* %"2_1", align 4 - %"2_01" = load { i32, {}, {} }, { i32, {}, {} }* %"2_0", align 4 - %"2_12" = load { i32, {}, {} }, { i32, {}, {} }* %"2_1", align 4 - %2 = extractvalue { i32, {}, {} } %"2_01", 0 - %3 = extractvalue { i32, {}, {} } %"2_12", 0 - %4 = and i32 %2, %3 - %5 = trunc i32 %4 to i1 - %6 = select i1 %5, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %6, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + store i1 %0, i1* %"2_0", align 1 + store i1 %1, i1* %"2_1", align 1 + %"2_01" = load i1, i1* %"2_0", align 1 + %"2_12" = load i1, i1* %"2_1", align 1 + %2 = and i1 %"2_01", %"2_12" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__eq@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__eq@llvm14.snap index 443aba568..4b3267e25 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__eq@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__eq@llvm14.snap @@ -1,18 +1,16 @@ --- -source: src/extension/logic.rs +source: hugr-llvm/src/extension/logic.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define i1 @_hl.main.1(i1 %0, i1 %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %2 = extractvalue { i32, {}, {} } %0, 0 - %3 = extractvalue { i32, {}, {} } %1, 0 - %4 = icmp eq i32 %3, %2 - %5 = select i1 %4, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %5 + %2 = icmp eq i1 %1, %0 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__eq@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__eq@pre-mem2reg@llvm14.snap index d54c40db2..354c429a2 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__eq@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__eq@pre-mem2reg@llvm14.snap @@ -1,30 +1,28 @@ --- -source: src/extension/logic.rs +source: hugr-llvm/src/extension/logic.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define i1 @_hl.main.1(i1 %0, i1 %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"2_0" = alloca { i32, {}, {} }, align 8 - %"2_1" = alloca { i32, {}, {} }, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"2_0" = alloca i1, align 1 + %"2_1" = alloca i1, align 1 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } %0, { i32, {}, {} }* %"2_0", align 4 - store { i32, {}, {} } %1, { i32, {}, {} }* %"2_1", align 4 - %"2_01" = load { i32, {}, {} }, { i32, {}, {} }* %"2_0", align 4 - %"2_12" = load { i32, {}, {} }, { i32, {}, {} }* %"2_1", align 4 - %2 = extractvalue { i32, {}, {} } %"2_01", 0 - %3 = extractvalue { i32, {}, {} } %"2_12", 0 - %4 = icmp eq i32 %3, %2 - %5 = select i1 %4, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %5, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + store i1 %0, i1* %"2_0", align 1 + store i1 %1, i1* %"2_1", align 1 + %"2_01" = load i1, i1* %"2_0", align 1 + %"2_12" = load i1, i1* %"2_1", align 1 + %2 = icmp eq i1 %"2_12", %"2_01" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@llvm14.snap index 04b199fd3..396c02ee5 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@llvm14.snap @@ -5,14 +5,12 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1({ i32, {}, {} } %0) { +define i1 @_hl.main.1(i1 %0) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %1 = extractvalue { i32, {}, {} } %0, 0 - %2 = xor i32 %1, -1 - %3 = trunc i32 %2 to i1 - %4 = select i1 %3, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %4 + %1 = xor i1 %0, true + %2 = select i1 %1, i1 true, i1 false + ret i1 %2 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@pre-mem2reg@llvm14.snap index 86cf3f41c..ea0c1e98a 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@pre-mem2reg@llvm14.snap @@ -5,23 +5,21 @@ expression: mod_str ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1({ i32, {}, {} } %0) { +define i1 @_hl.main.1(i1 %0) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"2_0" = alloca { i32, {}, {} }, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"2_0" = alloca i1, align 1 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } %0, { i32, {}, {} }* %"2_0", align 4 - %"2_01" = load { i32, {}, {} }, { i32, {}, {} }* %"2_0", align 4 - %1 = extractvalue { i32, {}, {} } %"2_01", 0 - %2 = xor i32 %1, -1 - %3 = trunc i32 %2 to i1 - %4 = select i1 %3, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %4, { i32, {}, {} }* %"4_0", align 4 - %"4_02" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_02", { i32, {}, {} }* %"0", align 4 - %"03" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"03" + store i1 %0, i1* %"2_0", align 1 + %"2_01" = load i1, i1* %"2_0", align 1 + %1 = xor i1 %"2_01", true + %2 = select i1 %1, i1 true, i1 false + store i1 %2, i1* %"4_0", align 1 + %"4_02" = load i1, i1* %"4_0", align 1 + store i1 %"4_02", i1* %"0", align 1 + %"03" = load i1, i1* %"0", align 1 + ret i1 %"03" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__or@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__or@llvm14.snap index 6c6c0e3f9..fdee0bf8c 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__or@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__or@llvm14.snap @@ -1,19 +1,16 @@ --- -source: src/extension/logic.rs +source: hugr-llvm/src/extension/logic.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define i1 @_hl.main.1(i1 %0, i1 %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %2 = extractvalue { i32, {}, {} } %0, 0 - %3 = extractvalue { i32, {}, {} } %1, 0 - %4 = or i32 %2, %3 - %5 = trunc i32 %4 to i1 - %6 = select i1 %5, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - ret { i32, {}, {} } %6 + %2 = or i1 %0, %1 + %3 = select i1 %2, i1 true, i1 false + ret i1 %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__or@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__or@pre-mem2reg@llvm14.snap index 9057a51b3..03d0fccaf 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__or@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__or@pre-mem2reg@llvm14.snap @@ -1,31 +1,28 @@ --- -source: src/extension/logic.rs +source: hugr-llvm/src/extension/logic.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { i32, {}, {} } @_hl.main.1({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define i1 @_hl.main.1(i1 %0, i1 %1) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"2_0" = alloca { i32, {}, {} }, align 8 - %"2_1" = alloca { i32, {}, {} }, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"2_0" = alloca i1, align 1 + %"2_1" = alloca i1, align 1 + %"4_0" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } %0, { i32, {}, {} }* %"2_0", align 4 - store { i32, {}, {} } %1, { i32, {}, {} }* %"2_1", align 4 - %"2_01" = load { i32, {}, {} }, { i32, {}, {} }* %"2_0", align 4 - %"2_12" = load { i32, {}, {} }, { i32, {}, {} }* %"2_1", align 4 - %2 = extractvalue { i32, {}, {} } %"2_01", 0 - %3 = extractvalue { i32, {}, {} } %"2_12", 0 - %4 = or i32 %2, %3 - %5 = trunc i32 %4 to i1 - %6 = select i1 %5, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison } - store { i32, {}, {} } %6, { i32, {}, {} }* %"4_0", align 4 - %"4_03" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %"4_03", { i32, {}, {} }* %"0", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - ret { i32, {}, {} } %"04" + store i1 %0, i1* %"2_0", align 1 + store i1 %1, i1* %"2_1", align 1 + %"2_01" = load i1, i1* %"2_0", align 1 + %"2_12" = load i1, i1* %"2_1", align 1 + %2 = or i1 %"2_01", %"2_12" + %3 = select i1 %2, i1 true, i1 false + store i1 %3, i1* %"4_0", align 1 + %"4_03" = load i1, i1* %"4_0", align 1 + store i1 %"4_03", i1* %"0", align 1 + %"04" = load i1, i1* %"0", align 1 + ret i1 %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_const_external_symbol@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_const_external_symbol@llvm14.snap index e94ab8bfc..f706949a4 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_const_external_symbol@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_const_external_symbol@llvm14.snap @@ -1,21 +1,21 @@ --- -source: src/extension/prelude.rs +source: hugr-llvm/src/extension/prelude.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -@sym2 = external global { i32, { i64, { i32, {}, {}, {} } }, {} } +@sym2 = external global { i1, i64, i2 } @sym1 = external constant i64 -define { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } @_hl.main.1() { +define { i64, { i1, i64, i2 } } @_hl.main.1() { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %sym2 = load { i32, { i64, { i32, {}, {}, {} } }, {} }, { i32, { i64, { i32, {}, {}, {} } }, {} }* @sym2, align 4 + %sym2 = load { i1, i64, i2 }, { i1, i64, i2 }* @sym2, align 4 %sym1 = load i64, i64* @sym1, align 4 - %mrv = insertvalue { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } undef, i64 %sym1, 0 - %mrv5 = insertvalue { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } %mrv, { i32, { i64, { i32, {}, {}, {} } }, {} } %sym2, 1 - ret { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } %mrv5 + %mrv = insertvalue { i64, { i1, i64, i2 } } undef, i64 %sym1, 0 + %mrv5 = insertvalue { i64, { i1, i64, i2 } } %mrv, { i1, i64, i2 } %sym2, 1 + ret { i64, { i1, i64, i2 } } %mrv5 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_const_external_symbol@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_const_external_symbol@pre-mem2reg@llvm14.snap index f4c5e0ad7..97ce7d2b3 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_const_external_symbol@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_const_external_symbol@pre-mem2reg@llvm14.snap @@ -1,33 +1,33 @@ --- -source: src/extension/prelude.rs +source: hugr-llvm/src/extension/prelude.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -@sym2 = external global { i32, { i64, { i32, {}, {}, {} } }, {} } +@sym2 = external global { i1, i64, i2 } @sym1 = external constant i64 -define { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } @_hl.main.1() { +define { i64, { i1, i64, i2 } } @_hl.main.1() { alloca_block: %"0" = alloca i64, align 8 - %"1" = alloca { i32, { i64, { i32, {}, {}, {} } }, {} }, align 8 - %"7_0" = alloca { i32, { i64, { i32, {}, {}, {} } }, {} }, align 8 + %"1" = alloca { i1, i64, i2 }, align 8 + %"7_0" = alloca { i1, i64, i2 }, align 8 %"5_0" = alloca i64, align 8 br label %entry_block entry_block: ; preds = %alloca_block - %sym2 = load { i32, { i64, { i32, {}, {}, {} } }, {} }, { i32, { i64, { i32, {}, {}, {} } }, {} }* @sym2, align 4 - store { i32, { i64, { i32, {}, {}, {} } }, {} } %sym2, { i32, { i64, { i32, {}, {}, {} } }, {} }* %"7_0", align 4 + %sym2 = load { i1, i64, i2 }, { i1, i64, i2 }* @sym2, align 4 + store { i1, i64, i2 } %sym2, { i1, i64, i2 }* %"7_0", align 4 %sym1 = load i64, i64* @sym1, align 4 store i64 %sym1, i64* %"5_0", align 4 %"5_01" = load i64, i64* %"5_0", align 4 - %"7_02" = load { i32, { i64, { i32, {}, {}, {} } }, {} }, { i32, { i64, { i32, {}, {}, {} } }, {} }* %"7_0", align 4 + %"7_02" = load { i1, i64, i2 }, { i1, i64, i2 }* %"7_0", align 4 store i64 %"5_01", i64* %"0", align 4 - store { i32, { i64, { i32, {}, {}, {} } }, {} } %"7_02", { i32, { i64, { i32, {}, {}, {} } }, {} }* %"1", align 4 + store { i1, i64, i2 } %"7_02", { i1, i64, i2 }* %"1", align 4 %"03" = load i64, i64* %"0", align 4 - %"14" = load { i32, { i64, { i32, {}, {}, {} } }, {} }, { i32, { i64, { i32, {}, {}, {} } }, {} }* %"1", align 4 - %mrv = insertvalue { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } undef, i64 %"03", 0 - %mrv5 = insertvalue { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } %mrv, { i32, { i64, { i32, {}, {}, {} } }, {} } %"14", 1 - ret { i64, { i32, { i64, { i32, {}, {}, {} } }, {} } } %mrv5 + %"14" = load { i1, i64, i2 }, { i1, i64, i2 }* %"1", align 4 + %mrv = insertvalue { i64, { i1, i64, i2 } } undef, i64 %"03", 0 + %mrv5 = insertvalue { i64, { i1, i64, i2 } } %mrv, { i1, i64, i2 } %"14", 1 + ret { i64, { i1, i64, i2 } } %mrv5 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_make_tuple@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_make_tuple@llvm14.snap index dcdadc7c0..414ce0adf 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_make_tuple@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_make_tuple@llvm14.snap @@ -1,17 +1,16 @@ --- -source: src/extension/prelude.rs +source: hugr-llvm/src/extension/prelude.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { { { i32, {}, {} }, { i32, {}, {} } } } @_hl.main.1({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define { i1, i1 } @_hl.main.1(i1 %0, i1 %1) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %2 = insertvalue { { i32, {}, {} }, { i32, {}, {} } } undef, { i32, {}, {} } %0, 0 - %3 = insertvalue { { i32, {}, {} }, { i32, {}, {} } } %2, { i32, {}, {} } %1, 1 - %4 = insertvalue { { { i32, {}, {} }, { i32, {}, {} } } } poison, { { i32, {}, {} }, { i32, {}, {} } } %3, 0 - ret { { { i32, {}, {} }, { i32, {}, {} } } } %4 + %2 = insertvalue { i1, i1 } poison, i1 %0, 0 + %3 = insertvalue { i1, i1 } %2, i1 %1, 1 + ret { i1, i1 } %3 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_make_tuple@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_make_tuple@pre-mem2reg@llvm14.snap index a53dffb19..541d6f999 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_make_tuple@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_make_tuple@pre-mem2reg@llvm14.snap @@ -1,29 +1,28 @@ --- -source: src/extension/prelude.rs +source: hugr-llvm/src/extension/prelude.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { { { i32, {}, {} }, { i32, {}, {} } } } @_hl.main.1({ i32, {}, {} } %0, { i32, {}, {} } %1) { +define { i1, i1 } @_hl.main.1(i1 %0, i1 %1) { alloca_block: - %"0" = alloca { { { i32, {}, {} }, { i32, {}, {} } } }, align 8 - %"2_0" = alloca { i32, {}, {} }, align 8 - %"2_1" = alloca { i32, {}, {} }, align 8 - %"4_0" = alloca { { { i32, {}, {} }, { i32, {}, {} } } }, align 8 + %"0" = alloca { i1, i1 }, align 8 + %"2_0" = alloca i1, align 1 + %"2_1" = alloca i1, align 1 + %"4_0" = alloca { i1, i1 }, align 8 br label %entry_block entry_block: ; preds = %alloca_block - store { i32, {}, {} } %0, { i32, {}, {} }* %"2_0", align 4 - store { i32, {}, {} } %1, { i32, {}, {} }* %"2_1", align 4 - %"2_01" = load { i32, {}, {} }, { i32, {}, {} }* %"2_0", align 4 - %"2_12" = load { i32, {}, {} }, { i32, {}, {} }* %"2_1", align 4 - %2 = insertvalue { { i32, {}, {} }, { i32, {}, {} } } undef, { i32, {}, {} } %"2_01", 0 - %3 = insertvalue { { i32, {}, {} }, { i32, {}, {} } } %2, { i32, {}, {} } %"2_12", 1 - %4 = insertvalue { { { i32, {}, {} }, { i32, {}, {} } } } poison, { { i32, {}, {} }, { i32, {}, {} } } %3, 0 - store { { { i32, {}, {} }, { i32, {}, {} } } } %4, { { { i32, {}, {} }, { i32, {}, {} } } }* %"4_0", align 4 - %"4_03" = load { { { i32, {}, {} }, { i32, {}, {} } } }, { { { i32, {}, {} }, { i32, {}, {} } } }* %"4_0", align 4 - store { { { i32, {}, {} }, { i32, {}, {} } } } %"4_03", { { { i32, {}, {} }, { i32, {}, {} } } }* %"0", align 4 - %"04" = load { { { i32, {}, {} }, { i32, {}, {} } } }, { { { i32, {}, {} }, { i32, {}, {} } } }* %"0", align 4 - ret { { { i32, {}, {} }, { i32, {}, {} } } } %"04" + store i1 %0, i1* %"2_0", align 1 + store i1 %1, i1* %"2_1", align 1 + %"2_01" = load i1, i1* %"2_0", align 1 + %"2_12" = load i1, i1* %"2_1", align 1 + %2 = insertvalue { i1, i1 } poison, i1 %"2_01", 0 + %3 = insertvalue { i1, i1 } %2, i1 %"2_12", 1 + store { i1, i1 } %3, { i1, i1 }* %"4_0", align 1 + %"4_03" = load { i1, i1 }, { i1, i1 }* %"4_0", align 1 + store { i1, i1 } %"4_03", { i1, i1 }* %"0", align 1 + %"04" = load { i1, i1 }, { i1, i1 }* %"0", align 1 + ret { i1, i1 } %"04" } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_unpack_tuple@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_unpack_tuple@llvm14.snap index 71f756ee7..6ff5fe365 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_unpack_tuple@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_unpack_tuple@llvm14.snap @@ -1,19 +1,18 @@ --- -source: src/extension/prelude.rs +source: hugr-llvm/src/extension/prelude.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { { i32, {}, {} }, { i32, {}, {} } } @_hl.main.1({ { { i32, {}, {} }, { i32, {}, {} } } } %0) { +define { i1, i1 } @_hl.main.1({ i1, i1 } %0) { alloca_block: br label %entry_block entry_block: ; preds = %alloca_block - %1 = extractvalue { { { i32, {}, {} }, { i32, {}, {} } } } %0, 0 - %2 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %1, 0 - %3 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %1, 1 - %mrv = insertvalue { { i32, {}, {} }, { i32, {}, {} } } undef, { i32, {}, {} } %2, 0 - %mrv6 = insertvalue { { i32, {}, {} }, { i32, {}, {} } } %mrv, { i32, {}, {} } %3, 1 - ret { { i32, {}, {} }, { i32, {}, {} } } %mrv6 + %1 = extractvalue { i1, i1 } %0, 0 + %2 = extractvalue { i1, i1 } %0, 1 + %mrv = insertvalue { i1, i1 } undef, i1 %1, 0 + %mrv6 = insertvalue { i1, i1 } %mrv, i1 %2, 1 + ret { i1, i1 } %mrv6 } diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_unpack_tuple@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_unpack_tuple@pre-mem2reg@llvm14.snap index 89772dbf5..bad354037 100644 --- a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_unpack_tuple@pre-mem2reg@llvm14.snap +++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__prelude__test__prelude_unpack_tuple@pre-mem2reg@llvm14.snap @@ -1,34 +1,33 @@ --- -source: src/extension/prelude.rs +source: hugr-llvm/src/extension/prelude.rs expression: mod_str --- ; ModuleID = 'test_context' source_filename = "test_context" -define { { i32, {}, {} }, { i32, {}, {} } } @_hl.main.1({ { { i32, {}, {} }, { i32, {}, {} } } } %0) { +define { i1, i1 } @_hl.main.1({ i1, i1 } %0) { alloca_block: - %"0" = alloca { i32, {}, {} }, align 8 - %"1" = alloca { i32, {}, {} }, align 8 - %"2_0" = alloca { { { i32, {}, {} }, { i32, {}, {} } } }, align 8 - %"4_0" = alloca { i32, {}, {} }, align 8 - %"4_1" = alloca { i32, {}, {} }, align 8 + %"0" = alloca i1, align 1 + %"1" = alloca i1, align 1 + %"2_0" = alloca { i1, i1 }, align 8 + %"4_0" = alloca i1, align 1 + %"4_1" = alloca i1, align 1 br label %entry_block entry_block: ; preds = %alloca_block - store { { { i32, {}, {} }, { i32, {}, {} } } } %0, { { { i32, {}, {} }, { i32, {}, {} } } }* %"2_0", align 4 - %"2_01" = load { { { i32, {}, {} }, { i32, {}, {} } } }, { { { i32, {}, {} }, { i32, {}, {} } } }* %"2_0", align 4 - %1 = extractvalue { { { i32, {}, {} }, { i32, {}, {} } } } %"2_01", 0 - %2 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %1, 0 - %3 = extractvalue { { i32, {}, {} }, { i32, {}, {} } } %1, 1 - store { i32, {}, {} } %2, { i32, {}, {} }* %"4_0", align 4 - store { i32, {}, {} } %3, { i32, {}, {} }* %"4_1", align 4 - %"4_02" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4 - %"4_13" = load { i32, {}, {} }, { i32, {}, {} }* %"4_1", align 4 - store { i32, {}, {} } %"4_02", { i32, {}, {} }* %"0", align 4 - store { i32, {}, {} } %"4_13", { i32, {}, {} }* %"1", align 4 - %"04" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4 - %"15" = load { i32, {}, {} }, { i32, {}, {} }* %"1", align 4 - %mrv = insertvalue { { i32, {}, {} }, { i32, {}, {} } } undef, { i32, {}, {} } %"04", 0 - %mrv6 = insertvalue { { i32, {}, {} }, { i32, {}, {} } } %mrv, { i32, {}, {} } %"15", 1 - ret { { i32, {}, {} }, { i32, {}, {} } } %mrv6 + store { i1, i1 } %0, { i1, i1 }* %"2_0", align 1 + %"2_01" = load { i1, i1 }, { i1, i1 }* %"2_0", align 1 + %1 = extractvalue { i1, i1 } %"2_01", 0 + %2 = extractvalue { i1, i1 } %"2_01", 1 + store i1 %1, i1* %"4_0", align 1 + store i1 %2, i1* %"4_1", align 1 + %"4_02" = load i1, i1* %"4_0", align 1 + %"4_13" = load i1, i1* %"4_1", align 1 + store i1 %"4_02", i1* %"0", align 1 + store i1 %"4_13", i1* %"1", align 1 + %"04" = load i1, i1* %"0", align 1 + %"15" = load i1, i1* %"1", align 1 + %mrv = insertvalue { i1, i1 } undef, i1 %"04", 0 + %mrv6 = insertvalue { i1, i1 } %mrv, i1 %"15", 1 + ret { i1, i1 } %mrv6 } diff --git a/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_0.snap b/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_0.snap index 1a797730d..5509a5dc2 100644 --- a/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_0.snap +++ b/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_0.snap @@ -1,5 +1,5 @@ --- -source: src/types.rs -expression: "[[]+[]] -> [[]][]" +source: hugr-llvm/src/types.rs +expression: "[Bool] -> []" --- -"void ({ i32, {}, {} })" +"void (i1)" diff --git a/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_1.snap b/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_1.snap index 5b3ba60f0..d32b4461d 100644 --- a/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_1.snap +++ b/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_1.snap @@ -1,5 +1,5 @@ --- -source: src/types.rs -expression: "[[]] -> [[]][[]+[]+[]]" +source: hugr-llvm/src/types.rs +expression: "[Unit] -> [[]+[]+[]]" --- -"{ i32, {}, {}, {} } ({ {} })" +"i2 ({})" diff --git a/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_2.snap b/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_2.snap index ed1260816..4de84f61a 100644 --- a/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_2.snap +++ b/hugr-llvm/src/snapshots/hugr_llvm__types__test__func_type_to_llvm@llvm14_2.snap @@ -1,5 +1,5 @@ --- -source: src/types.rs -expression: "[[]][[], []]" +source: hugr-llvm/src/types.rs +expression: "[] -> [Unit, Unit]" --- -"{ { {} }, { {} } } ()" +"{ {}, {} } ()" diff --git a/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_1.snap b/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_1.snap index 73de34574..7ac4a246d 100644 --- a/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_1.snap +++ b/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_1.snap @@ -1,5 +1,5 @@ --- -source: src/types.rs -expression: "[]" +source: hugr-llvm/src/types.rs +expression: Unit --- -"{ {} }" +"{}" diff --git a/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_2.snap b/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_2.snap index 786cbd18f..1412b280f 100644 --- a/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_2.snap +++ b/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_2.snap @@ -1,5 +1,5 @@ --- -source: src/types.rs -expression: "[⊥, []]+[[]+[], []+[]+[]]" +source: hugr-llvm/src/types.rs +expression: "[[]+[]+[]+[], Unit]+[Bool, []+[]+[]]" --- -"{ i32, { {}, { {} } }, { { i32, {}, {} }, { i32, {}, {}, {} } } }" +"{ i1, i2, i1 }" diff --git a/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_3.snap b/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_3.snap index 695c5e8c0..86a453cbe 100644 --- a/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_3.snap +++ b/hugr-llvm/src/snapshots/hugr_llvm__types__test__sum_type_to_llvm@llvm14_3.snap @@ -1,5 +1,5 @@ --- -source: src/types.rs -expression: "[]+[]" +source: hugr-llvm/src/types.rs +expression: Bool --- -"{ i32, {}, {} }" +"i1" diff --git a/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_5.snap b/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_5.snap index ddf37e9f5..8d428bce7 100644 --- a/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_5.snap +++ b/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_5.snap @@ -1,5 +1,5 @@ --- -source: src/types.rs -expression: "[int([BoundedNat { n: 2 }])]" +source: hugr-llvm/src/types.rs +expression: "[int(2)]" --- -"{ { i8 } }" +"i8" diff --git a/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_6.snap b/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_6.snap index 7ff728ad5..5553ed884 100644 --- a/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_6.snap +++ b/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_6.snap @@ -1,5 +1,5 @@ --- -source: src/types.rs -expression: "[int([BoundedNat { n: 6 }]), []]+[[]+[], int([BoundedNat { n: 2 }])]" +source: hugr-llvm/src/types.rs +expression: "[int(6), Unit]+[Bool, int(2)]" --- -"{ i32, { i64, { {} } }, { { i32, {}, {} }, i8 } }" +"{ i1, i8, i64, i1 }" diff --git a/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_7.snap b/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_7.snap index 076ea483d..58f531d51 100644 --- a/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_7.snap +++ b/hugr-llvm/src/snapshots/hugr_llvm__types__test__type_to_llvm@llvm14_7.snap @@ -1,5 +1,5 @@ --- -source: src/types.rs -expression: "Function([[]+[]] -> [[]][[]+[]+[]])" +source: hugr-llvm/src/types.rs +expression: "[Bool] -> [[]+[]+[]]" --- -"{ i32, {}, {}, {} } ({ i32, {}, {} })*" +"i2 (i1)*" diff --git a/hugr-llvm/src/sum.rs b/hugr-llvm/src/sum.rs index 059b37873..92422ac87 100644 --- a/hugr-llvm/src/sum.rs +++ b/hugr-llvm/src/sum.rs @@ -1,6 +1,10 @@ +mod layout; + +use std::{iter, slice}; + use crate::types::{HugrSumType, TypingSession}; -use anyhow::{anyhow, Result}; +use anyhow::{anyhow, ensure, Result}; use delegate::delegate; use hugr_core::types::TypeRow; use inkwell::{ @@ -9,7 +13,16 @@ use inkwell::{ types::{AnyType, AsTypeRef, BasicType, BasicTypeEnum, IntType, StructType}, values::{AnyValue, AsValueRef, BasicValue, BasicValueEnum, IntValue, StructValue}, }; -use itertools::{zip_eq, Itertools}; +use itertools::{izip, Itertools as _}; + +pub fn elidable_type<'c>(ty: impl BasicType<'c>) -> bool { + let ty = ty.as_basic_type_enum(); + match ty { + BasicTypeEnum::ArrayType(array_type) => array_type.is_empty(), + BasicTypeEnum::StructType(struct_type) => struct_type.count_fields() == 0, + _ => false, + } +} fn get_variant_typerow(sum_type: &HugrSumType, tag: u32) -> Result { sum_type @@ -18,38 +31,281 @@ fn get_variant_typerow(sum_type: &HugrSumType, tag: u32) -> Result { .and_then(|tr| Ok(TypeRow::try_from(tr.clone())?)) } -fn sum_type_has_tag_field(st: &HugrSumType) -> bool { - st.num_variants() >= 2 +/// Returns an `undef` value for any [BasicType]. +fn basic_type_undef<'c>(t: impl BasicType<'c>) -> BasicValueEnum<'c> { + let t = t.as_basic_type_enum(); + match t { + BasicTypeEnum::ArrayType(t) => t.get_undef().as_basic_value_enum(), + BasicTypeEnum::FloatType(t) => t.get_undef().as_basic_value_enum(), + BasicTypeEnum::IntType(t) => t.get_undef().as_basic_value_enum(), + BasicTypeEnum::PointerType(t) => t.get_undef().as_basic_value_enum(), + BasicTypeEnum::StructType(t) => t.get_undef().as_basic_value_enum(), + BasicTypeEnum::VectorType(t) => t.get_undef().as_basic_value_enum(), + } } +/// Returns an `undef` value for any [BasicType]. +fn basic_type_poison<'c>(t: impl BasicType<'c>) -> BasicValueEnum<'c> { + let t = t.as_basic_type_enum(); + match t { + BasicTypeEnum::ArrayType(t) => t.get_poison().as_basic_value_enum(), + BasicTypeEnum::FloatType(t) => t.get_poison().as_basic_value_enum(), + BasicTypeEnum::IntType(t) => t.get_poison().as_basic_value_enum(), + BasicTypeEnum::PointerType(t) => t.get_poison().as_basic_value_enum(), + BasicTypeEnum::StructType(t) => t.get_poison().as_basic_value_enum(), + BasicTypeEnum::VectorType(t) => t.get_poison().as_basic_value_enum(), + } +} + +#[derive(Debug, Clone, derive_more::Display)] +pub struct LLVMSumType<'c>(LLVMSumTypeEnum<'c>); + /// The opaque representation of a [HugrSumType]. /// -/// Using the public methods of this type one emit "tag"s,"untag"s, and -/// "get_tag"s while not exposing the underlying LLVM representation. +/// Provides an `impl`s of `BasicType`, allowing interoperation with other +/// inkwell tools. +/// +/// To obtain an [LLVMSumType] corresponding to a [HugrSumType] use +/// [LLVMSumType::new] or [LLVMSumType::try_new]. +/// +/// Any such [LLVMSumType] has a fixed underlying LLVM type, which can be +/// obtained by [BasicValue::as_basic_type_enum] or [LLVMSumType::value_type]. +/// Note this type is unspecified, and we go to some effort to ensure that it is +/// minimal and efficient. In particular unit types such as empty structs(`{}`) +/// are elided from the LLVM type where possible. See [elidable_type] for the +/// specification of which types are elided. +/// +/// Each [LLVMSumType] has an associated [IntType] tag type, which can be +/// obtained via [LLVMSumType::tag_type]. +/// +/// The value type [LLVMSumValue] represents values of this type. To obtain an +/// [LLVMSumValue] use [LLVMSumType::build_tag] or [LLVMSumType::value]. +/// /// -/// We offer impls of [BasicType] and parent traits. -#[derive(Debug, Clone)] -pub struct LLVMSumType<'c>(StructType<'c>, HugrSumType); - impl<'c> LLVMSumType<'c> { - pub fn try_new2( + delegate! { + to self.0 { + /// The underlying LLVM type. + pub fn value_type(&self) -> BasicTypeEnum<'c>; + /// The type of the value that would be returned by [LLVMSumValue::build_get_tag]. + pub fn tag_type(&self) -> IntType<'c>; + /// The number of variants in the represented [HugrSumType]. + pub fn num_variants(&self) -> usize; + /// The number of fields in the `tag`th variant of the represented [HugrSumType]. + /// Panics if `tag` is out of bounds. + pub fn num_fields_for_variant(&self, tag: usize) -> usize; + /// The LLVM types representing the fields in the `tag` variant of the represented [HugrSumType]. + /// Panics if `tag` is out of bounds. + pub fn fields_for_variant(&self, tag: usize) -> &[BasicTypeEnum<'c>]; + } + } + + /// Constructs a new [LLVMSumType] from a [HugrSumType], using `session` to + /// determine the types of the fields. + pub fn try_new(session: &TypingSession<'c, '_>, sum_type: HugrSumType) -> Result { + Ok(Self(LLVMSumTypeEnum::try_new(session, sum_type)?)) + } + + /// Constructs a new [LLVMSumType] from a `Vec` of variants. + /// Each variant is a `Vec` of LLVM types each corresponding to a field in the sum. + pub fn new( context: &'c Context, - variants: Vec>>, - sum_type: HugrSumType, - ) -> Result { - let has_tag_field = sum_type_has_tag_field(&sum_type); - let types = has_tag_field - .then_some(context.i32_type().as_basic_type_enum()) - .into_iter() - .chain( - variants - .iter() - .map(|lty_vec| context.struct_type(lty_vec, false).into()), - ) - .collect_vec(); - Ok(Self(context.struct_type(&types, false), sum_type.clone())) - } - /// Attempt to create a new `LLVMSumType` from a [HugrSumType]. + variant_types: impl Into>>>, + ) -> Self { + Self(LLVMSumTypeEnum::new(context, variant_types.into())) + } + + /// Returns an constant `undef` value of the underlying LLVM type. + pub fn get_undef(&self) -> impl BasicValue<'c> { + basic_type_undef(self.0.value_type()) + } + + /// Returns an constant `poison` value of the underlying LLVM type. + pub fn get_poison(&self) -> impl BasicValue<'c> { + basic_type_poison(self.0.value_type()) + } + + /// Emits instructions to construct an [LLVMSumValue] of this type. The + /// value will represent the `tag`th variant. + /// + /// TODO tag + vs. + pub fn build_tag( + &self, + builder: &Builder<'c>, + tag: usize, + vs: Vec>, + ) -> Result> { + self.value(self.0.build_tag(builder, tag, vs)?) + } + + /// Returns an [LLVMSumValue] of this type. + /// + /// Returns an error if `value.get_type() != self.value_type()`. + pub fn value(&self, value: impl BasicValue<'c>) -> Result> { + LLVMSumValue::try_new(value, self.clone()) + } +} + +/// The internal representation of a [HugrSumType]. +/// +/// This type is not public, so that it can be changed without breaking users. +#[derive(Debug, Clone)] +enum LLVMSumTypeEnum<'c> { + /// A Sum type with a single variant and all-elidable fields. + /// Represented by `{}` + /// Values of this type contain no information, so they never need to be + /// stored. One can always use `undef` to materialize a value of this type. + /// Represented by an empty struct. + Unit { + /// The LLVM types of the fields. One entry for each field in the Hugr + /// variant. Each field must be elidable. + variant_types: Vec>, + /// The LLVM type of the tag. Always `i1` for now. + /// We store it here so because otherwise we would need a &[Context] to + /// construct it. + tag_type: IntType<'c>, + /// The underlying LLVM type. Always `{}` for now. + value_type: StructType<'c>, + }, + /// A Sum type with more than one variant and all elidable fields. + /// Values of this type contain information only in their tag. + /// Represented by the value of their tag. + NoFields { + /// The LLVM types of the fields. One entry for each variant, with that + /// entry containing one entry per Hugr field in the variant. Each field + /// must be elidable. + variant_types: Vec>>, + /// The underlying LLVM type. For now it is the smallest integer type + /// large enough to index the variants. + value_type: IntType<'c>, + }, + /// A Sum type with a single variant and exactly one non-elidable field. + /// Values of this type contain information only in the value of their + /// non-elidable field. + /// Represented by the value of their non-elidable field. + SingleVariantSingleField { + /// The LLVM types of the fields. One entry for each Hugr field in the single + /// variant. + variant_types: Vec>, + /// The index into variant_types of the non-elidable field. + field_index: usize, + /// The LLVM type of the tag. Always `i1` for now. + /// We store it here so because otherwise we would need a &[Context] to + /// construct it. + tag_type: IntType<'c>, + }, + /// A Sum type with a single variant and more than one non-elidable field. + /// Values of this type contain information in the values of their + /// non-elidable fields. + /// Represented by a struct containing each elidable field. + SingleVariantMultiField { + /// The LLVM types of the fields. One entry for each Hugr field in the + /// single variant. + variant_types: Vec>, + /// For each field, an index into the fields of `value_type` + field_indices: Vec>, + /// The LLVM type of the tag. Always `i1` for now. + /// We store it here so because otherwise we would need a &[Context] to + /// construct it. + tag_type: IntType<'c>, + /// The underlying LLVM type. Has one field for each non-elidable field + /// in the single variant. + value_type: StructType<'c>, + }, + /// A Sum type with multiple variants and at least one non-elidable field. + /// Values of this type contain information in their tag and in the values + /// of their non-elidable fields. + /// Represented by a struct containing a tag and fields enough to store the + /// non-elidable fields of any one variant. + MultiVariant { + /// The LLVM types of the fields. One entry for each variant, with that + /// entry containing one entry per Hugr field in the variant. + variant_types: Vec>>, + /// For each field in each variant, an index into the fields of `value_type`. + field_indices: Vec>>, + /// The underlying LLVM type. The first field is of `tag_type`. The + /// remaining fields are minimal such that any one variant can be + /// injectively mapped into those fields. + value_type: StructType<'c>, + }, +} + +/// Returns the smallest width for an integer type to be able to represent values smaller than `num_variants +fn tag_width_for_num_variants(num_variants: usize) -> u32 { + debug_assert!(num_variants >= 1); + if num_variants == 1 { + return 1; + } + (num_variants - 1).ilog2() + 1 +} + +impl<'c> LLVMSumTypeEnum<'c> { + /// Constructs a new [LLVMSumTypeEnum] from a `Vec` of variants. + /// Each variant is a `Vec` of LLVM types each corresponding to a field in the sum. + pub fn new(context: &'c Context, variant_types: Vec>>) -> Self { + let result = match variant_types.len() { + 0 => panic!( + "LLVMSumType constructed with no variants. Void is not representable in LLVM" + ), + 1 => { + let variant_types = variant_types.into_iter().exactly_one().unwrap(); + let (fields, field_indices) = + layout::layout_variants(slice::from_ref(&variant_types)); + let field_indices = field_indices.into_iter().exactly_one().unwrap(); + match fields.len() { + 0 => Self::Unit { + variant_types, + tag_type: context.bool_type(), + value_type: context.struct_type(&[], false), + }, + 1 => { + let field_index = field_indices + .into_iter() + .enumerate() + .filter_map(|(i, f_i)| f_i.is_some().then_some(i)) + .exactly_one() + .unwrap(); + Self::SingleVariantSingleField { + variant_types, + field_index, + tag_type: context.bool_type(), + } + } + _num_fields => Self::SingleVariantMultiField { + variant_types, + field_indices, + tag_type: context.bool_type(), + value_type: context.struct_type(&fields, false), + }, + } + } + num_variants => { + let (mut fields, field_indices) = layout::layout_variants(&variant_types); + let tag_type = + context.custom_width_int_type(tag_width_for_num_variants(num_variants)); + if fields.is_empty() { + Self::NoFields { + variant_types, + value_type: tag_type, + } + } else { + // prefix the tag fields + fields.insert(0, tag_type.into()); + let value_type = context.struct_type(&fields, false); + Self::MultiVariant { + variant_types, + field_indices, + value_type, + } + } + } + }; + result + } + + /// Create to create a new `LLVMSumType` from a [HugrSumType]. + /// + /// Returns an error if any field cannot be converted to LLVM types. pub fn try_new(session: &TypingSession<'c, '_>, sum_type: HugrSumType) -> Result { assert!(sum_type.num_variants() < u32::MAX as usize); let variants = (0..sum_type.num_variants()) @@ -60,114 +316,154 @@ impl<'c> LLVMSumType<'c> { .collect::>>() }) .collect::>>()?; - Self::try_new2(session.iw_context(), variants, sum_type) - } - /// Returns an LLVM constant value of `undef`. - pub fn get_undef(&self) -> impl BasicValue<'c> { - self.0.get_undef() - } - - /// Returns an LLVM constant value of `poison`. - pub fn get_poison(&self) -> impl BasicValue<'c> { - self.0.get_poison() + Ok(Self::new(session.iw_context(), variants)) } /// Emit instructions to build a value of type `LLVMSumType`, being of variant `tag`. + /// + /// Returns an error if: + /// * `tag` is out of bounds + /// * `vs` does not have a length equal to the length of the `tag`th + /// variant of the represented Hugr type. + /// * Any entry of `vs` does not have the expected type. pub fn build_tag( &self, builder: &Builder<'c>, tag: usize, vs: Vec>, ) -> Result> { - let expected_num_fields = self.variant_num_fields(tag)?; - if expected_num_fields != vs.len() { - Err(anyhow!("LLVMSumType::build: wrong number of fields: expected: {expected_num_fields} actual: {}", vs.len()))? - } - let variant_field_index = self.get_variant_field_index(tag); - let row_t = self - .0 - .get_field_type_at_index(variant_field_index as u32) - .ok_or(anyhow!("LLVMSumType::build: no field type at index")) - .and_then(|row_t| { - if !row_t.is_struct_type() { - Err(anyhow!("LLVMSumType::build"))? + ensure!(tag < self.num_variants()); + ensure!(vs.len() == self.num_fields_for_variant(tag)); + ensure!(iter::zip(&vs, self.fields_for_variant(tag)).all(|(x, y)| &x.get_type() == y)); + let value = match self { + Self::Unit { value_type, .. } => value_type.get_undef().as_basic_value_enum(), + Self::NoFields { value_type, .. } => value_type + .const_int(tag as u64, false) + .as_basic_value_enum(), + Self::SingleVariantSingleField { field_index, .. } => vs[*field_index], + Self::SingleVariantMultiField { + value_type, + field_indices, + .. + } => { + let mut value = value_type.get_poison(); + for (mb_i, v) in itertools::zip_eq(field_indices, vs) { + if let Some(i) = mb_i { + value = builder + .build_insert_value(value, v, *i as u32, "")? + .into_struct_value(); + } } - Ok(row_t.into_struct_type()) - })?; - debug_assert!(zip_eq(vs.iter(), row_t.get_field_types().into_iter()) - .all(|(lhs, rhs)| lhs.as_basic_value_enum().get_type() == rhs)); - let mut row_v = row_t.get_undef(); - for (i, val) in vs.into_iter().enumerate() { - row_v = builder - .build_insert_value(row_v, val, i as u32, "")? - .into_struct_value(); - } - let mut sum_v = self.get_poison().as_basic_value_enum().into_struct_value(); - if self.has_tag_field() { - sum_v = builder - .build_insert_value( - sum_v, - self.get_tag_type().const_int(tag as u64, false), - 0u32, - "", - )? - .into_struct_value(); - } - Ok(builder - .build_insert_value(sum_v, row_v, variant_field_index as u32, "")? - .as_basic_value_enum()) + value.as_basic_value_enum() + } + Self::MultiVariant { + field_indices, + variant_types, + value_type, + } => { + let variant_field_types = &variant_types[tag]; + let variant_field_indices = &field_indices[tag]; + let mut value = builder + .build_insert_value( + value_type.get_poison(), + self.tag_type().const_int(tag as u64, false), + 0, + "", + )? + .into_struct_value(); + for (t, mb_i, v) in izip!(variant_field_types, variant_field_indices, vs) { + ensure!(&v.get_type() == t); + if let Some(i) = mb_i { + value = builder + .build_insert_value(value, v, *i as u32 + 1, "")? + .into_struct_value(); + } + } + value.as_basic_value_enum() + } + }; + debug_assert_eq!(value.get_type(), self.value_type()); + Ok(value) } /// Get the type of the value that would be returned by `build_get_tag`. - pub fn get_tag_type(&self) -> IntType<'c> { - self.0.get_context().i32_type() - } - - fn has_tag_field(&self) -> bool { - sum_type_has_tag_field(&self.1) + pub fn tag_type(&self) -> IntType<'c> { + match self { + Self::Unit { tag_type, .. } => *tag_type, + Self::NoFields { value_type, .. } => *value_type, + Self::SingleVariantSingleField { tag_type, .. } => *tag_type, + Self::SingleVariantMultiField { tag_type, .. } => *tag_type, + Self::MultiVariant { value_type, .. } => value_type + .get_field_type_at_index(0) + .unwrap() + .into_int_type(), + } } - fn get_variant_field_index(&self, tag: usize) -> usize { - tag + (if self.has_tag_field() { 1 } else { 0 }) + /// The underlying LLVM type. + pub fn value_type(&self) -> BasicTypeEnum<'c> { + match self { + Self::Unit { value_type, .. } => (*value_type).into(), + Self::NoFields { value_type, .. } => (*value_type).into(), + Self::SingleVariantSingleField { + field_index, + variant_types, + .. + } => variant_types[*field_index], + Self::SingleVariantMultiField { value_type, .. } + | Self::MultiVariant { value_type, .. } => (*value_type).into(), + } } - fn variant_num_fields(&self, tag: usize) -> Result { - self.get_variant(tag).map(|x| x.len()) + /// The number of variants in the represented [HugrSumType]. + pub fn num_variants(&self) -> usize { + match self { + Self::Unit { .. } + | Self::SingleVariantSingleField { .. } + | Self::SingleVariantMultiField { .. } => 1, + Self::NoFields { variant_types, .. } | Self::MultiVariant { variant_types, .. } => { + variant_types.len() + } + } } - pub fn get_variant(&self, tag: usize) -> Result { - let tr = self - .1 - .get_variant(tag) - .ok_or(anyhow!("Bad variant index {tag} in {}", self.1))? - .to_owned(); - tr.try_into() - .map_err(|rv| anyhow!("Row variable in {}: {rv}", self.1)) + /// The number of fields in the `tag`th variant of the represented [HugrSumType]. + /// Panics if `tag` is out of bounds. + pub(self) fn num_fields_for_variant(&self, variant: usize) -> usize { + self.fields_for_variant(variant).len() } - delegate! { - to self.1 { - pub(self) fn num_variants(&self) -> usize; + /// The LLVM types representing the fields in the `tag` variant of the represented [HugrSumType]. + /// Panics if `tag` is out of bounds. + pub(self) fn fields_for_variant(&self, variant: usize) -> &[BasicTypeEnum<'c>] { + assert!(variant < self.num_variants()); + match self { + Self::SingleVariantSingleField { variant_types, .. } + | Self::SingleVariantMultiField { variant_types, .. } + | Self::Unit { variant_types, .. } => &variant_types[..], + Self::MultiVariant { variant_types, .. } | Self::NoFields { variant_types, .. } => { + &variant_types[variant] + } } } } -impl<'c> From> for BasicTypeEnum<'c> { - fn from(value: LLVMSumType<'c>) -> Self { - value.0.as_basic_type_enum() +impl<'c> From> for BasicTypeEnum<'c> { + fn from(value: LLVMSumTypeEnum<'c>) -> Self { + value.value_type() } } -impl std::fmt::Display for LLVMSumType<'_> { +impl std::fmt::Display for LLVMSumTypeEnum<'_> { fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { - self.0.fmt(f) + self.value_type().fmt(f) } } unsafe impl AsTypeRef for LLVMSumType<'_> { fn as_type_ref(&self) -> inkwell::llvm_sys::prelude::LLVMTypeRef { - self.0.as_type_ref() + BasicTypeEnum::from(self.0.clone()).as_type_ref() } } @@ -176,9 +472,9 @@ unsafe impl<'c> AnyType<'c> for LLVMSumType<'c> {} unsafe impl<'c> BasicType<'c> for LLVMSumType<'c> {} /// A Value equivalent of [LLVMSumType]. Represents a [HugrSumType] Value on the -/// wire, offering functions for deconstructing such Values. +/// wire, offering functions for inspecting and deconstructing such Values. #[derive(Debug)] -pub struct LLVMSumValue<'c>(StructValue<'c>, LLVMSumType<'c>); +pub struct LLVMSumValue<'c>(BasicValueEnum<'c>, LLVMSumType<'c>); impl<'c> From> for BasicValueEnum<'c> { fn from(value: LLVMSumValue<'c>) -> Self { @@ -198,52 +494,81 @@ unsafe impl<'c> BasicValue<'c> for LLVMSumValue<'c> {} impl<'c> LLVMSumValue<'c> { pub fn try_new(value: impl BasicValue<'c>, sum_type: LLVMSumType<'c>) -> Result { - let value: StructValue<'c> = value - .as_basic_value_enum() - .try_into() - .map_err(|_| anyhow!("Not a StructValue"))?; - let (v_t, st_t) = ( - value.get_type().as_basic_type_enum(), - sum_type.as_basic_type_enum(), + let value = value.as_basic_value_enum(); + ensure!( + value.get_type() == sum_type.value_type(), + "Cannot construct LLVMSumValue of type {sum_type} from value of type {}", + value.get_type() ); - if v_t != st_t { - Err(anyhow!( - "LLVMSumValue::new: type of value does not match sum_type: {v_t} != {st_t}" - ))? - } Ok(Self(value, sum_type)) } + pub fn get_type(&self) -> LLVMSumType<'c> { + self.1.clone() + } + /// Emit instructions to read the tag of a value of type `LLVMSumType`. /// /// The type of the value is that returned by [LLVMSumType::get_tag_type]. pub fn build_get_tag(&self, builder: &Builder<'c>) -> Result> { - if self.1.has_tag_field() { - Ok(builder.build_extract_value(self.0, 0, "")?.into_int_value()) - } else { - Ok(self.1.get_tag_type().const_int(0, false)) - } + let result = match self.get_type().0 { + LLVMSumTypeEnum::Unit { tag_type, .. } + | LLVMSumTypeEnum::SingleVariantSingleField { tag_type, .. } + | LLVMSumTypeEnum::SingleVariantMultiField { tag_type, .. } => { + anyhow::Ok(tag_type.const_int(0, false)) + } + LLVMSumTypeEnum::NoFields { .. } => Ok(self.0.into_int_value()), + LLVMSumTypeEnum::MultiVariant { .. } => { + let value: StructValue = self.0.into_struct_value(); + Ok(builder.build_extract_value(value, 0, "")?.into_int_value()) + } + }?; + debug_assert_eq!(result.get_type(), self.tag_type()); + Ok(result) } /// Emit instructions to read the inner values of a value of type /// `LLVMSumType`, on the assumption that it's tag is `tag`. /// - /// If it's tag is not `tag`, the returned values will be poison. + /// If it's tag is not `tag`, the returned values are unspecified. pub fn build_untag( &self, builder: &Builder<'c>, tag: usize, ) -> Result>> { - debug_assert!(tag < self.1 .1.num_variants()); - - let v = builder - .build_extract_value(self.0, self.1.get_variant_field_index(tag) as u32, "")? - .into_struct_value(); - let r = (0..v.get_type().count_fields()) - .map(|i| Ok(builder.build_extract_value(v, i, "")?)) - .collect::>>()?; - debug_assert_eq!(r.len(), self.1.variant_num_fields(tag).unwrap()); - Ok(r) + ensure!(tag < self.num_variants(), "Bad tag {tag} in {}", self.1); + let results = match self.get_type().0 { + LLVMSumTypeEnum::Unit { .. } | LLVMSumTypeEnum::NoFields { .. } => Ok(vec![]), + LLVMSumTypeEnum::SingleVariantSingleField { .. } => Ok(vec![self.0]), + LLVMSumTypeEnum::SingleVariantMultiField { .. } => { + let value = self.0.into_struct_value(); + (0..value.get_type().count_fields()) + .map(|i| anyhow::Ok(builder.build_extract_value(value, i, "")?)) + .collect() + } + LLVMSumTypeEnum::MultiVariant { + variant_types, + field_indices, + .. + } => { + let value = self.0.into_struct_value(); + itertools::zip_eq(&variant_types[tag], &field_indices[tag]) + .map(|(ty, mb_i)| { + if let Some(i) = mb_i { + Ok(builder.build_extract_value(value, *i as u32 + 1, "")?) + } else { + Ok(basic_type_undef(*ty)) + } + }) + .collect() + } + }?; + #[cfg(debug_assertions)] + { + let result_types = results.iter().map(|x| x.get_type()).collect_vec(); + assert_eq!(&result_types, self.get_type().fields_for_variant(tag)); + } + Ok(results) } pub fn build_destructure( @@ -256,7 +581,7 @@ impl<'c> LLVMSumValue<'c> { .ok_or(anyhow!("No current insertion point"))?; let context = orig_bb.get_context(); let mut last_bb = orig_bb; - let tag_ty = self.1.get_tag_type(); + let tag_ty = self.tag_type(); let mut cases = vec![]; @@ -280,7 +605,98 @@ impl<'c> LLVMSumValue<'c> { delegate! { to self.1 { /// Get the type of the value that would be returned by `build_get_tag`. - pub fn get_tag_type(&self) -> IntType<'c>; + pub fn tag_type(&self) -> IntType<'c>; + /// The number of variants in the represented [HugrSumType]. + pub fn num_variants(&self) -> usize; + } + } +} + +#[cfg(test)] +mod test { + use hugr_core::extension::prelude::{bool_t, usize_t}; + use rstest::rstest; + + use crate::{ + test::{llvm_ctx, TestContext}, + types::HugrType, + }; + + use super::*; + + #[rstest] + #[case(1, 1)] + #[case(2, 1)] + #[case(3, 2)] + #[case(4, 2)] + #[case(5, 3)] + #[case(8, 3)] + #[case(9, 4)] + fn tag_width(#[case] num_variants: usize, #[case] expected: u32) { + assert_eq!(tag_width_for_num_variants(num_variants), expected); + } + + #[rstest] + fn sum_types(mut llvm_ctx: TestContext) { + llvm_ctx.add_extensions(|cem| cem.add_default_prelude_extensions()); + let ts = llvm_ctx.get_typing_session(); + let iwc = ts.iw_context(); + let empty_struct = iwc.struct_type(&[], false).as_basic_type_enum(); + let i1 = iwc.bool_type().as_basic_type_enum(); + let i2 = iwc.custom_width_int_type(2).as_basic_type_enum(); + let i64 = iwc.i64_type().as_basic_type_enum(); + + { + // one-variant-no-fields -> empty_struct + let hugr_type = HugrType::UNIT; + assert_eq!(ts.llvm_type(&hugr_type).unwrap(), empty_struct.clone()); + } + + { + // one-variant-elidable-fields -> empty_struct + let hugr_type = HugrType::new_tuple(vec![HugrType::UNIT, HugrType::UNIT]); + assert_eq!(ts.llvm_type(&hugr_type).unwrap(), empty_struct.clone()); + } + + { + // multi-variant-no-fields -> bare tag + let hugr_type = bool_t(); + assert_eq!(ts.llvm_type(&hugr_type).unwrap(), i1.clone()); + } + + { + // multi-variant-elidable-fields -> bare tag + let hugr_type = HugrType::new_sum(vec![vec![HugrType::UNIT]; 3]); + assert_eq!(ts.llvm_type(&hugr_type).unwrap(), i2.clone()); + } + + { + // one-variant-one-field -> bare field + let hugr_type = HugrType::new_tuple(vec![usize_t()]); + assert_eq!(ts.llvm_type(&hugr_type).unwrap(), i64.clone()); + } + + { + // one-variant-one-non-elidable-field -> bare field + let hugr_type = HugrType::new_tuple(vec![HugrType::UNIT, usize_t()]); + assert_eq!(ts.llvm_type(&hugr_type).unwrap(), i64.clone()); + } + + { + // one-variant-multi-field -> struct-of-fields + let hugr_type = HugrType::new_tuple(vec![usize_t(), bool_t(), HugrType::UNIT]); + let llvm_type = iwc.struct_type(&[i64, i1], false).into(); + assert_eq!(ts.llvm_type(&hugr_type).unwrap(), llvm_type); + } + + { + // multi-variant-multi-field -> struct-of-fields-with-tag + let hugr_type1 = + HugrType::new_sum([vec![bool_t(), HugrType::UNIT, usize_t()], vec![usize_t()]]); + let hugr_type2 = HugrType::new_sum([vec![usize_t(), bool_t()], vec![usize_t()]]); + let llvm_type = iwc.struct_type(&[i1, i64, i1], false).into(); + assert_eq!(ts.llvm_type(&hugr_type1).unwrap(), llvm_type); + assert_eq!(ts.llvm_type(&hugr_type2).unwrap(), llvm_type); } } } diff --git a/hugr-llvm/src/sum/layout.rs b/hugr-llvm/src/sum/layout.rs new file mode 100644 index 000000000..2efa5d197 --- /dev/null +++ b/hugr-llvm/src/sum/layout.rs @@ -0,0 +1,216 @@ +//! The algorithm for computing the fields of the struct representing a +//! [HugrSumType]. +//! +use std::borrow::Cow; +use std::cmp::Reverse; +use std::collections::BTreeMap; +use std::fmt; +use std::ops::RangeFrom; + +use inkwell::types::{BasicType, BasicTypeEnum}; +use itertools::Itertools as _; + +use super::elidable_type; + +/// Compute the layout of the non-tag fields of the struct representing a +/// HugrSumType +/// +/// The first return value are the non-tag fields of the struct. +/// +/// The second return value is a per-variant-per-field `Option`. If that +/// value is `None`, then the field should be elided from the struct. Values +/// for this field should be materialized via `undef`. If that value is +/// `Some(i)` then values of this field should be read and written to the `i`th +/// field of the struct. +pub(super) fn layout_variants<'c>( + variants: impl AsRef<[Vec>]>, +) -> (Vec>, Vec>>) { + let variants = variants.as_ref(); + let (sorted_fields, layout) = layout_variants_impl::( + variants + .iter() + .cloned() + .map(|x| x.into_iter().map_into().collect_vec()) + .collect_vec(), + |x| elidable_type(x.0), + ); + let sorted_fields = sorted_fields.into_iter().map_into().collect_vec(); + (sorted_fields, layout) +} + +fn size_of_type<'c>(t: impl BasicType<'c>) -> Option { + match t.as_basic_type_enum() { + BasicTypeEnum::ArrayType(t) => t.size_of().and_then(|x| x.get_zero_extended_constant()), + BasicTypeEnum::FloatType(t) => t.size_of().get_zero_extended_constant(), + BasicTypeEnum::IntType(t) => t.size_of().get_zero_extended_constant(), + BasicTypeEnum::PointerType(t) => t.size_of().get_zero_extended_constant(), + BasicTypeEnum::StructType(t) => t.size_of().and_then(|x| x.get_zero_extended_constant()), + BasicTypeEnum::VectorType(t) => t.size_of().and_then(|x| x.get_zero_extended_constant()), + } +} + +#[derive(derive_more::Debug, Clone, PartialEq, Eq)] +/// `BasicTypeEnum` does not `impl` `Ord`. We use this type to put an ordering `BasicTypeEnum`, +/// first by reverse-size and then by, string representation. +struct BasicTypeOrd<'c>( + BasicTypeEnum<'c>, + #[debug(skip)] u64, + #[debug(skip)] Cow<'c, String>, +); + +impl<'c> From> for BasicTypeOrd<'c> { + fn from(t: BasicTypeEnum<'c>) -> Self { + let size = size_of_type(t).unwrap_or(u64::MAX); + Self(t, size, Cow::Owned(format!("{t}"))) + } +} + +impl<'c> From> for BasicTypeEnum<'c> { + fn from(t: BasicTypeOrd<'c>) -> Self { + t.0 + } +} + +impl Ord for BasicTypeOrd<'_> { + fn cmp(&self, other: &Self) -> std::cmp::Ordering { + let key = |x: &Self| Reverse((x.1, x.2.clone())); + key(self).cmp(&key(other)) + } +} + +impl PartialOrd for BasicTypeOrd<'_> { + fn partial_cmp(&self, other: &Self) -> Option { + Some(self.cmp(other)) + } +} + +/// The implemenation of the layout algorithm. +/// We write this generically so that we can test it with simple types. +/// +/// Panics if `variants` is empty. +fn layout_variants_impl( + variants: impl AsRef<[Vec]>, + elide: impl Fn(&T) -> bool, +) -> (Vec, Vec>>) { + let variants = variants.as_ref(); + assert!(!variants.is_empty()); + // * sorted_fields is a Vec with enough copies of each T to represent any + // one variant. It will be the firstu return value. + // * t_to_index_map maps types to the index of the first + // occurence of that type. + let (sorted_fields, t_to_index_map) = { + // t_counts tracks, per-type, the maximum number of fields a variant + // has of that type. + let t_counts = { + let t_counts_per_variant = variants.iter().map(|variant| { + let mut t_counts = BTreeMap::::new(); + for t in variant.iter().flat_map(|t| (!elide(t)).then_some(t)) { + t_counts + .entry(t.clone()) + .and_modify(|count| *count += 1) + .or_insert(1); + } + t_counts + }); + let mut t_counts = BTreeMap::::new(); + for (t, count) in t_counts_per_variant.flatten() { + t_counts + .entry(t) + .and_modify(|x| *x = count.max(*x)) + .or_insert(count); + } + t_counts + }; + let mut t_to_index_map = BTreeMap::::default(); + let mut last_t = None; + let sorted_fields = t_counts + .into_iter() + .flat_map(|(t, count)| itertools::repeat_n(t, count)) + .enumerate() + .map(|(i, t)| { + if last_t.as_ref() != Some(&t) { + last_t = Some(t.clone()); + let _overwritten = t_to_index_map.insert(t.clone(), i).is_some(); + debug_assert!(!_overwritten); + } + t + }) + .collect_vec(); + (sorted_fields, t_to_index_map) + }; + + // the second return value. Here we record, per-variant, which field of + // `sorted_fields` represents each field. + let layout = variants + .iter() + .map(|variant| { + let mut t_to_range_map = BTreeMap::>::new(); + variant + .iter() + .map(|t| { + (!elide(t)).then(|| { + let field_index_iter = t_to_range_map + .entry(t.clone()) + .or_insert(t_to_index_map[t]..); + field_index_iter + .next() + .expect("We have ensured that there are enough fields of type t") + }) + }) + .collect_vec() + }) + .collect_vec(); + + #[cfg(debug_assertions)] + { + for (variant, variant_layout) in itertools::zip_eq(variants, layout.iter()) { + for (t, &mb_field_index) in itertools::zip_eq(variant, variant_layout) { + if elide(t) { + assert!(mb_field_index.is_none()) + } else { + assert_eq!( + Some(t), + mb_field_index.map(|field_index| &sorted_fields[field_index]) + ); + } + } + } + } + + (sorted_fields, layout) +} + +#[cfg(test)] +mod test { + use rstest::rstest; + + use super::*; + + #[rstest] + #[should_panic] + #[case::none([], [], [])] + #[case::one_empty([vec![]], [vec![]], [])] + #[case::multi_empty([vec![],vec![]], [vec![],vec![]], [])] + #[case::one_nonempty([vec![5]], [vec![Some(0)]], [5])] + #[case::one_nonempty_dups([vec![5,5]], [vec![Some(0),Some(1)]], [5,5])] + #[case::one_nonempty_all_elidable([vec![0,0]], [vec![None,None]], [])] + #[case::one_nonempty_some_elidable([vec![0, 1]], [vec![None,Some(0)]], [1])] + #[case::one_nonempty_one_empty([vec![5],vec![]], [vec![Some(0)],vec![]], [5])] + #[case::two_nonempty_no_dups_in_order([vec![5],vec![6]], [vec![Some(0)],vec![Some(1)]], [5,6])] + #[case::two_nonempty_no_dups_rev_order([vec![8],vec![7]], [vec![Some(1)],vec![Some(0)]], [7,8])] + #[case::two_nonempty_all_dups([vec![9,10],vec![10,9]], [vec![Some(0),Some(1)],vec![Some(1),Some(0)]], [9,10])] + #[case::three_nonempty_some_dups([vec![9,10],vec![9],vec![11,10,-1]], [vec![Some(1),Some(2)],vec![Some(1)],vec![Some(3),Some(2),Some(0)]], [-1,9,10,11])] + // #[case::two_nonempty_all_elidable([vec![0],vec![0],vec![11,10,-1]], [vec![Some(1),Some(2)],vec![Some(1)],vec![Some(3),Some(2),Some(0)]], [-1,9,10,11])] + fn layout_variants( + #[case] variants: impl AsRef<[Vec]>, + #[case] expected_layout: impl AsRef<[Vec>]>, + #[case] expected_fields: impl AsRef<[i32]>, + ) { + fn elidable(&x: &i32) -> bool { + x == 0 + } + let (sorted_fields, layout) = layout_variants_impl(variants, elidable); + assert_eq!(sorted_fields.as_slice(), expected_fields.as_ref()); + assert_eq!(layout.as_slice(), expected_layout.as_ref()); + } +} diff --git a/hugr-llvm/src/types.rs b/hugr-llvm/src/types.rs index b983f81f3..c91231c6c 100644 --- a/hugr-llvm/src/types.rs +++ b/hugr-llvm/src/types.rs @@ -124,9 +124,9 @@ pub mod test { } #[rstest] - #[case(0, SumType::new_unary(0))] + // #[case(0, SumType::new_unary(0))] #[case(1, SumType::new_unary(1))] - #[case(2,SumType::new([vec![Type::new_unit_sum(0), Type::new_unit_sum(1)], vec![Type::new_unit_sum(2), Type::new_unit_sum(3)]]))] + #[case(2,SumType::new([vec![Type::new_unit_sum(4), Type::new_unit_sum(1)], vec![Type::new_unit_sum(2), Type::new_unit_sum(3)]]))] #[case(3, SumType::new_unary(2))] fn sum_types(#[case] _id: i32, #[with(_id)] llvm_ctx: TestContext, #[case] st: SumType) { assert_snapshot!(