From 354b90d3b0fabf536359d7bcf945b9b6a4620c97 Mon Sep 17 00:00:00 2001
From: maxgerhardt <maximilian.gerhardt@rub.de>
Date: Sat, 6 Jan 2024 19:28:00 +0100
Subject: [PATCH] Sync latest firmware

---
 src/main.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/main.c b/src/main.c
index 8d94e9b..7f4d4cb 100644
--- a/src/main.c
+++ b/src/main.c
@@ -4,22 +4,22 @@
 #include "uart.h"
 #include "swio.h"
 
-#define TARGET_NRESET_PORT  PORTB
-#define TARGET_NRESET_DDR   DDRB
-#define TARGET_NRESET_BIT   1
+#define TARGET_POWER_PORT  PORTB
+#define TARGET_POWER_DDR   DDRB
+#define TARGET_POWER_BIT   1
 
-void target_reset(int x) {
+void target_power(int x) {
     if (x)
-        TARGET_NRESET_PORT &= ~_BV(TARGET_NRESET_BIT);
+        TARGET_POWER_PORT |= _BV(TARGET_POWER_BIT);
     else
-        TARGET_NRESET_PORT |= _BV(TARGET_NRESET_BIT);
+        TARGET_POWER_PORT &= ~_BV(TARGET_POWER_BIT);
 }
 
 #define PROTOCOL_START     '!'
 #define PROTOCOL_ACK       '+'
 #define PROTOCOL_TEST      '?'
-#define PROTOCOL_RESET     'a'
-#define PROTOCOL_NORES     'A'
+#define PROTOCOL_POWER_ON  'p'
+#define PROTOCOL_POWER_OFF 'P'
 #define PROTOCOL_WRITE_REG 'w'
 #define PROTOCOL_READ_REG  'r'
 
@@ -28,7 +28,7 @@ int main() {
     uint32_t val;
 
     // Make the target reset pin an output.
-    TARGET_NRESET_DDR |= _BV(TARGET_NRESET_BIT);
+    TARGET_POWER_DDR |= _BV(TARGET_POWER_BIT);
 
     uart_init();
     swio_init();
@@ -39,12 +39,12 @@ int main() {
             case PROTOCOL_TEST:
                 fputc(PROTOCOL_ACK, uart);
                 break;
-            case PROTOCOL_RESET:
-                target_reset(1);
+            case PROTOCOL_POWER_ON:
+                target_power(1);
                 fputc(PROTOCOL_ACK, uart);
                 break;
-            case PROTOCOL_NORES:
-                target_reset(0);
+            case PROTOCOL_POWER_OFF:
+                target_power(0);
                 fputc(PROTOCOL_ACK, uart);
                 break;
             case PROTOCOL_WRITE_REG: