How to set Heap size and Vector table base address?

[ZeroTech-SM]

Thank you for "platform-gd32", It makes so easy to develop GD32 with PlatformIO.

but I do now know how to set Heap memory size and Vector table base address.

If you have any answer, please share with me.

[maxgerhardt]

Are you working with the SPL framework or Arduino in your project?

[ZeroTech-SM]

Reply is so quick. Thank you for your speed.

I am using SPL framework not Arduino in my project.

Here is more information.

rocessing genericGD32F103C8 (platform: gd32; board: genericGD32F103C8; framework: spl)
----------Verbose mode can be enabled via -v, --verbose option
CONFIGURATION: https://docs.platformio.org/page/boards/gd32/genericGD32F103C8.html
PLATFORM: GD GD32 (1.0.0+sha.2d74cfe) > GD32F103C8 (20k RAM, 64k Flash)
HARDWARE: GD32F103C8T6 108MHz, 20KB RAM, 64KB Flash
DEBUG: Current (stlink) External (blackmagic, cmsis-dap, jlink, sipeed-rv-debugger, stlink)
PACKAGES:

• framework-spl-gd32 @ 2.10000.0+sha.b7f0688
• toolchain-gccarmnoneeabi @ 1.90201.191206 (9.2.1)
  Warning! Cannot find a linker script for the required board! Firmware will be linked with a default linker script!
  ==== STARTUP FILE: startup_gd32f10x_md.S ======
  SPL libraries are included: True
  CMSIS libraries are included: True
  LDF: Library Dependency Finder -> https://bit.ly/configure-pio-ldf
  LDF Modes: Finder ~ chain, Compatibility ~ soft
  Added CMSIS-DSP library for arm_cortexM3l_math

[maxgerhardt]

I see. Currently this is not well configurable, we will try and change this soon.

For SPL projects, a linker script template is used (https://github.com/CommunityGD32Cores/gd32-pio-spl-package/blob/main/platformio/ldscripts/tpl/linker.tpl#L14-L15). It currently specifies that 512 bytes of heap should be available in RAM. You would currently have to locally modify this file (C:\Users\<user>\.platformio\packages\framework-spl-gd32\tpl\linker.tpl) locally to change this number.

As for the vector base address, we are currently running an old version of the GD32F10x SPL code that does not handle it all, I will update it momentarily. The newest code however also isn't much better, it uses a hardcoded 0x0 offset:

https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32F10x/GD32F10x_Firmware_Library_V2.2.2/Firmware/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c#L45

https://github.com/CommunityGD32Cores/gigadevice-firmware-and-docs/blob/main/GD32F10x/GD32F10x_Firmware_Library_V2.2.2/Firmware/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c#L208-L212

without any #ifndef VECT_TAB_OFFSET :(.

This would of course only set the vector table offset after the firmware has booted, but if you have a bootloader that requires the firmware to be at some address, you also have to modify the start address of the firmware in the ELF file / generated code. Sadly this currently again hardcoded as 0x8000000 in

https://github.com/CommunityGD32Cores/gd32-pio-spl-package/blob/main/platformio/ldscripts/tpl/linker.tpl#L22

which you would also have to change locally.

I have some ideas for handling this better in a way that is consistent with other PlatformIO platforms (e.g. by respecting board_upload.offset_address). I would actually recommend to wait a bit we update the firmware and make the builder scripts better to allow for variable firmware start offsets / vector table offsets -- might take a day or two.

Very many of the heap operations are also untested at this point. I'm not sure if the GCC nosys or newlib-nano even uses the linker section we dedicated for the heap, and doesn't just use the stackpointer plus an offset in its sbrk() implementation. I need to have a closer look at this. We will then release a simple example with bootloader + firmware.

[ZeroTech-SM]

Firstly, Thank you for the answer with very detail information.

as you mentioned, I will make a project with bootloader function.
so, I asked about Vector table.

I will try with your information and wait the change.
Thank you again.

[maxgerhardt]

I've updated the GD32F10x SPL framework and made the necessay code change to allow a reconfigurable VECT_TAB_OFFSET.

I've released a bootloader + application example at https://github.com/CommunityGD32Cores/gd32-pio-projects/tree/main/gd32-spl-bootloader. Could you pio platform update https://github.com/CommunityGD32Cores/platform-gd32.git in the CLI to update and try that example? :)