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drs4command.list
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drs4command.list
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# ****************************************************************
# WaveDump Configuration File
# ****************************************************************
# Open Device
OPEN PCI 0 0 00320000
# OPEN USB 0 0 32100000
CHANNEL_ENABLE 0F
# GNUPlot path
GNUPLOT_PATH "/usr/bin/"
SAVE_CH_HEADER
## adjust trigger delay
#POST_TRIGGER 80 # good value for DREAM pmts
POST_TRIGGER 28 # good value for MCP studies
#BINARY_OUTPUT_FILE
# ****************************************************************
# Generic VME Write to a register of the board
# Syntax: WRITE_REGISTER REG_ADDR REG_DATA
# where REG_ADDR is the 16 bit address offset (Hex) and
# REG_DATA is the 32 bit register value to set (Hex).
# ****************************************************************
# ----------------------------------------------------------------
# Reset the board
# ----------------------------------------------------------------
#WRITE_REGISTER EF24 0
# ----------------------------------------------------------------
# readout speed
# ----------------------------------------------------------------
#WRITE_REGISTER 80D8 2 # frequency 1 GS/sec
WRITE_REGISTER 80D8 1 # 2.5 GS/sec
#WRITE_REGISTER 80D8 0 # 5 GS/sec
# ----------------------------------------------------------------
# BLT Event Number
# ----------------------------------------------------------------
WRITE_REGISTER EF1C 1 # maximum number of events in a Block Transfer
# ----------------------------------------------------------------
# Trigger Source Enable Mask
# ----------------------------------------------------------------
#WRITE_REGISTER 810C C000000f #old
WRITE_REGISTER 810C 00000000
# ----------------------------------------------------------------
# Front Panel Out Enable Mask (for BUSY)
# ----------------------------------------------------------------
WRITE_REGISTER 8110 0000000f # GR0,GR1,Gr3,Gr4 auto trigger
# ----------------------------------------------------------------
# Channel Configuration Register
# Bit 1 = Trigger Overlapped (Must be 0)
# Bit 3 = Test Waveform
# Bit 4 = Sequential Readout (Must be 1)
# Bit 6 = Local Trigger Polarity (0=Rising, 1=Falling)
# Bit 8 = Individual Trigger (Must be 1)
# Bit 11 = Abilitazione TR in readout
# Bit 12 = Abilitazione TR come Trigger
# ----------------------------------------------------------------
WRITE_REGISTER 8000 1950
#TRG NIM Setting
#Group 0,1 (Tr-0)
WRITE_REGISTER 10DC 8000 # OFFSETTRG= 150mV per input NIM
WRITE_REGISTER 10D4 5C16 # STRG about 1.12V (NIM)
#Group 2,3 (Tr-1)
WRITE_REGISTER 12DC 8000 # OFFSETTRG= 150mV per input NIM
WRITE_REGISTER 12D4 5C16 # STRG about 1.12V (NIM)
# ----------------------------------------------------------------
# Post Trigger window (8,5nsec per unit)
# ----------------------------------------------------------------
# was 8 - now optimized for BGO matrix 29OCT2010
WRITE_REGISTER 8114 8
# ----------------------------------------------------------------
# Group Enable Mask
# ----------------------------------------------------------------
# 4-bit mask : write a single digit hex number 1..f
## WRITE_REGISTER 8120 f # Read all 4 groups
## WRITE_REGISTER 8120 1 # Read only first group
WRITE_REGISTER 8120 3 # Read group 0 and group 1
# ----------------------------------------------------------------
# Set sampling length
# ----------------------------------------------------------------
#### WRITE_REGISTER 8020 0001 # acquire 520 sample/ch
#CHANNEL OFFSET
## offset configuration for PMTs (negative signals)
WRITE_REGISTER 1098 F6800 # DAC GROUP0 OFFSET all ch (baseline @ 3440)
WRITE_REGISTER 1198 F6800 # DAC GROUP1 OFFSET all ch
WRITE_REGISTER 1298 F6800 # DAC GROUP2 OFFSET all ch
WRITE_REGISTER 1398 F6800 # DAC GROUP3 OFFSET all ch
#Offset configuration for bipolar signals
##WRITE_REGISTER 1098 F8F00 # DAC GROUP0 OFFSET all ch set to 0mV (baseline @ 2024)
#Offset configuration for MCP (positive signals)
##WRITE_REGISTER 1098 FBF00 # DAC GROUP0 OFFSET all ch (baseline@450)
# Corrisponde a 3000 di base
#WRITE_REGISTER 1098 F7500 # DAC GROUP0 OFFSET all ch
#WRITE_REGISTER 1098 06000 # DAC GROUP0 OFFSET ch0
#WRITE_REGISTER 1098 16000 # DAC GROUP0 OFFSET ch1
#WRITE_REGISTER 1098 26000 # DAC GROUP0 OFFSET ch2
#WRITE_REGISTER 1098 36000 # DAC GROUP0 OFFSET ch3
#WRITE_REGISTER 1098 7A000 # DAC GROUP0 OFFSET ch7
# Corrisponde a 4000 di base
#WRITE_REGISTER 1198 F5950 # DAC GROUP1 OFFSET all ch
#WRITE_REGISTER 1198 0A000 # DAC GROUP1 OFFSET ch0
#WRITE_REGISTER 1198 1A000 # DAC GROUP1 OFFSET ch1
#WRITE_REGISTER 1198 7A000 # DAC GROUP1 OFFSET ch7
# Interrupt configuration:
# syntax: USE_INTERRUPT level status_id event_number mode mask timeout
# where :
# level : the interrupt level (meaningful for VME devices only )
# status_id : the status id (meaningful for VME devices only )
# event_number : the number of events to wait for (>= 1)
# mode : 0 = RORA , 1 = ROAK
# mask : wait mask (hex format) (meaningful for VME devices only )
# timeout : wait timeout (msec)
# USE_INTERRUPT 0 0 1 0 ff 4000