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AliM1543C_ide.cpp
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AliM1543C_ide.cpp
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/* ES40 emulator.
* Copyright (C) 2007-2008 by the ES40 Emulator Project
*
* WWW : http://sourceforge.net/projects/es40
* E-mail : [email protected]
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* Although this is not required, the author would appreciate being notified of,
* and receiving any modifications you may make to the source code that might serve
* the general public.
*/
/**
* \file
* Contains the code for the emulated Ali M1543C IDE chipset part.
*
* $Id: AliM1543C_ide.cpp,v 1.20 2008/03/04 19:20:02 iamcamiel Exp $
*
* X-1.20 Camiel Vanderhoeven 04-MAR-2008
* Merged Brian wheeler's New IDE code into the standard controller.
*
* X-1.19.17 Brian Wheeler 27-FEB-2008
* Re-fire interrupts less often.
*
* X-1.19.16 Brian Wheeler 27-FEB-2008
* Improvement to last fix.
*
* X-1.19.15 Brian Wheeler 27-FEB-2008
* This patch fixes the vms boot problems from ide cdrom and it also
* allowed me to install tru64 -- albeit with timeouts:
* a) Clears the busmaster active bit when the bit 1 is written to the
* busmaster status register.
* b) Attempts to refire the interrupt if the controller seems to have
* missed it -- before the OS declares a timeout.
*
* X-1.19.14 Brian Wheeler 27-FEB-2008
* Avoid compiler warnings.
*
* X-1.19.13 Brian Wheeler 29-JAN-2008
* Avoid firing interrupts that occurred while interrupts were
* disabled.
*
* X-1.19.12 Camiel Vanderhoeven 28-JAN-2008
* Avoid compiler warnings.
*
* X-1.19.11 Brian Wheeler 26-JAN-2008
* Don't repeat interrupt too soon.
*
* X-1.19.10 Camiel Vanderhoeven 24-JAN-2008
* Use new CPCIDevice::do_pci_read and CPCIDevice::do_pci_write.
*
* X-1.19.9 Brian Wheeler 16-JAN-2008
* Less timeouts.
*
* X-1.19.8 Brian Wheeler 14-JAN-2008
* Less messages without debugging enabled.
*
* X-1.19.7 Fang Zhe 13-JAN-2008
* Big-endian support.
*
* X-1.19.6 Camiel Vanderhoeven 12-JAN-2008
* Use disk's SCSI engine for ATAPI devices.
*
* X-1.19.5 Brian Wheeler 10-JAN-2008
* - Stop dividing get_lba_size() by 4 in ATAPI Get Capacity. SRM can
* now boot cdrom images correctly, and OSes can use cdroms effectively...
* at least until they call an unimplemented SCSI command.
*
* X-1.19.4 Brian Wheeler 09-JAN-2008
* - During init, command_in_progress and command_cycle are cleared.
* - Writes to ide_control are processed correctly. Tru64 & FreeBSD
* recognize disks now.
* - interrupt is deasserted when command register is written.
* - Removed a bunch of debugging sections.
* - Made it quieter if DEBUG_IDE wasn't defined -- users should no longer
* see Debug Pause messages.
* - busy is asserted if we're currently processing a packet command when
* drq is deasserted (i.e. when the read buffer is empty). This lets us
* get back into the ATAPI state machine before the host can start
* messing with the controller.
* - Removed pauses for port 0x3n7 -- its really a floppy port.
* - Remove pause when reset is being started.
* - packet dma flag is presented when get_status() is run.
* - ATAPI command 0x1e (media lock) implemented as no-op.
* - ATAPI command 0x43 (read TOC) implemented as a hack.
* - ATAPI read now uses get_block_size() for determining transfers.
* - ATAPI state machine goes from DP34 to DI immediately upon completion
* instead of redirecting through DP2.
* - Added ATA Command 0xc6 (Set Multiple).
* .
*
* X-1.19.3 Brian wheeler 08-JAN-2008
* ATAPI improved.
*
* X-1.19.2 Brian wheeler 08-JAN-2008
* Handle blocksize correctly for ATAPI.
*
* X-1.19.1 Brian wheeler 08-JAN-2008
* Complete rewrite of IDE controller.
*
* X-1.19 Fang Zhe 08-JAN-2008
* Endianess.
*
* X-1.18 Camiel Vanderhoeven 06-JAN-2008
* Leave changing the blocksize to the disk itself.
*
* X-1.17 Camiel Vanderhoeven 04-JAN-2008
* Less messages fprint'ed.
*
* X-1.16 Camiel Vanderhoeven 02-JAN-2008
* Avoid compiler warnings.
*
* X-1.15 Camiel Vanderhoeven 30-DEC-2007
* Print file id on initialization.
*
* X-1.14 Camiel Vanderhoeven 29-DEC-2007
* Compileable with older compilers (VC 6.0). Avoid referencing
* uninitialized data.
*
* X-1.13 Camiel Vanderhoeven 28-DEC-2007
* Throw exceptions rather than just exiting when errors occur.
*
* X-1.12 Camiel Vanderhoeven 28-DEC-2007
* Keep the compiler happy.
*
* X-1.11 Camiel Vanderhoeven 28-DEC-2007
* Only delay IDE interrupts when NO_VMS is defined. (Need to fix this
* properly).
*
* X-1.10 Camiel Vanderhoeven 20-DEC-2007
* More checks if disk exists.
*
* X-1.9 Brian wheeler 19-DEC-2007
* Added basic ATAPI support.
*
* X-1.8 Brian wheeler 17-DEC-2007
* Delayed IDE interrupts. (NetBSD requirement)
*
* X-1.7 Camiel Vanderhoeven 17-DEC-2007
* SaveState file format 2.1
*
* X-1.6 Camiel Vanderhoeven 14-DEC-2007
* Commented out printing each IDE command.
*
* X-1.5 Camiel Vanderhoeven 12-DEC-2007
* Use disk controller base class.
*
* X-1.4 Camiel Vanderhoeven 11-DEC-2007
* Removed last references to ide_command[][].
*
* X-1.3 Camiel Vanderhoeven 11-DEC-2007
* Cleanup.
*
* X-1.2 Camiel Vanderhoeven 11-DEC-2007
* More complete IDE implementation allows NetBSD to recognize disks.
*
* X-1.1 Camiel Vanderhoeven 10-DEC-2007
* Initial version in CVS; this part was split off from the CAliM1543C
* class.
**/
#include "StdAfx.h"
#include "AliM1543C_ide.h"
#include "System.h"
#include <math.h>
#include "gui/scancodes.h"
#include "gui/keymap.h"
#include "AliM1543C.h"
#include "Disk.h"
#define PAUSE(msg) do { printf("Debug Pause: "); printf(msg); getc(stdin); } while(0);
#ifdef DEBUG_IDE
#define DEBUG_IDE_BUSMASTER
#define DEBUG_IDE_COMMAND
#define DEBUG_IDE_DMA
#define DEBUG_IDE_INTERRUPT
#define DEBUG_IDE_REG_COMMAND
#define DEBUG_IDE_REG_CONTROL
#define DEBUG_IDE_PACKET
#endif
u32 AliM1543C_ide_cfg_data[64] = {
/*00*/ 0x522910b9, // CFID: vendor + device
/*04*/ 0x02800000, // CFCS: command + status
/*08*/ 0x0101fac1, // CFRV: class + revision
/*0c*/ 0x00000000, // CFLT: latency timer + cache line size
/*10*/ 0x000001f1, // BAR0:
/*14*/ 0x000003f5, // BAR1:
/*18*/ 0x00000171, // BAR2:
/*1c*/ 0x00000375, // BAR3:
/*20*/ 0x0000f001, // BAR4:
/*24*/ 0x00000000, // BAR5:
/*28*/ 0x00000000, // CCIC: CardBus
/*2c*/ 0x00000000, // CSID: subsystem + vendor
/*30*/ 0x00000000, // BAR6: expansion rom base
/*34*/ 0x00000000, // CCAP: capabilities pointer
/*38*/ 0x00000000,
/*3c*/ 0x040201ff, // CFIT: interrupt configuration
0,0,
/*48*/ 0x4a000000, // UDMA test
/*4c*/ 0x1aba0000, // reserved
0,
/*54*/ 0x44445555, // udma setting + fifo treshold
0,0,0,0,0,0,0,0,
/*78*/ 0x00000021, // ide clock
0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
};
u32 AliM1543C_ide_cfg_mask[64] = {
/*00*/ 0x00000000, // CFID: vendor + device
/*04*/ 0x00000105, // CFCS: command + status
/*08*/ 0x00000000, // CFRV: class + revision
/*0c*/ 0x0000ffff, // CFLT: latency timer + cache line size
/*10*/ 0xfffffff8, // BAR0
/*14*/ 0xfffffffc, // BAR1: CBMA
/*18*/ 0xfffffff8, // BAR2:
/*1c*/ 0xfffffffc, // BAR3:
/*20*/ 0xfffffff0, // BAR4:
/*24*/ 0x00000000, // BAR5:
/*28*/ 0x00000000, // CCIC: CardBus
/*2c*/ 0x00000000, // CSID: subsystem + vendor
/*30*/ 0x00000000, // BAR6: expansion rom base
/*34*/ 0x00000000, // CCAP: capabilities pointer
/*38*/ 0x00000000,
/*3c*/ 0x000000ff, // CFIT: interrupt configuration
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
};
/**
* Constructor.
**/
CAliM1543C_ide::CAliM1543C_ide(CConfigurator * cfg, CSystem * c, int pcibus, int pcidev)
: CDiskController(cfg,c,pcibus,pcidev,2,2) {
if (theIDE != 0)
FAILURE("More than one IDE controller!!\n");
theIDE = this;
c->RegisterClock(this,true);
add_function(0,AliM1543C_ide_cfg_data, AliM1543C_ide_cfg_mask);
add_legacy_io(PRI_COMMAND, 0x1f0, 8);
add_legacy_io(PRI_CONTROL, 0x3f6, 2);
add_legacy_io(SEC_COMMAND, 0x170, 8);
add_legacy_io(SEC_CONTROL, 0x376, 2);
add_legacy_io(PRI_BUSMASTER, 0xf000, 8);
add_legacy_io(SEC_BUSMASTER, 0xf008, 8);
// create scsi busses
CSCSIBus * a = new CSCSIBus(cfg, c);
CSCSIBus * b = new CSCSIBus(cfg, c);
scsi_register(0, a, 7); // scsi id 7 by default
scsi_register(1, b, 7); // scsi id 7 by default
ResetPCI();
printf("%%IDE-I-INIT: New IDE emulator initialized.\n");
}
CAliM1543C_ide::~CAliM1543C_ide()
{
}
void CAliM1543C_ide::ResetPCI()
{
int i,j;
CPCIDevice::ResetPCI();
for (i=0;i<2;i++) {
CONTROLLER(i).bm_status = 0;
CONTROLLER(i).selected = 0;
for (j=0;j<2;j++) {
REGISTERS(i,j).error=0;
COMMAND(i,j).command_in_progress = 0;
COMMAND(i,j).command_cycle = 0;
STATUS(i,j).busy = false;
STATUS(i,j).drive_ready = false;
STATUS(i,j).drq = false;
STATUS(i,j).err = false;
STATUS(i,j).index_pulse = false;
STATUS(i,j).index_pulse_count = 0;
STATUS(i,j).seek_complete = false;
set_signature(i,j);
}
}
}
void CAliM1543C_ide::register_disk(class CDisk * dsk, int bus, int dev)
{
CDiskController::register_disk(dsk, bus, dev);
if (dsk->cdrom())
{
dsk->scsi_register(0,scsi_bus[bus],dev);
dsk->set_atapi_mode();
}
}
static u32 ide_magic1 = 0xB222654D;
static u32 ide_magic2 = 0xD456222C;
/**
* Save state to a Virtual Machine State file.
**/
int CAliM1543C_ide::SaveState(FILE *f)
{
long ss = sizeof(state);
int res;
if (res = CPCIDevice::SaveState(f))
return res;
fwrite(&ide_magic1,sizeof(u32),1,f);
fwrite(&ss,sizeof(long),1,f);
fwrite(&state,sizeof(state),1,f);
fwrite(&ide_magic2,sizeof(u32),1,f);
printf("%s: %d bytes saved.\n",devid_string,(int)ss);
return 0;
}
/**
* Restore state from a Virtual Machine State file.
**/
int CAliM1543C_ide::RestoreState(FILE *f)
{
long ss;
u32 m1;
u32 m2;
int res;
size_t r;
if (res = CPCIDevice::RestoreState(f))
return res;
r = fread(&m1,sizeof(u32),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
if (m1 != ide_magic1)
{
printf("%s: MAGIC 1 does not match!\n",devid_string);
return -1;
}
fread(&ss,sizeof(long),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
if (ss != sizeof(state))
{
printf("%s: STRUCT SIZE does not match!\n",devid_string);
return -1;
}
fread(&state,sizeof(state),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
r = fread(&m2,sizeof(u32),1,f);
if (r!=1)
{
printf("%s: unexpected end of file!\n",devid_string);
return -1;
}
if (m2 != ide_magic2)
{
printf("%s: MAGIC 1 does not match!\n",devid_string);
return -1;
}
printf("%s: %d bytes restored.\n",devid_string,(int)ss);
return 0;
}
/*
* Region read/write redirection
*/
u32 CAliM1543C_ide::ReadMem_Legacy(int index, u32 address, int dsize) {
int channel = 0;
switch(index) {
case SEC_COMMAND:
channel=1;
case PRI_COMMAND:
return ide_command_read(channel,address,dsize);
case SEC_CONTROL:
channel=1;
case PRI_CONTROL:
return ide_control_read(channel,address);
case SEC_BUSMASTER:
channel=1;
case PRI_BUSMASTER:
return ide_busmaster_read(channel,address,dsize);
}
return 0;
}
void CAliM1543C_ide::WriteMem_Legacy(int index, u32 address, int dsize, u32 data) {
int channel = 0;
switch(index) {
case SEC_COMMAND:
channel=1;
case PRI_COMMAND:
ide_command_write(channel,address,dsize,data);
break;
case SEC_CONTROL:
channel=1;
case PRI_CONTROL:
ide_control_write(channel,address,data);
break;
case SEC_BUSMASTER:
channel=1;
case PRI_BUSMASTER:
ide_busmaster_write(channel,address,dsize,data);
break;
}
}
u32 CAliM1543C_ide::ReadMem_Bar(int func, int bar, u32 address, int dsize) {
int channel = 0;
switch(bar) {
case BAR_SEC_COMMAND:
channel = 1;
case BAR_PRI_COMMAND:
return ide_command_read(channel,address,dsize);
case BAR_SEC_CONTROL:
channel = 1;
case BAR_PRI_CONTROL:
// we have to offset by two because the BAR starts at 3f4 vs 3f6
return ide_control_read(channel,address-2);
case BAR_BUSMASTER:
if (address <8)
return ide_busmaster_read(0,address,dsize);
else
return ide_busmaster_read(1,address-8,dsize);
}
return 0;
}
void CAliM1543C_ide::WriteMem_Bar(int func, int bar, u32 address, int dsize, u32 data) {
int channel = 0;
switch(bar) {
case BAR_SEC_COMMAND:
channel = 1;
case BAR_PRI_COMMAND:
ide_command_write(channel,address, dsize,data);
return;
case BAR_SEC_CONTROL:
channel = 1;
case BAR_PRI_CONTROL:
// we have to offset by two because the BAR starts at 3f4 vs 3f6
ide_control_write(channel,address-2, data);
return;
case BAR_BUSMASTER:
if (address <8)
return ide_busmaster_write(0,address,data,dsize);
else
return ide_busmaster_write(1,address-8,data,dsize);
return;
}
}
/*
* Register read/write handlers
*/
u32 CAliM1543C_ide::ide_command_read(int index, u32 address, int dsize) {
u32 data = 0;
if(!get_disk(index,0) &&
!get_disk(index,1)) {
// no disks are present, so the data lines actually float to
// a high state, which is logical 1.
return 0xffffffff;
}
switch(address) {
case REG_COMMAND_DATA:
if(!SEL_STATUS(index).drq) {
#ifdef DEBUG_IDE_REG_COMMAND
printf("Reading from data buffer when data is not ready.\n");
ide_status(index);
PAUSE("WTF");
#endif
break;
}
data = 0;
switch(dsize) {
case 32:
data = CONTROLLER(index).data[CONTROLLER(index).data_ptr++];
data |= CONTROLLER(index).data[CONTROLLER(index).data_ptr++] << 16;
break;
case 16:
data = CONTROLLER(index).data[CONTROLLER(index).data_ptr++];
}
if(CONTROLLER(index).data_ptr >= CONTROLLER(index).data_size)
{
// there's no more to take.
SEL_STATUS(index).drq=false;
if(SEL_COMMAND(index).current_command == 0xa0 &&
SEL_COMMAND(index).command_in_progress)
{
// packet is a weird case. We're actually going to set the
// controller to busy so we can end up in the ATAPI state
// machine before the host has a chance to do anything
// unexpected.
SEL_STATUS(index).busy=true;
SEL_STATUS(index).drive_ready=false;
#ifdef DEBUG_IDE_PACKET
printf("%%IDE-I-READCMD: Asserting Busy so we can resume ATAPI in state %s.\n",packet_states[SEL_COMMAND(index).packet_phase]);
#endif
}
}
if(CONTROLLER(index).data_ptr > IDE_BUFFER_SIZE) {
printf("%%IDE-W-OVERFLOW: data pointer past end of buffer, setting to 0.\n");
CONTROLLER(index).data_ptr=0;
SEL_STATUS(index).drq=false;
}
break;
case REG_COMMAND_ERROR:
data = SEL_REGISTERS(index).error;
break;
case REG_COMMAND_SECTOR_COUNT:
data = SEL_REGISTERS(index).sector_count;
break;
case REG_COMMAND_SECTOR_NO:
data = SEL_REGISTERS(index).sector_no;
break;
case REG_COMMAND_CYL_LOW:
data = SEL_REGISTERS(index).cylinder_no & 0xff;
break;
case REG_COMMAND_CYL_HI:
data = (SEL_REGISTERS(index).cylinder_no >> 8) & 0xff;
break;
case REG_COMMAND_DRIVE:
data = 0x80
| (SEL_REGISTERS(index).lba_mode ? 0x40 : 0x00)
| 0x20 //512 byte sector size
| (CONTROLLER(index).selected ? 0x10 : 0x00)
| (SEL_REGISTERS(index).head_no & 0x0f );
break;
case REG_COMMAND_STATUS:
// get the status and clear the interrupt.
data = get_status(index);
theAli->pic_deassert(1,6+index);
CONTROLLER(index).interrupt_fired=0;
#ifdef DEBUG_IDE_INTERRUPT
printf("%%IDE-I-INTERRUPT: Interrupt Acknowledged.\n");
#endif
break;
}
#ifdef DEBUG_IDE_REG_COMMAND
if(address != 0)
printf("%%IDE-I-REGCMD: Read from command register %d (%s) on controller %d, value: %x\n",address,register_names[address],index,data);
#endif
return data;
}
void CAliM1543C_ide::ide_command_write(int index, u32 address, int dsize, u32 data) {
#ifdef DEBUG_IDE_REG_COMMAND
if(address != 0)
printf("%%IDE-I-REGCMD: Write to command register %d (%s) on controller %d, value: %x\n",address,register_names[address],index,data);
SEL_STATUS(index).debug_status_update=true;
#endif
switch(address) {
case REG_COMMAND_DATA:
if(!SEL_STATUS(index).drq) {
#ifdef DEBUG_IDE_REG_COMMAND
printf("%%IDE-I-DATA: Unrequested data written to data port: %x\n",data);
ide_status(index);
#endif
break;
}
switch(dsize) {
case 32:
CONTROLLER(index).data[CONTROLLER(index).data_ptr++] = data & 0xffff;
CONTROLLER(index).data[CONTROLLER(index).data_ptr++] = (data>>16) & 0xffff;
break;
case 16:
CONTROLLER(index).data[CONTROLLER(index).data_ptr++] = data & 0xffff;
}
if(CONTROLLER(index).data_ptr >= CONTROLLER(index).data_size) {
// we don't want any more.
SEL_STATUS(index).drq=false;
SEL_STATUS(index).busy=true;
}
if(CONTROLLER(index).data_ptr > IDE_BUFFER_SIZE) {
printf("%%IDE-W-OVERFLOW: data pointer overflow, setting to 0.\n");
CONTROLLER(index).data_ptr=0;
SEL_STATUS(index).drq=false;
}
break;
case REG_COMMAND_FEATURES:
REGISTERS(index,0).features = data;
REGISTERS(index,1).features = data;
break;
case REG_COMMAND_SECTOR_COUNT:
REGISTERS(index,0).sector_count =
REGISTERS(index,1).sector_count = data & 0xff;
break;
case REG_COMMAND_SECTOR_NO:
REGISTERS(index,0).sector_no =
REGISTERS(index,1).sector_no = data & 0xff;
break;
case REG_COMMAND_CYL_LOW:
REGISTERS(index,0).cylinder_no =
REGISTERS(index,1).cylinder_no = (REGISTERS(index,1).cylinder_no & 0xff00) | (data & 0xff);
break;
case REG_COMMAND_CYL_HI:
REGISTERS(index,0).cylinder_no =
REGISTERS(index,1).cylinder_no = (REGISTERS(index,1).cylinder_no & 0xff) | ((data<<8) & 0xff00);
break;
case REG_COMMAND_DRIVE:
CONTROLLER(index).selected = (data >> 4) & 1;
REGISTERS(index,0).head_no =
REGISTERS(index,1).head_no = data & 0x0f;
REGISTERS(index,0).lba_mode =
REGISTERS(index,1).lba_mode = (data >> 6) & 1;
break;
case REG_COMMAND_COMMAND:
theAli->pic_deassert(1,6+index); // interrupt is cleared on write.
if(!SEL_DISK(index)) {
#ifdef DEBUG_IDE
printf("%%IDE-I-NODEV: Command to non-existing device %d.%d. cmd=%x\n",index,CONTROLLER(index).selected,data);
#endif
}
if(SEL_COMMAND(index).command_in_progress==true) {
// we're already working, why is another command being issued?
// chances are, its a timing issue. We will (hopefully) force
// the previous command to completion by calling DoClock() before
// processing the new command. Unfortunately, if the registers
// have changed dramatically, it may actually be destructive.
#ifdef DEBUG_IDE
printf("%%IDE-W-CIP: Command is already in progress.\n");
PAUSE("dang it!");
#endif
DoClock();
}
if((data & 0xf0) == 0x10)
data = 0x10;
SEL_COMMAND(index).command_in_progress=false;
SEL_COMMAND(index).current_command=data;
SEL_COMMAND(index).command_cycle=0;
SEL_STATUS(index).drq=false;
CONTROLLER(index).data_ptr=0;
if(data!=0x00) { // not a nop
SEL_STATUS(index).busy=true;
SEL_COMMAND(index).command_in_progress=true;
SEL_COMMAND(index).packet_phase=PACKET_NONE;
} else {
// this is a nop, so we cancel everything that's pending and
// pretend that this operation got done super fast!
if(SEL_DISK(index))
command_aborted(index,data);
}
break;
}
}
u32 CAliM1543C_ide::ide_control_read(int index, u32 address) {
u32 data=0;
switch(address) {
case 0:
data = get_status(index);
#ifdef DEBUG_IDE_REG_CONTROL
static u32 last_data = 0;
if(last_data != data) {
printf("%%IDE-I-READCTRL: alternate status on IDE control %d: 0x%02x\n", index, data);
}
last_data=data;
#endif
break;
case 1:
// 3x7h drive address register. (floppy?)
data |= (CONTROLLER(index).selected==0)?1:2;
data |= (SEL_REGISTERS(index).head_no)<<2;
data = (~data) & 0xff; // negate everything
#ifdef DEBUG_IDE_REG_CONTROL
printf("%%IDE-I-READCTRL: drive address port on IDE control %d: 0x%02x\n", index, data);
#endif
break;
}
return data;
}
/**
* Write to the IDE controller control interface.
**/
void CAliM1543C_ide::ide_control_write(int index, u32 address, u32 data)
{
bool prev_reset;
#ifdef DEBUG_IDE_REG_CONTROL
printf("%%IDE-I-WRITCTRL: write port %d on IDE control %d: 0x%02x\n", (u32)(address),index, data);
#endif
switch(address) {
case 0:
prev_reset = CONTROLLER(index).reset;
CONTROLLER(index).reset = (data>>2) & 1;
CONTROLLER(index).disable_irq = (data>>1) & 1;
if (!prev_reset && CONTROLLER(index).reset) {
#ifdef DEBUG_IDE_REG_CONTROL
printf("IDE reset on index %d started.\n",index);
#endif
STATUS(index,0).busy = true;
STATUS(index,0).drive_ready = false;
STATUS(index,0).seek_complete = true;
STATUS(index,0).drq = false;
STATUS(index,0).err = false;
COMMAND(index,0).current_command = 0;
COMMAND(index,0).command_in_progress = false;
STATUS(index,1).busy = true;
STATUS(index,1).drive_ready = false;
STATUS(index,1).seek_complete = true;
STATUS(index,1).drq = false;
STATUS(index,1).err = false;
COMMAND(index,1).current_command = 0;
COMMAND(index,1).command_in_progress = false;
CONTROLLER(index).reset_in_progress = true;
SEL_REGISTERS(index).error = 0x01; // no error
COMMAND(index,0).current_command = 0;
CONTROLLER(index).disable_irq = false;
} else if (prev_reset && !CONTROLLER(index).reset) {
#ifdef DEBUG_IDE_REG_CONTROL
printf("IDE reset on index %d ended.\n",index);
#endif
STATUS(index,0).busy = false;
STATUS(index,0).drive_ready = true;
STATUS(index,1).busy = false;
STATUS(index,1).drive_ready = true;
CONTROLLER(index).reset_in_progress = false;
set_signature(index,0);
set_signature(index,1);
}
break;
case 1:
// floppy?
break;
}
}
/**
* Read from the IDE controller busmaster interface.
**/
u32 CAliM1543C_ide::ide_busmaster_read(int index, u32 address, int dsize)
{
u32 data;
switch(dsize) {
case 8:
data = CONTROLLER(index).busmaster[address];
break;
case 32:
data = *(u32 *)(&CONTROLLER(index).busmaster[address]);
break;
default:
printf("16-bit read from busmaster.\n");
exit(1);
data = 0;
break;
}
#ifdef DEBUG_IDE_BUSMASTER
printf("%%IDE-I-READBUSM: read port %d on IDE bus master %d: 0x%02x, %d bytes\n", (u32)(address), index, data, dsize/8);
#endif
return data;
}
/**
* Write to the IDE controller busmaster interface.
**/
void CAliM1543C_ide::ide_busmaster_write(int index, u32 address, u32 data, int dsize)
{
#ifdef DEBUG_IDE_BUSMASTER
if(!(dsize==8 && (address >= 4 && address <=7)))
printf("%%IDE-I-WRITBUSM: write port %d on IDE bus master %d: 0x%02x, %d bytes\n", (u32)(address),index, data, dsize/8);
#endif
u32 prd_address;
u32 base,control;
switch(dsize) {
case 32:
ide_busmaster_write(index,address,data & 0xff, 8);
ide_busmaster_write(index,address+1,(data >> 8) & 0xff, 8);
ide_busmaster_write(index,address+2,(data >> 16) & 0xff, 8);
ide_busmaster_write(index,address+3,(data >> 24) & 0xff, 8);
return;
case 16:
ide_busmaster_write(index,address,data & 0xff, 8);
ide_busmaster_write(index,address+1,(data >> 8) & 0xff, 8);
return;
}
switch(address) {
case 0: // command register
#ifdef DEBUG_IDE_BUSMASTER
printf("%%IDE-I-BUSM: Bus master command got data: %x (%s,%s)\n",data,
(data & 0x08 ? "write" : "read"),
(data & 0x01 ? "start" : "stop"));
#endif
// bits 7:4 & 2:1 are reserved and must return zero on read.
CONTROLLER(index).busmaster[0] = data & 0x09;
if(data & 0x01) {
// set the status register
CONTROLLER(index).busmaster[2] |= 0x01;
} else {
// clear the status register
CONTROLLER(index).busmaster[2] &= 0xfe;
}
break;
case 2: // status
// bit 7 = simplex only (0=both channels are independent)
// bit 6 = drive 1 dma capable.
// bit 5 = drive 0 dma capable.
// bit 4,3 = reserved
// bit 2 = interrupt (write 1 to reset)
// bit 1 = error (write 1 to reset)
// bit 0 = busmaster active.
CONTROLLER(index).busmaster[2] = data & 0x67;
//#ifdef DEBUG_IDE_BUSMASTER
//printf("-IDE-I-BUSM: Bus master status write, init data: %x\n",CONTROLLER(index).busmaster[2]);
//#endif
if(data & 0x04) // interrupt
CONTROLLER(index).busmaster[2] &= ~0x04;
if(data & 0x02) // error
CONTROLLER(index).busmaster[2] &= ~0x02;
if(data & 0x01) // busy
CONTROLLER(index).busmaster[2] &= ~0x01;
//#ifdef DEBUG_IDE_BUSMASTER
//printf("-IDE-I-BUSM: Bus master status write, final data: %x\n",CONTROLLER(index).busmaster[2]);
//#endif
break;
case 4: // descriptor table pointer register(s)
case 5:
case 6:
CONTROLLER(index).busmaster[address]=data;
break;
case 7:
CONTROLLER(index).busmaster[address]=data;
prd_address = endian_32(*(u32 *)(&CONTROLLER(index).busmaster[4]));
#ifdef DEBUG_IDE_BUSMASTER
printf("%IDE-I-PRD: Virtual address: %" LL "x \n", endian_32(*(u32 *)(&CONTROLLER(index).busmaster[4])));
printf("-IDE-I-PRD: Physical address: %" LL "x \n", prd_address);
do {
do_pci_read(prd_address, &base, 4, 1);
do_pci_read(prd_address+4, &control, 4, 1);
printf("-IDE-I-PRD: base: %x, control: %x \n",base, control);
prd_address+=8;
} while(base & 0x80 == 0);
#endif
break;
default:
break;
}
}
void CAliM1543C_ide::set_signature(int index, int id)
{
// Device signature
REGISTERS(index,id).head_no = 0;
REGISTERS(index,id).sector_count = 1;
REGISTERS(index,id).sector_no = 1;
if (get_disk(index,id)) {
if (!get_disk(index,id)->cdrom()) {
REGISTERS(index,id).cylinder_no = 0;
CONTROLLER(index).selected = 0; // XXX: This may not be correct.
} else {
REGISTERS(index,id).cylinder_no = 0xeb14;
}
} else {
REGISTERS(index,id).cylinder_no = 0xffff;
}
}
void CAliM1543C_ide::raise_interrupt(int index) {
#ifdef DEBUG_IDE_INTERRUPT
printf("%%IDE-I-INTERRUPT: Interrupt scheduled to be raised on controller %d.\n",index);
#endif
CONTROLLER(index).interrupt_pending=true;
}
u8 CAliM1543C_ide::get_status(int index)
{
u8 data;
if (!SEL_DISK(index)) {
#ifdef DEBUG_IDE_REG_COMMAND
printf("%%IDE-I-STATUS: Read status for nonexiting device %d.%d\n",index,CONTROLLER(index).selected);
#endif
return 0;
}
data = (SEL_STATUS(index).busy ? 0x80 : 0x00)
| (SEL_STATUS(index).drive_ready ? 0x40 : 0x00)
| (SEL_STATUS(index).fault ? 0x20 : 0x00)
| (SEL_STATUS(index).seek_complete ? 0x10 : 0x00)
| (SEL_STATUS(index).drq ? 0x08 : 0x00)
| (SEL_STATUS(index).index_pulse ? 0x02 : 0x00)
| (SEL_STATUS(index).err ? 0x01 : 0x00);
SEL_STATUS(index).index_pulse_count++;
SEL_STATUS(index).index_pulse = false;
if (SEL_STATUS(index).index_pulse_count >= 10) {
SEL_STATUS(index).index_pulse_count = 0;
SEL_STATUS(index).index_pulse = true;
}
#ifdef DEBUG_IDE_REG_COMMAND
if((SEL_STATUS(index).debug_last_status & 0xfd) != (data & 0xfd) || SEL_STATUS(index).debug_status_update) {
printf("%%IDE-I-STATUS: Controller %d status: %x = %s %s %s %s %s %s %s\n",index,
data,
SEL_STATUS(index).busy?"busy":"",
SEL_STATUS(index).drive_ready?"drdy":"",
SEL_STATUS(index).fault?"fault":"",
SEL_STATUS(index).seek_complete?"seek_complete":"",
SEL_STATUS(index).drq?"drq":"",
SEL_STATUS(index).index_pulse?"pulse":"",
SEL_STATUS(index).err?"error":"");
SEL_STATUS(index).debug_status_update=false;
}
SEL_STATUS(index).debug_last_status=data;
#endif
return data;
}
void CAliM1543C_ide::identify_drive(int index, bool packet)
{
char serial_number[21];
char model_number[41];
char rev_number[9];
size_t i;
// clear the block.
for(i=0;i<256;i++)
CONTROLLER(index).data[i]=0;
CONTROLLER(index).data_ptr = 0;
CONTROLLER(index).data_size = 256;
// The data here was taken from T13/1153D revision 18
if(!packet) {
// flags: 0x0080 = removable, 0x0040 = fixed.
CONTROLLER(index).data[0] = SEL_DISK(index)->cdrom() ? 0x0080 : 0x0040;