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sim_main.cpp
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sim_main.cpp
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#define MIN_FRAME 1000
#define MAX_FRAME 2000
#include <iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include "imgui_functions.h"
#include <verilated.h>
#include "Vcore_3do___024root.h"
#include "Vcore_3do.h"
#include "verilated_vcd_c.h"
// libopera includes...
#include "opera_3do.h"
#include "opera_arm.h"
#include "opera_clio.h"
#include "opera_clock.h"
#include "opera_core.h"
#include "opera_diag_port.h"
#include "opera_dsp.h"
#include "opera_madam.h"
#include "opera_region.h"
#include "opera_sport.h"
#include "opera_vdlp.h"
#include "opera_xbus.h"
#include "opera_xbus_cdrom_plugin.h"
#include "opera_cdrom.h"
#include "opera_nvram.h"
#include "inline.h"
#include "sim_xbus.h"
#include "opera_vdlp_i.h"
//extern vdlp_t g_VDLP;
uint32_t opera_line;
uint32_t opera_field;
volatile extern xbus_datum_t XBUS;
volatile extern sim_xbus_device xdev[16];
//extern cdrom_device_t g_CDROM_DEVICE;
volatile extern uint32_t CDIMAGE_SECTOR;
uint8_t* dram;
uint8_t* vram;
int flagtime;
extern arm_core_t CPU;
FILE* logfile;
FILE* inst_file;
FILE* soundfile;
FILE* isofile;
FILE* ramdump;
FILE* cel_file;
uint32_t cel_size = 0;
uint32_t sound_out;
extern int sim_xbus_fiq_request = 0;
#include <d3d11.h>
#define DIRECTINPUT_VERSION 0x0800
#include <dinput.h>
#include <tchar.h>
// DirectX data
static ID3D11Device* g_pd3dDevice = NULL;
static ID3D11DeviceContext* g_pd3dDeviceContext = NULL;
static IDXGIFactory* g_pFactory = NULL;
static ID3D11Buffer* g_pVB = NULL;
static ID3D11Buffer* g_pIB = NULL;
static ID3D10Blob* g_pVertexShaderBlob = NULL;
static ID3D11VertexShader* g_pVertexShader = NULL;
static ID3D11InputLayout* g_pInputLayout = NULL;
static ID3D11Buffer* g_pVertexConstantBuffer = NULL;
static ID3D10Blob* g_pPixelShaderBlob = NULL;
static ID3D11PixelShader* g_pPixelShader = NULL;
static ID3D11SamplerState* g_pFontSampler = NULL;
static ID3D11SamplerState* g_pFontSampler2 = NULL;
static ID3D11ShaderResourceView* g_pFontTextureView = NULL;
static ID3D11ShaderResourceView* g_pFontTextureView2 = NULL;
static ID3D11RasterizerState* g_pRasterizerState = NULL;
static ID3D11BlendState* g_pBlendState = NULL;
static ID3D11DepthStencilState* g_pDepthStencilState = NULL;
static int g_VertexBufferSize = 5000, g_IndexBufferSize = 10000;
// Instantiation of module.
Vcore_3do* top = new Vcore_3do;
char decode_string[64];
char issue_string[64];
char shifter_string[64];
char alu_string[64];
char memory_string[64];
char rb_string[64];
bool old_fiq_n = 1;
bool next_ack = 0;
bool rom2_select = 0; // Select the BIOS ROM at startup! (not Kanji).
bool map_bios = 1;
uint32_t rom_byteswapped;
uint32_t rom2_byteswapped;
uint32_t ram_byteswapped;
uint16_t shift_reg = 0;
bool toggle = 1;
char my_string[1024];
bool trace = 0;
bool inst_trace = 0;
bool soundtrace = 0;
int pix_count = 0;
uint32_t cur_pc;
uint32_t old_pc;
bool dump_ram = 0;
unsigned char rgb[3];
bool prev_vsync = 0;
int frame_count = 0;
bool prev_hsync = 0;
int line_count = 0;
bool trig_irq = 0;
bool trig_fiq = 0;
bool run_enable = 0;
bool single_step = 0;
bool multi_step = 0;
int multi_step_amount = 8;
int spr_width = 128;
FILE* vgap;
// Data
static IDXGISwapChain* g_pSwapChain = NULL;
static ID3D11RenderTargetView* g_mainRenderTargetView = NULL;
void CreateRenderTarget()
{
ID3D11Texture2D* pBackBuffer;
g_pSwapChain->GetBuffer(0, __uuidof(ID3D11Texture2D), (LPVOID*)&pBackBuffer);
g_pd3dDevice->CreateRenderTargetView(pBackBuffer, NULL, &g_mainRenderTargetView);
pBackBuffer->Release();
}
void CleanupRenderTarget()
{
if (g_mainRenderTargetView) { g_mainRenderTargetView->Release(); g_mainRenderTargetView = NULL; }
}
HRESULT CreateDeviceD3D(HWND hWnd)
{
// Setup swap chain
DXGI_SWAP_CHAIN_DESC sd;
ZeroMemory(&sd, sizeof(sd));
sd.BufferCount = 2;
sd.BufferDesc.Width = 0;
sd.BufferDesc.Height = 0;
sd.BufferDesc.Format = DXGI_FORMAT_R8G8B8A8_UNORM;
sd.BufferDesc.RefreshRate.Numerator = 60;
sd.BufferDesc.RefreshRate.Denominator = 1;
sd.Flags = DXGI_SWAP_CHAIN_FLAG_ALLOW_MODE_SWITCH;
sd.BufferUsage = DXGI_USAGE_RENDER_TARGET_OUTPUT;
sd.OutputWindow = hWnd;
sd.SampleDesc.Count = 1;
sd.SampleDesc.Quality = 0;
sd.Windowed = TRUE;
sd.SwapEffect = DXGI_SWAP_EFFECT_DISCARD;
UINT createDeviceFlags = 0;
//createDeviceFlags |= D3D11_CREATE_DEVICE_DEBUG;
D3D_FEATURE_LEVEL featureLevel;
const D3D_FEATURE_LEVEL featureLevelArray[2] = { D3D_FEATURE_LEVEL_11_0, D3D_FEATURE_LEVEL_10_0, };
if (D3D11CreateDeviceAndSwapChain(NULL, D3D_DRIVER_TYPE_HARDWARE, NULL, createDeviceFlags, featureLevelArray, 2, D3D11_SDK_VERSION, &sd, &g_pSwapChain, &g_pd3dDevice, &featureLevel, &g_pd3dDeviceContext) != S_OK)
return E_FAIL;
CreateRenderTarget();
return S_OK;
}
void CleanupDeviceD3D()
{
CleanupRenderTarget();
if (g_pSwapChain) { g_pSwapChain->Release(); g_pSwapChain = NULL; }
if (g_pd3dDeviceContext) { g_pd3dDeviceContext->Release(); g_pd3dDeviceContext = NULL; }
if (g_pd3dDevice) { g_pd3dDevice->Release(); g_pd3dDevice = NULL; }
}
extern LRESULT ImGui_ImplWin32_WndProcHandler(HWND hWnd, UINT msg, WPARAM wParam, LPARAM lParam);
LRESULT WINAPI WndProc(HWND hWnd, UINT msg, WPARAM wParam, LPARAM lParam)
{
if (ImGui_ImplWin32_WndProcHandler(hWnd, msg, wParam, lParam))
return true;
switch (msg)
{
case WM_SIZE:
if (g_pd3dDevice != NULL && wParam != SIZE_MINIMIZED)
{
CleanupRenderTarget();
g_pSwapChain->ResizeBuffers(0, (UINT)LOWORD(lParam), (UINT)HIWORD(lParam), DXGI_FORMAT_UNKNOWN, 0);
CreateRenderTarget();
}
return 0;
case WM_SYSCOMMAND:
if ((wParam & 0xfff0) == SC_KEYMENU) // Disable ALT application menu
return 0;
break;
case WM_DESTROY:
PostQuitMessage(0);
return 0;
}
return DefWindowProc(hWnd, msg, wParam, lParam);
}
static float values[90] = { 0 };
static int values_offset = 0;
int my_x = 0;
int my_y = 0;
vluint64_t main_time = 0; // Current simulation time.
unsigned int file_size;
unsigned int iso_size;
unsigned char buffer[16];
unsigned int rom_size = 1024 * 1024; // 1MB. (8-bit wide, 32-bit access). BIOS.
uint8_t* rom_ptr = (uint8_t*)malloc(rom_size);
unsigned int rom2_size = 1024 * 1024; // 1MB. (8-bit wide, 32-bit access). Kanji font ROM.
uint8_t* rom2_ptr = (uint8_t*)malloc(rom2_size);
unsigned int ram_size = 1024 * 2048; // 2MB. (8-bit wide, 32-bit access).
uint8_t* ram_ptr = (uint8_t*)malloc(ram_size);
unsigned int vram_size = 1024 * 1024; // 1MB. (8-bit wide, 32-bit access).
//unsigned int vram_size = 1024 * 2048; // 2MB. (8-bit wide, 32-bit access).
uint8_t* vram_ptr = (uint8_t*)malloc(vram_size);
unsigned int nvram_size = 1024 * 128; // 128KB?
uint8_t* nvram_ptr = (uint8_t*)malloc(nvram_size);
unsigned int disp_size = 1024 * 1024 * 4; // 4MB. (32-bit wide). Sim display window.
uint32_t* disp_ptr = (uint32_t*)malloc(disp_size);
unsigned int disp2_size = 1024 * 1024 * 4; // 4MB. (32-bit wide). Opera display window.
uint32_t* disp2_ptr = (uint32_t*)malloc(disp2_size);
double sc_time_stamp() { // Called by $time in Verilog.
return main_time;
}
extern opera_cdrom_get_size_cb_t CDROM_GET_SIZE;
extern opera_cdrom_set_sector_cb_t CDROM_SET_SECTOR;
extern opera_cdrom_read_sector_cb_t CDROM_READ_SECTOR;
uint16_t CDIMAGE_SECTOR_SIZE = 2048;
static
uint32_t
cdimage_get_size(void)
{
return (iso_size / CDIMAGE_SECTOR_SIZE);
}
static
void
cdimage_set_sector(const uint32_t sector_)
{
CDIMAGE_SECTOR = sector_;
}
static
void
cdimage_read_sector(void* buf_)
{ uint32_t start_offset = CDIMAGE_SECTOR * CDIMAGE_SECTOR_SIZE;
//if (CDIMAGE_SECTOR_SIZE == 2352) start_offset += 16;
//if ( start_offset>(iso_size -CDIMAGE_SECTOR_SIZE) ) start_offset=(iso_size - CDIMAGE_SECTOR_SIZE); // Clamp the max offset.
fseek(isofile, start_offset, SEEK_SET);
fread(buf_, 1, CDIMAGE_SECTOR_SIZE, isofile);
}
uint32_t g_OPT_VIDEO_WIDTH = 0;
uint32_t g_OPT_VIDEO_HEIGHT = 0;
uint32_t g_OPT_VIDEO_PITCH_SHIFT = 0;
uint32_t g_OPT_VDLP_FLAGS = 0;
uint32_t g_OPT_VDLP_PIXEL_FORMAT = 0;
uint32_t g_OPT_ACTIVE_DEVICES = 0;
void my_opera_init() {
opera_cdrom_set_callbacks(cdimage_get_size, cdimage_set_sector, cdimage_read_sector);
//opera_3do_init(libopera_callback);
opera_clock_init();
opera_arm_init();
uint32_t size = (384 * 288 * 4);
if (!g_VIDEO_BUFFER) g_VIDEO_BUFFER = (uint32_t*)calloc(size, sizeof(uint32_t));
opera_vdlp_configure(g_VIDEO_BUFFER, (vdlp_pixel_format_e)VDLP_PIXEL_FORMAT_XRGB8888, g_OPT_VDLP_FLAGS);
dram = opera_arm_ram_get();
vram = opera_arm_vram_get();
opera_vdlp_init(vram);
opera_sport_init(vram);
opera_madam_init(dram);
opera_nvram_init();
//opera_xbus_init(xbus_cdrom_plugin);
//opera_xbus_device_load(0, NULL);
sim_xbus_init(xbus_cdrom_plugin);
sim_xbus_device_load(0, NULL);
cdimage_set_sector(0);
// 0x40 for start from 3D0-CD
// 0x01/0x02 from PhotoCD ??
// (NO use 0x40/0x02 for BIOS test)
opera_clio_init(0x40); // bit[6]=DIPIR.
//opera_clio_init(0x01); // <- This value gets written to CLIO cstatbits. bit[0]=POR.
opera_dsp_init();
}
static uint16_t sim_SNDDebugFIFO0;
static uint16_t sim_SNDDebugFIFO1;
static uint16_t sim_RCVDebugFIFO0;
static uint16_t sim_RCVDebugFIFO1;
static uint16_t sim_GetIdx;
static uint16_t sim_SendIdx;
void
sim_diag_port_init(const int32_t test_code_)
{
int32_t test_code = test_code_;
sim_GetIdx = 16;
sim_SendIdx = 16;
sim_SNDDebugFIFO0 = 0;
sim_SNDDebugFIFO1 = 0;
if (test_code >= 0)
{
test_code ^= 0xFF;
test_code |= 0xA000;
}
else
{
test_code = 0;
}
sim_RCVDebugFIFO0 = test_code;
sim_RCVDebugFIFO1 = test_code;
}
void
sim_diag_port_send(const uint32_t val_)
{
if (sim_GetIdx != 16)
{
sim_GetIdx = 16;
sim_SendIdx = 16;
sim_SNDDebugFIFO0 = 0;
sim_SNDDebugFIFO1 = 0;
}
sim_SNDDebugFIFO0 |= ((val_ & 1) << (sim_SendIdx - 1));
sim_SNDDebugFIFO1 |= (((val_ & 1) >> 1) << (sim_SendIdx - 1));
sim_SendIdx--;
if (sim_SendIdx == 0)
sim_SendIdx = 16;
}
uint32_t
sim_diag_port_get(void)
{
unsigned int val = 0;
if (sim_SendIdx != 16)
{
sim_GetIdx = 16;
sim_SendIdx = 16;
}
val = ((sim_RCVDebugFIFO0 >> (sim_GetIdx - 1)) & 0x1);
val |= (((sim_RCVDebugFIFO1 >> (sim_GetIdx - 1)) & 0x1) << 0x1);
sim_GetIdx--;
if (sim_GetIdx == 0)
sim_GetIdx = 16;
return val;
}
volatile uint32_t vdl_ctl = 0x00004410;
volatile uint32_t vdl_curr = 0x002C0000;
volatile uint32_t vdl_prev = 0x002C0000;
volatile uint32_t vdl_next = 0x002C0000;
volatile uint32_t clut[256];
void sim_process_vdl() {
// Load default CLUT...
clut[0x00] = 0x000000; clut[0x01] = 0x080808; clut[0x02] = 0x101010; clut[0x03] = 0x191919; clut[0x04] = 0x212121; clut[0x05] = 0x292929; clut[0x06] = 0x313131; clut[0x07] = 0x3A3A3A;
clut[0x08] = 0x424242; clut[0x09] = 0x4A4A4A; clut[0x0A] = 0x525252; clut[0x0B] = 0x5A5A5A; clut[0x0C] = 0x636363; clut[0x0D] = 0x6B6B6B; clut[0x0E] = 0x737373; clut[0x0F] = 0x7B7B7B;
clut[0x10] = 0x848484; clut[0x11] = 0x8C8C8C; clut[0x12] = 0x949494; clut[0x13] = 0x9C9C9C; clut[0x14] = 0xA5A5A5; clut[0x15] = 0xADADAD; clut[0x16] = 0xB5B5B5; clut[0x17] = 0xBDBDBD;
clut[0x18] = 0xC5C5C5; clut[0x19] = 0xCECECE; clut[0x1A] = 0xD6D6D6; clut[0x1B] = 0xDEDEDE; clut[0x1C] = 0xE6E6E6; clut[0x1D] = 0xEFEFEF; clut[0x1E] = 0xF8F8F8; clut[0x1F] = 0xFFFFFF;
uint32_t header = top->rootp->core_3do__DOT__madam_inst__DOT__dma_stack_inst__DOT__dma24_curaddr & 0xfffff; // Mask address to 1MB (VRAM).
// Read the VDL / CLUT from vram_ptr...
if (header>0) {
vdl_ctl = 0x00000000;
vdl_curr = 0x00000000;
vdl_prev = 0x00000000;
vdl_next = 0x00000000;
for (int i = 0; i <= 35; i++) {
if (i == 0) {
vdl_ctl |= (vram_ptr[header + (i*4) + 0]) << 24;
vdl_ctl |= (vram_ptr[header + (i*4) + 1]) << 16;
vdl_ctl |= (vram_ptr[header + (i*4) + 2]) << 8;
vdl_ctl |= (vram_ptr[header + (i*4) + 3]) << 0;
}
if (i == 1) {
vdl_curr |= (vram_ptr[header + (i*4) + 0]) << 24;
vdl_curr |= (vram_ptr[header + (i*4) + 1]) << 16;
vdl_curr |= (vram_ptr[header + (i*4) + 2]) << 8;
vdl_curr |= (vram_ptr[header + (i*4) + 3]) << 0;
}
if (i == 2) {
vdl_prev |= (vram_ptr[header + (i*4) + 0]) << 24;
vdl_prev |= (vram_ptr[header + (i*4) + 1]) << 16;
vdl_prev |= (vram_ptr[header + (i*4) + 2]) << 8;
vdl_prev |= (vram_ptr[header + (i*4) + 3]) << 0;
}
if (i == 3) {
vdl_next |= (vram_ptr[header + (i*4) + 0]) << 24;
vdl_next |= (vram_ptr[header + (i*4) + 1]) << 16;
vdl_next |= (vram_ptr[header + (i*4) + 2]) << 8;
vdl_next |= (vram_ptr[header + (i*4) + 3]) << 0;
}
//else if (i>=4) clut[i-4] = vram_ptr[header+i]; // TESTING !!!
}
}
// Copy the VRAM pixels into disp_ptr...
// Just a dumb test atm. Assuming 16bpp from vram_ptr, with odd and even pixels in the upper/lower 16 bits.
//
// vram_ptr is 32-bit wide!
// vram_size = 1MB, so needs to be divided by 4 if used as an index.
//
uint32_t my_line = 0;
//uint32_t offset = 0xC0000;
uint32_t offset = vdl_curr & 0xfffff;
//uint32_t offset = vdl_next & 0xfffff;
for (uint32_t i = 0; i < (vram_size / 16); i++) {
uint16_t pixel;
if ((i % 320) == 0) my_line++;
pixel = vram_ptr[ (offset+(i*4)+0)&0xfffff ]<<8 | vram_ptr[ (offset+(i*4)+1)&0xfffff ];
rgb[0] = clut[(pixel & 0x7C00) >> 10] >> 16;
rgb[1] = clut[(pixel & 0x03E0) >> 5] >> 8;
rgb[2] = clut[(pixel & 0x001F) << 0] >> 0;
disp_ptr[i + (my_line * 320)] = 0xff<<24 | rgb[2]<<16 | rgb[1]<<8 | rgb[0]; // Our debugger framebuffer is in the 32-bit ABGR format.
pixel = vram_ptr[ (offset+(i*4)+2)&0xfffff ]<<8 | vram_ptr[ (offset+(i*4)+3)&0xfffff ];
rgb[0] = clut[(pixel & 0x7C00) >> 10] >> 16;
rgb[1] = clut[(pixel & 0x03E0) >> 5] >> 8;
rgb[2] = clut[(pixel & 0x001F) << 0] >> 0;
disp_ptr[i + (my_line * 320) + 320] = 0xff<<24 | rgb[2]<<16 | rgb[1]<<8 | rgb[0]; // Our debugger framebuffer is in the 32-bit ABGR format.
}
}
volatile uint32_t opera_vdl_ctl = 0x00000000;
volatile uint32_t opera_vdl_curr = 0x00000000;
volatile uint32_t opera_vdl_prev = 0x00000000;
volatile uint32_t opera_vdl_next = 0x00000000;
volatile uint32_t opera_clut[256];
void opera_process_vdl() {
// Load default CLUT...
clut[0x00] = 0x000000; clut[0x01] = 0x080808; clut[0x02] = 0x101010; clut[0x03] = 0x191919; clut[0x04] = 0x212121; clut[0x05] = 0x292929; clut[0x06] = 0x313131; clut[0x07] = 0x3A3A3A;
clut[0x08] = 0x424242; clut[0x09] = 0x4A4A4A; clut[0x0A] = 0x525252; clut[0x0B] = 0x5A5A5A; clut[0x0C] = 0x636363; clut[0x0D] = 0x6B6B6B; clut[0x0E] = 0x737373; clut[0x0F] = 0x7B7B7B;
clut[0x10] = 0x848484; clut[0x11] = 0x8C8C8C; clut[0x12] = 0x949494; clut[0x13] = 0x9C9C9C; clut[0x14] = 0xA5A5A5; clut[0x15] = 0xADADAD; clut[0x16] = 0xB5B5B5; clut[0x17] = 0xBDBDBD;
clut[0x18] = 0xC5C5C5; clut[0x19] = 0xCECECE; clut[0x1A] = 0xD6D6D6; clut[0x1B] = 0xDEDEDE; clut[0x1C] = 0xE6E6E6; clut[0x1D] = 0xEFEFEF; clut[0x1E] = 0xF8F8F8; clut[0x1F] = 0xFFFFFF;
volatile uint32_t header = g_VDLP.curr_vdl & 0xfffff;
// Read the VDL / CLUT from vram_ptr...
if (header>0) {
for (int i = 0; i <= 35; i++) {
if (i == 0) {
opera_vdl_ctl |= (vram[header + (i*4) + 0]) << 24;
opera_vdl_ctl |= (vram[header + (i*4) + 1]) << 16;
opera_vdl_ctl |= (vram[header + (i*4) + 2]) << 8;
opera_vdl_ctl |= (vram[header + (i*4) + 3]) << 0;
}
if (i == 1) {
opera_vdl_curr |= (vram[header + (i*4) + 0]) << 24;
opera_vdl_curr |= (vram[header + (i*4) + 1]) << 16;
opera_vdl_curr |= (vram[header + (i*4) + 2]) << 8;
opera_vdl_curr |= (vram[header + (i*4) + 3]) << 0;
}
if (i == 2) {
opera_vdl_prev |= (vram[header + (i*4) + 0]) << 24;
opera_vdl_prev |= (vram[header + (i*4) + 1]) << 16;
opera_vdl_prev |= (vram[header + (i*4) + 2]) << 8;
opera_vdl_prev |= (vram[header + (i*4) + 3]) << 0;
}
if (i == 3) {
opera_vdl_next |= (vram[header + (i*4) + 0]) << 24;
opera_vdl_next |= (vram[header + (i*4) + 1]) << 16;
opera_vdl_next |= (vram[header + (i*4) + 2]) << 8;
opera_vdl_next |= (vram[header + (i*4) + 3]) << 0;
}
//else if (i>=4) clut[i-4] = vram_ptr[header+i]; // TESTING !!!
}
}
// Copy the VRAM pixels into disp_ptr...
// Just a dumb test atm. Assuming 16bpp from vram_ptr, with odd and even pixels in the upper/lower 16 bits.
//
// vram_ptr is 32-bit wide!
// vram_size = 1MB, so needs to be divided by 4 if used as an index.
//
//uint32_t offset = opera_vdl_curr & 0xfffff;
//uint32_t offset = opera_vdl_next & 0xfffff;
uint32_t offset = g_VDLP.curr_bmp & 0xfffff;
//uint32_t offset = opera_vdlp_bmp_origin & 0xfffff;
//uint32_t offset = 0x21000;
//uint32_t offset = 0xC0000;
uint32_t my_line = opera_line;
for (int i = 0; i < 320; i++) {
uint16_t pixel;
pixel = vram[offset + (i * 4) + 3] << 8 | vram[offset + (i * 4) + 2];
rgb[0] = clut[(pixel & 0x7C00) >> 10] >> 16;
rgb[1] = clut[(pixel & 0x03E0) >> 5] >> 8;
rgb[2] = clut[(pixel & 0x001F) << 0] >> 0;
disp2_ptr[i + (my_line * 320)] = 0xff << 24 | rgb[2] << 16 | rgb[1] << 8 | rgb[0]; // Our debugger framebuffer is in the 32-bit ABGR format.
pixel = vram[offset + (i * 4) + 1] << 8 | vram[offset + (i * 4) + 0];
rgb[0] = clut[(pixel & 0x7C00) >> 10] >> 16;
rgb[1] = clut[(pixel & 0x03E0) >> 5] >> 8;
rgb[2] = clut[(pixel & 0x001F) << 0] >> 0;
disp2_ptr[i + (my_line * 320) + 320] = 0xff << 24 | rgb[2] << 16 | rgb[1] << 8 | rgb[0]; // Our debugger framebuffer is in the 32-bit ABGR format.
}
/*
for (int i = 0; i < (vram_size / 16); i++) {
uint16_t pixel;
if ((i % 320) == 0) my_line++;
pixel = vram[offset + (i * 4) + 3] << 8 | vram[offset + (i * 4) + 2];
rgb[0] = clut[(pixel & 0x7C00) >> 10] >> 16;
rgb[1] = clut[(pixel & 0x03E0) >> 5] >> 8;
rgb[2] = clut[(pixel & 0x001F) << 0] >> 0;
disp2_ptr[i + (my_line * 320)] = 0xff << 24 | rgb[2] << 16 | rgb[1] << 8 | rgb[0]; // Our debugger framebuffer is in the 32-bit ABGR format.
pixel = vram[offset + (i * 4) + 1] << 8 | vram[offset + (i * 4) + 0];
rgb[0] = clut[(pixel & 0x7C00) >> 10] >> 16;
rgb[1] = clut[(pixel & 0x03E0) >> 5] >> 8;
rgb[2] = clut[(pixel & 0x001F) << 0] >> 0;
disp2_ptr[i + (my_line * 320) + 320] = 0xff << 24 | rgb[2] << 16 | rgb[1] << 8 | rgb[0]; // Our debugger framebuffer is in the 32-bit ABGR format.
}
*/
}
uint32_t svf_src_addr = 00;
void svf_set_source() {
svf_src_addr = (top->mem_addr & 0x7ff) << 9;
}
void svf_page_copy() {
uint32_t dest_addr = (top->mem_addr & 0x7ff) << 9; // Remember, the *address* is used here, not o_wb_dat.
uint32_t mask = top->o_wb_dat; // The write *data* is used as an mask. I think? ElectronAsh.
uint32_t keep = mask ^ 0xffffffff;
uint8_t keep0 = (keep >> 24) & 0xff;
uint8_t keep1 = (keep >> 16) & 0xff;
uint8_t keep2 = (keep >> 8) & 0xff;
uint8_t keep3 = (keep >> 0) & 0xff;
uint8_t mask0 = (mask >> 24) & 0xff;
uint8_t mask1 = (mask >> 16) & 0xff;
uint8_t mask2 = (mask >> 8) & 0xff;
uint8_t mask3 = (mask >> 0) & 0xff;
for(int i = 0; i < 2048; i += 4) // Block size is 2KB. Copying a WORD at a time, so i+=4.
{
vram_ptr[dest_addr+i+0] = (vram_ptr[dest_addr+i+0] & keep0) | (vram_ptr[svf_src_addr+i+0] & mask0);
vram_ptr[dest_addr+i+1] = (vram_ptr[dest_addr+i+1] & keep1) | (vram_ptr[svf_src_addr+i+1] & mask1);
vram_ptr[dest_addr+i+2] = (vram_ptr[dest_addr+i+2] & keep2) | (vram_ptr[svf_src_addr+i+2] & mask2);
vram_ptr[dest_addr+i+3] = (vram_ptr[dest_addr+i+3] & keep3) | (vram_ptr[svf_src_addr+i+3] & mask3);
}
}
uint32_t svf_color = 0;
void svf_set_color() {
svf_color = top->o_wb_dat;
}
void svf_flash_write() { // "Color fill", basically.
uint32_t dest_addr = (top->mem_addr & 0x7ff) << 9; // Remember, the *address* is used here, not o_wb_dat.
uint32_t mask = top->o_wb_dat; // The write *data* is used as an mask. I think? ElectronAsh.
uint32_t keep = mask ^ 0xffffffff;
uint8_t keep0 = (keep>>24) & 0xff;
uint8_t keep1 = (keep>>16) & 0xff;
uint8_t keep2 = (keep>>8) & 0xff;
uint8_t keep3 = (keep>>0) & 0xff;
uint8_t mask0 = (mask>>24) & 0xff;
uint8_t mask1 = (mask>>16) & 0xff;
uint8_t mask2 = (mask>>8) & 0xff;
uint8_t mask3 = (mask>>0) & 0xff;
for (int i = 0; i < 2048; i+=4) // Block size is 2KB. Writing a WORD at a time, so i+=4.
{
vram_ptr[dest_addr+i+0] = (vram_ptr[dest_addr+i+0] & keep0) | ((svf_color>>24) & mask0);
vram_ptr[dest_addr+i+1] = (vram_ptr[dest_addr+i+1] & keep1) | ((svf_color>>16) & mask1);
vram_ptr[dest_addr+i+2] = (vram_ptr[dest_addr+i+2] & keep2) | ((svf_color>>8) & mask2);
vram_ptr[dest_addr+i+3] = (vram_ptr[dest_addr+i+3] & keep3) | ((svf_color>>0) & mask3);
}
}
#define PBUS_BUF_SIZE 256
#define PBUS_FLIGHTSTICK_ID_0 0x01
#define PBUS_FLIGHTSTICK_ID_1 0x7B
#define PBUS_JOYPAD_ID 0x80
#define PBUS_MOUSE_ID 0x49
#define PBUS_LIGHTGUN_ID 0x4D
#define PBUS_ORBATAK_TRACKBALL_ID PBUS_MOUSE_ID
#define PBUS_ORBATAK_BUTTONS_ID 0xC0
#define PBUS_JOYPAD_SHIFT_LT 0x02
#define PBUS_JOYPAD_SHIFT_RT 0x03
#define PBUS_JOYPAD_SHIFT_X 0x04
#define PBUS_JOYPAD_SHIFT_P 0x05
#define PBUS_JOYPAD_SHIFT_C 0x06
#define PBUS_JOYPAD_SHIFT_B 0x07
#define PBUS_JOYPAD_SHIFT_A 0x00
#define PBUS_JOYPAD_SHIFT_L 0x01
#define PBUS_JOYPAD_SHIFT_R 0x02
#define PBUS_JOYPAD_SHIFT_U 0x03
#define PBUS_JOYPAD_SHIFT_D 0x04
uint8_t pbus_buf[PBUS_BUF_SIZE];
uint32_t pbus_idx;
void pbus_dma() {
bool jp_d = ImGui::IsKeyPressed(ImGuiKey_DownArrow);
bool jp_u = ImGui::IsKeyPressed(ImGuiKey_UpArrow);
bool jp_r = ImGui::IsKeyPressed(ImGuiKey_RightArrow);
bool jp_l = ImGui::IsKeyPressed(ImGuiKey_LeftArrow);
bool jp_a = ImGui::IsKeyPressed(ImGuiKey_A);
bool jp_b = ImGui::IsKeyPressed(ImGuiKey_B);
bool jp_c = ImGui::IsKeyPressed(ImGuiKey_C);
bool jp_p = ImGui::IsKeyPressed(ImGuiKey_P);
bool jp_x = ImGui::IsKeyPressed(ImGuiKey_X);
bool jp_rt = ImGui::IsKeyPressed(ImGuiKey_R);
bool jp_lt = ImGui::IsKeyPressed(ImGuiKey_L);
uint32_t str = top->rootp->core_3do__DOT__madam_inst__DOT__dma_stack_inst__DOT__dma23_curaddr; // 0x570.
uint32_t len = top->rootp->core_3do__DOT__madam_inst__DOT__dma_stack_inst__DOT__dma23_curlen; // 0x574.
uint32_t end = top->rootp->core_3do__DOT__madam_inst__DOT__dma_stack_inst__DOT__dma23_nextaddr; // 0x578.
uint32_t temp_word = 0x00000000;
str += 4;
len -= 4;
end += 4;
pbus_idx = 0;
pbus_buf[0] = ((PBUS_JOYPAD_ID) |
(jp_d << PBUS_JOYPAD_SHIFT_D) |
(jp_u << PBUS_JOYPAD_SHIFT_U) |
(jp_r << PBUS_JOYPAD_SHIFT_R) |
(jp_l << PBUS_JOYPAD_SHIFT_L) |
(jp_a << PBUS_JOYPAD_SHIFT_A));
pbus_buf[1] = ((jp_b << PBUS_JOYPAD_SHIFT_B) |
(jp_c << PBUS_JOYPAD_SHIFT_C) |
(jp_p << PBUS_JOYPAD_SHIFT_P) |
(jp_x << PBUS_JOYPAD_SHIFT_X) |
(jp_rt << PBUS_JOYPAD_SHIFT_RT) |
(jp_lt << PBUS_JOYPAD_SHIFT_LT));
temp_word = (pbus_buf[0] << 24) | (pbus_buf[1] << 16) | (pbus_buf[2] << 8) | (pbus_buf[3] << 0);
//ram_ptr[ dst&0x1fffff ] = temp_word; // ram_ptr is now BYTE addressed!
fprintf(logfile, "PBUS DMA toRAM: 0x%08X len: 0x%08X fromRAM: 0x%08X\n", str, len, end);
/*
for (int i = 0; i < 8; i+=4) {
ram_ptr[ (dst&0x1fffff)+i ] = pbus_buf[i+0] << 24;
temp_word = ram_ptr[ (dst&0x1fffff)+i ];
ram_ptr[ (dst&0x1fffff)+i ] = temp_word&0xff00ffff | (pbus_buf[i+1] << 16);
temp_word = ram_ptr[ (dst&0x1fffff)+i ];
ram_ptr[ (dst&0x1fffff)+i ] = temp_word&0xffff00ff | (pbus_buf[i+2] << 8);
temp_word = ram_ptr[ (dst&0x1fffff)+i ];
ram_ptr[ (dst&0x1fffff)+i ] = temp_word&0xffffff00 | (pbus_buf[i+3] << 0);
}
*/
//pbus_buf[pbus_idx++] = 0xffffffff; // Pad the last word??
//top->rootp->core_3do__DOT__madam_inst__DOT__dma_stack_inst__DOT__dma23_curaddr += len;
//top->rootp->core_3do__DOT__madam_inst__DOT__dma_stack_inst__DOT__dma23_nextaddr += len;
//0x8000FFFF 0xFFFFFFFF 0xFFFF0000 0xFFFFFFFF
//0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
ram_ptr[str+0]= pbus_buf[0]; ram_ptr[str+1]= pbus_buf[1]; ram_ptr[str+2]= 0xff; ram_ptr[str+3]= 0xff,
ram_ptr[str+4]= 0xff; ram_ptr[str+5]= 0xff; ram_ptr[str+6]= 0xff; ram_ptr[str+7]= 0xff;
ram_ptr[str+8]= 0xff; ram_ptr[str+9]= 0xff; ram_ptr[str+10]=0xff; ram_ptr[str+11]=0xff,
ram_ptr[str+12]=0xff; ram_ptr[str+13]=0xff; ram_ptr[str+14]=0xff; ram_ptr[str+15]=0xff;
ram_ptr[str+16]=0xff; ram_ptr[str+17]=0xff; ram_ptr[str+18]=0x00; ram_ptr[str+19]=0x00,
ram_ptr[str+20]=0xff; ram_ptr[str+21]=0xff; ram_ptr[str+22]=0xff; ram_ptr[str+23]=0xff;
ram_ptr[str+24]=0xff; ram_ptr[str+25]=0xff; ram_ptr[str+26]=0xff; ram_ptr[str+27]=0xff,
ram_ptr[str+28]=0xff; ram_ptr[str+29]=0xff; ram_ptr[str+30]=0xff; ram_ptr[str+31]=0xff;
ram_ptr[str+32]=0xff; ram_ptr[str+33]=0xff; ram_ptr[str+34]=0xff; ram_ptr[str+35]=0xff;
top->rootp->core_3do__DOT__madam_inst__DOT__dma_stack_inst__DOT__dma23_curlen = 0xfffffffc; // Set the length to -4 when done?
top->rootp->core_3do__DOT__clio_inst__DOT__irq1_pend |= 1; // Bit 0 of irq1_pend is the PBUS DMA Done bit.
top->rootp->core_3do__DOT__madam_inst__DOT__mctl &= ~0x8000; // Clear bit 15 (PBUS DMA Enable) of mctl reg.
/*
for (int i=str; i<end; i+=4) {
fprintf(logfile, "0x%08X: ", i);
fprintf(logfile, "0x%02X%02X%02X%02X\n", ram_ptr[i+0], ram_ptr[i+1], ram_ptr[i+2], ram_ptr[i+3]);
}
*/
}
void opera_tick() {
opera_3do_process_frame(&opera_line, &opera_field); // Tweaked, to render one LINE at a time. ElectronAsh.
//opera_arm_execute(); // <- This contains all of our Opera fprintfs.
//opera_clock_push_cycles(main_time);
//if (opera_clock_dsp_queued()) libopera_callback(EXT_DSP_TRIGGER, NULL);
//if (opera_clock_dsp_queued()) opera_lr_dsp_process();
if (opera_clock_dsp_queued()) {
//g_DSP_BUF[g_DSP_BUF_IDX++] = opera_dsp_loop();
//g_DSP_BUF_IDX &= DSP_BUF_SIZE_MASK;
sound_out = opera_dsp_loop(); // Almost certain this is the DSP sound output. ElectronAsh.
//fprintf(soundfile, "Sound 0x%08X: ", sound_out);
if (soundtrace) {
fputc( (sound_out>>24) & 0xff, soundfile);
fputc( (sound_out>>16) & 0xff, soundfile);
fputc( (sound_out>>8) & 0xff, soundfile);
fputc( (sound_out>>0) & 0xff, soundfile);
}
}
}
static void sim_clio_handle_dma(uint32_t val_)
{
if (val_ & 0x00100000) // Check if the Xbus DMA Enable bit in the write to 0x03400304 (CLIO dmactrl) is set.
{
int len; // Needs to be a signed int, so the while (len >= 0) below works.
uint32_t trg;
uint8_t b0, b1, b2, b3;
trg = top->rootp->core_3do__DOT__madam_inst__DOT__dma_stack_inst__DOT__dma20_curaddr; // 0x03300540. DMA Target (Source/Dest address). Likely always the dest, for a CDROM DMA?
len = top->rootp->core_3do__DOT__madam_inst__DOT__dma_stack_inst__DOT__dma20_curlen; // 0x03300544. DMA Length (in BYTES).
fprintf(logfile, "Xbus DMA trg: 0x%08X len: 0x%08X\n", trg, len);
top->rootp->core_3do__DOT__clio_inst__DOT__dmactrl &= ~0x00100000; // Clear bit [20] in the CLIO dmactrl reg.
top->rootp->core_3do__DOT__clio_inst__DOT__expctl &= ~0x80; // Clear bit [7] in the CLIO expctl reg "DMA has control of Xbus".
//if (top->rootp->core_3do__DOT__clio_inst__DOT__expctl & 0x200) // XB_DmadirectION bit.There was an "else" after this "if" in
//{ // the Opera source, but the code was identical.
while (len >= 0) // Very likely because the CDROM drive is always Xbus -> RAM. ElectronAsh.
{
b3 = sim_xbus_fifo_get_data();
b2 = sim_xbus_fifo_get_data();
b1 = sim_xbus_fifo_get_data();
b0 = sim_xbus_fifo_get_data();
//fprintf(logfile, "Addr: 0x%08X 0x%02X%02X%02X%02X\n", trg, b0, b1, b2, b3);
// Mask address, so DMA can only target 2MB main DRAM ,or 1MB VRAM (but not registers?). ElectronAsh.
if (trg < 0x200000) {
ram_ptr[ (trg & 0x1fffff) + 0 ] = b0;
ram_ptr[ (trg & 0x1fffff) + 1 ] = b1;
ram_ptr[ (trg & 0x1fffff) + 2 ] = b2;
ram_ptr[ (trg & 0x1fffff) + 3 ] = b3;
}
/*
else {
vram_ptr[ (trg & 0xfffff) + 0 ] = b0;
vram_ptr[ (trg & 0xfffff) + 1 ] = b1;
vram_ptr[ (trg & 0xfffff) + 2 ] = b2;
vram_ptr[ (trg & 0xfffff) + 3 ] = b3;
}
*/
trg += 4;
len -= 4;
}
top->rootp->core_3do__DOT__clio_inst__DOT__expctl |= 0x80; // Set bit [7] in the CLIO expctl reg "ARM has control of Xbus".
//}
top->rootp->core_3do__DOT__madam_inst__DOT__dma_stack_inst__DOT__dma20_curlen = 0xFFFFFFFC; // Length reg should end up with this value once it wraps 0?
top->rootp->core_3do__DOT__clio_inst__DOT__irq0_pend |= (1<<29); // Set the IRQ0 Pending bit, for "XBus DMA Done"!
}
}
static
void
sim_if_set_set_reset(uint32_t* output_,
uint32_t val_,
uint32_t mask_chk_,
uint32_t mask_set_)
{
if ((val_ & mask_chk_) == mask_chk_)
{
*output_ = ((val_ & mask_set_) ?
(*output_ | mask_set_) :
(*output_ & ~mask_set_));
}
}
void handle_adbio_write() {
sim_if_set_set_reset(&top->rootp->core_3do__DOT__clio_inst__DOT__adbio_reg, top->o_wb_dat, 0x10, 0x01);
sim_if_set_set_reset(&top->rootp->core_3do__DOT__clio_inst__DOT__adbio_reg, top->o_wb_dat, 0x20, 0x02);
sim_if_set_set_reset(&top->rootp->core_3do__DOT__clio_inst__DOT__adbio_reg, top->o_wb_dat, 0x40, 0x04);
sim_if_set_set_reset(&top->rootp->core_3do__DOT__clio_inst__DOT__adbio_reg, top->o_wb_dat, 0x80, 0x08);
}
int verilate() {
if (!Verilated::gotFinish()) {
if (main_time < 50) {
top->reset_n = 0; // Assert reset (active LOW)
frame_count = 0;
}
if (main_time == 50) { // Do == here, so we can still reset it in the main loop.
top->reset_n = 1; // Deassert reset./
}
if (top->reset_n) {
/*
if (top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__u_zap_writeback__DOT__o_trace_valid &&
top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__u_zap_writeback__DOT__o_trace_uop_last)
opera_tick();
*/
map_bios = 0;
top->rootp->core_3do__DOT__madam_inst__DOT__map_bios = 0;
//top->rootp->core_3do__DOT__madam_inst__DOT__nextccb = 0x000BB770;
//top->rootp->core_3do__DOT__madam_inst__DOT__nextccb = 0x000B7ee4;
//top->rootp->core_3do__DOT__madam_inst__DOT__nextccb = 0x000bc4f0;
//top->rootp->core_3do__DOT__madam_inst__DOT__nextccb = 0x000Bfc70;
top->rootp->core_3do__DOT__madam_inst__DOT__nextccb = 0x00000000;
}
pix_count++;
uint16_t spr_wi = (top->rootp->core_3do__DOT__madam_inst__DOT__pre1&0x7ff) + 1;
//uint16_t spr_wi = spr_width;
/*
clut[0x00] = 0x35ED42; clut[0x01] = 0x3035EF; clut[0x02] = 0x31CD35; clut[0x03] = 0xAB2DAD; clut[0x04] = 0x3E0E29; clut[0x05] = 0x8B4650; clut[0x06] = 0x256A25; clut[0x07] = 0x492128;
clut[0x08] = 0x467142; clut[0x09] = 0x514E92; clut[0x0a] = 0x56D44E; clut[0x0b] = 0xB456B2; clut[0x0c] = 0x5EF456; clut[0x0d] = 0xD518E6; clut[0x0e] = 0x1D0614; clut[0x0f] = 0xC56335;
clut[0x10] = 0x5F176B; clut[0x11] = 0x587399; clut[0x12] = 0x77BA7F; clut[0x13] = 0xFF0C62; clut[0x14] = 0x7BDE00; clut[0x15] = 0x010000; clut[0x16] = 0x000000; clut[0x17] = 0x000000;
clut[0x18] = 0x000000; clut[0x19] = 0x003FE6; clut[0x1a] = 0x462000; clut[0x1b] = 0x0B8DB0; clut[0x1c] = 0x000B8D; clut[0x1d] = 0xFC000B; clut[0x1e] = 0xB4F400; clut[0x1f] = 0x800000;
*/
// PLUT, for coded_packed_6bpp.cel...
clut[0x00] = 0x7FFF; clut[0x01] = 0x698C; clut[0x02] = 0x64E8; clut[0x03] = 0x60A6; clut[0x04] = 0x7BBD; clut[0x05] = 0x6B5B; clut[0x06] = 0x5EF7; clut[0x07] = 0x4A52;
clut[0x08] = 0x2951; clut[0x09] = 0x3192; clut[0x0a] = 0x4E73; clut[0x0b] = 0x2110; clut[0x0c] = 0x0C6C; clut[0x0d] = 0x56B5; clut[0x0f] = 0x10AE; clut[0x17] = 0x39CE;
clut[0x10] = 0x294A; clut[0x11] = 0x1084; clut[0x12] = 0x18C0; clut[0x13] = 0x2528; clut[0x14] = 0x318C; clut[0x15] = 0x2108; clut[0x16] = 0x0840; clut[0x17] = 0x2921;
clut[0x18] = 0x0000; clut[0x19] = 0x3161; clut[0x1a] = 0x3DC2; clut[0x1b] = 0x4A02; clut[0x1c] = 0x5E83; clut[0x1d] = 0x6AE3; clut[0x1f] = 0x7B64; clut[0x27] = 0x7F84;
/*
// PLUT, for one of the BIOS "Please Insert CD" screen CELs...
clut[0x00] = 0x35ED; clut[0x01] = 0x4230; clut[0x02] = 0x35EF; clut[0x03] = 0x31CD; clut[0x04] = 0x35AB; clut[0x05] = 0x2DAD; clut[0x06] = 0x3E0E; clut[0x07] = 0x298B;
clut[0x08] = 0x4650; clut[0x09] = 0x256A; clut[0x0a] = 0x2549; clut[0x0b] = 0x2128; clut[0x0c] = 0x4671; clut[0x0d] = 0x4251; clut[0x0e] = 0x4E92; clut[0x0f] = 0x56D4;
clut[0x10] = 0x4EB4; clut[0x11] = 0x56B2; clut[0x12] = 0x5EF4; clut[0x13] = 0x56D5; clut[0x14] = 0x18E6; clut[0x15] = 0x1D06; clut[0x16] = 0x14C5; clut[0x17] = 0x6335;
clut[0x18] = 0x5F17; clut[0x19] = 0x6B58; clut[0x1a] = 0x7399; clut[0x1b] = 0x77BA; clut[0x1c] = 0x7FFF; clut[0x1d] = 0x0C62; clut[0x1e] = 0x7BDE; clut[0x1f] = 0x0001;
clut[0x20] = 0x0000; clut[0x21] = 0x0000; clut[0x22] = 0x0000; clut[0x23] = 0x0000; clut[0x24] = 0x0000; clut[0x25] = 0x0000; clut[0x26] = 0x3FE6; clut[0x27] = 0x4620;
clut[0x28] = 0x000B; clut[0x29] = 0x8DB0; clut[0x2a] = 0x000B; clut[0x2b] = 0x8DFC; clut[0x2c] = 0x000B; clut[0x2d] = 0xB4F4; clut[0x2e] = 0x0080; clut[0x2f] = 0x0000;
*/
//if (top->i_wb_dat==0x00f00104) run_enable = 0;
/*
//if (my_x == spr_wi || top->rootp->core_3do__DOT__madam_inst__DOT__unpacker_inst__DOT__eol) {
if (top->rootp->core_3do__DOT__madam_inst__DOT__unpacker_inst__DOT__eol) {
my_x = 0;
my_y++;
}
if (top->rootp->core_3do__DOT__madam_inst__DOT__unpacker_inst__DOT__pix_valid) {
uint16_t colour = clut[top->rootp->core_3do__DOT__madam_inst__DOT__unpacker_inst__DOT__col_out];
rgb[0] = (colour & 0x7C00) >> 7;
rgb[1] = (colour & 0x03E0) >> 2;
rgb[2] = (colour & 0x001F) << 3;
disp_ptr[ ((my_y*320) + my_x) & 0xfffff] = 0xff<<24 | rgb[2]<<16 | rgb[1]<<8 | rgb[0]; // ABGR.
my_x++;
}
*/
//jp_a = top->rootp->core_3do__DOT__clio_inst__DOT__field; // Toggling "A" button, to test joypad. (works in BIOS joypad test)
//cur_pc = top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__pc_from_alu;
//cur_pc = top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__u_zap_alu_main__DOT__o_pc_plus_8_ff;
//cur_pc = top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__postalu_pc_plus_8_ff - 8;
cur_pc = top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__u_zap_writeback__DOT__i_pc_plus_8_buf_ff - 8;
//if (top->mem_addr==0x000011664) run_enable = 0;
//if (cur_pc==0x00000ee0) run_enable=0;
//if (top->mem_addr==0x0000FEDC && top->o_wb_we) run_enable = 0;
/*
if (frame_count==30 && top->rootp->core_3do__DOT__clio_inst__DOT__hcnt==0 && top->rootp->core_3do__DOT__clio_inst__DOT__vcnt==9) {
run_enable = 0;
//inst_trace = 1;
}
*/
/*
if (cur_pc == 0x000117F8) {
inst_trace = 1;
//run_enable = 0;
}
*/
uint32_t decode_word[16];
uint32_t issue_word[16];
uint32_t shifter_word[16];
uint32_t alu_word[16];
uint32_t memory_word[16];
uint32_t rb_word[16];
for (int i = 0; i < 16; i++) {
decode_word[i] = top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__decode_decompile[i];
issue_word[i] = top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__issue_decompile[i];
shifter_word[i] = top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__shifter_decompile[i];
alu_word[i] = top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__alu_decompile[i];
memory_word[i] = top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__memory_decompile[i];
rb_word[i] = top->rootp->core_3do__DOT__zap_top_inst__DOT__u_zap_core__DOT__rb_decompile[i];
}
for (int i = 0; i < 64; i += 4) {