-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathProject.out.sdc
120 lines (76 loc) · 4.62 KB
/
Project.out.sdc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
## Generated SDC file "Project.out.sdc"
## Copyright (C) 2020 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and any partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors. Please
## refer to the applicable agreement for further details, at
## https://fpgasoftware.intel.com/eula.
## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
## DATE "Thu Jun 02 14:10:06 2022"
##
## DEVICE "EP4CE115F29C7"
##
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {clock} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]
create_clock -name {processorClock} -period 500.000 -waveform { 0.000 250.000 } [get_nets {Filter|Out}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {processorClock}] -rise_to [get_clocks {processorClock}] 1.000
set_clock_uncertainty -rise_from [get_clocks {processorClock}] -fall_to [get_clocks {processorClock}] 1.000
set_clock_uncertainty -fall_from [get_clocks {processorClock}] -rise_to [get_clocks {processorClock}] 1.000
set_clock_uncertainty -fall_from [get_clocks {processorClock}] -fall_to [get_clocks {processorClock}] 1.000
set_clock_uncertainty -rise_from [get_clocks {clock}] -rise_to [get_clocks {clock}] 1.000
set_clock_uncertainty -rise_from [get_clocks {clock}] -fall_to [get_clocks {clock}] 1.000
set_clock_uncertainty -fall_from [get_clocks {clock}] -rise_to [get_clocks {clock}] 1.000
set_clock_uncertainty -fall_from [get_clocks {clock}] -fall_to [get_clocks {clock}] 1.000
#set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] 1.000
#set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] 1.000
#set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] 1.000
#set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] 1.000
#**************************************************************
# Set Input Delay
#**************************************************************
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************