From 4242a4e4cf774eb266f27c92ec99233e7de8a77f Mon Sep 17 00:00:00 2001
From: Paulo Matos <pmatos@igalia.com>
Date: Wed, 22 Jan 2025 10:07:36 +0100
Subject: [PATCH] instcount: Ensure predicate cache is reset when control flow
 leaves block

---
 unittests/InstructionCountCI/X87ldst-SVE.json | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json
index 81b6b205cd..b715c7907a 100644
--- a/unittests/InstructionCountCI/X87ldst-SVE.json
+++ b/unittests/InstructionCountCI/X87ldst-SVE.json
@@ -55,8 +55,8 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0xa (10)",
+        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w22, w22, w20",
@@ -96,8 +96,8 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0xa (10)",
+        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
@@ -108,8 +108,8 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x14 (20)",
+        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
@@ -120,8 +120,8 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x1e (30)",
+        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
@@ -132,8 +132,8 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x28 (40)",
+        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
@@ -144,8 +144,8 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x32 (50)",
+        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
@@ -156,8 +156,8 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x3c (60)",
+        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w23, w22, w20",
@@ -168,8 +168,8 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
-        "ptrue p2.h, vl5",
         "add x21, x4, #0x46 (70)",
+        "ptrue p2.h, vl5",
         "st1h {z2.h}, p2, [x21]",
         "ldrb w21, [x28, #1298]",
         "lsl w22, w22, w20",