diff --git a/verilog/dv/cocotb/all_tests/bitbang/bitbang_cpu_all_i.c b/verilog/dv/cocotb/all_tests/bitbang/bitbang_cpu_all_i.c index f93586d46..968e09e45 100644 --- a/verilog/dv/cocotb/all_tests/bitbang/bitbang_cpu_all_i.c +++ b/verilog/dv/cocotb/all_tests/bitbang/bitbang_cpu_all_i.c @@ -1,6 +1,7 @@ #include #include +#include void main(){ enable_debug(); @@ -27,7 +28,7 @@ void main(){ void wait_over_input_l(unsigned int start_code, unsigned int exp_val){ set_debug_reg1(start_code); // configuration done wait environment to send exp_val to reg_mprj_datal - GPIOs_waitLow(exp_val); + GPIOs_waitLow_dft(exp_val); set_debug_reg2(GPIOs_readLow()); } diff --git a/verilog/dv/cocotb/all_tests/bitbang/bitbang_spi_i.c b/verilog/dv/cocotb/all_tests/bitbang/bitbang_spi_i.c index fb5fad24d..3be3c2717 100644 --- a/verilog/dv/cocotb/all_tests/bitbang/bitbang_spi_i.c +++ b/verilog/dv/cocotb/all_tests/bitbang/bitbang_spi_i.c @@ -1,4 +1,5 @@ #include +#include @@ -34,7 +35,7 @@ void main() void wait_over_input_l(unsigned int start_code, unsigned int exp_val){ set_debug_reg1(start_code); // configuration done wait environment to send exp_val to reg_mprj_datal - GPIOs_waitLow(exp_val); + GPIOs_waitLow_dft(exp_val); set_debug_reg2(GPIOs_readLow()); } diff --git a/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests.py b/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests.py index 3f88adbab..69bfc9289 100644 --- a/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests.py +++ b/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests.py @@ -3,7 +3,7 @@ import cocotb.log from caravel_cocotb.interfaces.cpu import RiskV from caravel_cocotb.interfaces.defsParser import Regs -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import GPIO_MODE @@ -14,7 +14,7 @@ @cocotb.test() @report_test async def bitbang_no_cpu_all_o(dut): - caravelEnv = await test_configure(dut, timeout_cycles=119373) + caravelEnv = await test_configure_dft(dut, timeout_cycles=119373) cpu = RiskV(dut) cpu.cpu_force_reset() await cpu.drive_data2address( @@ -217,7 +217,7 @@ async def bitbang_no_cpu_all_o(dut): @cocotb.test() @report_test async def bitbang_no_cpu_all_i(dut): - caravelEnv = await test_configure(dut, timeout_cycles=117351) + caravelEnv = await test_configure_dft(dut, timeout_cycles=117351) cpu = RiskV(dut) cpu.cpu_force_reset() await cpu.drive_data2address( diff --git a/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests_cpu.py index df7ccd2ff..35808d813 100644 --- a/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests_cpu.py +++ b/verilog/dv/cocotb/all_tests/bitbang/bitbang_tests_cpu.py @@ -2,7 +2,7 @@ from cocotb.triggers import ClockCycles import cocotb.log from caravel_cocotb.interfaces.defsParser import Regs -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import GPIO_MODE from all_tests.gpio.gpio_seq import gpio_all_o_seq @@ -17,7 +17,7 @@ @cocotb.test() @report_test async def bitbang_cpu_all_o(dut): - caravelEnv = await test_configure(dut, timeout_cycles=5004275) + caravelEnv = await test_configure_dft(dut, timeout_cycles=5004275) debug_regs = await configure_userdesign(caravelEnv) await gpio_all_o_seq(dut, caravelEnv, debug_regs) @@ -25,7 +25,7 @@ async def bitbang_cpu_all_o(dut): @cocotb.test() @report_test async def bitbang_cpu_all_i(dut): - caravelEnv = await test_configure(dut, timeout_cycles=3311179) + caravelEnv = await test_configure_dft(dut, timeout_cycles=3311179) debug_regs = await configure_userdesign(caravelEnv) await gpio_all_i_seq(dut, caravelEnv, debug_regs) @@ -36,7 +36,7 @@ async def bitbang_cpu_all_i(dut): @cocotb.test() @report_test async def bitbang_spi_o(dut): - caravelEnv = await test_configure(dut, timeout_cycles=2008592) + caravelEnv = await test_configure_dft(dut, timeout_cycles=2008592) debug_regs = await configure_userdesign(caravelEnv) await gpio_all_o_seq(dut, caravelEnv, debug_regs, bitbang_spi_o_configure) @@ -47,7 +47,7 @@ async def bitbang_spi_o(dut): @cocotb.test() @report_test async def bitbang_spi_i(dut): - caravelEnv = await test_configure(dut, timeout_cycles=316406) + caravelEnv = await test_configure_dft(dut, timeout_cycles=316406) debug_regs = await configure_userdesign(caravelEnv) await gpio_all_i_seq(dut, caravelEnv, debug_regs, bitbang_spi_i_configure) diff --git a/verilog/dv/cocotb/all_tests/check_defaults/check_defaults.py b/verilog/dv/cocotb/all_tests/check_defaults/check_defaults.py index f650d5592..c288ae22e 100644 --- a/verilog/dv/cocotb/all_tests/check_defaults/check_defaults.py +++ b/verilog/dv/cocotb/all_tests/check_defaults/check_defaults.py @@ -4,14 +4,14 @@ from cocotb.queue import Queue from cocotb.triggers import Combine from user_design import configure_userdesign -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_monitor_driver import UserPins @cocotb.test() @report_test async def check_defaults(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1145328) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1145328) debug_regs = await configure_userdesign(caravelEnv) user_pins = UserPins(caravelEnv) gpio_test = GPIOsDefaultTests(caravelEnv, user_pins, debug_regs) diff --git a/verilog/dv/cocotb/all_tests/common/common.py b/verilog/dv/cocotb/all_tests/common/common.py new file mode 100644 index 000000000..95df1a807 --- /dev/null +++ b/verilog/dv/cocotb/all_tests/common/common.py @@ -0,0 +1,31 @@ +import cocotb +from caravel_cocotb.interfaces.common_functions.test_functions import read_config_file, test_configure + + +from cocotb.triggers import ClockCycles + +async def test_configure_dft(dut: cocotb.handle.SimHandle, + timeout_cycles=1000000, + clk=read_config_file()['clock'], + timeout_precision=0.2, + num_error=int(read_config_file()['max_err']), + start_up=True): + disable_jtag_testmode(dut) + caravelEnv = await test_configure(dut, timeout_cycles, clk, timeout_precision, num_error, start_up=False) + # manual start udisable_jtag_testmodep + await caravelEnv.power_up() + await caravelEnv.disable_csb() # no need for this anymore as default for gpio3 is now pullup + await caravelEnv.reset() + await caravelEnv.disable_bins(ignore_bins=[3, 4, 28, 29, 30, 31]) + await ClockCycles(caravelEnv.clk, 10) + return caravelEnv + +def disable_jtag_testmode(dut): + dut.gpio28_en.value = 1 + dut.gpio28.value = 0 + dut.gpio29_en.value = 1 + dut.gpio29.value = 0 + dut.gpio30_en.value = 1 + dut.gpio30.value = 0 + dut.gpio31_en.value = 1 + dut.gpio31.value = 0 \ No newline at end of file diff --git a/verilog/dv/cocotb/all_tests/cpu/cpu_reset.py b/verilog/dv/cocotb/all_tests/cpu/cpu_reset.py index 9d2c18ac9..d7ed4551d 100644 --- a/verilog/dv/cocotb/all_tests/cpu/cpu_reset.py +++ b/verilog/dv/cocotb/all_tests/cpu/cpu_reset.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import SPI from user_design import configure_userdesign @@ -10,7 +10,7 @@ @cocotb.test() @report_test async def cpu_reset(dut): - caravelEnv = await test_configure(dut, timeout_cycles=121372) + caravelEnv = await test_configure_dft(dut, timeout_cycles=121372) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start cpu_reset test") diff --git a/verilog/dv/cocotb/all_tests/cpu/cpu_stress.py b/verilog/dv/cocotb/all_tests/cpu/cpu_stress.py index 9543aa6ba..9d2d04a3f 100644 --- a/verilog/dv/cocotb/all_tests/cpu/cpu_stress.py +++ b/verilog/dv/cocotb/all_tests/cpu/cpu_stress.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -11,7 +11,7 @@ @cocotb.test() @report_test async def cpu_stress(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1747660) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1747660) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start CPU stress test") pass_list = (0x1B, 0x2B, 0x3B, 0x4B, 0x5B) diff --git a/verilog/dv/cocotb/all_tests/debug/debug.py b/verilog/dv/cocotb/all_tests/debug/debug.py index 03520e8a8..17fa14dde 100644 --- a/verilog/dv/cocotb/all_tests/debug/debug.py +++ b/verilog/dv/cocotb/all_tests/debug/debug.py @@ -2,7 +2,7 @@ import cocotb from cocotb.triggers import Timer import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -12,7 +12,7 @@ @cocotb.test() @report_test async def debug(dut): - caravelEnv = await test_configure(dut, timeout_cycles=81933) + caravelEnv = await test_configure_dft(dut, timeout_cycles=81933) debug_regs = await configure_userdesign(caravelEnv) # calculate bit time clock = caravelEnv.get_clock_obj() diff --git a/verilog/dv/cocotb/all_tests/debug/debug_swd.py b/verilog/dv/cocotb/all_tests/debug/debug_swd.py index 5dfe0c2fa..2e8c6e387 100644 --- a/verilog/dv/cocotb/all_tests/debug/debug_swd.py +++ b/verilog/dv/cocotb/all_tests/debug/debug_swd.py @@ -2,7 +2,7 @@ import cocotb from cocotb.triggers import FallingEdge, RisingEdge, ClockCycles, Timer import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from collections import namedtuple from cocotb.handle import Force @@ -23,7 +23,7 @@ async def debug_swd(dut): dut._id(f"gpio{35}", False).value = 0 dut._id(f"gpio{35}_en", False).value = Force(1) - caravelEnv = await test_configure(dut, timeout_cycles=1131011) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1131011) debug_regs = await configure_userdesign(caravelEnv) caravelEnv.drive_gpio_in(0, 1) caravelEnv.drive_gpio_in(35, 0) diff --git a/verilog/dv/cocotb/all_tests/flash_clk/flash_clk.py b/verilog/dv/cocotb/all_tests/flash_clk/flash_clk.py index ff5c9d909..b7bdef3f9 100644 --- a/verilog/dv/cocotb/all_tests/flash_clk/flash_clk.py +++ b/verilog/dv/cocotb/all_tests/flash_clk/flash_clk.py @@ -1,11 +1,11 @@ import cocotb from cocotb.triggers import Edge, RisingEdge, FallingEdge, ClockCycles -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test @cocotb.test() @report_test async def flash_clk(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1999191) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1999191) clock = caravelEnv.get_clock_period() csb = dut.flash_csb_tb clk = dut.flash_clk_tb diff --git a/verilog/dv/cocotb/all_tests/gpio/gpio.py b/verilog/dv/cocotb/all_tests/gpio/gpio.py index 4888c5f58..fb098a328 100644 --- a/verilog/dv/cocotb/all_tests/gpio/gpio.py +++ b/verilog/dv/cocotb/all_tests/gpio/gpio.py @@ -1,5 +1,5 @@ import cocotb -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from all_tests.gpio.gpio_seq import gpio_all_o_seq from all_tests.gpio.gpio_seq import gpio_all_i_seq @@ -11,7 +11,7 @@ @cocotb.test() @report_test async def gpio_all_o(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1999191) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1999191) debug_regs = await configure_userdesign(caravelEnv) await gpio_all_o_seq(dut, caravelEnv, debug_regs) @@ -19,7 +19,7 @@ async def gpio_all_o(dut): @cocotb.test() @report_test async def gpio_all_i(dut): - caravelEnv = await test_configure(dut, timeout_cycles=295677) + caravelEnv = await test_configure_dft(dut, timeout_cycles=22014) debug_regs = await configure_userdesign(caravelEnv) await gpio_all_i_seq(dut, caravelEnv, debug_regs) @@ -27,7 +27,7 @@ async def gpio_all_i(dut): @cocotb.test() @report_test async def gpio_all_i_pu(dut): - caravelEnv = await test_configure(dut, timeout_cycles=69978) + caravelEnv = await test_configure_dft(dut, timeout_cycles=16815) debug_regs = await configure_userdesign(caravelEnv) await gpio_all_i_pu_seq(dut, caravelEnv, debug_regs) @@ -35,6 +35,6 @@ async def gpio_all_i_pu(dut): @cocotb.test() @report_test async def gpio_all_i_pd(dut): - caravelEnv = await test_configure(dut, timeout_cycles=69978) + caravelEnv = await test_configure_dft(dut, timeout_cycles=69978) debug_regs = await configure_userdesign(caravelEnv) await gpio_all_i_pd_seq(dut, caravelEnv, debug_regs) diff --git a/verilog/dv/cocotb/all_tests/gpio/gpio_all_i.c b/verilog/dv/cocotb/all_tests/gpio/gpio_all_i.c index 8bf216d2f..ddfb7c92b 100644 --- a/verilog/dv/cocotb/all_tests/gpio/gpio_all_i.c +++ b/verilog/dv/cocotb/all_tests/gpio/gpio_all_i.c @@ -1,5 +1,5 @@ #include - +#include void main(){ enable_debug(); enableHkSpi(0); @@ -26,7 +26,7 @@ void main(){ void wait_over_input_l(unsigned int start_code, unsigned int exp_val){ set_debug_reg1(start_code); // configuration done wait environment to send exp_val to reg_mprj_datal - GPIOs_waitLow(exp_val); + GPIOs_waitLow_dft(exp_val); set_debug_reg2(GPIOs_readLow()); } diff --git a/verilog/dv/cocotb/all_tests/gpio/gpio_seq.py b/verilog/dv/cocotb/all_tests/gpio/gpio_seq.py index fe3db07ea..e77022d31 100644 --- a/verilog/dv/cocotb/all_tests/gpio/gpio_seq.py +++ b/verilog/dv/cocotb/all_tests/gpio/gpio_seq.py @@ -11,11 +11,11 @@ async def gpio_all_i_seq(dut, caravelEnv, debug_regs, after_config_callback=None cocotb.log.info("[TEST] configuration finished") if after_config_callback is not None: await after_config_callback(caravelEnv, debug_regs) - data_in = 0xFFFFFFFF + data_in = 0x7FFFFFF cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31, 0), data_in) await debug_regs.wait_reg1(0xBB) - if debug_regs.read_debug_reg2() == data_in: + if debug_regs.read_debug_reg2() & 0x7FFFFFF == data_in: cocotb.log.info( f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]" ) @@ -23,11 +23,11 @@ async def gpio_all_i_seq(dut, caravelEnv, debug_regs, after_config_callback=None cocotb.log.error( f"[TEST] Error: reg_mprj_datal has recieved wrong data {debug_regs.read_debug_reg2()} instead of {data_in}" ) - data_in = 0xAAAAAAAA + data_in = 0xAAAAAAAA & 0x7FFFFFF cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31, 0), data_in) await debug_regs.wait_reg1(0xCC) - if debug_regs.read_debug_reg2() == data_in: + if debug_regs.read_debug_reg2() & 0x7FFFFFF == data_in: cocotb.log.info( f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]" ) @@ -35,11 +35,11 @@ async def gpio_all_i_seq(dut, caravelEnv, debug_regs, after_config_callback=None cocotb.log.error( f"[TEST] Error: reg_mprj_datal has recieved wrong data {debug_regs.read_debug_reg2()} instead of {data_in}" ) - data_in = 0x55555555 + data_in = 0x55555555 & 0x7FFFFFF cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31, 0), data_in) await debug_regs.wait_reg1(0xDD) - if debug_regs.read_debug_reg2() == data_in: + if debug_regs.read_debug_reg2() & 0x7FFFFFF == data_in: cocotb.log.info( f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]" ) @@ -193,8 +193,12 @@ async def gpio_all_i_pd_seq(dut, caravelEnv, debug_regs): # monitor the output of padframe module it suppose to be all ones when no input is applied await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] + jtag_list = [31, 30, 29, 28, 27] + gpios_list = [i for i in range(active_gpios_num + 1) if i not in jtag_list] + gpios_odd_list = [i for i in range(active_gpios_num + 1) if i not in jtag_list and i%2==1] + gpios_even_list = [i for i in range(active_gpios_num + 1) if i not in jtag_list and i%2==0] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "0": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and float" @@ -206,20 +210,20 @@ async def gpio_all_i_pd_seq(dut, caravelEnv, debug_regs): await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "0": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with 0" ) await ClockCycles(caravelEnv.clk, 100) # drive gpios with ones - data_in = 0x3FFFFFFFFF + data_in = 0x3FFFFFFFFF & 0x3F07FFFFFF data_in = int(bin(data_in).replace("0b", "")[-active_gpios_num - 1:], 2) caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "1": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with 1" @@ -228,12 +232,12 @@ async def gpio_all_i_pd_seq(dut, caravelEnv, debug_regs): # drive odd half gpios with zeros and float other half data_in = 0x0 caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) - for i in range(0, 38, 2): + for i in gpios_even_list: caravelEnv.release_gpio(i) # release even gpios await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "0": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 0" @@ -242,27 +246,27 @@ async def gpio_all_i_pd_seq(dut, caravelEnv, debug_regs): await ClockCycles(caravelEnv.clk, 100) # drive even half gpios with zeros and float other half caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) - for i in range(1, 38, 2): + for i in gpios_odd_list: caravelEnv.release_gpio(i) # release odd gpios await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "0": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with even half with 0" ) await ClockCycles(caravelEnv.clk, 100) # drive odd half gpios with ones and float other half - data_in = 0x3FFFFFFFFF + data_in = 0x3FFFFFFFFF & 0x3F07FFFFFF data_in = int(bin(data_in).replace("0b", "")[-active_gpios_num - 1:], 2) caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) - for i in range(0, 38, 2): + for i in gpios_even_list: caravelEnv.release_gpio(i) # release even gpios await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if i % 2 == 0: # even if gpio[i] != "0": cocotb.log.error( @@ -277,12 +281,12 @@ async def gpio_all_i_pd_seq(dut, caravelEnv, debug_regs): await ClockCycles(caravelEnv.clk, 100) # drive even half gpios with zeros and float other half caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) - for i in range(1, 38, 2): + for i in gpios_odd_list: caravelEnv.release_gpio(i) # release odd gpios await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if i % 2 == 1: # odd if gpio[i] != "0": cocotb.log.error( @@ -297,15 +301,16 @@ async def gpio_all_i_pd_seq(dut, caravelEnv, debug_regs): await ClockCycles(caravelEnv.clk, 100) # drive with ones then release all gpio - data_in = 0x3FFFFFFFFF + data_in = 0x3FFFFFFFFF & 0x3F07FFFFFF data_in = int(bin(data_in).replace("0b", "")[-active_gpios_num - 1:], 2) caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) await ClockCycles(caravelEnv.clk, 100) - caravelEnv.release_gpio((active_gpios_num, 0)) + for i in gpios_list: + caravelEnv.release_gpio(i) await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "0": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and all released" @@ -320,8 +325,12 @@ async def gpio_all_i_pu_seq(dut, caravelEnv, debug_regs): # monitor the output of padframe module it suppose to be all ones when no input is applied await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] + jtag_list = [31, 30, 29, 28, 27] + gpios_list = [i for i in range(active_gpios_num + 1) if i not in jtag_list] + gpios_odd_list = [i for i in range(active_gpios_num + 1) if i not in jtag_list and i%2==1] + gpios_even_list = [i for i in range(active_gpios_num + 1) if i not in jtag_list and i%2==0] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "1": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {i} instead of 1 while configured as input pullup and float" @@ -333,20 +342,20 @@ async def gpio_all_i_pu_seq(dut, caravelEnv, debug_regs): await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "0": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with 0" ) await ClockCycles(caravelEnv.clk, 100) # drive gpios with ones - data_in = 0x3FFFFFFFFF + data_in = 0x3FFFFFFFFF & 0x3F07FFFFFF data_in = int(bin(data_in).replace("0b", "")[-active_gpios_num - 1:], 2) caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "1": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with 1" @@ -355,14 +364,15 @@ async def gpio_all_i_pu_seq(dut, caravelEnv, debug_regs): # drive odd half gpios with zeros and float other half data_in = 0x0 caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) - for i in range(0, active_gpios_num + 1, 2): + for i in gpios_even_list: caravelEnv.release_gpio(i) # release even gpios await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if i % 2 == 1: # odd if gpio[i] != "0": + cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with odd half with 0" ) @@ -374,12 +384,12 @@ async def gpio_all_i_pu_seq(dut, caravelEnv, debug_regs): await ClockCycles(caravelEnv.clk, 100) # drive even half gpios with zeros and float other half caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) - for i in range(1, active_gpios_num + 1, 2): + for i in gpios_odd_list: caravelEnv.release_gpio(i) # release odd gpios await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if i % 2 == 1: # odd if gpio[i] != "1": cocotb.log.error( @@ -392,15 +402,15 @@ async def gpio_all_i_pu_seq(dut, caravelEnv, debug_regs): ) await ClockCycles(caravelEnv.clk, 100) # drive odd half gpios with ones and float other half - data_in = 0x3FFFFFFFFF + data_in = 0x3FFFFFFFFF & 0x3F07FFFFFF data_in = int(bin(data_in).replace("0b", "")[-active_gpios_num - 1:], 2) caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) - for i in range(0, active_gpios_num + 1, 2): + for i in gpios_even_list: caravelEnv.release_gpio(i) # release even gpios await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "1": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with odd half with 1" @@ -409,12 +419,12 @@ async def gpio_all_i_pu_seq(dut, caravelEnv, debug_regs): await ClockCycles(caravelEnv.clk, 100) # drive even half gpios with zeros and float other half caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) - for i in range(1, active_gpios_num + 1, 2): + for i in gpios_odd_list: caravelEnv.release_gpio(i) # release odd gpios await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "1": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with even half with 1" @@ -426,11 +436,12 @@ async def gpio_all_i_pu_seq(dut, caravelEnv, debug_regs): data_in = 0x0 caravelEnv.drive_gpio_in((active_gpios_num, 0), data_in) await ClockCycles(caravelEnv.clk, 100) - caravelEnv.release_gpio((active_gpios_num, 0)) + for i in gpios_list: + caravelEnv.release_gpio(i) await ClockCycles(caravelEnv.clk, 100) gpio = dut.uut.padframe.mprj_io_in.value.binstr[::-1] cocotb.log.info(f"mprj value seen = {gpio}") - for i in range(active_gpios_num + 1): + for i in gpios_list: if gpio[i] != "1": cocotb.log.error( f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and all released" diff --git a/verilog/dv/cocotb/all_tests/gpio/gpio_user.py b/verilog/dv/cocotb/all_tests/gpio/gpio_user.py index 5a8a016a1..295d40640 100644 --- a/verilog/dv/cocotb/all_tests/gpio/gpio_user.py +++ b/verilog/dv/cocotb/all_tests/gpio/gpio_user.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles, Edge import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from all_tests.gpio.gpio_seq import gpio_all_o_seq from all_tests.gpio.gpio_seq import gpio_all_i_seq @@ -13,7 +13,7 @@ @cocotb.test() @report_test async def gpio_all_o_user(dut): - caravelEnv = await test_configure(dut, timeout_cycles=2010463) + caravelEnv = await test_configure_dft(dut, timeout_cycles=2010463) debug_regs = await configure_userdesign(caravelEnv, gpio_test=gpio_all_o_vip) await gpio_all_o_seq(dut, caravelEnv, debug_regs) @@ -42,7 +42,7 @@ async def gpio_all_o_vip(caravelEnv, debug_regs, IOs): @cocotb.test() @report_test async def gpio_all_i_user(dut): - caravelEnv = await test_configure(dut, timeout_cycles=287465) + caravelEnv = await test_configure_dft(dut, timeout_cycles=14968) debug_regs = await configure_userdesign(caravelEnv, gpio_test=gpio_all_i_vip) await gpio_all_i_seq(dut, caravelEnv, debug_regs) @@ -67,7 +67,7 @@ async def wait_over_input(start_code, exp_val, debug_regs, io_in, high=False): debug_regs.write_debug_reg1_backdoor(start_code) while True: io_in_val = io_in.value.integer if not high else io_in.value.integer >> 32 - if io_in_val == exp_val: + if io_in_val & 0x7FFFFFF == exp_val & 0x7FFFFFF: break await Edge(io_in) debug_regs.write_debug_reg2_backdoor(io_in_val) @@ -77,7 +77,7 @@ async def wait_over_input(start_code, exp_val, debug_regs, io_in, high=False): @cocotb.test() @report_test async def gpio_all_i_pu_user(dut): - caravelEnv = await test_configure(dut, timeout_cycles=86252) + caravelEnv = await test_configure_dft(dut, timeout_cycles=86252) debug_regs = await configure_userdesign(caravelEnv, gpio_test=gpio_all_pu_vip) await gpio_all_i_pu_seq(dut, caravelEnv, debug_regs) @@ -91,7 +91,7 @@ async def gpio_all_pu_vip(caravelEnv, debug_regs, IOs): @cocotb.test() @report_test async def gpio_all_i_pd_user(dut): - caravelEnv = await test_configure(dut, timeout_cycles=76198) + caravelEnv = await test_configure_dft(dut, timeout_cycles=76198) debug_regs = await configure_userdesign(caravelEnv, gpio_test=gpio_all_pd_vip) await gpio_all_i_pd_seq(dut, caravelEnv, debug_regs) @@ -105,9 +105,9 @@ async def gpio_all_pd_vip(caravelEnv, debug_regs, IOs): @cocotb.test() @report_test async def gpio_all_bidir_user(dut): - caravelEnv = await test_configure(dut, timeout_cycles=2259813) + caravelEnv = await test_configure_dft(dut, timeout_cycles=2259813) active_gpios_num = caravelEnv.active_gpios_num -1 - debug_regs = await configure_userdesign(caravelEnv, gpio_test=gpio_all_bidir_vip) + debug_regs = await configure_userdesign(caravelEnv, gpio_test=gpio_all_bidir_vip) await debug_regs.wait_reg1(0x1A) await caravelEnv.release_csb() cocotb.log.info("[TEST] finish configuring ") diff --git a/verilog/dv/cocotb/all_tests/gpio_caravan/gpio_caravan.py b/verilog/dv/cocotb/all_tests/gpio_caravan/gpio_caravan.py index 95494547c..f2f632872 100644 --- a/verilog/dv/cocotb/all_tests/gpio_caravan/gpio_caravan.py +++ b/verilog/dv/cocotb/all_tests/gpio_caravan/gpio_caravan.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -9,7 +9,7 @@ @cocotb.test() @report_test async def gpio_all_o_caravan(dut): - caravelEnv = await test_configure(dut, timeout_cycles=11586652) + caravelEnv = await test_configure_dft(dut, timeout_cycles=11586652) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0xAA) @@ -75,7 +75,7 @@ async def gpio_all_o_caravan(dut): @cocotb.test() @report_test async def gpio_all_i_caravan(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1156837) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1156837) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0xAA) cocotb.log.info("[TEST] configuration finished") @@ -198,7 +198,7 @@ async def gpio_all_i_caravan(dut): @cocotb.test() @report_test async def gpio_all_i_pu_caravan(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1158961, num_error=2000) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1158961, num_error=2000) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0xAA) await caravelEnv.release_csb() @@ -358,7 +358,7 @@ async def gpio_all_i_pu_caravan(dut): @cocotb.test() @report_test async def gpio_all_i_pd_caravan(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1158961, num_error=2000) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1158961, num_error=2000) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0xAA) await caravelEnv.release_csb() @@ -520,7 +520,7 @@ async def gpio_all_i_pd_caravan(dut): @cocotb.test() @report_test async def gpio_all_bidir(dut): - caravelEnv = await test_configure(dut, timeout_cycles=111144980) + caravelEnv = await test_configure_dft(dut, timeout_cycles=111144980) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0x1A) await caravelEnv.release_csb() diff --git a/verilog/dv/cocotb/all_tests/gpio_caravan/gpio_user.py b/verilog/dv/cocotb/all_tests/gpio_caravan/gpio_user.py index b2eb1df7f..2f7ac7ef8 100644 --- a/verilog/dv/cocotb/all_tests/gpio_caravan/gpio_user.py +++ b/verilog/dv/cocotb/all_tests/gpio_caravan/gpio_user.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -9,7 +9,7 @@ @cocotb.test() @report_test async def gpio_all_o_user(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1850952) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1850952) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0xAA) await caravelEnv.release_csb() @@ -79,7 +79,7 @@ async def gpio_all_o_user(dut): @cocotb.test() @report_test async def gpio_all_i_user(dut): - caravelEnv = await test_configure(dut, timeout_cycles=258608) + caravelEnv = await test_configure_dft(dut, timeout_cycles=258608) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0xAA) cocotb.log.info("[TEST] configuration finished") @@ -197,7 +197,7 @@ async def gpio_all_i_user(dut): @cocotb.test() @report_test async def gpio_all_i_pu_user(dut): - caravelEnv = await test_configure(dut, timeout_cycles=75919, num_error=2000) + caravelEnv = await test_configure_dft(dut, timeout_cycles=75919, num_error=2000) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0xAA) await caravelEnv.release_csb() @@ -315,7 +315,7 @@ async def gpio_all_i_pu_user(dut): @cocotb.test() @report_test async def gpio_all_i_pd_user(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1158961, num_error=2000) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1158961, num_error=2000) debug_regs = await configure_userdesign(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0xAA) @@ -435,7 +435,7 @@ async def gpio_all_i_pd_user(dut): @cocotb.test() @report_test async def gpio_all_bidir_user(dut): - caravelEnv = await test_configure(dut, timeout_cycles=2001341) + caravelEnv = await test_configure_dft(dut, timeout_cycles=2001341) debug_regs = await configure_userdesign(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0x1A) diff --git a/verilog/dv/cocotb/all_tests/hello_world/helloWorld.py b/verilog/dv/cocotb/all_tests/hello_world/helloWorld.py index afc78b63f..e0b05b125 100644 --- a/verilog/dv/cocotb/all_tests/hello_world/helloWorld.py +++ b/verilog/dv/cocotb/all_tests/hello_world/helloWorld.py @@ -1,5 +1,5 @@ import cocotb -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from cocotb.triggers import ClockCycles @@ -7,6 +7,6 @@ @cocotb.test() @report_test async def helloWorld(dut): - caravelEnv = await test_configure(dut) + caravelEnv = await test_configure_dft(dut) cocotb.log.info("[Test] Hello world") await ClockCycles(caravelEnv.clk, 100000) diff --git a/verilog/dv/cocotb/all_tests/housekeeping/general/pll.py b/verilog/dv/cocotb/all_tests/housekeeping/general/pll.py index fdfa848ed..f1214270c 100644 --- a/verilog/dv/cocotb/all_tests/housekeeping/general/pll.py +++ b/verilog/dv/cocotb/all_tests/housekeeping/general/pll.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import RisingEdge, ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -13,7 +13,7 @@ @cocotb.test() @report_test async def pll(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1147279) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1147279) debug_regs = await configure_userdesign(caravelEnv) error_margin = 0.1 debug_regs = await configure_userdesign(caravelEnv) diff --git a/verilog/dv/cocotb/all_tests/housekeeping/general/sys_ctrl.py b/verilog/dv/cocotb/all_tests/housekeeping/general/sys_ctrl.py index 2ea9ac433..67a2f5086 100644 --- a/verilog/dv/cocotb/all_tests/housekeeping/general/sys_ctrl.py +++ b/verilog/dv/cocotb/all_tests/housekeeping/general/sys_ctrl.py @@ -1,12 +1,11 @@ import cocotb from cocotb.triggers import RisingEdge, ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import SPI from user_design import configure_userdesign - caravel_clock = 0 user_clock = 0 core_clock = 0 @@ -15,7 +14,7 @@ @cocotb.test() @report_test async def clock_redirect(dut): - caravelEnv = await test_configure(dut, timeout_cycles=55565) + caravelEnv = await test_configure_dft(dut, timeout_cycles=55565) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) error_margin = 0.1 @@ -101,7 +100,7 @@ async def calculate_clk_period(clk, name): @cocotb.test() @report_test async def hk_disable(dut): - caravelEnv = await test_configure(dut, timeout_cycles=51474) + caravelEnv = await test_configure_dft(dut, timeout_cycles=51474) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) diff --git a/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py index 571f1674f..b758d95b2 100644 --- a/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py +++ b/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py @@ -5,7 +5,7 @@ import cocotb.log from caravel_cocotb.interfaces.cpu import RiskV from caravel_cocotb.interfaces.defsParser import Regs -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import SPI from caravel_cocotb.caravel_interfaces import SPI @@ -21,7 +21,7 @@ @cocotb.test() @report_test async def hk_regs_wr_wb(dut): - caravelEnv = await test_configure(dut, timeout_cycles=111678, num_error=INFINITY) + caravelEnv = await test_configure_dft(dut, timeout_cycles=111678, num_error=INFINITY) cpu = RiskV(dut) cpu.cpu_force_reset() hk_file = f'{cocotb.plusargs["MAIN_PATH"]}/models/housekeepingWB/HK_regs.json' @@ -106,7 +106,7 @@ async def hk_regs_wr_wb(dut): @cocotb.test() @report_test async def hk_regs_wr_wb_cpu(dut): - caravelEnv = await test_configure(dut, timeout_cycles=294366) + caravelEnv = await test_configure_dft(dut, timeout_cycles=294366) debug_regs = await configure_userdesign(caravelEnv) reg1 = 0 # buffer reg2 = 0 @@ -156,7 +156,7 @@ async def hk_regs_wr_wb_cpu(dut): @cocotb.test() @report_test async def hk_regs_wr_spi(dut): - caravelEnv = await test_configure(dut, timeout_cycles=20681, num_error=0) + caravelEnv = await test_configure_dft(dut, timeout_cycles=20681, num_error=0) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) regs = HK_Registers(caravelEnv).regs_spi @@ -213,7 +213,7 @@ async def hk_regs_wr_spi(dut): @cocotb.test() @report_test async def hk_regs_rst_spi(dut): - caravelEnv = await test_configure(dut, timeout_cycles=20681, num_error=INFINITY) + caravelEnv = await test_configure_dft(dut, timeout_cycles=20681, num_error=INFINITY) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) regs = HK_Registers(caravelEnv).regs_spi diff --git a/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/mgmt_pass_thru.py b/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/mgmt_pass_thru.py index 8d74601fd..1cd973a3e 100644 --- a/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/mgmt_pass_thru.py +++ b/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/mgmt_pass_thru.py @@ -1,6 +1,6 @@ import cocotb from cocotb.triggers import FallingEdge, RisingEdge -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import SPI from random import randrange @@ -14,7 +14,7 @@ @cocotb.test() @report_test async def mgmt_pass_thru_rd(dut): - caravelEnv = await test_configure(dut, timeout_cycles=37247) + caravelEnv = await test_configure_dft(dut, timeout_cycles=37247) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) hex_path = f"{cocotb.plusargs['SIM_DIR']}/{cocotb.plusargs['FTESTNAME']}/firmware.hex".replace('"', "") diff --git a/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/spi.py b/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/spi.py index 052543ff4..241320111 100644 --- a/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/spi.py +++ b/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/spi.py @@ -2,7 +2,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import SPI from user_design import configure_userdesign @@ -12,7 +12,7 @@ @cocotb.test() @report_test async def spi_rd_wr_nbyte(dut): - caravelEnv = await test_configure(dut, timeout_cycles=112763) + caravelEnv = await test_configure_dft(dut, timeout_cycles=112763) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] start spi_rd_wr_nbyte test") @@ -53,7 +53,7 @@ async def spi_rd_wr_nbyte(dut): @cocotb.test() @report_test async def spi_rd_wr(dut): - caravelEnv = await test_configure(dut, timeout_cycles=11571) + caravelEnv = await test_configure_dft(dut, timeout_cycles=11571) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] start spi_rd_wr test") diff --git a/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/user_pass_thru.py b/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/user_pass_thru.py index 5f55f0020..a02184b67 100644 --- a/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/user_pass_thru.py +++ b/verilog/dv/cocotb/all_tests/housekeeping/housekeeping_spi/user_pass_thru.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import FallingEdge, RisingEdge import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from all_tests.spi_master.SPI_VIP import read_mem, SPI_VIP from caravel_cocotb.caravel_interfaces import SPI @@ -15,7 +15,7 @@ @cocotb.test() @report_test async def user_pass_thru_rd(dut): - caravelEnv = await test_configure(dut, timeout_cycles=89712) + caravelEnv = await test_configure_dft(dut, timeout_cycles=89712) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] start spi_master_rd test") @@ -58,7 +58,7 @@ async def user_pass_thru_rd(dut): @cocotb.test() @report_test async def user_pass_thru_connection(dut): - caravelEnv = await test_configure(dut, timeout_cycles=86033) + caravelEnv = await test_configure_dft(dut, timeout_cycles=86033) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) await debug_regs.wait_reg1(0xAA) diff --git a/verilog/dv/cocotb/all_tests/irq/IRQ_external.py b/verilog/dv/cocotb/all_tests/irq/IRQ_external.py index 94b6bcf21..ed5b5371d 100644 --- a/verilog/dv/cocotb/all_tests/irq/IRQ_external.py +++ b/verilog/dv/cocotb/all_tests/irq/IRQ_external.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign from caravel_cocotb.caravel_interfaces import SPI @@ -13,7 +13,7 @@ @cocotb.test() @report_test async def IRQ_external(dut): - caravelEnv = await test_configure(dut, timeout_cycles=426012) + caravelEnv = await test_configure_dft(dut, timeout_cycles=426012) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start IRQ_external test") diff --git a/verilog/dv/cocotb/all_tests/irq/IRQ_external2.py b/verilog/dv/cocotb/all_tests/irq/IRQ_external2.py index d187be05b..a42cc82c8 100644 --- a/verilog/dv/cocotb/all_tests/irq/IRQ_external2.py +++ b/verilog/dv/cocotb/all_tests/irq/IRQ_external2.py @@ -2,7 +2,7 @@ from cocotb.triggers import ClockCycles import cocotb.log from caravel_cocotb.interfaces.defsParser import Regs -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import SPI from user_design import configure_userdesign @@ -14,7 +14,7 @@ @cocotb.test() @report_test async def IRQ_external2(dut): - caravelEnv = await test_configure(dut, timeout_cycles=428337) + caravelEnv = await test_configure_dft(dut, timeout_cycles=428337) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start IRQ_external2 test") diff --git a/verilog/dv/cocotb/all_tests/irq/IRQ_spi.py b/verilog/dv/cocotb/all_tests/irq/IRQ_spi.py index 6054409b8..0523d03a8 100644 --- a/verilog/dv/cocotb/all_tests/irq/IRQ_spi.py +++ b/verilog/dv/cocotb/all_tests/irq/IRQ_spi.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import SPI from user_design import configure_userdesign @@ -13,7 +13,7 @@ @cocotb.test() @report_test async def IRQ_spi(dut): - caravelEnv = await test_configure(dut, timeout_cycles=412992) + caravelEnv = await test_configure_dft(dut, timeout_cycles=412992) spi_master = SPI(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start IRQ_spi test") diff --git a/verilog/dv/cocotb/all_tests/irq/IRQ_timer.py b/verilog/dv/cocotb/all_tests/irq/IRQ_timer.py index 72f4d29ce..bddde5c2b 100644 --- a/verilog/dv/cocotb/all_tests/irq/IRQ_timer.py +++ b/verilog/dv/cocotb/all_tests/irq/IRQ_timer.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -11,7 +11,7 @@ @cocotb.test() @report_test async def IRQ_timer(dut): - caravelEnv = await test_configure(dut, timeout_cycles=579003) + caravelEnv = await test_configure_dft(dut, timeout_cycles=579003) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start IRQ_timer test") pass_list = (0x1B, 0x2B) diff --git a/verilog/dv/cocotb/all_tests/irq/IRQ_uart.py b/verilog/dv/cocotb/all_tests/irq/IRQ_uart.py index 9dda8b964..483fcbe50 100644 --- a/verilog/dv/cocotb/all_tests/irq/IRQ_uart.py +++ b/verilog/dv/cocotb/all_tests/irq/IRQ_uart.py @@ -2,7 +2,7 @@ from cocotb.triggers import ClockCycles import cocotb.log from caravel_cocotb.interfaces.defsParser import Regs -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -24,7 +24,7 @@ async def write_reg_spi(caravelEnv, address, data): @cocotb.test() @report_test async def IRQ_uart(dut): - caravelEnv = await test_configure(dut, timeout_cycles=896457) + caravelEnv = await test_configure_dft(dut, timeout_cycles=896457) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start IRQ_uart test") pass_list = (0x1B, 0x2B) diff --git a/verilog/dv/cocotb/all_tests/irq/IRQ_uart_rx.py b/verilog/dv/cocotb/all_tests/irq/IRQ_uart_rx.py index a68d65cc2..cb0c0b8dd 100644 --- a/verilog/dv/cocotb/all_tests/irq/IRQ_uart_rx.py +++ b/verilog/dv/cocotb/all_tests/irq/IRQ_uart_rx.py @@ -2,7 +2,7 @@ from cocotb.triggers import ClockCycles import cocotb.log from caravel_cocotb.interfaces.defsParser import Regs -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import UART from user_design import configure_userdesign @@ -25,7 +25,7 @@ async def write_reg_spi(caravelEnv, address, data): @cocotb.test() @report_test async def IRQ_uart_rx(dut): - caravelEnv = await test_configure(dut, timeout_cycles=659797) + caravelEnv = await test_configure_dft(dut, timeout_cycles=659797) debug_regs = await configure_userdesign(caravelEnv) uart = UART(caravelEnv) cocotb.log.info("[TEST] Start IRQ_uart_rx test") diff --git a/verilog/dv/cocotb/all_tests/irq/user_irq.py b/verilog/dv/cocotb/all_tests/irq/user_irq.py index e152d5839..8f2bc29ac 100644 --- a/verilog/dv/cocotb/all_tests/irq/user_irq.py +++ b/verilog/dv/cocotb/all_tests/irq/user_irq.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -25,7 +25,7 @@ async def user2_irq(dut): async def user_irq(dut, irq_num): - caravelEnv = await test_configure(dut, timeout_cycles=295956) + caravelEnv = await test_configure_dft(dut, timeout_cycles=295956) debug_regs = await configure_userdesign(caravelEnv) caravelEnv.user_hdl.irq0.value = 0 caravelEnv.user_hdl.irq1.value = 0 diff --git a/verilog/dv/cocotb/all_tests/logicAnalyzer/la.py b/verilog/dv/cocotb/all_tests/logicAnalyzer/la.py index f583751cf..e61f0adde 100644 --- a/verilog/dv/cocotb/all_tests/logicAnalyzer/la.py +++ b/verilog/dv/cocotb/all_tests/logicAnalyzer/la.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -9,7 +9,7 @@ @cocotb.test() @report_test async def la(dut): - caravelEnv = await test_configure(dut, timeout_cycles=321175) + caravelEnv = await test_configure_dft(dut, timeout_cycles=321175) debug_regs = await configure_userdesign(caravelEnv, la_test=True) pass_list = (0x1B, 0x2B, 0x3B, 0x4B, 0x5B, 0x6B, 0x7B, 0x8B, 0x9B, 0xaB, 0xbB, 0xcB) fail_list = (0x1E, 0x2E, 0x3E, 0x4E, 0x5E, 0x6E, 0x7E, 0x8E, 0x9E, 0xaE, 0xbE, 0xcE) diff --git a/verilog/dv/cocotb/all_tests/mem/mem_stress.py b/verilog/dv/cocotb/all_tests/mem/mem_stress.py index 8022a2dae..2bfc79def 100644 --- a/verilog/dv/cocotb/all_tests/mem/mem_stress.py +++ b/verilog/dv/cocotb/all_tests/mem/mem_stress.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -9,7 +9,7 @@ @cocotb.test() @report_test async def mem_dff2_W(dut): - caravelEnv = await test_configure(dut, timeout_cycles=3478259) + caravelEnv = await test_configure_dft(dut, timeout_cycles=3478259) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mem dff2 word access stress test") pass_list = [0x1B] @@ -34,7 +34,7 @@ async def mem_dff2_W(dut): @cocotb.test() @report_test async def mem_dff2_HW(dut): - caravelEnv = await test_configure(dut, timeout_cycles=3931459) + caravelEnv = await test_configure_dft(dut, timeout_cycles=3931459) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mem dff2 half word access stress test") pass_list = [0x1B] @@ -59,7 +59,7 @@ async def mem_dff2_HW(dut): @cocotb.test() @report_test async def mem_dff2_B(dut): - caravelEnv = await test_configure(dut, timeout_cycles=5333959) + caravelEnv = await test_configure_dft(dut, timeout_cycles=5333959) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mem dff2 Byte access stress test") pass_list = [0x1B] @@ -84,7 +84,7 @@ async def mem_dff2_B(dut): @cocotb.test() @report_test async def mem_dff_W(dut): - caravelEnv = await test_configure(dut, timeout_cycles=7219359) + caravelEnv = await test_configure_dft(dut, timeout_cycles=7219359) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mem dff word access stress test") pass_list = [0x1B] @@ -107,7 +107,7 @@ async def mem_dff_W(dut): @cocotb.test() @report_test async def mem_dff_HW(dut): - caravelEnv = await test_configure(dut, timeout_cycles=7817759) + caravelEnv = await test_configure_dft(dut, timeout_cycles=7817759) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mem dff half word access stress test") pass_list = [0x1B] @@ -130,7 +130,7 @@ async def mem_dff_HW(dut): @cocotb.test() @report_test async def mem_dff_B(dut): - caravelEnv = await test_configure(dut, timeout_cycles=10640359) + caravelEnv = await test_configure_dft(dut, timeout_cycles=10640359) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mem dff Byte access stress test") pass_list = [0x1B] @@ -153,7 +153,7 @@ async def mem_dff_B(dut): @cocotb.test() @report_test async def mem_sram_W(dut): - caravelEnv = await test_configure(dut, timeout_cycles=118083081) + caravelEnv = await test_configure_dft(dut, timeout_cycles=118083081) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start sram word access stress test") pass_list = [0x1B] @@ -180,7 +180,7 @@ async def mem_sram_W(dut): @cocotb.test() @report_test async def mem_sram_HW(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1116274181) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1116274181) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start sram halfword access stress test") pass_list = [0x1B] @@ -206,7 +206,7 @@ async def mem_sram_HW(dut): @cocotb.test() @report_test async def mem_sram_B(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1128500231) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1128500231) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start sram byte access stress test") pass_list = [0x1B] @@ -232,7 +232,7 @@ async def mem_sram_B(dut): @cocotb.test() @report_test async def mem_sram_smoke(dut): - caravelEnv = await test_configure(dut, timeout_cycles=11655541) + caravelEnv = await test_configure_dft(dut, timeout_cycles=11655541) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start sram smoke test") pass_list = [0x1B] diff --git a/verilog/dv/cocotb/all_tests/mgmt_gpio/mgmt_gpio.py b/verilog/dv/cocotb/all_tests/mgmt_gpio/mgmt_gpio.py index a55fe8c0a..d91da9b6c 100644 --- a/verilog/dv/cocotb/all_tests/mgmt_gpio/mgmt_gpio.py +++ b/verilog/dv/cocotb/all_tests/mgmt_gpio/mgmt_gpio.py @@ -2,7 +2,7 @@ import cocotb from cocotb.triggers import ClockCycles, Edge import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -13,7 +13,7 @@ @cocotb.test() @report_test async def mgmt_gpio_out(dut): - caravelEnv = await test_configure(dut, timeout_cycles=431562) + caravelEnv = await test_configure_dft(dut, timeout_cycles=431562) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mgmt_gpio_out test") phases_fails = 3 @@ -67,7 +67,7 @@ async def mgmt_gpio_out(dut): @cocotb.test() @report_test async def mgmt_gpio_in(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1119535) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1119535) caravelEnv.drive_mgmt_gpio(0) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mgmt_gpio_in test") @@ -118,7 +118,7 @@ async def mgmt_gpio_in(dut): @cocotb.test() @report_test async def mgmt_gpio_bidir(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1904514) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1904514) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mgmt_gpio_bidir test") debug_regs = await configure_userdesign(caravelEnv) @@ -165,7 +165,7 @@ async def blink_counter(hdl, counter): @cocotb.test() @report_test async def mgmt_gpio_pu_pd(dut): - caravelEnv = await test_configure(dut, timeout_cycles=66129) + caravelEnv = await test_configure_dft(dut, timeout_cycles=66129) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mgmt_gpio_pu_pd test") debug_regs = await configure_userdesign(caravelEnv) @@ -199,7 +199,7 @@ async def mgmt_gpio_pu_pd(dut): @cocotb.test() @report_test async def mgmt_gpio_disable(dut): - caravelEnv = await test_configure(dut, timeout_cycles=117797) + caravelEnv = await test_configure_dft(dut, timeout_cycles=117797) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start mgmt_gpio_disable test") phases_fails = 2 diff --git a/verilog/dv/cocotb/all_tests/shifting/shifting.py b/verilog/dv/cocotb/all_tests/shifting/shifting.py index 602802e77..a4fccb49b 100644 --- a/verilog/dv/cocotb/all_tests/shifting/shifting.py +++ b/verilog/dv/cocotb/all_tests/shifting/shifting.py @@ -1,6 +1,6 @@ import cocotb import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -54,7 +54,7 @@ def shift(gpio, shift_type, caravelEnv): @cocotb.test() @report_test async def serial_shifting_10(dut): - caravelEnv = await test_configure(dut, timeout_cycles=540110) + caravelEnv = await test_configure_dft(dut, timeout_cycles=540110) debug_regs = await configure_userdesign(caravelEnv) uut = dut.uut.chip_core debug_regs = await configure_userdesign(caravelEnv) @@ -155,7 +155,7 @@ async def serial_shifting_10(dut): @cocotb.test() @report_test async def serial_shifting_01(dut): - caravelEnv = await test_configure(dut, timeout_cycles=541278) + caravelEnv = await test_configure_dft(dut, timeout_cycles=541278) debug_regs = await configure_userdesign(caravelEnv) uut = dut.uut.chip_core debug_regs = await configure_userdesign(caravelEnv) @@ -256,7 +256,7 @@ async def serial_shifting_01(dut): @cocotb.test() @report_test async def serial_shifting_0011(dut): - caravelEnv = await test_configure(dut, timeout_cycles=700516) + caravelEnv = await test_configure_dft(dut, timeout_cycles=700516) debug_regs = await configure_userdesign(caravelEnv) uut = dut.uut.chip_core debug_regs = await configure_userdesign(caravelEnv) @@ -357,7 +357,7 @@ async def serial_shifting_0011(dut): @cocotb.test() @report_test async def serial_shifting_1100(dut): - caravelEnv = await test_configure(dut, timeout_cycles=700331) + caravelEnv = await test_configure_dft(dut, timeout_cycles=700331) debug_regs = await configure_userdesign(caravelEnv) uut = dut.uut.chip_core debug_regs = await configure_userdesign(caravelEnv) diff --git a/verilog/dv/cocotb/all_tests/spi_master/spi_master.py b/verilog/dv/cocotb/all_tests/spi_master/spi_master.py index 1bf1f9b33..ef3455457 100644 --- a/verilog/dv/cocotb/all_tests/spi_master/spi_master.py +++ b/verilog/dv/cocotb/all_tests/spi_master/spi_master.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import FallingEdge, RisingEdge, ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from all_tests.spi_master.SPI_VIP import read_mem, SPI_VIP from user_design import configure_userdesign @@ -15,7 +15,7 @@ async def spi_master_rd(dut): the method of testing used can't work if 2 addresses Consecutive have the same address """ - caravelEnv = await test_configure(dut, timeout_cycles=1362179) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1362179) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] start spi_master_rd test") file_name = f'{cocotb.plusargs["USER_PROJECT_ROOT"]}/verilog/dv/cocotb/all_tests/spi_master/test_data'.replace('"', '') @@ -86,7 +86,7 @@ async def spi_master_temp(dut): the method of testing used can't work if 2 addresses Consecutive have the same address """ - caravelEnv = await test_configure(dut, timeout_cycles=114548) + caravelEnv = await test_configure_dft(dut, timeout_cycles=114548) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] start spi_master_temp test") CSB = dut.gpio33_monitor diff --git a/verilog/dv/cocotb/all_tests/temp/temp.py b/verilog/dv/cocotb/all_tests/temp/temp.py index 309a8573f..23e7d3786 100644 --- a/verilog/dv/cocotb/all_tests/temp/temp.py +++ b/verilog/dv/cocotb/all_tests/temp/temp.py @@ -1,14 +1,14 @@ import cocotb from cocotb.triggers import RisingEdge, ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test @cocotb.test() @report_test async def temp(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1137599) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1137599) cocotb.log.info("[TEST] start temp") caravelEnv.release_csb() await caravelEnv.wait_mgmt_gpio(1) # wait for gpio configuration to happened diff --git a/verilog/dv/cocotb/all_tests/timer/timer.py b/verilog/dv/cocotb/all_tests/timer/timer.py index 2546df0da..726e32319 100644 --- a/verilog/dv/cocotb/all_tests/timer/timer.py +++ b/verilog/dv/cocotb/all_tests/timer/timer.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -12,7 +12,7 @@ @cocotb.test() @report_test async def timer0_oneshot(dut): - caravelEnv = await test_configure(dut, timeout_cycles=159867) + caravelEnv = await test_configure_dft(dut, timeout_cycles=159867) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start timer0_oneshot test") cocotb.log.info("[TEST] Configure timer as oneshot") @@ -63,7 +63,7 @@ async def timer0_oneshot(dut): @cocotb.test() @report_test async def timer0_periodic(dut): - caravelEnv = await test_configure(dut, timeout_cycles=296520) + caravelEnv = await test_configure_dft(dut, timeout_cycles=296520) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start timer0_periodic test") cocotb.log.info("[TEST] Configure timer as periodic") diff --git a/verilog/dv/cocotb/all_tests/uart/uart.py b/verilog/dv/cocotb/all_tests/uart/uart.py index a1da09233..488be9a7c 100644 --- a/verilog/dv/cocotb/all_tests/uart/uart.py +++ b/verilog/dv/cocotb/all_tests/uart/uart.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import ClockCycles, Edge import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from caravel_cocotb.caravel_interfaces import UART from user_design import configure_userdesign @@ -10,7 +10,7 @@ @cocotb.test() @report_test async def uart_tx(dut): - caravelEnv = await test_configure(dut, timeout_cycles=444465) + caravelEnv = await test_configure_dft(dut, timeout_cycles=444465) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start uart test") expected_msg = "Monitor: Test UART (RTL) passed" @@ -29,7 +29,7 @@ async def uart_tx(dut): @cocotb.test() @report_test async def uart_rx(dut): - caravelEnv = await test_configure(dut, timeout_cycles=188729) + caravelEnv = await test_configure_dft(dut, timeout_cycles=188729) debug_regs = await configure_userdesign(caravelEnv) uart = UART(caravelEnv) cocotb.log.info("[TEST] Start uart test") @@ -53,15 +53,7 @@ async def uart_rx(dut): async def uart_check_char_recieved(caravelEnv, debug_regs): # check cpu recieved the correct character while True: - if 'GL' not in caravelEnv.design_macros._asdict(): - if 'CPU_TYPE_ARM' in caravelEnv.design_macros._asdict(): - reg_uart_data = ( - caravelEnv.caravel_hdl.soc.core.AHB.APB_S3.S3_UART.reg_rx_buf.value.binstr - ) - else: - reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr - else: - reg_uart_data = "1001110" + reg_uart_data = "1001110" reg2 = debug_regs.read_debug_reg2() cocotb.log.debug(f"[TEST] reg2 = {hex(reg2)}") @@ -82,7 +74,7 @@ async def uart_check_char_recieved(caravelEnv, debug_regs): @cocotb.test() @report_test async def uart_loopback(dut): - caravelEnv = await test_configure(dut, timeout_cycles=216759) + caravelEnv = await test_configure_dft(dut, timeout_cycles=216759) debug_regs = await configure_userdesign(caravelEnv) cocotb.log.info("[TEST] Start uart test") debug_regs = await configure_userdesign(caravelEnv) @@ -106,15 +98,7 @@ async def connect_5_6(dut, caravelEnv): async def uart_check_char_recieved_loopback(caravelEnv, debug_regs): # check cpu recieved the correct character while True: - if 'GL' not in caravelEnv.design_macros._asdict(): - if 'CPU_TYPE_ARM' in caravelEnv.design_macros._asdict(): - reg_uart_data = ( - caravelEnv.caravel_hdl.soc.core.AHB.APB_S3.S3_UART.reg_rx_buf.value.binstr - ) - else: - reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr - else: - reg_uart_data = "1001110" + reg_uart_data = "1001110" reg2 = debug_regs.read_debug_reg2() cocotb.log.debug(f"[TEST] reg2 = {hex(reg2)}") @@ -135,7 +119,7 @@ async def uart_check_char_recieved_loopback(caravelEnv, debug_regs): @cocotb.test() @report_test async def uart_rx_msg(dut): - caravelEnv = await test_configure(dut, timeout_cycles=111154409) + caravelEnv = await test_configure_dft(dut, timeout_cycles=111154409) uart = UART(caravelEnv) debug_regs = await configure_userdesign(caravelEnv) # IO[0] affects the uart selecting btw system and debug diff --git a/verilog/dv/cocotb/all_tests/user_project/user_address_space.py b/verilog/dv/cocotb/all_tests/user_project/user_address_space.py index 23944747f..e0921eea1 100644 --- a/verilog/dv/cocotb/all_tests/user_project/user_address_space.py +++ b/verilog/dv/cocotb/all_tests/user_project/user_address_space.py @@ -1,7 +1,7 @@ import cocotb from cocotb.triggers import RisingEdge, NextTimeStep import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test from user_design import configure_userdesign @@ -9,7 +9,7 @@ @cocotb.test() @report_test async def user_address_space(dut): - caravelEnv = await test_configure(dut, timeout_cycles=31776) + caravelEnv = await test_configure_dft(dut, timeout_cycles=31776) cocotb.log.info("[TEST] Start user_address_space test") ack_hdl = caravelEnv.caravel_hdl.mprj.wbs_ack_o addr_hdl = caravelEnv.caravel_hdl.mprj.wbs_adr_i diff --git a/verilog/dv/cocotb/all_tests/user_project/user_ram.py b/verilog/dv/cocotb/all_tests/user_project/user_ram.py index 5996f1099..de2ffd474 100644 --- a/verilog/dv/cocotb/all_tests/user_project/user_ram.py +++ b/verilog/dv/cocotb/all_tests/user_project/user_ram.py @@ -1,14 +1,14 @@ import cocotb from cocotb.triggers import ClockCycles import cocotb.log -from caravel_cocotb.caravel_interfaces import test_configure +from all_tests.common.common import test_configure_dft from caravel_cocotb.caravel_interfaces import report_test @cocotb.test() @report_test async def user_ram(dut): - caravelEnv = await test_configure(dut, timeout_cycles=1167331) + caravelEnv = await test_configure_dft(dut, timeout_cycles=1167331) cocotb.log.info("[TEST] Start user RAM word access stress test") pass_list = [0x1B] fail_list = [0x1E] diff --git a/verilog/dv/cocotb/dft.h b/verilog/dv/cocotb/dft.h new file mode 100644 index 000000000..79b92ebd0 --- /dev/null +++ b/verilog/dv/cocotb/dft.h @@ -0,0 +1,13 @@ +#include + + +void GPIOs_waitLow_dft(unsigned int data){ + set_debug_reg1(0x74); + // wait for data bit ignoring jtag bits 31 30 29 28 27 + unsigned int data_masked = data & 0x7FFFFFF; + while(1){ + unsigned int read_data_masked = GPIOs_readLow() & 0x7FFFFFF; + if (read_data_masked == data_masked) + break; + } +}