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As part of the Surelog project (a /potentially/ competing ANTLR4 based SystemVerilog parser) and Verible project (a /potentially/ Bison based SystemVerilog parser focused on code linting and formatting) we have been trying to create a system which allows different parsers be interfaced to multiple different tools (like Yosys, Verilator, Icarus, etc).
I'll definitely take a look, thanks for raising the issue.
Philosophically, slang is already designed to be the fastest (which it seems to be) and (eventually) the most complete parser (along with other front-end pieces) that all other tools can simply link to and do their backend work. Having a standard for the object model does seem (genuinely!) useful, but I'm also hoping people will ditch the auto-generated parsers and go with this one since it's faster and provides much nicer error messages, but I also realize that's not likely to make me friends in the short term. I'll look more into UHDM and see how I can incorporate it into that goal.
As part of the Surelog project (a /potentially/ competing ANTLR4 based SystemVerilog parser) and Verible project (a /potentially/ Bison based SystemVerilog parser focused on code linting and formatting) we have been trying to create a system which allows different parsers be interfaced to multiple different tools (like Yosys, Verilator, Icarus, etc).
The attempt at doing this project is called Universal Hardware Data Model (UHDM) and structured kind of like this;

It would be awesome to see more parsers trying to support this API to make sure the API isn't over fitted to Surelog.
I understand this is potentially quite a huge task so don't expect you to /actually/ do this but thought it could hurt to propose the idea.
FYI the related UHDM issue is at https://github.com/alainmarcel/UHDM/issues/319
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