diff --git a/src/design_notebooks/2024fall/nm4207.md b/src/design_notebooks/2024fall/nm4207.md
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--- a/src/design_notebooks/2024fall/nm4207.md
+++ b/src/design_notebooks/2024fall/nm4207.md
@@ -1,30 +1,40 @@
 # Noah Mays-Smith's Design Notebook
 
-Week One:
+## Week One:
 Created first design notebook
 
-Week 1.5:
+## Week 1.5:
+Project Work:
 Finished Lab 1: https://github.com/Noahms12/lab1
 
 Had some problems with updating my notebook. I need to get the hang of the order that everything is done in. 
 Suggestion for "Your first design notebook". The description "(link/to/repo)" is not clear on whether it wants a link to a file within our repo or a link to my personal github. I'd recommend changing it to something like "https://github.com/example"
 
-Week 2:
+## Week 2:
+Project Work:
 Started work on Lab 2: https://github.com/Noahms12/onboarding-lab-2.git
 
 Attended the meeting on Thursday and asked some questions about parts of lab 1 that I was confused about as well as asked for help figuring out the workflow for each lab.
 Worked through excercise 1 after reteaching myself some verilog. Then I compared my solution to people in previous semesters to ensure it was correct. I cannot figure out where to run the command "ctest --output-on-failure ." to test my code for Excercise 1. I ran it in all of the files in the lab directory, but every time I got the output "No tests were found!!!"
 
 
-Week 3:
+## Week 3:
+Project Work:
 Finished work on Lab 2: https://github.com/Noahms12/onboarding-lab-2.git
 
 Finished working on Lab 2. Excersises definitely helped me remember verilog from my classes, and I'm feeling much more confident with it now. Still couldn't figure out how to test my code aaas described at the beginning of the lab 2 description, but I compared my work to other members' Lab 2's to make sure I was doing everything correctly.
 
 
-Week 4:
+## Week 4:
+Project Work:
 Started Lab 3: https://github.com/Noahms12/onboarding-lab-3.git
 
 Got through exercise 1, and started exercise 2. I haven't combined c++ with verilog before in this way, so understanding how things like the uint16_t data type work, and how I can manipulate it is difficult. I've looked at a few completed design notebooks to get some ideas, but out of the ones i've found, there's a lot of syntax that I'm not familiar with. 
 
 Also attended the meeting on thursday to try to figure out the problem last week with testing my code, but was unable to find an immediate solution. 
+
+## Week 5:
+Project Work:
+-None-
+
+Still working on Lab 3, but I wasn't able to get a lot of work done because of midterms and multiple personal events this week. I have updated the formatting of my notebook to what it is supposed to be.