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lar1test.c
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/************************************************************************
* File: pcie_diag.c
*
* Sample user-mode diagnostics application for accessing PCIE
* devices using WinDriver's API.
* Code was generated by DriverWizard v10.21.
*
* Jungo Confidential. Copyright (c) 2011 Jungo Ltd. http://www.jungo.com
*************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#include "wdc_defs.h"
#include "wdc_lib.h"
#include "utils.h"
#include "status_strings.h"
#include "samples/shared/diag_lib.h"
#include "samples/shared/wdc_diag_lib.h"
#include "samples/shared/pci_regs.h"
#include "pcie_lib.h"
/*************************************************************
General definitions
*************************************************************/
/* Error messages display */
#define PCIE_ERR printf
/*************************************************************
Global variables
*************************************************************/
/* User's input command */
static CHAR gsInput[256];
/* --------------------------------------------------
PCIE configuration registers information
-------------------------------------------------- */
/* Configuration registers information array */
const WDC_REG gPCIE_CfgRegs[] = {
{ WDC_AD_CFG_SPACE, PCI_VID, WDC_SIZE_16, WDC_READ_WRITE, "VID", "Vendor ID" },
{ WDC_AD_CFG_SPACE, PCI_DID, WDC_SIZE_16, WDC_READ_WRITE, "DID", "Device ID" },
{ WDC_AD_CFG_SPACE, PCI_CR, WDC_SIZE_16, WDC_READ_WRITE, "CMD", "Command" },
{ WDC_AD_CFG_SPACE, PCI_SR, WDC_SIZE_16, WDC_READ_WRITE, "STS", "Status" },
{ WDC_AD_CFG_SPACE, PCI_REV, WDC_SIZE_32, WDC_READ_WRITE, "RID_CLCD", "Revision ID & Class Code" },
{ WDC_AD_CFG_SPACE, PCI_CCSC, WDC_SIZE_8, WDC_READ_WRITE, "SCC", "Sub Class Code" },
{ WDC_AD_CFG_SPACE, PCI_CCBC, WDC_SIZE_8, WDC_READ_WRITE, "BCC", "Base Class Code" },
{ WDC_AD_CFG_SPACE, PCI_CLSR, WDC_SIZE_8, WDC_READ_WRITE, "CALN", "Cache Line Size" },
{ WDC_AD_CFG_SPACE, PCI_LTR, WDC_SIZE_8, WDC_READ_WRITE, "LAT", "Latency Timer" },
{ WDC_AD_CFG_SPACE, PCI_HDR, WDC_SIZE_8, WDC_READ_WRITE, "HDR", "Header Type" },
{ WDC_AD_CFG_SPACE, PCI_BISTR, WDC_SIZE_8, WDC_READ_WRITE, "BIST", "Built-in Self Test" },
{ WDC_AD_CFG_SPACE, PCI_BAR0, WDC_SIZE_32, WDC_READ_WRITE, "BADDR0", "Base Address 0" },
{ WDC_AD_CFG_SPACE, PCI_BAR1, WDC_SIZE_32, WDC_READ_WRITE, "BADDR1", "Base Address 1" },
{ WDC_AD_CFG_SPACE, PCI_BAR2, WDC_SIZE_32, WDC_READ_WRITE, "BADDR2", "Base Address 2" },
{ WDC_AD_CFG_SPACE, PCI_BAR3, WDC_SIZE_32, WDC_READ_WRITE, "BADDR3", "Base Address 3" },
{ WDC_AD_CFG_SPACE, PCI_BAR4, WDC_SIZE_32, WDC_READ_WRITE, "BADDR4", "Base Address 4" },
{ WDC_AD_CFG_SPACE, PCI_BAR5, WDC_SIZE_32, WDC_READ_WRITE, "BADDR5", "Base Address 5" },
{ WDC_AD_CFG_SPACE, PCI_CIS, WDC_SIZE_32, WDC_READ_WRITE, "CIS", "CardBus CIS Pointer" },
{ WDC_AD_CFG_SPACE, PCI_SVID, WDC_SIZE_16, WDC_READ_WRITE, "SVID", "Sub-system Vendor ID" },
{ WDC_AD_CFG_SPACE, PCI_SDID, WDC_SIZE_16, WDC_READ_WRITE, "SDID", "Sub-system Device ID" },
{ WDC_AD_CFG_SPACE, PCI_EROM, WDC_SIZE_32, WDC_READ_WRITE, "EROM", "Expansion ROM Base Address" },
{ WDC_AD_CFG_SPACE, PCI_CAP, WDC_SIZE_8, WDC_READ_WRITE, "NEW_CAP", "New Capabilities Pointer" },
{ WDC_AD_CFG_SPACE, PCI_ILR, WDC_SIZE_32, WDC_READ_WRITE, "INTLN", "Interrupt Line" },
{ WDC_AD_CFG_SPACE, PCI_IPR, WDC_SIZE_32, WDC_READ_WRITE, "INTPIN", "Interrupt Pin" },
{ WDC_AD_CFG_SPACE, PCI_MGR, WDC_SIZE_32, WDC_READ_WRITE, "MINGNT", "Minimum Required Burst Period" },
{ WDC_AD_CFG_SPACE, PCI_MLR, WDC_SIZE_32, WDC_READ_WRITE, "MAXLAT", "Maximum Latency" },
};
#define PCIE_CFG_REGS_NUM sizeof(gPCIE_CfgRegs) / sizeof(WDC_REG)
/* TODO: For read-only or write-only registers, change the direction field of
the relevant registers in gPCIE_CfgRegs to WDC_READ or WDC_WRITE. */
/* NOTE: You can define additional configuration registers in gPCIE_CfgRegs. */
const WDC_REG *gpPCIE_CfgRegs = gPCIE_CfgRegs;
/* -----------------------------------------------
PCIE run-time registers information
----------------------------------------------- */
/* Run-time registers information array */
/* const WDC_REG gPCIE_Regs[]; */
const WDC_REG *gpPCIE_Regs = NULL;
/* TODO: You can remove the comment from the gPCIE_Regs array declaration and
fill the array with run-time registers information for your device,
in which case be sure to set gpPCIE_Regs to point to gPCIE_Regs. */
#define PCIE_REGS_NUM 0
/*************************************************************
Static functions prototypes
*************************************************************/
/* -----------------------------------------------
Main diagnostics menu
----------------------------------------------- */
static void MenuMain(WDC_DEVICE_HANDLE *phDev, WDC_DEVICE_HANDLE *phDev2);
/* -----------------------------------------------
Device find, open and close
----------------------------------------------- */
static WDC_DEVICE_HANDLE DeviceFindAndOpen(DWORD dwVendorId, DWORD dwDeviceId);
static BOOL DeviceFind(DWORD dwVendorId, DWORD dwDeviceId, WD_PCI_SLOT *pSlot);
static WDC_DEVICE_HANDLE DeviceOpen(const WD_PCI_SLOT *pSlot);
static void DeviceClose(WDC_DEVICE_HANDLE hDev);
/* -----------------------------------------------
Read/write memory and I/O addresses
----------------------------------------------- */
static void MenuReadWriteAddr(WDC_DEVICE_HANDLE hDev);
static void SetAddrSpace(WDC_DEVICE_HANDLE hDev, PDWORD pdwAddrSpace);
/* -----------------------------------------------
Read/write the configuration space
----------------------------------------------- */
static void MenuReadWriteCfgSpace(WDC_DEVICE_HANDLE hDev);
/* -----------------------------------------------
Read/write the run-time registers
----------------------------------------------- */
static void MenuReadWriteRegs(WDC_DEVICE_HANDLE hDev);
/* -----------------------------------------------
Interrupt handling
----------------------------------------------- */
static void MenuInterrupts(WDC_DEVICE_HANDLE hDev);
static void DiagIntHandler(WDC_DEVICE_HANDLE hDev, PCIE_INT_RESULT *pIntResult);
/* ----------------------------------------------------
Plug-and-play and power management events handling
---------------------------------------------------- */
static void MenuEvents(WDC_DEVICE_HANDLE hDev);
static void DiagEventHandler(WDC_DEVICE_HANDLE hDev, DWORD dwAction);
static void Menujsebii_test(WDC_DEVICE_HANDLE hDev);
static void MenuMBtest(WDC_DEVICE_HANDLE hDev, WDC_DEVICE_HANDLE hDev2);
static int pcie_send(WDC_DEVICE_HANDLE hDev, int mode, int nword, UINT32 *buff_send);
static int pcie_send_6_1(WDC_DEVICE_HANDLE hDev, int mode, int nword, UINT32 *buff_send);
static int pcie_send_1(WDC_DEVICE_HANDLE hDev, int mode, int nword, UINT32 *buff_send);
static int pcie_rec_16b(WDC_DEVICE_HANDLE hDev, int mode, int istart, int nword, int ipr_status, UINT32 *buff_rec);
static int pcie_rec(WDC_DEVICE_HANDLE hDev, int mode, int istart, int nword, int ipr_status, UINT32 *buff_rec);
static int pcie_rec_2(WDC_DEVICE_HANDLE hDev, int mode, int istart, int nword, int ipr_status, UINT32 *buff_rec);
static int pcie_rec_6_1(WDC_DEVICE_HANDLE hDev, int mode, int istart, int nword, int ipr_status, UINT32 *buff_rec);
static int pcie_rec_6_2(WDC_DEVICE_HANDLE hDev, int mode, int istart, int nword, int ipr_status, UINT32 *buff_rec);
static int xmit_boot(WDC_DEVICE_HANDLE hDev, int imod_xmit);
static int fem_boot(WDC_DEVICE_HANDLE hDev, int imod_fem);
/*************************************************************
Functions implementation
*************************************************************/
int main(void)
{
struct timeval start;
gettimeofday(&start,NULL);
long seconds, useconds;
seconds = start.tv_sec;
useconds = start.tv_usec;
printf("\nStart time of program: %ld sec %ld usec\n",seconds,useconds);
WDC_DEVICE_HANDLE hDev = NULL;
WDC_DEVICE_HANDLE hDev1 = NULL;
WDC_DEVICE_HANDLE hDev2 = NULL;
DWORD dwStatus;
printf("\n");
printf("PCIE diagnostic utility.\n");
printf("Application accesses hardware using " WD_PROD_NAME ".\n");
/* Initialize the PCIE library */
dwStatus = PCIE_LibInit();
if (WD_STATUS_SUCCESS != dwStatus)
{
PCIE_ERR("pcie_diag: Failed to initialize the PCIE library: %s",
PCIE_GetLastErr());
return dwStatus;
}
/* Find and open a PCIE device (by default ID) */
if (PCIE_DEFAULT_VENDOR_ID)
hDev = DeviceFindAndOpen(PCIE_DEFAULT_VENDOR_ID, PCIE_DEFAULT_DEVICE_ID);
if (PCIE_DEFAULT_VENDOR_ID)
hDev1 = DeviceFindAndOpen(PCIE_DEFAULT_VENDOR_ID, PCIE_DEFAULT_DEVICE_ID+1);
if (PCIE_DEFAULT_VENDOR_ID)
hDev2 = DeviceFindAndOpen(PCIE_DEFAULT_VENDOR_ID, PCIE_DEFAULT_DEVICE_ID+2);
/* Display main diagnostics menu for communicating with the device */
MenuMain(&hDev, &hDev2);
/* Perform necessary cleanup before exiting the program */
if (hDev)
DeviceClose(hDev);
DeviceClose(hDev1);
DeviceClose(hDev2);
dwStatus = PCIE_LibUninit();
if (WD_STATUS_SUCCESS != dwStatus)
PCIE_ERR("pcie_diag: Failed to uninit the PCIE library: %s", PCIE_GetLastErr());
return dwStatus;
}
/* -----------------------------------------------
Main diagnostics menu
----------------------------------------------- */
/* Main menu options */
enum {
MENU_MAIN_SCAN_PCI_BUS = 1,
MENU_MAIN_FIND_AND_OPEN,
MENU_MAIN_RW_ADDR,
MENU_MAIN_RW_CFG_SPACE,
MENU_MAIN_RW_REGS,
MENU_MAIN_ENABLE_DISABLE_INT,
MENU_MAIN_EVENTS,
MENU_MAIN_MB_TEST, /* add new route for testing */
MENU_MAIN_JSEBII_TEST, /* add new route for testing */
MENU_MAIN_EXIT = DIAG_EXIT_MENU,
};
/* Main diagnostics menu */
static void MenuMain(WDC_DEVICE_HANDLE *phDev, WDC_DEVICE_HANDLE *phDev2)
{
DWORD option;
do
{
printf("\n");
printf("PCIE main menu\n");
printf("--------------\n");
printf("%d. Scan PCI bus\n", MENU_MAIN_SCAN_PCI_BUS);
printf("%d. Find and open a PCIE device\n", MENU_MAIN_FIND_AND_OPEN);
if (*phDev)
{
printf("%d. Read/write memory and IO addresses on the device\n",
MENU_MAIN_RW_ADDR);
printf("%d. Read/write the device's configuration space\n",
MENU_MAIN_RW_CFG_SPACE);
if (PCIE_REGS_NUM)
{
printf("%d. Read/write the run-time registers\n",
MENU_MAIN_RW_REGS);
}
printf("%d. Enable/disable the device's interrupts\n",
MENU_MAIN_ENABLE_DISABLE_INT);
printf("%d. Register/unregister plug-and-play and power management "
"events\n", MENU_MAIN_EVENTS);
printf("%d. MicroBoone test\n", MENU_MAIN_MB_TEST);
printf("%d. Test loop for PCIe\n", MENU_MAIN_JSEBII_TEST);
}
printf("%d. Exit\n", MENU_MAIN_EXIT);
/**
if (DIAG_INPUT_FAIL == DIAG_GetMenuOption(&option,
*phDev ? MENU_MAIN_EVENTS : MENU_MAIN_FIND_AND_OPEN))
{
continue;
}
**/
if (DIAG_INPUT_FAIL == DIAG_GetMenuOption(&option,
*phDev ? MENU_MAIN_JSEBII_TEST : MENU_MAIN_FIND_AND_OPEN))
{
continue;
}
switch (option)
{
case MENU_MAIN_EXIT: /* Exit menu */
break;
case MENU_MAIN_SCAN_PCI_BUS: /* Scan PCI bus */
WDC_DIAG_PciDevicesInfoPrintAll(FALSE);
break;
case MENU_MAIN_FIND_AND_OPEN: /* Find and open a PCIE device */
if (*phDev)
DeviceClose(*phDev);
*phDev = DeviceFindAndOpen(0, 0);
break;
case MENU_MAIN_RW_ADDR: /* Read/write memory and I/O addresses */
MenuReadWriteAddr(*phDev);
break;
case MENU_MAIN_RW_CFG_SPACE: /* Read/Write the PCIE configuration space */
MenuReadWriteCfgSpace(*phDev);
break;
case MENU_MAIN_RW_REGS: /* Read/write the run-time registers */
if (PCIE_REGS_NUM)
MenuReadWriteRegs(*phDev);
else
printf("Invalid selection\n");
break;
case MENU_MAIN_ENABLE_DISABLE_INT: /* Enable/disable interrupts */
MenuInterrupts(*phDev);
break;
case MENU_MAIN_EVENTS: /* Register/unregister plug-and-play and power management events */
MenuEvents(*phDev);
break;
case MENU_MAIN_MB_TEST: /* my test loop DMA */
MenuMBtest(*phDev, *phDev2);
break;
case MENU_MAIN_JSEBII_TEST: /* my test loop DMA */
Menujsebii_test(*phDev);
break;
}
} while (MENU_MAIN_EXIT != option);
}
/* -----------------------------------------------
Device find, open and close
----------------------------------------------- */
/* Find and open a PCIE device */
static WDC_DEVICE_HANDLE DeviceFindAndOpen(DWORD dwVendorId, DWORD dwDeviceId)
{
WD_PCI_SLOT slot;
if (!DeviceFind(dwVendorId, dwDeviceId, &slot))
return NULL;
return DeviceOpen(&slot);
}
/* Find a PCIE device */
static BOOL DeviceFind(DWORD dwVendorId, DWORD dwDeviceId, WD_PCI_SLOT *pSlot)
{
DWORD dwStatus;
DWORD i, dwNumDevices;
WDC_PCI_SCAN_RESULT scanResult;
if (dwVendorId == 0)
{
if (DIAG_INPUT_SUCCESS != DIAG_InputDWORD((PVOID)&dwVendorId,
"Enter vendor ID", TRUE, 0, 0))
{
return FALSE;
}
if (DIAG_INPUT_SUCCESS != DIAG_InputDWORD((PVOID)&dwDeviceId,
"Enter device ID", TRUE, 0, 0))
{
return FALSE;
}
}
BZERO(scanResult);
dwStatus = WDC_PciScanDevices(dwVendorId, dwDeviceId, &scanResult);
if (WD_STATUS_SUCCESS != dwStatus)
{
PCIE_ERR("DeviceFind: Failed scanning the PCI bus.\n"
"Error: 0x%lx - %s\n", dwStatus, Stat2Str(dwStatus));
return FALSE;
}
dwNumDevices = scanResult.dwNumDevices;
if (!dwNumDevices)
{
PCIE_ERR("No matching device was found for search criteria "
"(Vendor ID 0x%lX, Device ID 0x%lX)\n",
dwVendorId, dwDeviceId);
return FALSE;
}
printf("\n");
printf("Found %ld matching device%s [ Vendor ID 0x%lX%s, Device ID 0x%lX%s ]:\n",
dwNumDevices, dwNumDevices > 1 ? "s" : "",
dwVendorId, dwVendorId ? "" : " (ALL)",
dwDeviceId, dwDeviceId ? "" : " (ALL)");
for (i = 0; i < dwNumDevices; i++)
{
printf("\n");
printf("%2ld. Vendor ID: 0x%lX, Device ID: 0x%lX\n",
i + 1,
scanResult.deviceId[i].dwVendorId,
scanResult.deviceId[i].dwDeviceId);
WDC_DIAG_PciDeviceInfoPrint(&scanResult.deviceSlot[i], FALSE);
}
printf("\n");
if (dwNumDevices > 1)
{
sprintf(gsInput, "Select a device (1 - %ld): ", dwNumDevices);
i = 0;
if (DIAG_INPUT_SUCCESS != DIAG_InputDWORD((PVOID)&i,
gsInput, FALSE, 1, dwNumDevices))
{
return FALSE;
}
}
*pSlot = scanResult.deviceSlot[i - 1];
return TRUE;
}
/* Open a handle to a PCIE device */
static WDC_DEVICE_HANDLE DeviceOpen(const WD_PCI_SLOT *pSlot)
{
WDC_DEVICE_HANDLE hDev;
DWORD dwStatus;
WD_PCI_CARD_INFO deviceInfo;
/* Retrieve the device's resources information */
BZERO(deviceInfo);
deviceInfo.pciSlot = *pSlot;
dwStatus = WDC_PciGetDeviceInfo(&deviceInfo);
if (WD_STATUS_SUCCESS != dwStatus)
{
PCIE_ERR("DeviceOpen: Failed retrieving the device's resources information.\n"
"Error 0x%lx - %s\n", dwStatus, Stat2Str(dwStatus));
return NULL;
}
/* NOTE: You can modify the device's resources information here, if
necessary (mainly the deviceInfo.Card.Items array or the items number -
deviceInfo.Card.dwItems) in order to register only some of the resources
or register only a portion of a specific address space, for example. */
/* Open a handle to the device */
hDev = PCIE_DeviceOpen(&deviceInfo);
if (!hDev)
{
PCIE_ERR("DeviceOpen: Failed opening a handle to the device: %s",
PCIE_GetLastErr());
return NULL;
}
return hDev;
}
/* Close handle to a PCIE device */
static void DeviceClose(WDC_DEVICE_HANDLE hDev)
{
if (!hDev)
return;
if (!PCIE_DeviceClose(hDev))
{
PCIE_ERR("DeviceClose: Failed closing PCIE device: %s",
PCIE_GetLastErr());
}
}
/* Read/write memory or I/O space address menu */
static void MenuMBtest(WDC_DEVICE_HANDLE hDev, WDC_DEVICE_HANDLE hDev2)
{
#include "wdc_defs.h"
#define poweroff 0x0
#define poweron 0x1
#define configure_s30 0x2
#define configure_s60 0x3
#define configure_cont 0x20
#define rdstatus 0x80
#define loopback 0x04
#define dcm2_run_off 254
#define dcm2_run_on 255
#define dcm2_online 2
#define dcm2_setmask 3
#define dcm2_offline_busy 4
#define dcm2_load_packet_a 10
#define dcm2_load_packet_b 11
#define dcm2_offline_load 9
#define dcm2_status_read 20
#define dcm2_led_sel 29
#define dcm2_buffer_status_read 30
#define dcm2_status_read_inbuf 21
#define dcm2_status_read_evbuf 22
#define dcm2_status_read_noevnt 23
#define dcm2_zero 12
#define dcm2_compressor_hold 31
#define dcm2_5_readdata 4
#define dcm2_5_firstdcm 8
#define dcm2_5_lastdcm 9
#define dcm2_5_status_read 5
#define dcm2_5_source_id 25
#define dcm2_5_lastchnl 24
#define dcm2_packet_id_a 25
#define dcm2_packet_id_b 26
#define dcm2_hitformat_a 27
#define dcm2_hitformat_b 28
#define part_run_off 254
#define part_run_on 255
#define part_online 2
#define part_offline_busy 3
#define part_offline_hold 4
#define part_status_read 20
#define part_source_id 25
#define t1_tr_bar 0
#define t2_tr_bar 4
#define cs_bar 2
/** command register location **/
#define tx_mode_reg 0x28
#define t1_cs_reg 0x18
#define r1_cs_reg 0x1c
#define t2_cs_reg 0x20
#define r2_cs_reg 0x24
#define tx_md_reg 0x28
#define cs_dma_add_low_reg 0x0
#define cs_dma_add_high_reg 0x4
#define cs_dma_by_cnt 0x8
#define cs_dma_cntrl 0xc
#define cs_dma_msi_abort 0x10
/** define status bits **/
#define cs_init 0x20000000
#define cs_mode_p 0x8000000
#define cs_mode_n 0x0
#define cs_start 0x40000000
#define cs_done 0x80000000
#define dma_tr1 0x100000
#define dma_tr2 0x200000
#define dma_tr12 0x300000
#define dma_3dw_trans 0x0
#define dma_4dw_trans 0x0
#define dma_3dw_rec 0x40
#define dma_4dw_rec 0x60
#define dma_in_progress 0x80000000
#define dma_abort 0x2
#define mb_cntrl_add 0x1
#define mb_cntrl_test_on 0x1
#define mb_cntrl_test_off 0x0
#define mb_cntrl_set_run_on 0x2
#define mb_cntrl_set_run_off 0x3
#define mb_cntrl_set_trig1 0x4
#define mb_cntrl_set_trig2 0x5
#define mb_cntrl_load_frame 0x6
#define mb_cntrl_load_trig_pos 0x7
#define mb_feb_power_add 0x1
#define mb_feb_conf_add 0x2
#define mb_feb_pass_add 0x3
#define mb_feb_lst_on 1
#define mb_feb_lst_off 0
#define mb_feb_rxreset 2
#define mb_feb_align 3
#define mb_feb_adc_align 1
#define mb_feb_a_nocomp 2
#define mb_feb_b_nocomp 3
#define mb_feb_blocksize 4
#define mb_feb_timesize 5
#define mb_feb_mod_number 6
#define mb_feb_a_id 7
#define mb_feb_b_id 8
#define mb_feb_max 9
#define mb_feb_test_source 10
#define mb_feb_test_sample 11
#define mb_feb_test_frame 12
#define mb_feb_test_channel 13
#define mb_feb_test_ph 14
#define mb_feb_test_base 15
#define mb_feb_test_ram_data 16
#define mb_feb_a_test 17
#define mb_feb_b_test 18
#define mb_feb_a_rdhed 21
#define mb_feb_a_rdbuf 22
#define mb_feb_b_rdhed 23
#define mb_feb_b_rdbuf 24
#define mb_feb_read_probe 30
#define mb_feb_adc_reset 33
#define mb_a_buf_status 34
#define mb_b_buf_status 35
#define mb_a_ham_status 36
#define mb_b_ham_status 37
#define mb_feb_a_maxwords 40
#define mb_feb_b_maxwords 41
#define mb_feb_hold_enable 42
#define mb_pmt_adc_reset 1
#define mb_pmt_spi_add 2
#define mb_pmt_adc_data_load 3
#define mb_xmit_conf_add 0x2
#define mb_xmit_pass_add 0x3
#define mb_xmit_modcount 0x1
#define mb_xmit_enable_1 0x2
#define mb_xmit_enable_2 0x3
#define mb_xmit_test1 0x4
#define mb_xmit_test2 0x5
#define mb_xmit_testdata 10
#define mb_xmit_rdstatus 20
#define mb_xmit_rdcounters 21
#define mb_xmit_link_reset 22
#define mb_opt_dig_reset 23
#define mb_xmit_dpa_fifo_reset 24
#define mb_xmit_dpa_word_align 25
#define mb_trig_run 1
#define mb_trig_frame_size 2
#define mb_trig_deadtime_size 3
#define mb_trig_active_size 4
#define mb_trig_delay1_size 5
#define mb_trig_delay2_size 6
#define mb_trig_enable 7
#define mb_trig_calib_delay 8
#define mb_trig_prescale0 10
#define mb_trig_prescale1 11
#define mb_trig_prescale2 12
#define mb_trig_prescale3 13
#define mb_trig_prescale4 14
#define mb_trig_prescale5 15
#define mb_trig_prescale6 16
#define mb_trig_prescale7 17
#define mb_trig_prescale8 18
#define mb_trig_mask0 20
#define mb_trig_mask1 21
#define mb_trig_mask2 22
#define mb_trig_mask3 23
#define mb_trig_mask4 24
#define mb_trig_mask5 25
#define mb_trig_mask6 26
#define mb_trig_mask7 27
#define mb_trig_mask8 28
#define mb_trig_rd_param 30
#define mb_trig_pctrig 31
#define mb_trig_rd_status 32
#define mb_trig_reset 33
#define mb_trig_calib 34
#define mb_trig_rd_gps 35
#define mb_trig_g1_allow_min 36
#define mb_trig_g1_allow_max 37
#define mb_trig_g2_allow_min 38
#define mb_trig_g2_allow_max 39
#define mb_trig_sel1 40
#define mb_trig_sel2 41
#define mb_trig_sel3 42
#define mb_trig_sel4 43
#define mb_trig_g1_width 45
#define mb_trig_g2_width 46
#define mb_trig_p1_delay 50
#define mb_trig_p1_width 51
#define mb_trig_p2_delay 52
#define mb_trig_p2_width 53
#define mb_trig_p3_delay 54
#define mb_trig_p3_width 55
#define mb_trig_pulse_delay 58
#define mb_trig_output_select 59
#define mb_trig_pulse1 60
#define mb_trig_pulse2 61
#define mb_trig_pulse3 62
#define mb_trig_frame_trig 63
#define mb_trig_rd_counter 70
#define mb_gate_fake_sel 80
#define mb_fake_gate_width 47
#define mb_scaler_out_sel_0 81
#define mb_scaler_out_sel_1 82
#define mb_shaper_pulsetime 1
#define mb_shaper_dac 2
#define mb_shaper_pattern 3
#define mb_shaper_write 4
#define mb_shaper_pulse 5
#define mb_shaper_entrig 6
#define mb_feb_pmt_gate_size 47
#define mb_feb_pmt_beam_delay 48
#define mb_feb_pmt_beam_size 49
#define mb_feb_pmt_trig_delay 87
#define mb_feb_pmt_gate1_size 88
#define mb_feb_pmt_beam1_delay 89
#define mb_feb_pmt_beam1_size 90
#define mb_feb_pmt_trig1_delay 91
#define mb_feb_pmt_ch_set 50
#define mb_feb_pmt_delay0 51
#define mb_feb_pmt_delay1 52
#define mb_feb_pmt_precount 53
#define mb_feb_pmt_thresh0 54
#define mb_feb_pmt_thresh1 55
#define mb_feb_pmt_thresh2 56
#define mb_feb_pmt_thresh3 57
#define mb_feb_pmt_width 58
#define mb_feb_pmt_deadtime 59
#define mb_feb_pmt_window 60
#define mb_feb_pmt_words 61
#define mb_feb_pmt_cos_mul 62
#define mb_feb_pmt_cos_thres 63
#define mb_feb_pmt_mich_mul 64
#define mb_feb_pmt_mich_thres 65
#define mb_feb_pmt_beam_mul 66
#define mb_feb_pmt_beam_thres 67
#define mb_feb_pmt_en_top 68
#define mb_feb_pmt_en_upper 69
#define mb_feb_pmt_en_lower 70
#define mb_feb_pmt_blocksize 71
#define mb_feb_pmt_test 80
#define mb_feb_pmt_clear 81
#define mb_feb_pmt_test_data 82
#define mb_feb_pmt_pulse 83
#define mb_feb_pmt_rxreset 84
#define mb_feb_pmt_align_pulse 85
#define mb_feb_pmt_rd_counters 86
#define mb_version 254
#define dma_buffer_size 10000000
#define xmit_fake_sram_w_addr 5
#define xmit_fake_sram_w_dat 6
#define xmit_fake_sram_block 7
#define xmit_fake_sram_write 8
#define xmit_fake_digitalreset 23
static DWORD dwAddrSpace;
static UINT32 u32Data;
static unsigned short u16Data;
static unsigned long long u64Data, u64Data1;
static DWORD dwOffset;
static long imod,ichip;
unsigned short *buffp;
/*
WDC_ADDR_MODE mode;
WDC_ADDR_RW_OPTIONS options;
*/
static UINT32 i,j,k,ifr,nread,iprint,iwrite,ik,il,is,checksum;
static UINT32 istop,newcmd,irand,ioffset,kword,lastchnl,ib;
static UINT32 send_array[40000],read_array[dma_buffer_size],read_array1[40000];
static UINT32 read_array_c[40000];
static UINT32 read_comp[8000];
static UINT32 nmask,index,itmp,nword_tot,nevent,iv,ijk,islow_read;
static UINT32 imod_p,imod_trig,imod_shaper;
unsigned short idcm_read_array[40000],read_array_s[1600000];
static UINT32 idcm_read_array32[40000];
static UINT32 idcm_send_array[400000];
static UINT32 idcm_verify_array[400000];
static int icomp_l,comp_s,ia,ic,ihuff;
UINT32 *idcm_send_p,*idcm_verify_p,*pbuffp_rec;
DWORD dwDMABufSize;
PVOID pbuf;
WD_DMA *pDma;
DWORD dwStatus;
DWORD dwOptions = DMA_FROM_DEVICE;
UINT32 iread,icheck,izero;
UINT32 buf_send[40000];
static int count,num,counta,nword,ireadback,nloop,ierror;
static int ij,nsend,iloop,inew,idma_readback,iadd,jevent;
static int itest,iframe,irun,ichip_c,dummy1,itrig_c;
static int idup,ihold,idouble,ihold_set,istatus_read;
static int idone,tr_bar,t_cs_reg,r_cs_reg,dma_tr;
static int timesize,ipulse,ibase,a_id,itrig_delay;
static int iset,ncount,nsend_f,nwrite,itrig_ext;
static int imod_xmit,idiv,isample, imod_xmit_fake;
static int iframe_length, itrig,idrift_time,ijtrig;
static int idelay0, idelay1, threshold0, threshold1, pmt_words;
static int cos_mult, cos_thres, en_top, en_upper, en_lower;
static int irise, ifall, istart_time, use_pmt, pmt_testpulse;
static int ich_head, ich_sample, ich_frm,idebug,ntot_rec,nred;
static int ineu,ibusy_send,ibusy_test,ihold_word,ndma_loop;
static int irawprint,ifem_fst,ifem_lst,ifem_loop,imod_fem;
static int pmt_deadtime,pmt_mich_window;
static int oframe,osample,odiv,cframe,csample,cdiv;
static int idac_shaper, pmt_dac_scan,pmt_precount, ichoice;
static int inewcode, p1_delay, p1_width, pulse_trig_delay;
static int p2_delay,p2_width,itrig_pulse,p3_delay,p3_width;
int fake_data_array[65536], fake_array_pack[49152];
unsigned char charchannel;
unsigned char carray[4000];
struct timespec tim, tim2;
tim.tv_sec = 0;
tim.tv_nsec =128000;
// tim.tv_nsec =172000;
PVOID pbuf_rec;
WD_DMA *pDma_rec;
DWORD dwOptions_send = DMA_TO_DEVICE | DMA_ALLOW_CACHE;
// DWORD dwOptions_rec = DMA_FROM_DEVICE | DMA_ALLOW_CACHE | DMA_ALLOW_64BIT_ADDRESS;
DWORD dwOptions_rec = DMA_FROM_DEVICE | DMA_ALLOW_64BIT_ADDRESS;
static UINT64 *buffp_rec64;
static UINT32 *buffp_rec32;
UINT32 *px, *py, *py1;
FILE *outf,*inpf;
nread = 4096*2+6; /*16384 32768, 65536+4; number of byte to be readout */
ifr=0;
iwrite =0;
iprint =0;
icheck =0;
istop=0;
printf("Input the command code for test......\n");
printf(" (1) boot FPGA 5\n");
printf(" (2) boot FPGA 1-4 \n");
printf(" (3) loop back test \n");
printf(" (4) MB controller test loopback\n");
printf(" (5) MB controller output test \n");
printf(" (6) MB FEM booting \n");
printf(" (7) Fake data read \n");
printf(" (8) Fake data read - test 2 \n");
printf(" (9) ADC basic testing \n");
printf(" (10) ADC testing \n");
printf(" (11) Lar1 XMIT board fake data test\n");
printf(" (12) BNL ADC testing \n");
printf(" (14) new FEM FPGA code testing \n");
printf(" (15) 2 FEM and XMIT test \n");
printf(" (16) trigger board test \n");
printf(" (17) shapper baord test \n");
printf(" (18) new BNL ADC testing \n");
printf(" (19) Lar1 FEM read test \n");
printf(" (20) Lar1 fem plus xmit \n");
printf(" (21) SuperNova readout test \n");
printf(" (22) PMT ADC systen readout test \n");
printf(" (23) XMIT module busy test \n");
printf(" (24) SuperNova readout test -- 2 buffer mode \n");
printf(" (26) multiple ADC module test \n");
scanf("%d",&newcmd);
switch(newcmd) {
case 1:
printf(" number of loop \n");
scanf("%d",&nloop);
printf(" enter number of word per packet\n");
scanf("%d",&nsend);
printf(" enter 1 for loopback check\n");
scanf("%d",&ireadback);
printf(" type 1 to use new PCie FPGA code \n");
scanf("%d",&inew);
if(ireadback == 1) {
printf(" enter 1 for readback in DCM mode\n");
scanf("%d",&idma_readback);
}
if(iwrite ==1) outf = fopen("/home/chi/test.dat","w");
printf(" scope loop test \n");
/*
dwDMABufSize = 140000;
dwStatus = WDC_DMAContigBufLock(hDev, &pbuf, dwOptions, dwDMABufSize, &pDma);
if (WD_STATUS_SUCCESS != dwStatus) {
printf("Failed locking a receive Contiguous DMA buffer. Error 0x%lx - %s\n", dwStatus, Stat2Str(dwStatus));
}
*/
px = &buf_send;
py = &read_array;
imod =11;
ichip=6;
for (j=0; j<nloop; j++) {
if(inew == 1) {
dwAddrSpace =2;
u32Data = 0xf0000008;
dwOffset = 0x28;
WDC_WriteAddr32(hDev, dwAddrSpace, dwOffset, u32Data);
}
ifr=0;
/** initialize **/
/* if(j ==0) { */
buf_send[0]=0x0;
buf_send[1]=0x0;
i=1;
k=1;
i = pcie_send(hDev, i, k, px);
/* } */
/** test command 1 ***/
if (j == 0) {
buf_send[0]=(imod <<11)+ (ichip << 8) + poweron;
buf_send[1]=0x1111;
i= 1;
k= 2;
/** try to cover 1.5*100ms */
i = pcie_send(hDev, i, k, px);
for (k=0; k<150000000; k++) {
ik=k+1;
i=ik*ik;
}
}
buf_send[0]=(imod <<11)+ (ichip << 8) + configure_s60;
buf_send[1]=0x5555aaaa;
buf_send[2]=0;
i= 1;
k= 2;
i = pcie_send(hDev, i, k, px);
for (k=0; k<1000000; k++) {
ik=k+1;
i=ik*ik;
}
/** test command 2 **/
/* buf_send[0]=(imod <<11)+ (ichip << 8) + poweroff;
buf_send[1]=0x1111;
i= 1;
k= 2;
i = pcie_send(hDev, i, k, px);
*/
if(ireadback == 1) {
buf_send[0]=(imod <<11)+ (ichip << 8) + loopback;
i= 1;
k= 1;
i = pcie_send(hDev, i, k, px);
}
inpf = fopen("/home/chi/dcm2_1152_boot","r");
/* read data as characters (28941) */
count = 0;
counta= 0;
while (fread(&charchannel,sizeof(char),1,inpf)==1) {
carray[count] = charchannel;
count++;
counta++;
/* if ((count)%1998==0) { */
/* nsend = 499; normal is 999 */
if((count%(nsend*2)) == 0){ /* normal is 1998 */
/* printf(" loop = %d\n",dummy1); */
buf_send[0] = (imod <<11) + (ichip << 8) + configure_cont + (carray[0]<<16);
send_array[0] =buf_send[0];
/* printf(" counta = %d, first word = %x, %x, %x \n",counta,buf_send[0], carray[0], carray[1]); */
for (ij=0; ij< nsend; ij++) {
buf_send[ij+1] = carray[2*ij+1]+ (carray[2*ij+2]<<16);
send_array[ij+1] = buf_send[ij+1];
}
nword =nsend+1;
/*
buf_send[0] = (imod <<11) + (ichip << 8) + configure_cont + (carray[0]<<16) +(carray[1]<<24) ;
for (ij=0; ij<499;ij++){
buf_send[ij+1] = carray[4*ij+2]+(carray[4*ij+3]<<8)+(carray[4*ij+4]<<16)+(carray[4*ij+5]<<24);
}
nword = 500;
*/
i=1;
/*
printf(" counta = %d, first word = %x \n",counta,buf_send[0]);
printf(" counta = %d, first word+1 = %x \n",counta,buf_send[1]);
printf(" counta = %d, last word-1= %x \n",counta,buf_send[498]);
printf(" counta = %d, last word = %x \n",counta,buf_send[499]);
*/
/* if(counta < 4*nsend+1) { */
if(ireadback == 1) {
if(idma_readback == 1) {
i=pcie_rec(hDev,1,1,nword,0,py); /** set up readback **/
}
else {
if(ifr ==0) {
WDC_WriteAddr32(hDev, dwAddrSpace, dwOffset, u32Data);
dwAddrSpace =2;
u32Data = 0x20000000;
dwOffset = 0x1c;
WDC_WriteAddr32(hDev, dwAddrSpace, dwOffset, u32Data);
printf(" receiver inited \n");
}
ifr =1;
dwAddrSpace =2;
u32Data = 0x40000000+nword*4;
dwOffset = 0x1c;
WDC_WriteAddr32(hDev, dwAddrSpace, dwOffset, u32Data);