From 550ab043e458a10a45392ce76015ca50181dda8a Mon Sep 17 00:00:00 2001
From: Tanmay Shah <tanmay.shah@amd.com>
Date: Fri, 4 Aug 2023 09:51:54 -0700
Subject: [PATCH] dts: xilinx: add dtsi files for both r5f cores

Xilinx ZynqMP platform has cortex-r5 cluster which can be
configured in lockstep or split mode. In lockstep mode
only one core is available where as in split mode two cores
can run independently in AMP mode. Introduce dtsi files for
RPU core0 and core1 to include separtely in case application
is being built for Asynchronous MultiProcessing use.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
---
 dts/arm/xilinx/zynqmp_rpu.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/dts/arm/xilinx/zynqmp_rpu.dtsi b/dts/arm/xilinx/zynqmp_rpu.dtsi
index cf52b4337939b0a..d94f512e45aafaf 100644
--- a/dts/arm/xilinx/zynqmp_rpu.dtsi
+++ b/dts/arm/xilinx/zynqmp_rpu.dtsi
@@ -21,6 +21,13 @@
 			reg = <0>;
 		};
 
+		cpu1: cpu@1 {
+			status = "disabled";
+			device_type = "cpu";
+			compatible = "arm,cortex-r5f";
+			reg = <0>;
+		};
+
 		cpu1: cpu@1 {
 			status = "disabled";
 			device_type = "cpu";