Yosys Synthesis using only Nand Gates
The goal of this repository is to share how I did to synthesize any verilog code to netilst with just NAND gates. If you know other ways to do it or came up with some optimitzations please let me know. I'd appreciate if you contributed.
In each folder i'll add README.md explaining what I did and how to run it. It's repository is not intended to be a tutorial but I will try to explain every step i followed.