diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_hsem.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_hsem.h
new file mode 100644
index 00000000000..cdc5884d462
--- /dev/null
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_hsem.h
@@ -0,0 +1,192 @@
+#include "stm32h7x3xx_memorymap.h"
+
+/* Register Offsets ***********************************************************/
+
+#define STM32_HSEM_R0_OFFSET 0x0
+#define STM32_HSEM_R1_OFFSET 0x4
+#define STM32_HSEM_R2_OFFSET 0x8
+#define STM32_HSEM_R3_OFFSET 0xC
+#define STM32_HSEM_R4_OFFSET 0x10
+#define STM32_HSEM_R5_OFFSET 0x14
+#define STM32_HSEM_R6_OFFSET 0x18
+#define STM32_HSEM_R7_OFFSET 0x1C
+#define STM32_HSEM_R8_OFFSET 0x20
+#define STM32_HSEM_R9_OFFSET 0x24
+#define STM32_HSEM_R10_OFFSET 0x28
+#define STM32_HSEM_R11_OFFSET 0x2C
+#define STM32_HSEM_R12_OFFSET 0x30
+#define STM32_HSEM_R13_OFFSET 0x34
+#define STM32_HSEM_R14_OFFSET 0x38
+#define STM32_HSEM_R15_OFFSET 0x3C
+#define STM32_HSEM_R16_OFFSET 0x40
+#define STM32_HSEM_R17_OFFSET 0x44
+#define STM32_HSEM_R18_OFFSET 0x48
+#define STM32_HSEM_R19_OFFSET 0x4C
+#define STM32_HSEM_R20_OFFSET 0x50
+#define STM32_HSEM_R21_OFFSET 0x54
+#define STM32_HSEM_R22_OFFSET 0x58
+#define STM32_HSEM_R23_OFFSET 0x5C
+#define STM32_HSEM_R24_OFFSET 0x60
+#define STM32_HSEM_R25_OFFSET 0x64
+#define STM32_HSEM_R26_OFFSET 0x68
+#define STM32_HSEM_R27_OFFSET 0x6C
+#define STM32_HSEM_R28_OFFSET 0x70
+#define STM32_HSEM_R29_OFFSET 0x74
+#define STM32_HSEM_R30_OFFSET 0x78
+#define STM32_HSEM_R31_OFFSET 0x7C
+#define STM32_HSEM_RLR0_OFFSET 0x80
+#define STM32_HSEM_RLR1_OFFSET 0x84
+#define STM32_HSEM_RLR2_OFFSET 0x88
+#define STM32_HSEM_RLR3_OFFSET 0x8C
+#define STM32_HSEM_RLR4_OFFSET 0x90
+#define STM32_HSEM_RLR5_OFFSET 0x94
+#define STM32_HSEM_RLR6_OFFSET 0x98
+#define STM32_HSEM_RLR7_OFFSET 0x9C
+#define STM32_HSEM_RLR8_OFFSET 0xA0
+#define STM32_HSEM_RLR9_OFFSET 0xA4
+#define STM32_HSEM_RLR10_OFFSET 0xA8
+#define STM32_HSEM_RLR11_OFFSET 0xAC
+#define STM32_HSEM_RLR12_OFFSET 0xB0
+#define STM32_HSEM_RLR13_OFFSET 0xB4
+#define STM32_HSEM_RLR14_OFFSET 0xB8
+#define STM32_HSEM_RLR15_OFFSET 0xBC
+#define STM32_HSEM_RLR16_OFFSET 0xC0
+#define STM32_HSEM_RLR17_OFFSET 0xC4
+#define STM32_HSEM_RLR18_OFFSET 0xC8
+#define STM32_HSEM_RLR19_OFFSET 0xCC
+#define STM32_HSEM_RLR20_OFFSET 0xD0
+#define STM32_HSEM_RLR21_OFFSET 0xD4
+#define STM32_HSEM_RLR22_OFFSET 0xD8
+#define STM32_HSEM_RLR23_OFFSET 0xDC
+#define STM32_HSEM_RLR24_OFFSET 0xE0
+#define STM32_HSEM_RLR25_OFFSET 0xE4
+#define STM32_HSEM_RLR26_OFFSET 0xE8
+#define STM32_HSEM_RLR27_OFFSET 0xEC
+#define STM32_HSEM_RLR28_OFFSET 0xF0
+#define STM32_HSEM_RLR29_OFFSET 0xF4
+#define STM32_HSEM_RLR30_OFFSET 0xF8
+#define STM32_HSEM_RLR31_OFFSET 0xFC
+#define STM32_HSEM_C1IER_OFFSET 0x100
+#define STM32_HSEM_C1ICR_OFFSET 0x104
+#define STM32_HSEM_C1ISR_OFFSET 0x108
+#define STM32_HSEM_C1MISR_OFFSET 0x10C
+#define STM32_HSEM_C2IER_OFFSET 0x110
+#define STM32_HSEM_C2ICR_OFFSET 0x114
+#define STM32_HSEM_C2ISR_OFFSET 0x118
+#define STM32_HSEM_C2MISR_OFFSET 0x11C
+#define STM32_HSEM_CR_OFFSET 0x140
+#define STM32_HSEM_KEYR_OFFSET 0x144
+
+/* Register Addresses *********************************************************/
+
+#define STM32_HSEM_R0 (STM32_HSEM_BASE + STM32_HSEM_R0_OFFSET)
+#define STM32_HSEM_R1 (STM32_HSEM_BASE + STM32_HSEM_R1_OFFSET)
+#define STM32_HSEM_R2 (STM32_HSEM_BASE + STM32_HSEM_R2_OFFSET)
+#define STM32_HSEM_R3 (STM32_HSEM_BASE + STM32_HSEM_R3_OFFSET)
+#define STM32_HSEM_R4 (STM32_HSEM_BASE + STM32_HSEM_R4_OFFSET)
+#define STM32_HSEM_R5 (STM32_HSEM_BASE + STM32_HSEM_R5_OFFSET)
+#define STM32_HSEM_R6 (STM32_HSEM_BASE + STM32_HSEM_R6_OFFSET)
+#define STM32_HSEM_R7 (STM32_HSEM_BASE + STM32_HSEM_R7_OFFSET)
+#define STM32_HSEM_R8 (STM32_HSEM_BASE + STM32_HSEM_R8_OFFSET)
+#define STM32_HSEM_R9 (STM32_HSEM_BASE + STM32_HSEM_R9_OFFSET)
+#define STM32_HSEM_R10 (STM32_HSEM_BASE + STM32_HSEM_R10_OFFSET)
+#define STM32_HSEM_R11 (STM32_HSEM_BASE + STM32_HSEM_R11_OFFSET)
+#define STM32_HSEM_R12 (STM32_HSEM_BASE + STM32_HSEM_R12_OFFSET)
+#define STM32_HSEM_R13 (STM32_HSEM_BASE + STM32_HSEM_R13_OFFSET)
+#define STM32_HSEM_R14 (STM32_HSEM_BASE + STM32_HSEM_R14_OFFSET)
+#define STM32_HSEM_R15 (STM32_HSEM_BASE + STM32_HSEM_R15_OFFSET)
+#define STM32_HSEM_R16 (STM32_HSEM_BASE + STM32_HSEM_R16_OFFSET)
+#define STM32_HSEM_R17 (STM32_HSEM_BASE + STM32_HSEM_R17_OFFSET)
+#define STM32_HSEM_R18 (STM32_HSEM_BASE + STM32_HSEM_R18_OFFSET)
+#define STM32_HSEM_R19 (STM32_HSEM_BASE + STM32_HSEM_R19_OFFSET)
+#define STM32_HSEM_R20 (STM32_HSEM_BASE + STM32_HSEM_R20_OFFSET)
+#define STM32_HSEM_R21 (STM32_HSEM_BASE + STM32_HSEM_R21_OFFSET)
+#define STM32_HSEM_R22 (STM32_HSEM_BASE + STM32_HSEM_R22_OFFSET)
+#define STM32_HSEM_R23 (STM32_HSEM_BASE + STM32_HSEM_R23_OFFSET)
+#define STM32_HSEM_R24 (STM32_HSEM_BASE + STM32_HSEM_R24_OFFSET)
+#define STM32_HSEM_R25 (STM32_HSEM_BASE + STM32_HSEM_R25_OFFSET)
+#define STM32_HSEM_R26 (STM32_HSEM_BASE + STM32_HSEM_R26_OFFSET)
+#define STM32_HSEM_R27 (STM32_HSEM_BASE + STM32_HSEM_R27_OFFSET)
+#define STM32_HSEM_R28 (STM32_HSEM_BASE + STM32_HSEM_R28_OFFSET)
+#define STM32_HSEM_R29 (STM32_HSEM_BASE + STM32_HSEM_R29_OFFSET)
+#define STM32_HSEM_R30 (STM32_HSEM_BASE + STM32_HSEM_R30_OFFSET)
+#define STM32_HSEM_R31 (STM32_HSEM_BASE + STM32_HSEM_R31_OFFSET)
+#define STM32_HSEM_RLR0 (STM32_HSEM_BASE + STM32_HSEM_RLR0_OFFSET)
+#define STM32_HSEM_RLR1 (STM32_HSEM_BASE + STM32_HSEM_RLR1_OFFSET)
+#define STM32_HSEM_RLR2 (STM32_HSEM_BASE + STM32_HSEM_RLR2_OFFSET)
+#define STM32_HSEM_RLR3 (STM32_HSEM_BASE + STM32_HSEM_RLR3_OFFSET)
+#define STM32_HSEM_RLR4 (STM32_HSEM_BASE + STM32_HSEM_RLR4_OFFSET)
+#define STM32_HSEM_RLR5 (STM32_HSEM_BASE + STM32_HSEM_RLR5_OFFSET)
+#define STM32_HSEM_RLR6 (STM32_HSEM_BASE + STM32_HSEM_RLR6_OFFSET)
+#define STM32_HSEM_RLR7 (STM32_HSEM_BASE + STM32_HSEM_RLR7_OFFSET)
+#define STM32_HSEM_RLR8 (STM32_HSEM_BASE + STM32_HSEM_RLR8_OFFSET)
+#define STM32_HSEM_RLR9 (STM32_HSEM_BASE + STM32_HSEM_RLR9_OFFSET)
+#define STM32_HSEM_RLR10 (STM32_HSEM_BASE + STM32_HSEM_RLR10_OFFSET)
+#define STM32_HSEM_RLR11 (STM32_HSEM_BASE + STM32_HSEM_RLR11_OFFSET)
+#define STM32_HSEM_RLR12 (STM32_HSEM_BASE + STM32_HSEM_RLR12_OFFSET)
+#define STM32_HSEM_RLR13 (STM32_HSEM_BASE + STM32_HSEM_RLR13_OFFSET)
+#define STM32_HSEM_RLR14 (STM32_HSEM_BASE + STM32_HSEM_RLR14_OFFSET)
+#define STM32_HSEM_RLR15 (STM32_HSEM_BASE + STM32_HSEM_RLR15_OFFSET)
+#define STM32_HSEM_RLR16 (STM32_HSEM_BASE + STM32_HSEM_RLR16_OFFSET)
+#define STM32_HSEM_RLR17 (STM32_HSEM_BASE + STM32_HSEM_RLR17_OFFSET)
+#define STM32_HSEM_RLR18 (STM32_HSEM_BASE + STM32_HSEM_RLR18_OFFSET)
+#define STM32_HSEM_RLR19 (STM32_HSEM_BASE + STM32_HSEM_RLR19_OFFSET)
+#define STM32_HSEM_RLR20 (STM32_HSEM_BASE + STM32_HSEM_RLR20_OFFSET)
+#define STM32_HSEM_RLR21 (STM32_HSEM_BASE + STM32_HSEM_RLR21_OFFSET)
+#define STM32_HSEM_RLR22 (STM32_HSEM_BASE + STM32_HSEM_RLR22_OFFSET)
+#define STM32_HSEM_RLR23 (STM32_HSEM_BASE + STM32_HSEM_RLR23_OFFSET)
+#define STM32_HSEM_RLR24 (STM32_HSEM_BASE + STM32_HSEM_RLR24_OFFSET)
+#define STM32_HSEM_RLR25 (STM32_HSEM_BASE + STM32_HSEM_RLR25_OFFSET)
+#define STM32_HSEM_RLR26 (STM32_HSEM_BASE + STM32_HSEM_RLR26_OFFSET)
+#define STM32_HSEM_RLR27 (STM32_HSEM_BASE + STM32_HSEM_RLR27_OFFSET)
+#define STM32_HSEM_RLR28 (STM32_HSEM_BASE + STM32_HSEM_RLR28_OFFSET)
+#define STM32_HSEM_RLR29 (STM32_HSEM_BASE + STM32_HSEM_RLR29_OFFSET)
+#define STM32_HSEM_RLR30 (STM32_HSEM_BASE + STM32_HSEM_RLR30_OFFSET)
+#define STM32_HSEM_RLR31 (STM32_HSEM_BASE + STM32_HSEM_RLR31_OFFSET)
+#define STM32_HSEM_C1IER (STM32_HSEM_BASE + STM32_HSEM_C1IER_OFFSET)
+#define STM32_HSEM_C1ICR (STM32_HSEM_BASE + STM32_HSEM_C1ICR_OFFSET)
+#define STM32_HSEM_C1ISR (STM32_HSEM_BASE + STM32_HSEM_C1ISR_OFFSET)
+#define STM32_HSEM_C1MISR (STM32_HSEM_BASE + STM32_HSEM_C1MISR_OFFSET)
+#define STM32_HSEM_C2IER (STM32_HSEM_BASE + STM32_HSEM_C2IER_OFFSET)
+#define STM32_HSEM_C2ICR (STM32_HSEM_BASE + STM32_HSEM_C2ICR_OFFSET)
+#define STM32_HSEM_C2ISR (STM32_HSEM_BASE + STM32_HSEM_C2ISR_OFFSET)
+#define STM32_HSEM_C2MISR (STM32_HSEM_BASE + STM32_HSEM_C2MISR_OFFSET)
+#define STM32_HSEM_CR (STM32_HSEM_BASE + STM32_HSEM_CR_OFFSET)
+#define STM32_HSEM_KEYR (STM32_HSEM_BASE + STM32_HSEM_KEYR_OFFSET)
+
+/* HSEM Rx registers 0 through 31 *********************************************/
+
+#define STM32_HSEM_Rx_PROCID (((1 << 8) - 1) << 0)
+#define STM32_HSEM_Rx_COREID (((1 << 4) - 1) << 8)
+#define STM32_HSEM_Rx_LOCK (((1 << 1) - 1) << 31)
+
+/* HSEM RLRx registers 0 through 31 *******************************************/
+
+#define STM32_HSEM_RLRx_PROCID (((1 << 8) - 1) << 0)
+#define STM32_HSEM_RLRx_COREID (((1 << 4) - 1) << 8)
+#define STM32_HSEM_RLRx_LOCK (((1 << 1) - 1) << 31)
+
+/* HSEM CxIER registers 1 and 2 ***********************************************/
+
+#define STM32_HSEM_CxIER_ISE (((1 << 32) - 1) << 0)
+
+/* HSEM CxICR registers 1 and 2 ***********************************************/
+
+#define STM32_HSEM_CxICR_ISC (((1 << 32) - 1) << 0)
+
+/* HSEM CxISR registers 1 and 2 ***********************************************/
+
+#define STM32_HSEM_CxISR_ISF (((1 << 32) - 1) << 0)
+
+/* HSEM CxMISR registers 1 and 2 **********************************************/
+
+#define STM32_HSEM_CxMISR_MISF (((1 << 32) - 1) << 0)
+
+/* HSEM CR register ***********************************************************/
+
+#define STM32_HSEM_CR_COREID (((1 << 4) - 1) << 8)
+#define STM32_HSEM_CR_KEY (((1 << 16) - 1) << 16)
+
+/* HSEM KEYR register *********************************************************/
+
+#define STM32_HSEM_KEYR_KEY (((1 << 16) - 1) << 16)