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topmodule_timesim.vhd
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topmodule_timesim.vhd
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: topmodule_timesim.vhd
-- /___/ /\ Timestamp: Sat Nov 03 11:49:05 2018
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -rpw 100 -ar Structure -tm topmodule -w -dir netgen/fit -ofmt vhdl -sim topmodule.nga topmodule_timesim.vhd
-- Device : XC2C128-6-VQ100 (Speed File: Version 14.0 Advance Product Specification)
-- Input file : topmodule.nga
-- Output file : C:\Matura_2_0\Screenbuffer_V2\CPLD_FIN\CPLD_BUFF\netgen\fit\topmodule_timesim.vhd
-- # of Entities : 1
-- Design Name : topmodule.nga
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity topmodule is
port (
sclk : in STD_LOGIC := 'X';
gclk : in STD_LOGIC := 'X';
proc_rcv_en : in STD_LOGIC := 'X';
proc_grclk_en : in STD_LOGIC := 'X';
proc_wr_b : in STD_LOGIC := 'X';
proc_wr_a : in STD_LOGIC := 'X';
proc_sclk : in STD_LOGIC := 'X';
proc_latch : in STD_LOGIC := 'X';
miso_a : in STD_LOGIC := 'X';
miso_b : in STD_LOGIC := 'X';
proc_mosi : in STD_LOGIC := 'X';
sdin : in STD_LOGIC := 'X';
sdprev : in STD_LOGIC := 'X';
done : out STD_LOGIC;
grayscale_clk : out STD_LOGIC;
latch_out1 : out STD_LOGIC;
latch_out2 : out STD_LOGIC;
mosi_a : out STD_LOGIC;
mosi_b : out STD_LOGIC;
panel_select : out STD_LOGIC;
reset : out STD_LOGIC;
sdout : out STD_LOGIC;
sdprev_en : out STD_LOGIC;
tsclk_a : out STD_LOGIC;
tsclk_b : out STD_LOGIC;
addr_sel : in STD_LOGIC_VECTOR ( 3 downto 0 );
line_select : out STD_LOGIC_VECTOR ( 7 downto 0 );
mode_data : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
end topmodule;
architecture Structure of topmodule is
signal addr_sel_0_II_UIM_1 : STD_LOGIC;
signal addr_sel_1_II_UIM_3 : STD_LOGIC;
signal addr_sel_2_II_UIM_5 : STD_LOGIC;
signal addr_sel_3_II_UIM_7 : STD_LOGIC;
signal sclk_II_UIM_9 : STD_LOGIC;
signal sclk_II_FCLK_10 : STD_LOGIC;
signal gclk_II_UIM_12 : STD_LOGIC;
signal gclk_II_FCLK_13 : STD_LOGIC;
signal proc_rcv_en_II_UIM_15 : STD_LOGIC;
signal proc_grclk_en_II_UIM_17 : STD_LOGIC;
signal proc_wr_b_II_UIM_19 : STD_LOGIC;
signal proc_wr_a_II_UIM_21 : STD_LOGIC;
signal proc_sclk_II_UIM_23 : STD_LOGIC;
signal proc_latch_II_UIM_25 : STD_LOGIC;
signal miso_a_II_UIM_27 : STD_LOGIC;
signal miso_b_II_UIM_29 : STD_LOGIC;
signal proc_mosi_II_UIM_31 : STD_LOGIC;
signal sdin_II_UIM_33 : STD_LOGIC;
signal sdin_II_IREG_34 : STD_LOGIC;
signal FOOBAR1_ctinst_5_35 : STD_LOGIC;
signal Gnd_36 : STD_LOGIC;
signal ser_in_serial_dout_0_MC_tsimcreated_prld_Q_37 : STD_LOGIC;
signal ser_in_serial_dout_0_MC_CE_38 : STD_LOGIC;
signal ser_in_serial_dout_0_Q : STD_LOGIC;
signal sdprev_II_UIM_41 : STD_LOGIC;
signal done_MC_Q_43 : STD_LOGIC;
signal grayscale_clk_MC_Q_45 : STD_LOGIC;
signal latch_out1_MC_Q_47 : STD_LOGIC;
signal latch_out2_MC_Q_49 : STD_LOGIC;
signal line_select_0_MC_Q_51 : STD_LOGIC;
signal line_select_1_MC_Q_53 : STD_LOGIC;
signal line_select_2_MC_Q_55 : STD_LOGIC;
signal line_select_3_MC_Q_57 : STD_LOGIC;
signal line_select_4_MC_Q_59 : STD_LOGIC;
signal line_select_5_MC_Q_61 : STD_LOGIC;
signal line_select_6_MC_Q_63 : STD_LOGIC;
signal line_select_7_MC_Q_65 : STD_LOGIC;
signal mode_data_0_MC_Q_67 : STD_LOGIC;
signal mode_data_1_MC_Q_69 : STD_LOGIC;
signal mode_data_2_MC_Q_71 : STD_LOGIC;
signal mosi_a_MC_Q_73 : STD_LOGIC;
signal mosi_b_MC_Q_75 : STD_LOGIC;
signal panel_select_MC_Q_77 : STD_LOGIC;
signal reset_MC_Q_79 : STD_LOGIC;
signal sdout_MC_Q_81 : STD_LOGIC;
signal sdprev_en_MC_Q_83 : STD_LOGIC;
signal tsclk_a_MC_Q_85 : STD_LOGIC;
signal tsclk_b_MC_Q_87 : STD_LOGIC;
signal done_MC_Q_tsimrenamed_net_Q : STD_LOGIC;
signal done_MC_D_89 : STD_LOGIC;
signal done_MC_tsimcreated_xor_Q_90 : STD_LOGIC;
signal Vcc_91 : STD_LOGIC;
signal done_MC_D1_92 : STD_LOGIC;
signal done_MC_D2_93 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd1_94 : STD_LOGIC;
signal reset_BUFR_98 : STD_LOGIC;
signal mode_data_2_MC_UIM_99 : STD_LOGIC;
signal panel_select_MC_UIM_114 : STD_LOGIC;
signal done_MC_D2_PT_0_115 : STD_LOGIC;
signal done_MC_D2_PT_1_116 : STD_LOGIC;
signal N_PZ_448_117 : STD_LOGIC;
signal done_MC_D2_PT_2_118 : STD_LOGIC;
signal mode_data_2_MC_Q_tsimrenamed_net_Q : STD_LOGIC;
signal mode_data_2_MC_RSTF_120 : STD_LOGIC;
signal mode_data_2_MC_tsimcreated_prld_Q_121 : STD_LOGIC;
signal mode_data_2_MC_D_122 : STD_LOGIC;
signal mode_data_2_MC_CE_123 : STD_LOGIC;
signal mode_data_2_MC_D1_124 : STD_LOGIC;
signal mode_data_2_MC_D2_125 : STD_LOGIC;
signal mode_data_1_MC_UIM_126 : STD_LOGIC;
signal ser_in_counter_STATE_or0000_127 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd2_128 : STD_LOGIC;
signal mode_data_1_MC_Q_tsimrenamed_net_Q : STD_LOGIC;
signal mode_data_1_MC_RSTF_130 : STD_LOGIC;
signal mode_data_1_MC_tsimcreated_prld_Q_131 : STD_LOGIC;
signal mode_data_1_MC_D_132 : STD_LOGIC;
signal mode_data_1_MC_CE_133 : STD_LOGIC;
signal mode_data_1_MC_D1_134 : STD_LOGIC;
signal mode_data_1_MC_D2_135 : STD_LOGIC;
signal mode_data_0_MC_UIM_136 : STD_LOGIC;
signal mode_data_0_MC_Q_tsimrenamed_net_Q : STD_LOGIC;
signal mode_data_0_MC_RSTF_138 : STD_LOGIC;
signal mode_data_0_MC_tsimcreated_prld_Q_139 : STD_LOGIC;
signal mode_data_0_MC_D_140 : STD_LOGIC;
signal mode_data_0_MC_CE_141 : STD_LOGIC;
signal mode_data_0_MC_D1_142 : STD_LOGIC;
signal mode_data_0_MC_D2_143 : STD_LOGIC;
signal ser_in_serial_dout_3_Q_144 : STD_LOGIC;
signal ser_in_serial_dout_3_MC_Q : STD_LOGIC;
signal FOOBAR2_ctinst_5_146 : STD_LOGIC;
signal ser_in_serial_dout_3_MC_tsimcreated_prld_Q_147 : STD_LOGIC;
signal ser_in_serial_dout_3_MC_D_148 : STD_LOGIC;
signal ser_in_serial_dout_3_MC_CE_149 : STD_LOGIC;
signal ser_in_serial_dout_3_MC_D1_150 : STD_LOGIC;
signal ser_in_serial_dout_3_MC_D2_151 : STD_LOGIC;
signal ser_in_serial_dout_2_Q_152 : STD_LOGIC;
signal ser_in_serial_dout_2_MC_Q : STD_LOGIC;
signal ser_in_serial_dout_2_MC_tsimcreated_prld_Q_154 : STD_LOGIC;
signal ser_in_serial_dout_2_MC_D_155 : STD_LOGIC;
signal ser_in_serial_dout_2_MC_CE_156 : STD_LOGIC;
signal ser_in_serial_dout_2_MC_D1_157 : STD_LOGIC;
signal ser_in_serial_dout_2_MC_D2_158 : STD_LOGIC;
signal ser_in_serial_dout_1_Q_159 : STD_LOGIC;
signal ser_in_serial_dout_1_MC_Q : STD_LOGIC;
signal ser_in_serial_dout_1_MC_tsimcreated_prld_Q_161 : STD_LOGIC;
signal ser_in_serial_dout_1_MC_D_162 : STD_LOGIC;
signal ser_in_serial_dout_1_MC_CE_163 : STD_LOGIC;
signal ser_in_serial_dout_1_MC_D1_164 : STD_LOGIC;
signal ser_in_serial_dout_1_MC_D2_165 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd1_MC_Q : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd1_MC_D_167 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd1_MC_tsimcreated_xor_Q_168 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd1_MC_tsimcreated_prld_Q_169 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd1_MC_D1_170 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd1_MC_D2_171 : STD_LOGIC;
signal N_PZ_383_172 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd1_MC_D2_PT_0_173 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd1_MC_D2_PT_1_174 : STD_LOGIC;
signal ser_in_counter_latchcount_0_MC_Q : STD_LOGIC;
signal ser_in_counter_latchcount_0_MC_D_176 : STD_LOGIC;
signal ser_in_counter_latchcount_0_MC_tsimcreated_xor_Q_177 : STD_LOGIC;
signal ser_in_counter_latchcount_0_MC_tsimcreated_prld_Q_178 : STD_LOGIC;
signal ser_in_counter_latchcount_0_MC_D1_179 : STD_LOGIC;
signal ser_in_counter_latchcount_0_MC_D2_180 : STD_LOGIC;
signal ser_in_counter_bitcount_1_MC_Q : STD_LOGIC;
signal ser_in_counter_bitcount_1_MC_D_182 : STD_LOGIC;
signal ser_in_counter_bitcount_1_MC_tsimcreated_xor_Q_183 : STD_LOGIC;
signal ser_in_counter_bitcount_1_MC_tsimcreated_prld_Q_184 : STD_LOGIC;
signal ser_in_counter_bitcount_1_MC_D1_185 : STD_LOGIC;
signal ser_in_counter_bitcount_1_MC_D2_186 : STD_LOGIC;
signal ser_in_counter_bitcount_1_MC_D2_PT_0_187 : STD_LOGIC;
signal ser_in_counter_bitcount_1_MC_D2_PT_1_188 : STD_LOGIC;
signal ser_in_counter_bitcount_0_MC_Q : STD_LOGIC;
signal ser_in_counter_bitcount_0_MC_D_190 : STD_LOGIC;
signal ser_in_counter_bitcount_0_MC_tsimcreated_xor_Q_191 : STD_LOGIC;
signal ser_in_counter_bitcount_0_MC_RSTF_192 : STD_LOGIC;
signal ser_in_counter_bitcount_0_MC_tsimcreated_prld_Q_193 : STD_LOGIC;
signal ser_in_counter_bitcount_0_MC_D1_194 : STD_LOGIC;
signal ser_in_counter_bitcount_0_MC_D2_195 : STD_LOGIC;
signal ser_in_counter_STATE_or0000_MC_Q_196 : STD_LOGIC;
signal ser_in_counter_STATE_or0000_MC_D_197 : STD_LOGIC;
signal ser_in_counter_STATE_or0000_MC_D1_198 : STD_LOGIC;
signal ser_in_counter_STATE_or0000_MC_D2_199 : STD_LOGIC;
signal ser_in_counter_STATE_or0000_MC_D2_PT_0_200 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0000_201 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0001_202 : STD_LOGIC;
signal ser_in_counter_STATE_or0000_MC_D2_PT_1_203 : STD_LOGIC;
signal ser_in_counter_STATE_or0000_MC_D2_PT_2_204 : STD_LOGIC;
signal ser_in_counter_STATE_or0000_MC_D2_PT_3_205 : STD_LOGIC;
signal ser_in_counter_STATE_or0000_MC_D2_PT_4_206 : STD_LOGIC;
signal reset_BUFR_MC_Q_207 : STD_LOGIC;
signal reset_BUFR_MC_D_208 : STD_LOGIC;
signal reset_BUFR_MC_D1_209 : STD_LOGIC;
signal reset_BUFR_MC_D2_210 : STD_LOGIC;
signal res_reg_0_MC_Q : STD_LOGIC;
signal res_reg_0_MC_D_228 : STD_LOGIC;
signal res_reg_0_MC_tsimcreated_xor_Q_229 : STD_LOGIC;
signal res_reg_0_MC_D1_230 : STD_LOGIC;
signal res_reg_0_MC_D2_231 : STD_LOGIC;
signal res_reg_0_MC_D2_PT_0_232 : STD_LOGIC;
signal tick_233 : STD_LOGIC;
signal res_reg_0_MC_D2_PT_1_234 : STD_LOGIC;
signal tick_MC_Q : STD_LOGIC;
signal FOOBAR7_ctinst_5_236 : STD_LOGIC;
signal tick_MC_tsimcreated_prld_Q_237 : STD_LOGIC;
signal tick_MC_D_238 : STD_LOGIC;
signal tick_MC_D1_239 : STD_LOGIC;
signal tick_MC_D2_240 : STD_LOGIC;
signal grclkgen_tgen_cnt_0_MC_Q : STD_LOGIC;
signal grclkgen_tgen_cnt_0_MC_D_244 : STD_LOGIC;
signal grclkgen_tgen_cnt_0_MC_tsimcreated_xor_Q_245 : STD_LOGIC;
signal FOOBAR3_ctinst_5_246 : STD_LOGIC;
signal grclkgen_tgen_cnt_0_MC_tsimcreated_prld_Q_247 : STD_LOGIC;
signal grclkgen_tgen_cnt_0_MC_D1_248 : STD_LOGIC;
signal grclkgen_tgen_cnt_0_MC_D2_249 : STD_LOGIC;
signal grclkgen_tgen_cnt_1_MC_Q : STD_LOGIC;
signal grclkgen_tgen_cnt_1_MC_D_251 : STD_LOGIC;
signal grclkgen_tgen_cnt_1_MC_tsimcreated_xor_Q_252 : STD_LOGIC;
signal grclkgen_tgen_cnt_1_MC_tsimcreated_prld_Q_253 : STD_LOGIC;
signal grclkgen_tgen_cnt_1_MC_D1_254 : STD_LOGIC;
signal grclkgen_tgen_cnt_1_MC_D2_255 : STD_LOGIC;
signal res_reg_10_MC_Q : STD_LOGIC;
signal res_reg_10_MC_D_257 : STD_LOGIC;
signal res_reg_10_MC_tsimcreated_xor_Q_258 : STD_LOGIC;
signal res_reg_10_MC_D1_259 : STD_LOGIC;
signal res_reg_10_MC_D2_260 : STD_LOGIC;
signal res_reg_10_MC_D2_PT_0_261 : STD_LOGIC;
signal res_reg_10_MC_D2_PT_1_262 : STD_LOGIC;
signal res_reg_1_MC_Q : STD_LOGIC;
signal res_reg_1_MC_D_264 : STD_LOGIC;
signal res_reg_1_MC_tsimcreated_xor_Q_265 : STD_LOGIC;
signal res_reg_1_MC_D1_266 : STD_LOGIC;
signal res_reg_1_MC_D2_267 : STD_LOGIC;
signal res_reg_1_MC_D2_PT_0_268 : STD_LOGIC;
signal res_reg_1_MC_D2_PT_1_269 : STD_LOGIC;
signal res_reg_2_MC_Q : STD_LOGIC;
signal res_reg_2_MC_D_271 : STD_LOGIC;
signal res_reg_2_MC_tsimcreated_xor_Q_272 : STD_LOGIC;
signal res_reg_2_MC_D1_273 : STD_LOGIC;
signal res_reg_2_MC_D2_274 : STD_LOGIC;
signal res_reg_2_MC_D2_PT_0_275 : STD_LOGIC;
signal res_reg_2_MC_D2_PT_1_276 : STD_LOGIC;
signal res_reg_3_MC_Q : STD_LOGIC;
signal res_reg_3_MC_D_278 : STD_LOGIC;
signal res_reg_3_MC_tsimcreated_xor_Q_279 : STD_LOGIC;
signal res_reg_3_MC_D1_280 : STD_LOGIC;
signal res_reg_3_MC_D2_281 : STD_LOGIC;
signal res_reg_3_MC_D2_PT_0_282 : STD_LOGIC;
signal res_reg_3_MC_D2_PT_1_283 : STD_LOGIC;
signal res_reg_4_MC_Q : STD_LOGIC;
signal res_reg_4_MC_D_285 : STD_LOGIC;
signal res_reg_4_MC_tsimcreated_xor_Q_286 : STD_LOGIC;
signal res_reg_4_MC_D1_287 : STD_LOGIC;
signal res_reg_4_MC_D2_288 : STD_LOGIC;
signal res_reg_4_MC_D2_PT_0_289 : STD_LOGIC;
signal res_reg_4_MC_D2_PT_1_290 : STD_LOGIC;
signal res_reg_5_MC_Q : STD_LOGIC;
signal res_reg_5_MC_D_292 : STD_LOGIC;
signal res_reg_5_MC_tsimcreated_xor_Q_293 : STD_LOGIC;
signal res_reg_5_MC_D1_294 : STD_LOGIC;
signal res_reg_5_MC_D2_295 : STD_LOGIC;
signal res_reg_5_MC_D2_PT_0_296 : STD_LOGIC;
signal res_reg_5_MC_D2_PT_1_297 : STD_LOGIC;
signal res_reg_6_MC_Q : STD_LOGIC;
signal res_reg_6_MC_D_299 : STD_LOGIC;
signal res_reg_6_MC_tsimcreated_xor_Q_300 : STD_LOGIC;
signal res_reg_6_MC_D1_301 : STD_LOGIC;
signal res_reg_6_MC_D2_302 : STD_LOGIC;
signal res_reg_6_MC_D2_PT_0_303 : STD_LOGIC;
signal res_reg_6_MC_D2_PT_1_304 : STD_LOGIC;
signal res_reg_7_MC_Q : STD_LOGIC;
signal res_reg_7_MC_D_306 : STD_LOGIC;
signal res_reg_7_MC_tsimcreated_xor_Q_307 : STD_LOGIC;
signal res_reg_7_MC_D1_308 : STD_LOGIC;
signal res_reg_7_MC_D2_309 : STD_LOGIC;
signal res_reg_7_MC_D2_PT_0_310 : STD_LOGIC;
signal res_reg_7_MC_D2_PT_1_311 : STD_LOGIC;
signal res_reg_8_MC_Q : STD_LOGIC;
signal res_reg_8_MC_D_313 : STD_LOGIC;
signal res_reg_8_MC_tsimcreated_xor_Q_314 : STD_LOGIC;
signal res_reg_8_MC_D1_315 : STD_LOGIC;
signal res_reg_8_MC_D2_316 : STD_LOGIC;
signal res_reg_8_MC_D2_PT_0_317 : STD_LOGIC;
signal res_reg_8_MC_D2_PT_1_318 : STD_LOGIC;
signal res_reg_9_MC_Q : STD_LOGIC;
signal res_reg_9_MC_D_320 : STD_LOGIC;
signal res_reg_9_MC_tsimcreated_xor_Q_321 : STD_LOGIC;
signal res_reg_9_MC_D1_322 : STD_LOGIC;
signal res_reg_9_MC_D2_323 : STD_LOGIC;
signal res_reg_9_MC_D2_PT_0_324 : STD_LOGIC;
signal res_reg_9_MC_D2_PT_1_325 : STD_LOGIC;
signal res_reg_11_MC_Q : STD_LOGIC;
signal res_reg_11_MC_D_327 : STD_LOGIC;
signal res_reg_11_MC_tsimcreated_xor_Q_328 : STD_LOGIC;
signal res_reg_11_MC_D1_329 : STD_LOGIC;
signal res_reg_11_MC_D2_330 : STD_LOGIC;
signal res_reg_11_MC_D2_PT_0_331 : STD_LOGIC;
signal res_reg_11_MC_D2_PT_1_332 : STD_LOGIC;
signal res_reg_12_MC_Q : STD_LOGIC;
signal res_reg_12_MC_D_334 : STD_LOGIC;
signal res_reg_12_MC_tsimcreated_xor_Q_335 : STD_LOGIC;
signal res_reg_12_MC_D1_336 : STD_LOGIC;
signal res_reg_12_MC_D2_337 : STD_LOGIC;
signal res_reg_12_MC_D2_PT_0_338 : STD_LOGIC;
signal res_reg_12_MC_D2_PT_1_339 : STD_LOGIC;
signal res_reg_13_MC_Q : STD_LOGIC;
signal res_reg_13_MC_D_341 : STD_LOGIC;
signal res_reg_13_MC_tsimcreated_xor_Q_342 : STD_LOGIC;
signal res_reg_13_MC_D1_343 : STD_LOGIC;
signal res_reg_13_MC_D2_344 : STD_LOGIC;
signal res_reg_13_MC_D2_PT_0_345 : STD_LOGIC;
signal res_reg_13_MC_D2_PT_1_346 : STD_LOGIC;
signal res_reg_14_MC_Q : STD_LOGIC;
signal res_reg_14_MC_D_348 : STD_LOGIC;
signal res_reg_14_MC_tsimcreated_xor_Q_349 : STD_LOGIC;
signal res_reg_14_MC_D1_350 : STD_LOGIC;
signal res_reg_14_MC_D2_351 : STD_LOGIC;
signal res_reg_14_MC_D2_PT_0_352 : STD_LOGIC;
signal res_reg_14_MC_D2_PT_1_353 : STD_LOGIC;
signal res_reg_15_MC_Q : STD_LOGIC;
signal res_reg_15_MC_D_355 : STD_LOGIC;
signal res_reg_15_MC_tsimcreated_xor_Q_356 : STD_LOGIC;
signal res_reg_15_MC_D1_357 : STD_LOGIC;
signal res_reg_15_MC_D2_358 : STD_LOGIC;
signal res_reg_15_MC_D2_PT_0_359 : STD_LOGIC;
signal res_reg_15_MC_D2_PT_1_360 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0000_MC_Q_361 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0000_MC_D_362 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0000_MC_D1_363 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0000_MC_D2_364 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0000_MC_D2_PT_0_365 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0000_MC_D2_PT_1_366 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0000_MC_D2_PT_2_367 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0000_MC_D2_PT_3_368 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0001_MC_Q_369 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0001_MC_D_370 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0001_MC_D1_371 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0001_MC_D2_372 : STD_LOGIC;
signal ser_in_serial_dout_7_Q_373 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0001_MC_D2_PT_0_374 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0001_MC_D2_PT_1_375 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0001_MC_D2_PT_2_376 : STD_LOGIC;
signal ser_in_comparator_Mxor_addr_valid_xor0000_xor0001_MC_D2_PT_3_377 : STD_LOGIC;
signal ser_in_serial_dout_7_MC_Q : STD_LOGIC;
signal ser_in_serial_dout_7_MC_tsimcreated_prld_Q_379 : STD_LOGIC;
signal ser_in_serial_dout_7_MC_D_380 : STD_LOGIC;
signal ser_in_serial_dout_7_MC_CE_381 : STD_LOGIC;
signal ser_in_serial_dout_7_MC_D1_382 : STD_LOGIC;
signal ser_in_serial_dout_7_MC_D2_383 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd2_MC_Q : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd2_MC_D_385 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd2_MC_tsimcreated_xor_Q_386 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd2_MC_tsimcreated_prld_Q_387 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd2_MC_D1_388 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd2_MC_D2_389 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd2_MC_D2_PT_0_390 : STD_LOGIC;
signal ser_in_counter_STATE_FSM_FFd2_MC_D2_PT_1_391 : STD_LOGIC;
signal ser_in_counter_bitcount_2_MC_Q : STD_LOGIC;
signal ser_in_counter_bitcount_2_MC_D_393 : STD_LOGIC;
signal ser_in_counter_bitcount_2_MC_tsimcreated_xor_Q_394 : STD_LOGIC;
signal ser_in_counter_bitcount_2_MC_tsimcreated_prld_Q_395 : STD_LOGIC;
signal ser_in_counter_bitcount_2_MC_D1_396 : STD_LOGIC;
signal ser_in_counter_bitcount_2_MC_D2_397 : STD_LOGIC;
signal ser_in_counter_bitcount_3_MC_Q : STD_LOGIC;
signal ser_in_counter_bitcount_3_MC_D_399 : STD_LOGIC;
signal ser_in_counter_bitcount_3_MC_tsimcreated_xor_Q_400 : STD_LOGIC;
signal ser_in_counter_bitcount_3_MC_tsimcreated_prld_Q_401 : STD_LOGIC;
signal ser_in_counter_bitcount_3_MC_D1_402 : STD_LOGIC;
signal ser_in_counter_bitcount_3_MC_D2_403 : STD_LOGIC;
signal ser_in_counter_bitcount_3_MC_D2_PT_0_404 : STD_LOGIC;
signal ser_in_counter_bitcount_3_MC_D2_PT_1_405 : STD_LOGIC;
signal ser_in_counter_bitcount_3_MC_D2_PT_2_406 : STD_LOGIC;
signal ser_in_counter_bitcount_3_MC_D2_PT_3_407 : STD_LOGIC;
signal ser_in_counter_bitcount_4_MC_Q : STD_LOGIC;
signal ser_in_counter_bitcount_4_MC_D_409 : STD_LOGIC;
signal ser_in_counter_bitcount_4_MC_tsimcreated_xor_Q_410 : STD_LOGIC;
signal ser_in_counter_bitcount_4_MC_tsimcreated_prld_Q_411 : STD_LOGIC;
signal ser_in_counter_bitcount_4_MC_D1_412 : STD_LOGIC;
signal ser_in_counter_bitcount_4_MC_D2_413 : STD_LOGIC;
signal ser_in_counter_bitcount_6_MC_Q : STD_LOGIC;
signal ser_in_counter_bitcount_6_MC_D_415 : STD_LOGIC;
signal ser_in_counter_bitcount_6_MC_tsimcreated_xor_Q_416 : STD_LOGIC;
signal ser_in_counter_bitcount_6_MC_tsimcreated_prld_Q_417 : STD_LOGIC;
signal ser_in_counter_bitcount_6_MC_D1_418 : STD_LOGIC;
signal ser_in_counter_bitcount_6_MC_D2_419 : STD_LOGIC;
signal ser_in_counter_bitcount_6_MC_D2_PT_0_420 : STD_LOGIC;
signal ser_in_counter_bitcount_6_MC_D2_PT_1_421 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_Q : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_D_423 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_tsimcreated_xor_Q_424 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_tsimcreated_prld_Q_425 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_D1_426 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_D2_427 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_D2_PT_0_428 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_D2_PT_1_429 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_D2_PT_2_430 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_D2_PT_3_431 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_D2_PT_4_432 : STD_LOGIC;
signal ser_in_counter_bitcount_5_MC_D2_PT_5_433 : STD_LOGIC;
signal ser_in_counter_bitcount_8_MC_Q : STD_LOGIC;
signal ser_in_counter_bitcount_8_MC_D_435 : STD_LOGIC;
signal ser_in_counter_bitcount_8_MC_tsimcreated_xor_Q_436 : STD_LOGIC;
signal ser_in_counter_bitcount_8_MC_tsimcreated_prld_Q_437 : STD_LOGIC;
signal ser_in_counter_bitcount_8_MC_D1_438 : STD_LOGIC;
signal ser_in_counter_bitcount_8_MC_D2_439 : STD_LOGIC;
signal ser_in_counter_bitcount_8_MC_D2_PT_0_440 : STD_LOGIC;
signal ser_in_counter_bitcount_8_MC_D2_PT_1_441 : STD_LOGIC;
signal ser_in_counter_bitcount_7_MC_Q : STD_LOGIC;
signal ser_in_counter_bitcount_7_MC_D_443 : STD_LOGIC;
signal ser_in_counter_bitcount_7_MC_tsimcreated_xor_Q_444 : STD_LOGIC;
signal ser_in_counter_bitcount_7_MC_tsimcreated_prld_Q_445 : STD_LOGIC;
signal ser_in_counter_bitcount_7_MC_D1_446 : STD_LOGIC;
signal ser_in_counter_bitcount_7_MC_D2_447 : STD_LOGIC;
signal ser_in_counter_bitcount_9_MC_Q : STD_LOGIC;
signal ser_in_counter_bitcount_9_MC_D_449 : STD_LOGIC;
signal ser_in_counter_bitcount_9_MC_tsimcreated_xor_Q_450 : STD_LOGIC;
signal ser_in_counter_bitcount_9_MC_tsimcreated_prld_Q_451 : STD_LOGIC;
signal ser_in_counter_bitcount_9_MC_D1_452 : STD_LOGIC;
signal ser_in_counter_bitcount_9_MC_D2_453 : STD_LOGIC;
signal ser_in_counter_bitcount_9_MC_D2_PT_0_454 : STD_LOGIC;
signal ser_in_counter_bitcount_9_MC_D2_PT_1_455 : STD_LOGIC;
signal N_PZ_448_MC_Q_456 : STD_LOGIC;
signal N_PZ_448_MC_D_457 : STD_LOGIC;
signal N_PZ_448_MC_D1_458 : STD_LOGIC;
signal N_PZ_448_MC_D2_459 : STD_LOGIC;
signal ser_in_counter_latchcount_1_MC_Q : STD_LOGIC;
signal ser_in_counter_latchcount_1_MC_D_461 : STD_LOGIC;
signal ser_in_counter_latchcount_1_MC_tsimcreated_xor_Q_462 : STD_LOGIC;
signal ser_in_counter_latchcount_1_MC_tsimcreated_prld_Q_463 : STD_LOGIC;
signal ser_in_counter_latchcount_1_MC_D1_464 : STD_LOGIC;
signal ser_in_counter_latchcount_1_MC_D2_465 : STD_LOGIC;
signal ser_in_counter_latchcount_2_MC_Q : STD_LOGIC;
signal ser_in_counter_latchcount_2_MC_D_467 : STD_LOGIC;
signal ser_in_counter_latchcount_2_MC_tsimcreated_xor_Q_468 : STD_LOGIC;
signal ser_in_counter_latchcount_2_MC_tsimcreated_prld_Q_469 : STD_LOGIC;
signal ser_in_counter_latchcount_2_MC_D1_470 : STD_LOGIC;
signal ser_in_counter_latchcount_2_MC_D2_471 : STD_LOGIC;
signal ser_in_counter_latchcount_3_MC_Q : STD_LOGIC;
signal ser_in_counter_latchcount_3_MC_D_473 : STD_LOGIC;
signal ser_in_counter_latchcount_3_MC_tsimcreated_xor_Q_474 : STD_LOGIC;
signal ser_in_counter_latchcount_3_MC_tsimcreated_prld_Q_475 : STD_LOGIC;
signal ser_in_counter_latchcount_3_MC_D1_476 : STD_LOGIC;
signal ser_in_counter_latchcount_3_MC_D2_477 : STD_LOGIC;
signal ser_in_counter_latchcount_4_MC_Q : STD_LOGIC;
signal ser_in_counter_latchcount_4_MC_D_479 : STD_LOGIC;
signal ser_in_counter_latchcount_4_MC_tsimcreated_xor_Q_480 : STD_LOGIC;
signal ser_in_counter_latchcount_4_MC_tsimcreated_prld_Q_481 : STD_LOGIC;
signal ser_in_counter_latchcount_4_MC_D1_482 : STD_LOGIC;
signal ser_in_counter_latchcount_4_MC_D2_483 : STD_LOGIC;
signal ser_in_counter_latchcount_5_MC_Q : STD_LOGIC;
signal ser_in_counter_latchcount_5_MC_D_485 : STD_LOGIC;
signal ser_in_counter_latchcount_5_MC_tsimcreated_xor_Q_486 : STD_LOGIC;
signal ser_in_counter_latchcount_5_MC_tsimcreated_prld_Q_487 : STD_LOGIC;
signal ser_in_counter_latchcount_5_MC_D1_488 : STD_LOGIC;
signal ser_in_counter_latchcount_5_MC_D2_489 : STD_LOGIC;
signal ser_in_counter_latchcount_6_MC_Q : STD_LOGIC;
signal ser_in_counter_latchcount_6_MC_D_491 : STD_LOGIC;
signal ser_in_counter_latchcount_6_MC_tsimcreated_xor_Q_492 : STD_LOGIC;
signal ser_in_counter_latchcount_6_MC_tsimcreated_prld_Q_493 : STD_LOGIC;
signal ser_in_counter_latchcount_6_MC_D1_494 : STD_LOGIC;
signal ser_in_counter_latchcount_6_MC_D2_495 : STD_LOGIC;
signal N_PZ_383_MC_Q_496 : STD_LOGIC;
signal N_PZ_383_MC_D_497 : STD_LOGIC;
signal N_PZ_383_MC_D1_498 : STD_LOGIC;
signal N_PZ_383_MC_D2_499 : STD_LOGIC;
signal N_PZ_383_MC_D2_PT_0_500 : STD_LOGIC;
signal N_PZ_383_MC_D2_PT_1_501 : STD_LOGIC;
signal panel_select_MC_Q_tsimrenamed_net_Q_502 : STD_LOGIC;
signal panel_select_MC_D_503 : STD_LOGIC;
signal panel_select_MC_D1_504 : STD_LOGIC;
signal panel_select_MC_D2_505 : STD_LOGIC;
signal panel_select_MC_D2_PT_0_506 : STD_LOGIC;
signal panel_select_MC_D2_PT_1_507 : STD_LOGIC;
signal panel_select_MC_D2_PT_2_508 : STD_LOGIC;
signal panel_select_MC_D2_PT_3_509 : STD_LOGIC;
signal panel_select_MC_D2_PT_4_510 : STD_LOGIC;
signal panel_select_MC_D2_PT_5_511 : STD_LOGIC;
signal panel_select_MC_D2_PT_6_512 : STD_LOGIC;
signal panel_select_MC_D2_PT_7_513 : STD_LOGIC;
signal panel_select_MC_D2_PT_8_514 : STD_LOGIC;
signal panel_select_MC_D2_PT_9_515 : STD_LOGIC;
signal panel_select_MC_D2_PT_10_516 : STD_LOGIC;
signal panel_select_MC_D2_PT_11_517 : STD_LOGIC;
signal panel_select_MC_D2_PT_12_518 : STD_LOGIC;
signal panel_select_MC_D2_PT_13_519 : STD_LOGIC;
signal panel_select_MC_D2_PT_14_520 : STD_LOGIC;
signal panel_select_MC_D2_PT_15_521 : STD_LOGIC;
signal panel_select_MC_D2_PT_16_522 : STD_LOGIC;
signal panel_select_MC_D2_PT_17_523 : STD_LOGIC;
signal panel_select_MC_D2_PT_18_524 : STD_LOGIC;
signal grayscale_clk_MC_Q_tsimrenamed_net_Q_525 : STD_LOGIC;
signal grayscale_clk_MC_D_526 : STD_LOGIC;
signal grayscale_clk_MC_D1_527 : STD_LOGIC;
signal grayscale_clk_MC_D2_528 : STD_LOGIC;
signal grclkgen_grclk_ctr_sig_529 : STD_LOGIC;
signal grayscale_clk_MC_D2_PT_0_530 : STD_LOGIC;
signal N_PZ_372_531 : STD_LOGIC;
signal grayscale_clk_MC_D2_PT_1_532 : STD_LOGIC;
signal grclkgen_proc_sclk_hlf_533 : STD_LOGIC;
signal grayscale_clk_MC_D2_PT_2_534 : STD_LOGIC;
signal grclkgen_grclk_ctr_sig_MC_Q : STD_LOGIC;
signal grclkgen_grclk_ctr_sig_MC_D_536 : STD_LOGIC;
signal grclkgen_grclk_ctr_sig_MC_tsimcreated_xor_Q_537 : STD_LOGIC;
signal FOOBAR6_ctinst_5_538 : STD_LOGIC;
signal grclkgen_grclk_ctr_sig_MC_tsimcreated_prld_Q_539 : STD_LOGIC;
signal grclkgen_grclk_ctr_sig_MC_D1_540 : STD_LOGIC;
signal grclkgen_grclk_ctr_sig_MC_D2_541 : STD_LOGIC;
signal N_PZ_371_542 : STD_LOGIC;
signal grclkgen_grclk_ctr_sig_MC_D2_PT_0_543 : STD_LOGIC;
signal grclkgen_grclk_ctr_sig_MC_D2_PT_1_544 : STD_LOGIC;
signal N_PZ_372_MC_Q_545 : STD_LOGIC;
signal N_PZ_372_MC_D_546 : STD_LOGIC;
signal N_PZ_372_MC_D1_547 : STD_LOGIC;
signal N_PZ_372_MC_D2_548 : STD_LOGIC;
signal N_PZ_371_MC_Q_549 : STD_LOGIC;
signal N_PZ_371_MC_D_550 : STD_LOGIC;
signal N_PZ_371_MC_D1_551 : STD_LOGIC;
signal N_PZ_371_MC_D2_552 : STD_LOGIC;
signal N_PZ_371_MC_D2_PT_0_553 : STD_LOGIC;
signal grclkgen_sync_proc_sclk_554 : STD_LOGIC;
signal N_PZ_371_MC_D2_PT_1_555 : STD_LOGIC;
signal grclkgen_sync_proc_sclk_MC_Q : STD_LOGIC;
signal grclkgen_sync_proc_sclk_MC_tsimcreated_prld_Q_557 : STD_LOGIC;
signal grclkgen_sync_proc_sclk_MC_D_558 : STD_LOGIC;
signal grclkgen_sync_proc_sclk_MC_D1_559 : STD_LOGIC;
signal grclkgen_sync_proc_sclk_MC_D2_560 : STD_LOGIC;
signal grclkgen_pulser_curState_FSM_FFd1_561 : STD_LOGIC;
signal grclkgen_pulser_curState_FSM_FFd1_MC_Q : STD_LOGIC;
signal grclkgen_pulser_curState_FSM_FFd1_MC_tsimcreated_prld_Q_563 : STD_LOGIC;
signal grclkgen_pulser_curState_FSM_FFd1_MC_D_564 : STD_LOGIC;
signal grclkgen_pulser_curState_FSM_FFd1_MC_D1_565 : STD_LOGIC;
signal grclkgen_pulser_curState_FSM_FFd1_MC_D2_566 : STD_LOGIC;
signal grclkgen_pulser_curState_FSM_FFd1_MC_D2_PT_0_567 : STD_LOGIC;
signal grclkgen_pulser_curState_FSM_FFd1_MC_D2_PT_1_568 : STD_LOGIC;
signal N_PZ_794_MC_Q_569 : STD_LOGIC;
signal N_PZ_794_570 : STD_LOGIC;
signal N_PZ_794_MC_D_571 : STD_LOGIC;
signal N_PZ_794_MC_D1_572 : STD_LOGIC;
signal N_PZ_794_MC_D2_573 : STD_LOGIC;
signal N_PZ_794_MC_D2_PT_0_574 : STD_LOGIC;
signal N_PZ_794_MC_D2_PT_1_575 : STD_LOGIC;
signal grclkgen_proc_sclk_hlf_MC_Q : STD_LOGIC;
signal grclkgen_proc_sclk_hlf_MC_tsimcreated_prld_Q_577 : STD_LOGIC;
signal grclkgen_proc_sclk_hlf_MC_D_578 : STD_LOGIC;
signal grclkgen_proc_sclk_hlf_MC_D1_579 : STD_LOGIC;
signal grclkgen_proc_sclk_hlf_MC_D2_580 : STD_LOGIC;
signal grclkgen_proc_sclk_hlf_MC_D2_PT_0_581 : STD_LOGIC;
signal grclkgen_proc_sclk_hlf_MC_D2_PT_1_582 : STD_LOGIC;
signal latch_out1_MC_Q_tsimrenamed_net_Q_583 : STD_LOGIC;
signal latch_out1_MC_D_584 : STD_LOGIC;
signal latch_out1_MC_D1_585 : STD_LOGIC;
signal latch_out1_MC_D2_586 : STD_LOGIC;
signal latch_out1_MC_D2_PT_0_587 : STD_LOGIC;
signal latch_out1_MC_D2_PT_1_588 : STD_LOGIC;
signal latch_out1_MC_D2_PT_2_589 : STD_LOGIC;
signal latch_out2_MC_Q_tsimrenamed_net_Q_590 : STD_LOGIC;
signal latch_out2_MC_D_591 : STD_LOGIC;
signal latch_out2_MC_D1_592 : STD_LOGIC;
signal latch_out2_MC_D2_593 : STD_LOGIC;
signal latch_out2_MC_D2_PT_0_594 : STD_LOGIC;
signal latch_out2_MC_D2_PT_1_595 : STD_LOGIC;
signal line_select_0_MC_Q_tsimrenamed_net_Q_596 : STD_LOGIC;
signal line_select_0_MC_D_597 : STD_LOGIC;
signal line_select_0_MC_D1_598 : STD_LOGIC;
signal line_select_0_MC_D2_599 : STD_LOGIC;
signal grclkgen_ctr_line_en_603 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_0_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_0_MC_D_605 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_0_MC_tsimcreated_xor_Q_606 : STD_LOGIC;
signal FOOBAR5_ctinst_6_607 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_0_MC_D1_608 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_0_MC_D2_609 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_0_MC_D2_PT_0_618 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_0_MC_D2_PT_1_619 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_D_621 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_tsimcreated_xor_Q_622 : STD_LOGIC;
signal FOOBAR5_ctinst_5_623 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_tsimcreated_prld_Q_624 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_D1_625 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_D2_626 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_D2_PT_0_627 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_D2_PT_1_628 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_D2_PT_2_629 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_D2_PT_3_630 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_D2_PT_4_631 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_0_MC_D2_PT_5_632 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_1_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_1_MC_D_634 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_1_MC_tsimcreated_xor_Q_635 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_1_MC_tsimcreated_prld_Q_636 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_1_MC_D1_637 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_1_MC_D2_638 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_1_MC_D2_PT_0_639 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_1_MC_D2_PT_1_640 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_2_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_2_MC_D_642 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_2_MC_tsimcreated_xor_Q_643 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_2_MC_tsimcreated_prld_Q_644 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_2_MC_D1_645 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_2_MC_D2_646 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_2_MC_D2_PT_0_647 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_2_MC_D2_PT_1_648 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_3_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_3_MC_D_650 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_3_MC_tsimcreated_xor_Q_651 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_3_MC_tsimcreated_prld_Q_652 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_3_MC_D1_653 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_3_MC_D2_654 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_3_MC_D2_PT_0_655 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_3_MC_D2_PT_1_656 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_4_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_4_MC_D_658 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_4_MC_tsimcreated_xor_Q_659 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_4_MC_tsimcreated_prld_Q_660 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_4_MC_D1_661 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_4_MC_D2_662 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_4_MC_D2_PT_0_663 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_4_MC_D2_PT_1_664 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_5_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_5_MC_D_666 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_5_MC_tsimcreated_xor_Q_667 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_5_MC_tsimcreated_prld_Q_668 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_5_MC_D1_669 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_5_MC_D2_670 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_5_MC_D2_PT_0_671 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_5_MC_D2_PT_1_672 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_6_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_6_MC_D_674 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_6_MC_tsimcreated_xor_Q_675 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_6_MC_tsimcreated_prld_Q_676 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_6_MC_D1_677 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_6_MC_D2_678 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_6_MC_D2_PT_0_679 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_6_MC_D2_PT_1_680 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_7_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_7_MC_D_682 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_7_MC_tsimcreated_xor_Q_683 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_7_MC_D1_684 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_7_MC_D2_685 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_7_MC_D2_PT_0_686 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_7_MC_D2_PT_1_687 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_7_MC_D2_PT_2_688 : STD_LOGIC;
signal grclkgen_ctr_cnt_gclk_7_MC_D2_PT_3_689 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_1_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_1_MC_D_691 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_1_MC_tsimcreated_xor_Q_692 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_1_MC_D1_693 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_1_MC_D2_694 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_1_MC_D2_PT_0_695 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_1_MC_D2_PT_1_696 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_2_MC_Q : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_2_MC_D_698 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_2_MC_tsimcreated_xor_Q_699 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_2_MC_D1_700 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_2_MC_D2_701 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_2_MC_D2_PT_0_702 : STD_LOGIC;
signal grclkgen_ctr_cnt_lines_2_MC_D2_PT_1_703 : STD_LOGIC;
signal grclkgen_ctr_line_en_MC_Q : STD_LOGIC;
signal grclkgen_ctr_line_en_MC_D_705 : STD_LOGIC;
signal grclkgen_ctr_line_en_MC_tsimcreated_xor_Q_706 : STD_LOGIC;
signal grclkgen_ctr_line_en_MC_tsimcreated_prld_Q_707 : STD_LOGIC;
signal grclkgen_ctr_line_en_MC_D1_708 : STD_LOGIC;
signal grclkgen_ctr_line_en_MC_D2_709 : STD_LOGIC;
signal grclkgen_ctr_line_en_MC_D2_PT_0_710 : STD_LOGIC;
signal grclkgen_ctr_line_en_MC_D2_PT_1_711 : STD_LOGIC;
signal line_select_1_MC_Q_tsimrenamed_net_Q_712 : STD_LOGIC;
signal line_select_1_MC_D_713 : STD_LOGIC;
signal line_select_1_MC_D1_714 : STD_LOGIC;
signal line_select_1_MC_D2_715 : STD_LOGIC;
signal line_select_2_MC_Q_tsimrenamed_net_Q_716 : STD_LOGIC;
signal line_select_2_MC_D_717 : STD_LOGIC;
signal line_select_2_MC_D1_718 : STD_LOGIC;
signal line_select_2_MC_D2_719 : STD_LOGIC;
signal line_select_3_MC_Q_tsimrenamed_net_Q_720 : STD_LOGIC;
signal line_select_3_MC_D_721 : STD_LOGIC;
signal line_select_3_MC_D1_722 : STD_LOGIC;
signal line_select_3_MC_D2_723 : STD_LOGIC;
signal line_select_4_MC_Q_tsimrenamed_net_Q_724 : STD_LOGIC;
signal line_select_4_MC_D_725 : STD_LOGIC;
signal line_select_4_MC_D1_726 : STD_LOGIC;
signal line_select_4_MC_D2_727 : STD_LOGIC;
signal line_select_5_MC_Q_tsimrenamed_net_Q_728 : STD_LOGIC;
signal line_select_5_MC_D_729 : STD_LOGIC;
signal line_select_5_MC_D1_730 : STD_LOGIC;
signal line_select_5_MC_D2_731 : STD_LOGIC;
signal line_select_6_MC_Q_tsimrenamed_net_Q_732 : STD_LOGIC;
signal line_select_6_MC_D_733 : STD_LOGIC;
signal line_select_6_MC_D1_734 : STD_LOGIC;
signal line_select_6_MC_D2_735 : STD_LOGIC;
signal line_select_7_MC_Q_tsimrenamed_net_Q_736 : STD_LOGIC;
signal line_select_7_MC_D_737 : STD_LOGIC;
signal line_select_7_MC_D1_738 : STD_LOGIC;
signal line_select_7_MC_D2_739 : STD_LOGIC;
signal mosi_a_MC_Q_tsimrenamed_net_Q_740 : STD_LOGIC;
signal mosi_a_MC_D_741 : STD_LOGIC;
signal mosi_a_MC_D1_742 : STD_LOGIC;
signal mosi_a_MC_D2_743 : STD_LOGIC;
signal serinf_flipflop_a_744 : STD_LOGIC;
signal mosi_a_MC_D2_PT_0_745 : STD_LOGIC;
signal mosi_a_MC_D2_PT_1_746 : STD_LOGIC;
signal serinf_flipflop_a_MC_Q : STD_LOGIC;
signal serinf_flipflop_a_MC_RSTF_748 : STD_LOGIC;
signal serinf_flipflop_a_MC_tsimcreated_prld_Q_749 : STD_LOGIC;
signal serinf_flipflop_a_MC_D_750 : STD_LOGIC;
signal serinf_flipflop_a_MC_D1_751 : STD_LOGIC;
signal serinf_flipflop_a_MC_D2_752 : STD_LOGIC;
signal serinf_flipflop_a_MC_D2_PT_0_753 : STD_LOGIC;
signal serinf_flipflop_a_MC_D2_PT_1_754 : STD_LOGIC;
signal serinf_flipflop_a_MC_D2_PT_2_755 : STD_LOGIC;
signal mosi_b_MC_Q_tsimrenamed_net_Q_756 : STD_LOGIC;
signal mosi_b_MC_D_757 : STD_LOGIC;
signal mosi_b_MC_D1_758 : STD_LOGIC;
signal mosi_b_MC_D2_759 : STD_LOGIC;
signal serinf_flipflop_b_760 : STD_LOGIC;
signal mosi_b_MC_D2_PT_0_761 : STD_LOGIC;
signal mosi_b_MC_D2_PT_1_762 : STD_LOGIC;
signal serinf_flipflop_b_MC_Q : STD_LOGIC;
signal serinf_flipflop_b_MC_RSTF_764 : STD_LOGIC;
signal serinf_flipflop_b_MC_tsimcreated_prld_Q_765 : STD_LOGIC;
signal serinf_flipflop_b_MC_D_766 : STD_LOGIC;
signal serinf_flipflop_b_MC_D1_767 : STD_LOGIC;
signal serinf_flipflop_b_MC_D2_768 : STD_LOGIC;
signal serinf_flipflop_b_MC_D2_PT_0_769 : STD_LOGIC;
signal serinf_flipflop_b_MC_D2_PT_1_770 : STD_LOGIC;
signal serinf_flipflop_b_MC_D2_PT_2_771 : STD_LOGIC;
signal reset_MC_Q_tsimrenamed_net_Q_772 : STD_LOGIC;
signal reset_MC_D_773 : STD_LOGIC;
signal reset_MC_D1_774 : STD_LOGIC;
signal reset_MC_D2_775 : STD_LOGIC;
signal sdout_MC_Q_tsimrenamed_net_Q_776 : STD_LOGIC;
signal sdout_MC_D_777 : STD_LOGIC;
signal sdout_MC_D1_778 : STD_LOGIC;
signal sdout_MC_D2_779 : STD_LOGIC;
signal sdout_MC_D2_PT_0_780 : STD_LOGIC;
signal sdout_MC_D2_PT_1_781 : STD_LOGIC;
signal sdprev_en_MC_UIM_782 : STD_LOGIC;
signal sdout_MC_D2_PT_2_783 : STD_LOGIC;
signal sdprev_en_MC_Q_tsimrenamed_net_Q_784 : STD_LOGIC;
signal sdprev_en_MC_D_785 : STD_LOGIC;
signal sdprev_en_MC_D1_786 : STD_LOGIC;
signal sdprev_en_MC_D2_787 : STD_LOGIC;
signal tsclk_a_MC_Q_tsimrenamed_net_Q_788 : STD_LOGIC;
signal tsclk_a_MC_D_789 : STD_LOGIC;
signal tsclk_a_MC_D1_790 : STD_LOGIC;
signal tsclk_a_MC_D2_791 : STD_LOGIC;
signal tsclk_a_MC_D2_PT_0_792 : STD_LOGIC;
signal serinf_ff_a_en_793 : STD_LOGIC;
signal tsclk_a_MC_D2_PT_1_794 : STD_LOGIC;
signal serinf_ff_a_en_MC_Q : STD_LOGIC;
signal serinf_ff_a_en_MC_RSTF_796 : STD_LOGIC;
signal serinf_ff_a_en_MC_tsimcreated_prld_Q_797 : STD_LOGIC;
signal serinf_ff_a_en_MC_D_798 : STD_LOGIC;
signal serinf_ff_a_en_MC_D1_799 : STD_LOGIC;
signal serinf_ff_a_en_MC_D2_800 : STD_LOGIC;
signal serinf_ff_a_en_MC_D2_PT_0_801 : STD_LOGIC;
signal serinf_ff_a_en_MC_D2_PT_1_802 : STD_LOGIC;
signal serinf_ff_a_en_MC_D2_PT_2_803 : STD_LOGIC;
signal tsclk_b_MC_Q_tsimrenamed_net_Q_804 : STD_LOGIC;
signal tsclk_b_MC_D_805 : STD_LOGIC;
signal tsclk_b_MC_D1_806 : STD_LOGIC;
signal tsclk_b_MC_D2_807 : STD_LOGIC;
signal tsclk_b_MC_D2_PT_0_808 : STD_LOGIC;
signal serinf_ff_b_en_809 : STD_LOGIC;
signal tsclk_b_MC_D2_PT_1_810 : STD_LOGIC;
signal serinf_ff_b_en_MC_Q : STD_LOGIC;
signal serinf_ff_b_en_MC_RSTF_812 : STD_LOGIC;
signal serinf_ff_b_en_MC_tsimcreated_prld_Q_813 : STD_LOGIC;
signal serinf_ff_b_en_MC_D_814 : STD_LOGIC;
signal serinf_ff_b_en_MC_D1_815 : STD_LOGIC;
signal serinf_ff_b_en_MC_D2_816 : STD_LOGIC;
signal serinf_ff_b_en_MC_D2_PT_0_817 : STD_LOGIC;
signal serinf_ff_b_en_MC_D2_PT_1_818 : STD_LOGIC;
signal serinf_ff_b_en_MC_D2_PT_2_819 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_0_MC_tsimcreated_prld_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_0_MC_tsimcreated_prld_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_0_MC_REG_IN : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_0_MC_REG_CLK : STD_LOGIC;
signal NlwBufferSignal_done_MC_tsimcreated_xor_IN0 : STD_LOGIC;
signal NlwBufferSignal_done_MC_tsimcreated_xor_IN1 : STD_LOGIC;
signal NlwBufferSignal_done_MC_REG_IN : STD_LOGIC;
signal NlwBufferSignal_done_MC_REG_CLK : STD_LOGIC;
signal NlwBufferSignal_done_MC_D_IN0 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D_IN1 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN0 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN1 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN2 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN3 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN4 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN5 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN6 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN7 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN8 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN9 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN10 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN11 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN12 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN13 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN14 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN15 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN16 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN17 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN18 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN19 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN20 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN21 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN22 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN23 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN24 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN25 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN26 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN27 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN28 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN29 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN30 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_0_IN31 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN0 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN1 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN2 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN3 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN4 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN5 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN6 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN7 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN8 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN9 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN10 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN11 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN12 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN13 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN14 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN15 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN16 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN17 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN18 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN19 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN20 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN21 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN22 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN23 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN24 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN25 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN26 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN27 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN28 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN29 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN30 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_1_IN31 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN0 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN1 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN2 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN3 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN4 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN5 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN6 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN7 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN8 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN9 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN10 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN11 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN12 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN13 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN14 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN15 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN16 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN17 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN18 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN19 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN20 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN21 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN22 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN23 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN24 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN25 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN26 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN27 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN28 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN29 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN30 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_PT_2_IN31 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_IN0 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_IN1 : STD_LOGIC;
signal NlwBufferSignal_done_MC_D2_IN2 : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_tsimcreated_prld_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_tsimcreated_prld_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_REG_IN : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_REG_CLK : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_D_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_D_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_D2_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_D2_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_RSTF_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_RSTF_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_CE_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_2_MC_CE_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_tsimcreated_prld_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_tsimcreated_prld_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_REG_IN : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_REG_CLK : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_D_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_D_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_D2_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_D2_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_RSTF_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_RSTF_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_CE_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_1_MC_CE_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_tsimcreated_prld_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_tsimcreated_prld_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_REG_IN : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_REG_CLK : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_D_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_D_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_D2_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_D2_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_RSTF_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_RSTF_IN1 : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_CE_IN0 : STD_LOGIC;
signal NlwBufferSignal_mode_data_0_MC_CE_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_3_MC_tsimcreated_prld_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_3_MC_tsimcreated_prld_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_3_MC_REG_IN : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_3_MC_REG_CLK : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_3_MC_D_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_3_MC_D_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_3_MC_D2_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_3_MC_D2_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_3_MC_CE_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_3_MC_CE_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_2_MC_tsimcreated_prld_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_2_MC_tsimcreated_prld_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_2_MC_REG_IN : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_2_MC_REG_CLK : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_2_MC_D_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_2_MC_D_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_2_MC_D2_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_2_MC_D2_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_2_MC_CE_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_2_MC_CE_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_1_MC_tsimcreated_prld_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_1_MC_tsimcreated_prld_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_1_MC_REG_IN : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_1_MC_REG_CLK : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_1_MC_D_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_1_MC_D_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_1_MC_D2_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_1_MC_D2_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_1_MC_CE_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_1_MC_CE_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_0_MC_CE_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_serial_dout_0_MC_CE_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_tsimcreated_xor_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_tsimcreated_xor_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_tsimcreated_prld_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_tsimcreated_prld_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_REG_IN : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_REG_CLK : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_D_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_D_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_D2_PT_0_IN0 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_D2_PT_0_IN1 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_D2_PT_0_IN2 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_D2_PT_0_IN3 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_D2_PT_0_IN4 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_D2_PT_0_IN5 : STD_LOGIC;
signal NlwBufferSignal_ser_in_counter_STATE_FSM_FFd1_MC_D2_PT_0_IN6 : STD_LOGIC;