Ensure translation stage always outputs ISA circuits
#13792
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jakelishman
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Changelog: Deprecation
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Pull Request Test Coverage Report for Build 13168271554Warning: This coverage report may be inaccurate.This pull request's base commit is no longer the HEAD commit of its target branch. This means it includes changes from outside the original pull request, including, potentially, unrelated coverage changes.
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This shifts the responsibility of the `translation` stage slightly to always output ISA circuits. It previously was not 100% required that they did this, at least implicitly because Qiskit's built-in plugins didn't always respect 2q direction. The builtin translation plugins now always respect 2q direction, which removes the need for the `pre_optimization` implicit stage, freeing it up for better user customisation. This (in theory) shouldn't have runtime impacts because the optimisation loop was already having to do this afterwards anyway. For potential plugins that _do_ respect gate direction (like the upcoming `BasisConstructor`), it can be a speedup in the default pipeline, since they won't need to run the gate-direction check any more.
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Summary
This shifts the responsibility of the
translationstage slightly to always output ISA circuits. It previously was not 100% required that they did this, at least implicitly because Qiskit's built-in plugins didn't always respect 2q direction.The builtin translation plugins now always respect 2q direction, which removes the need for the
pre_optimizationimplicit stage, freeing it up for better user customisation.This (in theory) shouldn't have runtime impacts because the optimisation loop was already having to do this afterwards anyway. For potential plugins that do respect gate direction (like the upcoming
BasisConstructor), it can be a speedup in the default pipeline, since they won't need to run the gate-direction check any more.Details and comments
Built on top of #13620, since it will need to change documentation in that PR.
Fix #13787.