diff --git a/FlashPro_Express_Projects/Programming_Files/BaseDesign_RTG4_Dev_Kit_AHB_ProgramFile.job b/FlashPro_Express_Projects/Programming_Files/BaseDesign_RTG4_Dev_Kit_AHB_ProgramFile.job
deleted file mode 100644
index 9cf32fa..0000000
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diff --git a/FlashPro_Express_Projects/Programming_Files/BaseDesign_RTG4_Dev_Kit_AXI_ProgramFile.job b/FlashPro_Express_Projects/Programming_Files/BaseDesign_RTG4_Dev_Kit_AXI_ProgramFile.job
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diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_MiV_RV32IMAF_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_MiV_RV32IMAF_CFG1_BaseDesign.job
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diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_MiV_RV32IMA_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_MiV_RV32IMA_CFG2_BaseDesign.job
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diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_MiV_RV32_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_MiV_RV32_CFG1_BaseDesign.job
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diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_MiV_RV32_CFG3_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_MiV_RV32_CFG3_BaseDesign.job
new file mode 100644
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diff --git a/FlashPro_Express_Projects/README.MD b/FlashPro_Express_Projects/README.MD
index 597a237..193b874 100644
--- a/FlashPro_Express_Projects/README.MD
+++ b/FlashPro_Express_Projects/README.MD
@@ -1,6 +1,6 @@
 # RTG4 Development Kit FPGA Programming Files
 
-This folder contains FlashPro Express **(v12.3)** projects for the RTG4 Development Kit Mi-V sample designs.
+This folder contains FlashPro Express v12.6 projects for the RTG4 Development Kit Mi-V sample designs.
 
 ## FlashPro Express
 The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express.
@@ -21,11 +21,11 @@ The programming files contained under this folder were exported from the designs
 
 ## Design Features
 The Libero designs include the following features:
-* A MIV_RV32IMA_L1_AHB or MIV_RV32IMA_L1_AXI soft RISC-V processor.
-* RISC-V debug block allowing on-target debug using SoftConsole.
-* The operating frequency of the design is 50MHz.
-* Target memory is LSRAM.
-* User peripherals (GPIO, Timers, UART).
+* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
+* A RISC-V debug block allowing on-target debug using SoftConsole
+* The operating frequency of the design is 50MHz
+* Target memory is SRAM (32kB)
+* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)
 
 The peripherals in this design are located at the following addresses.
 
@@ -36,4 +36,4 @@ The peripherals in this design are located at the following addresses.
 | CoreTimer_0   | 0x7000_3000   |
 | CoreTimer_1   | 0x7000_4000   |
 | CoreGPIO_OUT  | 0x7000_5000   |
-| LSRAM| 0x8000_0000|
+| SRAM| 0x8000_0000|
\ No newline at end of file
diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md
index eaf700e..e05897c 100644
--- a/Libero_Projects/README.md
+++ b/Libero_Projects/README.md
@@ -1,15 +1,39 @@
 # RTG4 Development Kit Mi-V Sample FPGA Designs
-This folder contains Tcl scripts that build Libero SoC (**v12.3**) design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs.
+This folder contains Tcl scripts that build Libero SoC v12.6 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
+
+#### RTG4_Dev_Kit_MiV_RV32IMA_BaseDesign
+
+| Config  | Description |
+| :------:|:------------|
+| CFG1    |This design uses the MiV_RV32IMA_L1_AHB core with an **AHB** interface for memory and peripherals|
+| CFG2    |This design uses the MiV_RV32IMA_L1_AXI core with an **AXI3** interface for memory and peripherals|
+
+
+#### RTG4_Dev_Kit_MiV_RV32IMAF_BaseDesign
+
+| Config  |Description |
+| :------:|:-----------|
+| CFG1    |  This design uses the MiV_RV32IMAF_L1_AHB core with an **AHB** interface for memory and peripherals|
+
+
+#### RTG4_Dev_Kit_MiV_RV32_BaseDesign
 
-## <a name="quick"></a> Instructions
 
+| Config  | Description|
+| :------:|:----------------------------------------|
+| CFG1    | This design uses the MiV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IMC</li><li>Multiplier: MACC (Pipelined)</li><li>Interfaces: AHB Master (mirrored), APB3 Master</li><li>Internal IRQs: 6</li><li>TCM: Enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled</li></ul>|
+| CFG2    | **Not available in this release**<ul> *This design uses the MiV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IM</li><li>Multiplier: Fabric</li><li>Interfaces: AXI4 Master (mirrored), APB3 Master</li><li>Internal IRQs: 6</li><li>TCM: Disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled* </li></ul>|
+| CFG3    | This design uses the MiV_RV32 core configured as follows: <ul><li>RISC-V Extensions: I</li><li>Multiplier: none</li><li>Interfaces: APB3 Master</li><li>Internal IRQs: 6</li><li>TCM: Enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled</li></ul>|
+
+
+## <a name="quick"></a> Instructions
 
 #### Running Libero SoC in GUI mode
     1. Open Libero SoC
     2. Execute the script, Project -> Execute Script
     3. Select the directory that the script is located in using the "..."
     4. Select the script and select "Open"
-    5. In the arguments text box, enter "AHB"
+    5. In the arguments text box, enter the type of configuration you want e.g. "CFG1"
     6. Select the "Run" button to execute the script
     7. Once complete, a script report will be generated.
 
@@ -17,41 +41,41 @@ Libero executes the script and opens the Mi-V sample project. The script adds Ti
 
 #### Running Libero SoC in GUI mode, with Script Arguments
     1. Open Libero SoC
-    2. Execute the script, Project -> Execute Script
+    2. Execute the selected script, Project -> Execute Script
     3. Select the directory that the script is located in, using the "..."
     4. Select the script and select "Open"
-    5. In the arguments text box, enter "AHB SYNTHESIZE"
+    5. In the arguments text box, enter "CFG1 SYNTHESIZE"
     6. Select the "Run" button to execute the script
     7. Once complete, a script report will be generated.
 
-In this example, the arguments "AHB SYNTHESIZE" are entered to take the project through to Synthesis.
+In this example, the arguments "CFG1 SYNTHESIZE" are entered to take the project through to Synthesis.
 
 Libero executes the script and opens the Mi-V sample project. The script adds Timing constraints to the project for Synthesis, Place and Route, and Timing Verification. Additionally, IO Constraints are added to the project for Place and Route. The project can now be taken through the remainder of the Libero SoC design flow.
 
 ## <a name="Script arguments"></a> Script Arguments
-In the examples above the arguments "AHB" and "AHB SYNTHESIZE" were entered. The complete set of script arguments are documented here.
+In the examples above the arguments "CFG1" and "CFG1 SYNTHESIZE" were entered. The complete set of script arguments are documented here.
 
-First argument:
-| Argument    |  Description   |
-| ------------- |:-------------:|
-| AHB      | Generate a sample design with the MiV_RV32IMA_L1_AHB |
-| AXI      | Generate a sample design with the MiV_RV32IMA_L1_AXI |
+#### First argument:
+| Argument                  |  Description   |
+| ------------------------- |:---------------|
+| CFG1..CFGn                | Generate a sample design for the selected configuration  |
 
-Second argument:
-| Argument    |  Description   |
-| ------------- |:-------------:|
-| SYNTHESIZE | Run synthesis on the design  |
-| PLACE_AND_ROUTE | Run place and route on the design  |
-| GENERATE_BITSTREAM | Generate the bitstream for the design|
-| EXPORT_PROGRAMMING_FILE | Export the programming file (.job) |
+
+#### Second argument:
+| Argument                  |  Description   |
+| ------------------------- |:---------------|
+| SYNTHESIZE                | Run synthesis on the design  |
+| PLACE_AND_ROUTE           | Run place and route on the design  |
+| GENERATE_BITSTREAM        | Generate the bitstream for the design|
+| EXPORT_PROGRAMMING_FILE   | Export the programming file (.job) |
 
 ## Design Features
 The Libero designs include the following features:
-* A MIV_RV32IMA_L1_AHB or MIV_RV32IMA_L1_AXI soft RISC-V processor.
-* RISC-V debug block allowing on-target debug using SoftConsole.
-* The operating frequency of the design is 50MHz.
-* Target memory is LSRAM.
-* User peripherals (GPIO, Timers, UART).
+* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
+* A RISC-V debug block allowing on-target debug using SoftConsole
+* The operating frequency of the design is 50MHz
+* Target memory is SRAM (32kB)
+* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)
 
 The peripherals in this design are located at the following addresses.
 
@@ -62,4 +86,5 @@ The peripherals in this design are located at the following addresses.
 | CoreTimer_0   | 0x7000_3000   |
 | CoreTimer_1   | 0x7000_4000   |
 | CoreGPIO_OUT  | 0x7000_5000   |
-| LSRAM| 0x8000_0000|
+| SRAM| 0x8000_0000|
+
diff --git a/Libero_Projects/RTG4_DEV_KIT.tcl b/Libero_Projects/RTG4_DEV_KIT.tcl
deleted file mode 100644
index 15ac1da..0000000
--- a/Libero_Projects/RTG4_DEV_KIT.tcl
+++ /dev/null
@@ -1,193 +0,0 @@
-set project_folder_name_axi MiV_AXI_BD
-set project_dir_axi "./$project_folder_name_axi"
-set Libero_project_name_axi RTG4_Dev_Kit_MiV_AXI_BaseDesign
-
-set project_folder_name_ahb MiV_AHB_BD
-set project_dir_ahb "./$project_folder_name_ahb"
-set Libero_project_name_ahb RTG4_Dev_Kit_MiV_AHB_BaseDesign
-
-set target [string toupper [lindex $argv 0]]
-set design_flow_stage [string toupper [lindex $argv 1]]
-
-
-proc create_new_project_label_axi { }\
-{
-   puts "-----------------------------------------------------------------------------------------------"
-   puts "-----------------------------------------------------------------------------------------------"
-   puts "---------------------------Creating New Project------------------------------------"
-   puts "------------RTG4_Dev_Kit_MiV_AXI_BaseDesign--------------------------"
-   puts "-----------------------------------------------------------------------------------------------"
-   puts "-----------------------------------------------------------------------------------------------"
-}
-
-proc create_new_project_label_ahb { }\
-{
-   puts "-----------------------------------------------------------------------------------------------"
-   puts "-----------------------------------------------------------------------------------------------"
-   puts "---------------------------Creating New Project------------------------------------"
-   puts "------------RTG4_Dev_Kit_MiV_AHB_BaseDesign------------------------"
-   puts "-----------------------------------------------------------------------------------------------"
-   puts "-----------------------------------------------------------------------------------------------"
-}
-
-proc project_exists { }\
-{
-   puts "-----------------------------------------------------------------------------------------------"
-   puts "----------------------------------------Error-----------------------------------------------"
-   puts "-----------------------------------------------------------------------------------------------"
-   puts "Project already exists in folder. Please rename or remove and rerun script."
-   puts "-----------------------------------------------------------------------------------------------"
-}
-
-proc invalid_argument { }\
-{
-   puts "-----------------------------------------------------------------------------------------------"
-   puts "----------------------Wrong Argument Entered ---------------------------------"
-   puts "-----------------------------------------------------------------------------------------------"
-   puts "Make sure you put AHB or AXI argument in front of the Design Flow argument."
-   puts "-----------------------------------------------------------------------------------------------"
-}
-
-proc  base_design_built {}\
-{
-  puts "-----------------------------------------------------------------------------------------------"
-  puts "------------------------------BaseDesign Built---------------------------------------"
-  puts "-----------------------------------------------------------------------------------------------"
-}
-
-if {"$target" == "AHB"} then {
-	if {[file exists $project_dir_ahb] == 1} then {
-		project_exists
-	} else {
-		create_new_project_label_ahb
-		new_project -location  $project_dir_ahb -name $Libero_project_name_ahb -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
-		import_files -convert_EDN_to_HDL 0 -hdl_source {./import/hdl/reset_synchronizer.v}
-		build_design_hierarchy
-		set_root reset_synchronizer
-		source ./import/components/AHB/import_component_and_constraints_rtg4_dev_kit_ahb.tcl
-		save_project
-        base_design_built
-	}
-} elseif {"$target" == "AXI"} then {
-	if {[file exists $project_dir_axi] == 1} then {
-		project_exists
-	} else {
-		create_new_project_label_axi
-		new_project -location  $project_dir_axi -name $Libero_project_name_axi -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
-		import_files -convert_EDN_to_HDL 0 -hdl_source {./import/hdl/reset_synchronizer.v}
-		build_design_hierarchy
-		set_root reset_synchronizer
-		source ./import/components/AXI/import_component_and_constraints_rtg4_dev_kit_axi.tcl
-		save_project
-        base_design_built
-	}
-} elseif {"$target" == "SYNTHESIZE"} then {
-		invalid_argument
-} elseif {"$target" == "PLACE_AND_ROUTE"} then {
-		invalid_argument
-} elseif {"$target" == "GENERATE_BITSTREAM"} then {
-		invalid_argument
-} elseif {"$target" == "EXPORT_PROGRAMMING_FILE"} then {
-		invalid_argument
-} else {
-	if {[file exists $project_dir_ahb] == 1} then {
-		project_exists
-	} else {
-		create_new_project_label_ahb
-		new_project -location  $project_dir_ahb -name $Libero_project_name_ahb -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
-		import_files -convert_EDN_to_HDL 0 -hdl_source {./import/hdl/reset_synchronizer.v}
-		build_design_hierarchy
-		set_root reset_synchronizer
-		source ./import/components/AHB/import_component_and_constraints_rtg4_dev_kit_ahb.tcl
-		save_project
-        base_design_built
-	}
-}
-
-if {"$design_flow_stage" == "SYNTHESIZE"} then {
-    puts "-----------------------------------------------------------------------------------------------"
-    puts "-------------------------Begin Synthesis---------------------------------------------"
-    puts "-----------------------------------------------------------------------------------------------"
-
-    # Configuring Place_and_Route tool for a timing pass.
-    configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:4} -params {RANDOM_SEED:8988747}
-
-    run_tool -name {SYNTHESIZE}
-    save_project
-
-    puts "-----------------------------------------------------------------------------------------------"
-    puts "---------------------------Synthesis Complete-------------------------------------"
-    puts "-----------------------------------------------------------------------------------------------"
-
-} elseif {"$design_flow_stage" == "PLACE_AND_ROUTE"} then {
-
-    puts "-----------------------------------------------------------------------------------------------"
-    puts "----------------------Begin Place and Route--------------------------------------"
-    puts "-----------------------------------------------------------------------------------------------"
-
-	# Configuring Place_and_Route tool for a timing pass.
-	configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:4} -params {RANDOM_SEED:8988747}
-
-	run_tool -name {PLACEROUTE}
-	save_project
-
-    puts "-----------------------------------------------------------------------------------------------"
-    puts "----------------------Place and Route Complete--------------------------------"
-    puts "-----------------------------------------------------------------------------------------------"
-
-} elseif {"$design_flow_stage" == "GENERATE_BITSTREAM"} then {
-
-    puts "-----------------------------------------------------------------------------------------------"
-    puts "----------------------------Generating Bitstream----------------------------------"
-    puts "-----------------------------------------------------------------------------------------------"
-
-    # Configuring Place_and_Route tool for a timing pass.
-	configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:4} -params {RANDOM_SEED:8988747}
-
-    run_tool -name {GENERATEPROGRAMMINGDATA}
-    run_tool -name {GENERATEPROGRAMMINGFILE}
-    save_project
-
-    puts "-----------------------------------------------------------------------------------------------"
-    puts "-------------------------------Bitstream Generated---------------------------------"
-    puts "-----------------------------------------------------------------------------------------------"
-
-} elseif {"$design_flow_stage" == "EXPORT_PROGRAMMING_FILE"} then {
-
-    puts "-----------------------------------------------------------------------------------------------"
-    puts "----------------------Exporting Programming Files----------------------------"
-    puts "-----------------------------------------------------------------------------------------------"
-
-    # Configuring Place_and_Route tool for a timing pass.
-    configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:4} -params {RANDOM_SEED:8988747}
-
-    # pre-requisite to enable exporting programming file function
-    run_tool -name {GENERATEPROGRAMMINGDATA}
-    run_tool -name {GENERATEPROGRAMMINGFILE}
-
-	if {"$target" == "AHB"} then {
-          export_prog_job \
-         -job_file_name {RTG4_Dev_Kit_MiV_AHB_BaseDesign} \
-         -export_dir {./MiV_AHB_BD/designer/BaseDesign/export} \
-         -force_rtg4_otp 0 \
-         -design_bitstream_format {PPD} 
-		save_project
-
-	} else {
-          export_prog_job \
-         -job_file_name {RTG4_Dev_Kit_MiV_AXI_BaseDesign} \
-         -export_dir {./MiV_AXI_BD/designer/BaseDesign/export} \
-         -force_rtg4_otp 0 \
-         -design_bitstream_format {PPD} 
-		save_project
-	}
-    puts "-----------------------------------------------------------------------------------------------"
-    puts "--------------------Programming Files Exported-------------------------------"
-    puts "-----------------------------------------------------------------------------------------------"
-
-} else {
-    puts "-----------------------------------------------------------------------------------------------"
-    puts "------------No Design Flow  Stage Selected at run time------------------"
-    puts "-----------------------------------------------------------------------------------------------"   
-
-}
diff --git a/Libero_Projects/RTG4_Dev_Kit_MiV_RV32IMAF_BaseDesign.tcl b/Libero_Projects/RTG4_Dev_Kit_MiV_RV32IMAF_BaseDesign.tcl
new file mode 100644
index 0000000..9ffb7f8
--- /dev/null
+++ b/Libero_Projects/RTG4_Dev_Kit_MiV_RV32IMAF_BaseDesign.tcl
@@ -0,0 +1,199 @@
+set project_folder_name_CFG1 MiV_CFG1_BD
+set project_dir_CFG1 "./$project_folder_name_CFG1"
+set Libero_project_name_CFG1 RTG4_Dev_Kit_MiV_RV32IMAF_CFG1_BaseDesign
+
+set config [string toupper [lindex $argv 0]]
+set design_flow_stage [string toupper [lindex $argv 1]]
+
+
+proc create_new_project_label { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "Creating a new project for the 'RTG4_Dev_Kit' board."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc project_exists { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "Error: A project exists for the 'RTG4_Dev_Kit' with this configuration."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc no_first_argument_entered { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "No 1st Argument has been entered."
+	puts "Enter the 1st Argument responsible for type of design configuration -'CFG1..CFGn' " 
+	puts "Default 'CFG1' design has been selected."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc invalid_first_argument { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Wrong 1st Argument has been entered."
+    puts "Make sure you enter a valid first argument -'CFG1..CFGn'."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc no_second_argument_entered { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "No 2nd Argument has been entered."
+	puts "Enter the 2nd Argument after the 1st to be taken further in the Design Flow." 
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc invalid_second_argument { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Wrong 2nd Argument has been entered."
+    puts "Make sure you enter a valid 2nd argument -'Synthesize...Export_Programming_File'."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc  base_design_built { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "BaseDesign built."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc download_cores_all_cfgs  { }\
+{
+	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.4.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.115} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:SgCore:OSC:2.0.101} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:SgCore:FCCC:2.0.201} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.6.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.5.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+}
+
+proc pre_configure_place_and_route { }\
+{
+    # Configuring Place_and_Route tool for a timing pass.
+    configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true}
+}
+
+proc run_verify_timing { }\
+{
+	run_tool -name {VERIFYTIMING}	
+}
+
+if {"$config" == "CFG1"} then {
+	if {[file exists $project_dir_CFG1] == 1} then {
+		project_exists
+	} else {
+		create_new_project_label
+		new_project -location  $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		download_cores_all_cfgs
+		source ./import/components/IMAF_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imaf_cfg1.tcl
+		save_project
+        base_design_built
+	}
+} elseif {"$config" != ""} then {
+		invalid_first_argument
+} else {
+	if {[file exists $project_dir_CFG1] == 1} then {
+		project_exists
+	} else {
+		no_first_argument_entered
+		create_new_project_label
+		new_project -location  $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		download_cores_all_cfgs
+		source ./import/components/IMAF_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imaf_cfg1.tcl
+		save_project
+        base_design_built
+	}
+} 
+
+configure_tool -name {SYNTHESIZE} -params {BLOCK_MODE:false} -params {BLOCK_PLACEMENT_CONFLICTS:ERROR} -params {BLOCK_ROUTING_CONFLICTS:LOCK} -params {CLOCK_ASYNC:150} -params {CLOCK_DATA:5000} -params {CLOCK_GLOBAL:2} -params {PA4_GB_COUNT:16} -params {PA4_GB_MAX_RCLKINT_INSERTION:16} -params {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT:300} -params {RAM_OPTIMIZED_FOR_POWER:0} -params {RETIMING:false} -params {SYNPLIFY_OPTIONS:} -params {SYNPLIFY_TCL_FILE:}
+
+if {"$design_flow_stage" == "SYNTHESIZE"} then {
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Begin Synthesis..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+	pre_configure_place_and_route
+    run_tool -name {SYNTHESIZE}
+    save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Synthesis Complete."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+} elseif {"$design_flow_stage" == "PLACE_AND_ROUTE"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Begin Place and Route..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+	pre_configure_place_and_route
+	run_verify_timing
+	save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Place and Route Complete."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+
+} elseif {"$design_flow_stage" == "GENERATE_BITSTREAM"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Generating Bitstream..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+	pre_configure_place_and_route
+	run_verify_timing
+    run_tool -name {GENERATEPROGRAMMINGDATA}
+    run_tool -name {GENERATEPROGRAMMINGFILE}
+    save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Bitstream Generated."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+
+} elseif {"$design_flow_stage" == "EXPORT_PROGRAMMING_FILE"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Exporting Programming Files..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+	pre_configure_place_and_route
+	run_verify_timing
+	run_tool -name {GENERATEPROGRAMMINGDATA}
+	run_tool -name {GENERATEPROGRAMMINGFILE}
+
+		export_prog_job \
+			-job_file_name {RTG4_Dev_Kit_MiV_RV32IMAF_CFG1_BaseDesign} \
+			-export_dir {./MiV_CFG1_BD/designer/BaseDesign/export} \
+			-force_rtg4_otp 0 \
+			-design_bitstream_format {PPD} 
+		save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Programming Files Exported."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+} elseif {"$design_flow_stage" != ""} then {
+	invalid_second_argument
+} else {
+	no_second_argument_entered
+}
\ No newline at end of file
diff --git a/Libero_Projects/RTG4_Dev_Kit_MiV_RV32IMA_BaseDesign.tcl b/Libero_Projects/RTG4_Dev_Kit_MiV_RV32IMA_BaseDesign.tcl
new file mode 100644
index 0000000..1f07bb0
--- /dev/null
+++ b/Libero_Projects/RTG4_Dev_Kit_MiV_RV32IMA_BaseDesign.tcl
@@ -0,0 +1,224 @@
+set project_folder_name_CFG1 MiV_CFG1_BD
+set project_dir_CFG1 "./$project_folder_name_CFG1"
+set Libero_project_name_CFG1 RTG4_Dev_Kit_MiV_RV32IMA_CFG1_BaseDesign
+
+set project_folder_name_CFG2 MiV_CFG2_BD
+set project_dir_CFG2 "./$project_folder_name_CFG2"
+set Libero_project_name_CFG2 RTG4_Dev_Kit_MiV_RV32IMA_CFG2_BaseDesign
+
+set config [string toupper [lindex $argv 0]]
+set design_flow_stage [string toupper [lindex $argv 1]]
+
+
+proc create_new_project_label { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "Creating a new project for the 'RTG4_Dev_Kit' board."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc project_exists { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "Error: A project exists for the 'RTG4_Dev_Kit' with this configuration."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc no_first_argument_entered { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "No 1st Argument has been entered."
+	puts "Enter the 1st Argument responsible for type of design configuration -'CFG1..CFGn' " 
+	puts "Default 'CFG1' design has been selected."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc invalid_first_argument { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Wrong 1st Argument has been entered."
+    puts "Make sure you enter a valid first argument -'CFG1..CFGn'."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc no_second_argument_entered { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "No 2nd Argument has been entered."
+	puts "Enter the 2nd Argument after the 1st to be taken further in the Design Flow." 
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc invalid_second_argument { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Wrong 2nd Argument has been entered."
+    puts "Make sure you enter a valid 2nd argument -'Synthesize...Export_Programming_File'."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc  base_design_built { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "BaseDesign built."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc download_cores_all_cfgs  { }\
+{
+	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.4.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.115} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:SgCore:OSC:2.0.101} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:SgCore:FCCC:2.0.201} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.6.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.5.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+}
+
+proc pre_configure_place_and_route { }\
+{
+    # Configuring Place_and_Route tool for a timing pass.
+    configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true}
+}
+
+proc run_verify_timing { }\
+{
+	run_tool -name {VERIFYTIMING}	
+}
+
+if {"$config" == "CFG1"} then {
+	if {[file exists $project_dir_CFG1] == 1} then {
+		project_exists
+	} else {
+		create_new_project_label
+		new_project -location  $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		download_cores_all_cfgs
+		source ./import/components/IMA_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg1.tcl
+		save_project
+        base_design_built
+	}
+} elseif {"$config" == "CFG2"} then {
+	if {[file exists $project_dir_CFG2] == 1} then {
+		project_exists
+	} else {
+		create_new_project_label
+		new_project -location  $project_dir_CFG2 -name $Libero_project_name_CFG2 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		download_cores_all_cfgs
+		source ./import/components/IMA_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg2.tcl
+		save_project
+        base_design_built
+	}
+} elseif {"$config" != ""} then {
+		invalid_first_argument
+} else {
+	if {[file exists $project_dir_CFG1] == 1} then {
+		project_exists
+	} else {
+		no_first_argument_entered
+		create_new_project_label
+		new_project -location  $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		download_cores_all_cfgs
+		source ./import/components/IMA_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg1.tcl
+		save_project
+        base_design_built
+	}
+}
+ 
+	configure_tool -name {SYNTHESIZE} -params {BLOCK_MODE:false} -params {BLOCK_PLACEMENT_CONFLICTS:ERROR} -params {BLOCK_ROUTING_CONFLICTS:LOCK} -params {CLOCK_ASYNC:150} -params {CLOCK_DATA:5000} -params {CLOCK_GLOBAL:2} -params {PA4_GB_COUNT:16} -params {PA4_GB_MAX_RCLKINT_INSERTION:16} -params {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT:300} -params {RAM_OPTIMIZED_FOR_POWER:0} -params {RETIMING:false} -params {SYNPLIFY_OPTIONS:} -params {SYNPLIFY_TCL_FILE:}
+
+if {"$design_flow_stage" == "SYNTHESIZE"} then {
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Begin Synthesis..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+	pre_configure_place_and_route
+    run_tool -name {SYNTHESIZE}
+    save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Synthesis Complete."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+} elseif {"$design_flow_stage" == "PLACE_AND_ROUTE"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Begin Place and Route..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+	pre_configure_place_and_route
+	run_verify_timing
+	save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Place and Route Complete."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+
+} elseif {"$design_flow_stage" == "GENERATE_BITSTREAM"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Generating Bitstream..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+	pre_configure_place_and_route
+	run_verify_timing
+    run_tool -name {GENERATEPROGRAMMINGDATA}
+    run_tool -name {GENERATEPROGRAMMINGFILE}
+    save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Bitstream Generated."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+
+} elseif {"$design_flow_stage" == "EXPORT_PROGRAMMING_FILE"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Exporting Programming Files..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+	pre_configure_place_and_route
+	run_verify_timing
+	run_tool -name {GENERATEPROGRAMMINGDATA}
+	run_tool -name {GENERATEPROGRAMMINGFILE}
+
+	if {"$config" == "CFG1"} then {
+          export_prog_job \
+         -job_file_name {RTG4_Dev_Kit_MiV_RV32IMA_CFG1_BaseDesign} \
+		 -export_dir {./MiV_CFG1_BD/designer/BaseDesign/export} \
+         -force_rtg4_otp 0 \
+         -design_bitstream_format {PPD} 
+		save_project
+
+	} else {
+          export_prog_job \
+         -job_file_name {RTG4_Dev_Kit_MiV_RV32IMA_CFG2_BaseDesign} \
+		 -export_dir {./MiV_CFG2_BD/designer/BaseDesign/export} \
+         -force_rtg4_otp 0 \
+         -design_bitstream_format {PPD} 
+		save_project
+	}
+	
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Programming Files Exported."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+} elseif {"$design_flow_stage" != ""} then {
+	invalid_second_argument
+} else {
+	no_second_argument_entered
+}
diff --git a/Libero_Projects/RTG4_Dev_Kit_MiV_RV32_BaseDesign .tcl b/Libero_Projects/RTG4_Dev_Kit_MiV_RV32_BaseDesign .tcl
new file mode 100644
index 0000000..25fcc98
--- /dev/null
+++ b/Libero_Projects/RTG4_Dev_Kit_MiV_RV32_BaseDesign .tcl	
@@ -0,0 +1,269 @@
+set project_folder_name_CFG1 MiV_CFG1_BD
+set project_dir_CFG1 "./$project_folder_name_CFG1"
+set Libero_project_name_CFG1 RTG4_Dev_Kit_MiV_RV32_CFG1_BaseDesign
+
+set project_folder_name_CFG2 MiV_CFG2_BD
+set project_dir_CFG2 "./$project_folder_name_CFG2"
+set Libero_project_name_CFG2 RTG4_Dev_Kit_MiV_RV32_CFG2_BaseDesign
+
+set project_folder_name_CFG3 MiV_CFG3_BD
+set project_dir_CFG3 "./$project_folder_name_CFG3"
+set Libero_project_name_CFG3 RTG4_Dev_Kit_MiV_RV32_CFG3_BaseDesign
+
+set config [string toupper [lindex $argv 0]]
+set design_flow_stage [string toupper [lindex $argv 1]]
+
+
+proc create_new_project_label { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "Creating a new project for the 'RTG4_Dev_Kit' board."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc project_exists { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "Error: A project exists for the 'RTG4_Dev_Kit' with this configuration."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc no_first_argument_entered { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "No 1st Argument has been entered."
+	puts "Enter the 1st Argument responsible for type of design configuration -'CFG1..CFGn' " 
+	puts "Default 'CFG1' design has been selected."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc invalid_first_argument { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Wrong 1st Argument has been entered."
+    puts "Make sure you enter a valid first argument -'CFG1..CFGn'."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc no_second_argument_entered { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "No 2nd Argument has been entered."
+	puts "Enter the 2nd Argument after the 1st to be taken further in the Design Flow." 
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc invalid_second_argument { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Wrong 2nd Argument has been entered."
+    puts "Make sure you enter a valid 2nd argument -'Synthesize...Export_Programming_File'."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc  base_design_built { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+	puts "BaseDesign built."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+proc config2_not_available { }\
+{
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "RTG4_Dev_Kit_MiV_RV32_CFG2_BaseDesign is not available in this release."
+    puts "Try a different BaseDesign configuration that uses MiV_RV32."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+}
+
+
+proc download_cores_all_cfgs  { }\
+{
+	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.4.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.115} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:SgCore:OSC:2.0.101} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:SgCore:FCCC:2.0.201} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.6.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.5.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+}
+
+proc pre_configure_place_and_route {config}\
+{
+	if {"$config" == "CFG1"} then {
+		# Configuring Place_and_Route tool for a timing pass CFG1
+		configure_tool -name {PLACEROUTE} -params {DELAY_ANALYSIS:MAX} -params {EFFORT_LEVEL:true} -params {INCRPLACEANDROUTE:false} -params {IOREG_COMBINING:true} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:2} -params {RANDOM_SEED:0} -params {TDPR:true}
+	# } elseif {"$config" == "CFG2"} then {
+		# # Configuring Place_and_Route tool for a timing pass CFG2
+		# configure_tool -name {PLACEROUTE} -params {DELAY_ANALYSIS:MAX} -params {EFFORT_LEVEL:true} -params {INCRPLACEANDROUTE:false} -params {IOREG_COMBINING:true} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:7} -params {RANDOM_SEED:5} -params {TDPR:true}
+	} else {
+		#Configuring Place_and_Route tool for a timing pass CFG3
+		configure_tool -name {PLACEROUTE} -params {DELAY_ANALYSIS:MAX} -params {EFFORT_LEVEL:true} -params {INCRPLACEANDROUTE:false} -params {IOREG_COMBINING:true} -params {REPAIR_MIN_DELAY:true} -params {START_SEED_INDEX:6} -params {RANDOM_SEED:4} -params {TDPR:true}
+	}
+}
+
+proc run_verify_timing { }\
+{
+	run_tool -name {VERIFYTIMING}	
+}
+
+if {"$config" == "CFG1"} then {
+	if {[file exists $project_dir_CFG1] == 1} then {
+		project_exists
+	} else {
+		create_new_project_label
+		new_project -location  $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		project_settings -enable_set_mitigation 0
+		download_cores_all_cfgs
+		source ./import/components/IMC_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg1.tcl
+		save_project
+        base_design_built
+	}
+} elseif {"$config" == "CFG2"} then {
+	# if {[file exists $project_dir_CFG2] == 1} then {
+		# project_exists
+	# } else {
+		# create_new_project_label
+		# new_project -location  $project_dir_CFG2 -name $Libero_project_name_CFG2 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		# project_settings -enable_set_mitigation 0
+		# download_cores_all_cfgs
+		# source ./import/components/IMC_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg2.tcl
+		# save_project
+        # base_design_built
+	#}
+		config2_not_available
+} elseif {"$config" == "CFG3"} then {
+	if {[file exists $project_dir_CFG3] == 1} then {
+		project_exists
+	} else {
+		create_new_project_label
+		new_project -location  $project_dir_CFG3 -name $Libero_project_name_CFG3 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		project_settings -enable_set_mitigation 0
+		download_cores_all_cfgs
+		source ./import/components/IMC_CFG3/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg3.tcl
+		save_project
+        base_design_built
+	}
+} elseif {"$config" != ""} then {
+		invalid_first_argument
+} else {
+	if {[file exists $project_dir_CFG1] == 1} then {
+		project_exists
+	} else {
+		no_first_argument_entered
+		create_new_project_label
+		new_project -location  $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
+		project_settings -enable_set_mitigation 1
+		download_cores_all_cfgs
+		source ./import/components/IMC_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg1.tcl
+		save_project
+        base_design_built
+	}
+} 
+
+if {"$config" != "CFG2"} then {
+	configure_tool -name {SYNTHESIZE} -params {BLOCK_MODE:false} -params {BLOCK_PLACEMENT_CONFLICTS:ERROR} -params {BLOCK_ROUTING_CONFLICTS:LOCK} -params {CLOCK_ASYNC:60} -params {CLOCK_DATA:5000} -params {CLOCK_GLOBAL:2} -params {PA4_GB_COUNT:16} -params {PA4_GB_MAX_RCLKINT_INSERTION:16} -params {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT:300} -params {RAM_OPTIMIZED_FOR_POWER:0} -params {RETIMING:true} -params {SYNPLIFY_OPTIONS:} -params {SYNPLIFY_TCL_FILE:}
+}
+
+if {"$design_flow_stage" == "SYNTHESIZE"} then {
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Begin Synthesis..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+	pre_configure_place_and_route $config
+    run_tool -name {SYNTHESIZE}
+    save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Synthesis Complete."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+} elseif {"$design_flow_stage" == "PLACE_AND_ROUTE"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Begin Place and Route..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+	pre_configure_place_and_route $config
+	run_verify_timing
+	save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Place and Route Complete."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+
+} elseif {"$design_flow_stage" == "GENERATE_BITSTREAM"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Generating Bitstream..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+	pre_configure_place_and_route $config
+	run_verify_timing
+    run_tool -name {GENERATEPROGRAMMINGDATA}
+    run_tool -name {GENERATEPROGRAMMINGFILE}
+    save_project
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Bitstream Generated."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+
+} elseif {"$design_flow_stage" == "EXPORT_PROGRAMMING_FILE"} then {
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Exporting Programming Files..."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+
+	pre_configure_place_and_route $config
+	run_verify_timing
+	run_tool -name {GENERATEPROGRAMMINGDATA}
+	run_tool -name {GENERATEPROGRAMMINGFILE}
+
+	if {"$config" == "CFG1"} then {
+		export_prog_job \
+			-job_file_name {RTG4_Dev_Kit_MiV_RV32_CFG1_BaseDesign} \
+			-export_dir {./MiV_CFG1_BD/designer/BaseDesign/export} \
+			-force_rtg4_otp 0 \
+			-design_bitstream_format {PPD} 
+		save_project
+	# } elseif {"$config" == "CFG2"} then {
+		# export_prog_job \
+			# -job_file_name {RTG4_Dev_Kit_MiV_RV32_CFG2_BaseDesign} \
+			# -export_dir {./MiV_CFG2_BD/designer/BaseDesign/export} \
+			# -force_rtg4_otp 0 \
+			# -design_bitstream_format {PPD} 
+		# save_project
+	} else {
+		export_prog_job \
+			-job_file_name {RTG4_Dev_Kit_MiV_RV32_CFG3_BaseDesign} \
+			-export_dir {./MiV_CFG3_BD/designer/BaseDesign/export} \
+			-force_rtg4_otp 0 \
+			-design_bitstream_format {PPD} 
+		save_project
+	}
+
+	puts "\n---------------------------------------------------------------------------------------------------------"
+    puts "Programming Files Exported."
+	puts "--------------------------------------------------------------------------------------------------------- \n"
+
+} elseif {"$design_flow_stage" != ""} then {
+	invalid_second_argument
+} else {
+	no_second_argument_entered
+}
\ No newline at end of file
diff --git a/Libero_Projects/import/components/AHB/import_component_and_constraints_rtg4_dev_kit_ahb.tcl b/Libero_Projects/import/components/AHB/import_component_and_constraints_rtg4_dev_kit_ahb.tcl
deleted file mode 100644
index 927ec27..0000000
--- a/Libero_Projects/import/components/AHB/import_component_and_constraints_rtg4_dev_kit_ahb.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-set project_folder_name MiV_AHB_BD
-set project_dir2 "./$project_folder_name"
-
-
-puts "-------------------------------------------------------------------------"
-puts "-----------------------IMPORTING COMPONENTS------------------------------"
-puts "-------------------------------------------------------------------------"
-
-
-source ./import/components/AHB/top_level_rtg4_dev_kit_ahb.tcl
-
-build_design_hierarchy
-set_root BaseDesign
-
-puts "-------------------------------------------------------------------------"
-puts "--------------------APPLYING DESIGN CONSTRAINTS--------------------------"
-puts "-------------------------------------------------------------------------"
-
-import_files -io_pdc ./import/constraints/io/io_constraints.pdc
-import_files -sdc    ./import/constraints/io_jtag_constraints.sdc
-
-## Associate SDC constraint file to Place and Route tool
-organize_tool_files -tool {PLACEROUTE} \
-    -file $project_dir2/constraint/io_jtag_constraints.sdc \
-    -file $project_dir2/constraint/io/io_constraints.pdc \
-    -module {BaseDesign::work} -input_type {constraint}
-
-organize_tool_files -tool {SYNTHESIZE} \
-    -file $project_dir2/constraint/io_jtag_constraints.sdc \
-    -module {BaseDesign::work} -input_type {constraint}
-
-organize_tool_files -tool {VERIFYTIMING} \
-    -file $project_dir2/constraint/io_jtag_constraints.sdc \
-    -module {BaseDesign::work} -input_type {constraint}
-set_root BaseDesign
-
-run_tool -name {CONSTRAINT_MANAGEMENT}
-derive_constraints_sdc
diff --git a/Libero_Projects/import/components/AHB/top_level_rtg4_dev_kit_ahb.tcl b/Libero_Projects/import/components/AHB/top_level_rtg4_dev_kit_ahb.tcl
deleted file mode 100644
index c67c048..0000000
--- a/Libero_Projects/import/components/AHB/top_level_rtg4_dev_kit_ahb.tcl
+++ /dev/null
@@ -1,798 +0,0 @@
-#RTG4 Dev Kit = RTG4150-1657CG
-#Libero's TCL top level script
-# Core: MiV_RV32IMA_L1_AXI
-#
-# Creating SmartDesign BaseDesign
-set sd_name {BaseDesign}
-create_smartdesign -sd_name ${sd_name}
-
-# Disable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 0
-
-# Creating the RTG4FCCC_0 instance
-create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:2.0.201} -component_name {RTG4FCCC_0} -params {\
-"ADVANCED_TAB_CHANGED:false" \
-"CLK0_IS_USED:false" \
-"CLK0_PAD_IS_USED:false" \
-"CLK1_IS_USED:false" \
-"CLK1_PAD_IS_USED:false" \
-"CLK2_IS_USED:false" \
-"CLK2_PAD_IS_USED:false" \
-"CLK3_IS_USED:false" \
-"CLK3_PAD_IS_USED:false" \
-"DYN_CONF_IS_USED:false" \
-"ENABLE_AUTO_RESET_LOGIC:false" \
-"EXPOSE_CGL_ENABLE_ARST_SIGNALS:false" \
-"GL0_BP_IN_0_FREQ:100" \
-"GL0_BP_IN_0_SRC:IO_HARDWIRED_0" \
-"GL0_BP_IN_1_FREQ:100" \
-"GL0_BP_IN_1_SRC:IO_HARDWIRED_0" \
-"GL0_FREQUENCY_LOCKED:false" \
-"GL0_IN_0_SRC:PLL" \
-"GL0_IN_1_SRC:UNUSED" \
-"GL0_IS_INVERTED:false" \
-"GL0_IS_USED:true" \
-"GL0_OUT_0_FREQ:50" \
-"GL0_OUT_1_FREQ:50" \
-"GL0_OUT_IS_GATED:false" \
-"GL0_PLL_IN_0_PHASE:0" \
-"GL0_PLL_IN_1_PHASE:0" \
-"GL1_BP_IN_0_FREQ:100" \
-"GL1_BP_IN_0_SRC:IO_HARDWIRED_0" \
-"GL1_BP_IN_1_FREQ:100" \
-"GL1_BP_IN_1_SRC:IO_HARDWIRED_0" \
-"GL1_FREQUENCY_LOCKED:false" \
-"GL1_IN_0_SRC:PLL" \
-"GL1_IN_1_SRC:UNUSED" \
-"GL1_IS_INVERTED:false" \
-"GL1_IS_USED:false" \
-"GL1_OUT_0_FREQ:50" \
-"GL1_OUT_1_FREQ:50" \
-"GL1_OUT_IS_GATED:false" \
-"GL1_PLL_IN_0_PHASE:0" \
-"GL1_PLL_IN_1_PHASE:0" \
-"GL2_BP_IN_0_FREQ:100" \
-"GL2_BP_IN_0_SRC:IO_HARDWIRED_0" \
-"GL2_BP_IN_1_FREQ:100" \
-"GL2_BP_IN_1_SRC:IO_HARDWIRED_0" \
-"GL2_FREQUENCY_LOCKED:false" \
-"GL2_IN_0_SRC:PLL" \
-"GL2_IN_1_SRC:UNUSED" \
-"GL2_IS_INVERTED:false" \
-"GL2_IS_USED:false" \
-"GL2_OUT_0_FREQ:100" \
-"GL2_OUT_1_FREQ:50" \
-"GL2_OUT_IS_GATED:false" \
-"GL2_PLL_IN_0_PHASE:0" \
-"GL2_PLL_IN_1_PHASE:0" \
-"GL3_BP_IN_0_FREQ:100" \
-"GL3_BP_IN_0_SRC:IO_HARDWIRED_0" \
-"GL3_BP_IN_1_FREQ:100" \
-"GL3_BP_IN_1_SRC:IO_HARDWIRED_0" \
-"GL3_FREQUENCY_LOCKED:false" \
-"GL3_IN_0_SRC:PLL" \
-"GL3_IN_1_SRC:UNUSED" \
-"GL3_IS_INVERTED:false" \
-"GL3_IS_USED:false" \
-"GL3_OUT_0_FREQ:100" \
-"GL3_OUT_1_FREQ:50" \
-"GL3_OUT_IS_GATED:false" \
-"GL3_PLL_IN_0_PHASE:0" \
-"GL3_PLL_IN_1_PHASE:0" \
-"GPD0_IS_USED:false" \
-"GPD0_NOPIPE_RSTSYNC:true" \
-"GPD0_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC" \
-"GPD1_IS_USED:false" \
-"GPD1_NOPIPE_RSTSYNC:true" \
-"GPD1_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC" \
-"GPD2_IS_USED:false" \
-"GPD2_NOPIPE_RSTSYNC:true" \
-"GPD2_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC" \
-"GPD3_IS_USED:false" \
-"GPD3_NOPIPE_RSTSYNC:true" \
-"GPD3_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC" \
-"GPD_EXPOSE_RESETS:false" \
-"GPD_SYNC_STYLE:G3STYLE_AND_LOCK_RSTSYNC" \
-"INCLUDE_RECONFIGURATION_LOGIC:true" \
-"INIT:088101249000020B80404040664C993186071C11C16C" \
-"IO_HARDWIRED_0_IS_DIFF:false" \
-"IO_HARDWIRED_1_IS_DIFF:false" \
-"IO_HARDWIRED_2_IS_DIFF:false" \
-"IO_HARDWIRED_3_IS_DIFF:false" \
-"MODE_10V:false" \
-"NGMUX0_HOLD_IS_USED:false" \
-"NGMUX1_HOLD_IS_USED:false" \
-"NGMUX2_HOLD_IS_USED:false" \
-"NGMUX3_HOLD_IS_USED:false" \
-"NGMUX_EXPOSE_HOLD:false" \
-"PLL_DELAY:0" \
-"PLL_EXPOSE_BYPASS:false" \
-"PLL_EXPOSE_READY_VDDPLL:false" \
-"PLL_EXPOSE_RESETS:false" \
-"PLL_EXT_FB_GL:EXT_FB_GL0" \
-"PLL_FB_SRC:CCC_INTERNAL" \
-"PLL_IN_FREQ:50.000" \
-"PLL_IN_SRC:OSC_50MHZ" \
-"PLL_IS_USED:true" \
-"PLL_LOCK_IND:1024" \
-"PLL_LOCK_WND:6000" \
-"PLL_SSM_DEPTH:0.5" \
-"PLL_SSM_ENABLE:false" \
-"PLL_SSM_FREQ:40" \
-"PLL_SUPPLY_VOLTAGE:25_V" \
-"PLL_VCO_TARGET:700" \
-"RCOSC_25_50MHZ_IS_USED:true" \
-"RX0_RECOVERY_BLOCK_DATA:Unused-Unused" \
-"RX0_RECOVERY_BLOCK_IS_USED:false" \
-"RX0_RECOVERY_BLOCK_STROBE:Unused" \
-"RX0_SPACE_WIRE_MODE_IS_USED:true" \
-"RX1_RECOVERY_BLOCK_DATA:Unused-Unused" \
-"RX1_RECOVERY_BLOCK_IS_USED:false" \
-"RX1_RECOVERY_BLOCK_STROBE:Unused" \
-"RX1_SPACE_WIRE_MODE_IS_USED:true" \
-"VCOFREQUENCY:800.000" \
-"Y0_IS_USED:false" \
-"Y1_IS_USED:false" \
-"Y2_IS_USED:false" \
-"Y3_IS_USED:false"	} 
-# Parameters for the RTG4FCCC_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0}
-
-
-
-# Add RCOSC_50MHZ_0 instance
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0}
-
-
-
-# Add reset_synchronizer_0 instance
-sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} 
-
-
-
-# Add SYSRESET_0 instance
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0}
-
-
-
-# Add AND2_0 instance
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} 
-
-
-
-
-# Creating the CoreAPB3_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.1.100} -component_name {CoreAPB3_0} -params {\
-"APB_DWIDTH:32"  \
-"APBSLOT0ENABLE:false"  \
-"APBSLOT1ENABLE:true"  \
-"APBSLOT2ENABLE:true"  \
-"APBSLOT3ENABLE:true"  \
-"APBSLOT4ENABLE:true"  \
-"APBSLOT5ENABLE:true"  \
-"APBSLOT6ENABLE:false"  \
-"APBSLOT7ENABLE:false"  \
-"APBSLOT8ENABLE:false"  \
-"APBSLOT9ENABLE:false"  \
-"APBSLOT10ENABLE:false"  \
-"APBSLOT11ENABLE:false"  \
-"APBSLOT12ENABLE:false"  \
-"APBSLOT13ENABLE:false"  \
-"APBSLOT14ENABLE:false"  \
-"APBSLOT15ENABLE:false"  \
-"IADDR_OPTION:0"  \
-"MADDR_BITS:16"  \
-"SC_0:false"  \
-"SC_1:false"  \
-"SC_2:false"  \
-"SC_3:false"  \
-"SC_4:false"  \
-"SC_5:false"  \
-"SC_6:false"  \
-"SC_7:false"  \
-"SC_8:false"  \
-"SC_9:false"  \
-"SC_10:false"  \
-"SC_11:false"  \
-"SC_12:false"  \
-"SC_13:false"  \
-"SC_14:false"  \
-"SC_15:false"  \
-"UPR_NIBBLE_POSN:6"   }
-# Parameters for CoreAPB3_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0}
-
-
-
-# Creating the COREAHBTOAPB3_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:COREAHBTOAPB3:3.1.100} -component_name {COREAHBTOAPB3_0} -params { }
-# Parameters for COREAHBTOAPB3_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0}
-
-
-
-# Creating the CoreAHBL_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.4.102} -component_name {CoreAHBL_0} -params {\
-"HADDR_SHG_CFG:1"  \
-"M0_AHBSLOT0ENABLE:false"  \
-"M0_AHBSLOT1ENABLE:false"  \
-"M0_AHBSLOT2ENABLE:false"  \
-"M0_AHBSLOT3ENABLE:false"  \
-"M0_AHBSLOT4ENABLE:false"  \
-"M0_AHBSLOT5ENABLE:false"  \
-"M0_AHBSLOT6ENABLE:false"  \
-"M0_AHBSLOT7ENABLE:true"  \
-"M0_AHBSLOT8ENABLE:false"  \
-"M0_AHBSLOT9ENABLE:false"  \
-"M0_AHBSLOT10ENABLE:false"  \
-"M0_AHBSLOT11ENABLE:false"  \
-"M0_AHBSLOT12ENABLE:false"  \
-"M0_AHBSLOT13ENABLE:false"  \
-"M0_AHBSLOT14ENABLE:false"  \
-"M0_AHBSLOT15ENABLE:false"  \
-"M0_AHBSLOT16ENABLE:false"  \
-"M1_AHBSLOT0ENABLE:false"  \
-"M1_AHBSLOT1ENABLE:false"  \
-"M1_AHBSLOT2ENABLE:false"  \
-"M1_AHBSLOT3ENABLE:false"  \
-"M1_AHBSLOT4ENABLE:false"  \
-"M1_AHBSLOT5ENABLE:false"  \
-"M1_AHBSLOT6ENABLE:false"  \
-"M1_AHBSLOT7ENABLE:false"  \
-"M1_AHBSLOT8ENABLE:true"  \
-"M1_AHBSLOT9ENABLE:false"  \
-"M1_AHBSLOT10ENABLE:false"  \
-"M1_AHBSLOT11ENABLE:false"  \
-"M1_AHBSLOT12ENABLE:false"  \
-"M1_AHBSLOT13ENABLE:false"  \
-"M1_AHBSLOT14ENABLE:false"  \
-"M1_AHBSLOT15ENABLE:false"  \
-"M1_AHBSLOT16ENABLE:false"  \
-"M2_AHBSLOT0ENABLE:false"  \
-"M2_AHBSLOT1ENABLE:false"  \
-"M2_AHBSLOT2ENABLE:false"  \
-"M2_AHBSLOT3ENABLE:false"  \
-"M2_AHBSLOT4ENABLE:false"  \
-"M2_AHBSLOT5ENABLE:false"  \
-"M2_AHBSLOT6ENABLE:false"  \
-"M2_AHBSLOT7ENABLE:false"  \
-"M2_AHBSLOT8ENABLE:false"  \
-"M2_AHBSLOT9ENABLE:false"  \
-"M2_AHBSLOT10ENABLE:false"  \
-"M2_AHBSLOT11ENABLE:false"  \
-"M2_AHBSLOT12ENABLE:false"  \
-"M2_AHBSLOT13ENABLE:false"  \
-"M2_AHBSLOT14ENABLE:false"  \
-"M2_AHBSLOT15ENABLE:false"  \
-"M2_AHBSLOT16ENABLE:false"  \
-"M3_AHBSLOT0ENABLE:false"  \
-"M3_AHBSLOT1ENABLE:false"  \
-"M3_AHBSLOT2ENABLE:false"  \
-"M3_AHBSLOT3ENABLE:false"  \
-"M3_AHBSLOT4ENABLE:false"  \
-"M3_AHBSLOT5ENABLE:false"  \
-"M3_AHBSLOT6ENABLE:false"  \
-"M3_AHBSLOT7ENABLE:false"  \
-"M3_AHBSLOT8ENABLE:false"  \
-"M3_AHBSLOT9ENABLE:false"  \
-"M3_AHBSLOT10ENABLE:false"  \
-"M3_AHBSLOT11ENABLE:false"  \
-"M3_AHBSLOT12ENABLE:false"  \
-"M3_AHBSLOT13ENABLE:false"  \
-"M3_AHBSLOT14ENABLE:false"  \
-"M3_AHBSLOT15ENABLE:false"  \
-"M3_AHBSLOT16ENABLE:false"  \
-"MASTER0_INTERFACE:1"	\
-"MASTER1_INTERFACE:1"	\
-"MASTER2_INTERFACE:1"	\
-"MASTER3_INTERFACE:1"	\
-"MEMSPACE:1"  \
-"SC_0:false"  \
-"SC_1:false"  \
-"SC_2:false"  \
-"SC_3:false"  \
-"SC_4:false"  \
-"SC_5:false"  \
-"SC_6:false"  \
-"SC_7:false"  \
-"SC_8:false"  \
-"SC_9:false"  \
-"SC_10:false"  \
-"SC_11:false"  \
-"SC_12:false"  \
-"SC_13:false"  \
-"SC_14:false"  \
-"SC_15:false"   \
-"SLAVE0_INTERFACE:1"	\
-"SLAVE1_INTERFACE:1"	\
-"SLAVE2_INTERFACE:1"	\
-"SLAVE3_INTERFACE:1"	\
-"SLAVE4_INTERFACE:1"	\
-"SLAVE5_INTERFACE:1"	\
-"SLAVE6_INTERFACE:1"	\
-"SLAVE7_INTERFACE:1"	\
-"SLAVE8_INTERFACE:1"	\
-"SLAVE9_INTERFACE:1"	\
-"SLAVE10_INTERFACE:1"	\
-"SLAVE11_INTERFACE:1"	\
-"SLAVE12_INTERFACE:1"	\
-"SLAVE13_INTERFACE:1"	\
-"SLAVE14_INTERFACE:1"	\
-"SLAVE15_INTERFACE:1"	\
-"SLAVE16_INTERFACE:1"	}
-# Parameters for CoreAHBL_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -instance_name {CoreAHBL_0}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND}
-
-
-
-# Creating the CoreGPIO_IN instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_IN} -params {\
-"APB_WIDTH:32"  \
-"FIXED_CONFIG_0:true"  \
-"FIXED_CONFIG_1:true"  \
-"FIXED_CONFIG_2:false"  \
-"FIXED_CONFIG_3:false"  \
-"FIXED_CONFIG_4:false"  \
-"FIXED_CONFIG_5:false"  \
-"FIXED_CONFIG_6:false"  \
-"FIXED_CONFIG_7:false"  \
-"FIXED_CONFIG_8:false"  \
-"FIXED_CONFIG_9:false"  \
-"FIXED_CONFIG_10:false"  \
-"FIXED_CONFIG_11:false"  \
-"FIXED_CONFIG_12:false"  \
-"FIXED_CONFIG_13:false"  \
-"FIXED_CONFIG_14:false"  \
-"FIXED_CONFIG_15:false"  \
-"FIXED_CONFIG_16:false"  \
-"FIXED_CONFIG_17:false"  \
-"FIXED_CONFIG_18:false"  \
-"FIXED_CONFIG_19:false"  \
-"FIXED_CONFIG_20:false"  \
-"FIXED_CONFIG_21:false"  \
-"FIXED_CONFIG_22:false"  \
-"FIXED_CONFIG_23:false"  \
-"FIXED_CONFIG_24:false"  \
-"FIXED_CONFIG_25:false"  \
-"FIXED_CONFIG_26:false"  \
-"FIXED_CONFIG_27:false"  \
-"FIXED_CONFIG_28:false"  \
-"FIXED_CONFIG_29:false"  \
-"FIXED_CONFIG_30:false"  \
-"FIXED_CONFIG_31:false"  \
-"INT_BUS:0"  \
-"IO_INT_TYPE_0:7"  \
-"IO_INT_TYPE_1:7"  \
-"IO_INT_TYPE_2:7"  \
-"IO_INT_TYPE_3:7"  \
-"IO_INT_TYPE_4:7"  \
-"IO_INT_TYPE_5:7"  \
-"IO_INT_TYPE_6:7"  \
-"IO_INT_TYPE_7:7"  \
-"IO_INT_TYPE_8:7"  \
-"IO_INT_TYPE_9:7"  \
-"IO_INT_TYPE_10:7"  \
-"IO_INT_TYPE_11:7"  \
-"IO_INT_TYPE_12:7"  \
-"IO_INT_TYPE_13:7"  \
-"IO_INT_TYPE_14:7"  \
-"IO_INT_TYPE_15:7"  \
-"IO_INT_TYPE_16:7"  \
-"IO_INT_TYPE_17:7"  \
-"IO_INT_TYPE_18:7"  \
-"IO_INT_TYPE_19:7"  \
-"IO_INT_TYPE_20:7"  \
-"IO_INT_TYPE_21:7"  \
-"IO_INT_TYPE_22:7"  \
-"IO_INT_TYPE_23:7"  \
-"IO_INT_TYPE_24:7"  \
-"IO_INT_TYPE_25:7"  \
-"IO_INT_TYPE_26:7"  \
-"IO_INT_TYPE_27:7"  \
-"IO_INT_TYPE_28:7"  \
-"IO_INT_TYPE_29:7"  \
-"IO_INT_TYPE_30:7"  \
-"IO_INT_TYPE_31:7"  \
-"IO_NUM:2"  \
-"IO_TYPE_0:0"  \
-"IO_TYPE_1:0"  \
-"IO_TYPE_2:0"  \
-"IO_TYPE_3:0"  \
-"IO_TYPE_4:0"  \
-"IO_TYPE_5:0"  \
-"IO_TYPE_6:0"  \
-"IO_TYPE_7:0"  \
-"IO_TYPE_8:0"  \
-"IO_TYPE_9:0"  \
-"IO_TYPE_10:0"  \
-"IO_TYPE_11:0"  \
-"IO_TYPE_12:0"  \
-"IO_TYPE_13:0"  \
-"IO_TYPE_14:0"  \
-"IO_TYPE_15:0"  \
-"IO_TYPE_16:0"  \
-"IO_TYPE_17:0"  \
-"IO_TYPE_18:0"  \
-"IO_TYPE_19:0"  \
-"IO_TYPE_20:0"  \
-"IO_TYPE_21:0"  \
-"IO_TYPE_22:0"  \
-"IO_TYPE_23:0"  \
-"IO_TYPE_24:0"  \
-"IO_TYPE_25:0"  \
-"IO_TYPE_26:0"  \
-"IO_TYPE_27:0"  \
-"IO_TYPE_28:0"  \
-"IO_TYPE_29:0"  \
-"IO_TYPE_30:0"  \
-"IO_TYPE_31:0"  \
-"IO_VAL_0:0"  \
-"IO_VAL_1:0"  \
-"IO_VAL_2:0"  \
-"IO_VAL_3:0"  \
-"IO_VAL_4:0"  \
-"IO_VAL_5:0"  \
-"IO_VAL_6:0"  \
-"IO_VAL_7:0"  \
-"IO_VAL_8:0"  \
-"IO_VAL_9:0"  \
-"IO_VAL_10:0"  \
-"IO_VAL_11:0"  \
-"IO_VAL_12:0"  \
-"IO_VAL_13:0"  \
-"IO_VAL_14:0"  \
-"IO_VAL_15:0"  \
-"IO_VAL_16:0"  \
-"IO_VAL_17:0"  \
-"IO_VAL_18:0"  \
-"IO_VAL_19:0"  \
-"IO_VAL_20:0"  \
-"IO_VAL_21:0"  \
-"IO_VAL_22:0"  \
-"IO_VAL_23:0"  \
-"IO_VAL_24:0"  \
-"IO_VAL_25:0"  \
-"IO_VAL_26:0"  \
-"IO_VAL_27:0"  \
-"IO_VAL_28:0"  \
-"IO_VAL_29:0"  \
-"IO_VAL_30:0"  \
-"IO_VAL_31:0"  \
-"OE_TYPE:1"   }
-# Parameters for CoreGPIO_IN
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT}
-
-
-
-# Creating CoreGPIO_OUT
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_OUT} -params {\
-"APB_WIDTH:32"  \
-"FIXED_CONFIG_0:true"  \
-"FIXED_CONFIG_1:true"  \
-"FIXED_CONFIG_2:true"  \
-"FIXED_CONFIG_3:true"  \
-"FIXED_CONFIG_4:false"  \
-"FIXED_CONFIG_5:false"  \
-"FIXED_CONFIG_6:false"  \
-"FIXED_CONFIG_7:false"  \
-"FIXED_CONFIG_8:false"  \
-"FIXED_CONFIG_9:false"  \
-"FIXED_CONFIG_10:false"  \
-"FIXED_CONFIG_11:false"  \
-"FIXED_CONFIG_12:false"  \
-"FIXED_CONFIG_13:false"  \
-"FIXED_CONFIG_14:false"  \
-"FIXED_CONFIG_15:false"  \
-"FIXED_CONFIG_16:false"  \
-"FIXED_CONFIG_17:false"  \
-"FIXED_CONFIG_18:false"  \
-"FIXED_CONFIG_19:false"  \
-"FIXED_CONFIG_20:false"  \
-"FIXED_CONFIG_21:false"  \
-"FIXED_CONFIG_22:false"  \
-"FIXED_CONFIG_23:false"  \
-"FIXED_CONFIG_24:false"  \
-"FIXED_CONFIG_25:false"  \
-"FIXED_CONFIG_26:false"  \
-"FIXED_CONFIG_27:false"  \
-"FIXED_CONFIG_28:false"  \
-"FIXED_CONFIG_29:false"  \
-"FIXED_CONFIG_30:false"  \
-"FIXED_CONFIG_31:false"  \
-"INT_BUS:0"  \
-"IO_INT_TYPE_0:7"  \
-"IO_INT_TYPE_1:7"  \
-"IO_INT_TYPE_2:7"  \
-"IO_INT_TYPE_3:7"  \
-"IO_INT_TYPE_4:7"  \
-"IO_INT_TYPE_5:7"  \
-"IO_INT_TYPE_6:7"  \
-"IO_INT_TYPE_7:7"  \
-"IO_INT_TYPE_8:7"  \
-"IO_INT_TYPE_9:7"  \
-"IO_INT_TYPE_10:7"  \
-"IO_INT_TYPE_11:7"  \
-"IO_INT_TYPE_12:7"  \
-"IO_INT_TYPE_13:7"  \
-"IO_INT_TYPE_14:7"  \
-"IO_INT_TYPE_15:7"  \
-"IO_INT_TYPE_16:7"  \
-"IO_INT_TYPE_17:7"  \
-"IO_INT_TYPE_18:7"  \
-"IO_INT_TYPE_19:7"  \
-"IO_INT_TYPE_20:7"  \
-"IO_INT_TYPE_21:7"  \
-"IO_INT_TYPE_22:7"  \
-"IO_INT_TYPE_23:7"  \
-"IO_INT_TYPE_24:7"  \
-"IO_INT_TYPE_25:7"  \
-"IO_INT_TYPE_26:7"  \
-"IO_INT_TYPE_27:7"  \
-"IO_INT_TYPE_28:7"  \
-"IO_INT_TYPE_29:7"  \
-"IO_INT_TYPE_30:7"  \
-"IO_INT_TYPE_31:7"  \
-"IO_NUM:4"  \
-"IO_TYPE_0:1"  \
-"IO_TYPE_1:1"  \
-"IO_TYPE_2:1"  \
-"IO_TYPE_3:1"  \
-"IO_TYPE_4:0"  \
-"IO_TYPE_5:0"  \
-"IO_TYPE_6:0"  \
-"IO_TYPE_7:0"  \
-"IO_TYPE_8:0"  \
-"IO_TYPE_9:0"  \
-"IO_TYPE_10:0"  \
-"IO_TYPE_11:0"  \
-"IO_TYPE_12:0"  \
-"IO_TYPE_13:0"  \
-"IO_TYPE_14:0"  \
-"IO_TYPE_15:0"  \
-"IO_TYPE_16:0"  \
-"IO_TYPE_17:0"  \
-"IO_TYPE_18:0"  \
-"IO_TYPE_19:0"  \
-"IO_TYPE_20:0"  \
-"IO_TYPE_21:0"  \
-"IO_TYPE_22:0"  \
-"IO_TYPE_23:0"  \
-"IO_TYPE_24:0"  \
-"IO_TYPE_25:0"  \
-"IO_TYPE_26:0"  \
-"IO_TYPE_27:0"  \
-"IO_TYPE_28:0"  \
-"IO_TYPE_29:0"  \
-"IO_TYPE_30:0"  \
-"IO_TYPE_31:0"  \
-"IO_VAL_0:0"  \
-"IO_VAL_1:0"  \
-"IO_VAL_2:0"  \
-"IO_VAL_3:0"  \
-"IO_VAL_4:0"  \
-"IO_VAL_5:0"  \
-"IO_VAL_6:0"  \
-"IO_VAL_7:0"  \
-"IO_VAL_8:0"  \
-"IO_VAL_9:0"  \
-"IO_VAL_10:0"  \
-"IO_VAL_11:0"  \
-"IO_VAL_12:0"  \
-"IO_VAL_13:0"  \
-"IO_VAL_14:0"  \
-"IO_VAL_15:0"  \
-"IO_VAL_16:0"  \
-"IO_VAL_17:0"  \
-"IO_VAL_18:0"  \
-"IO_VAL_19:0"  \
-"IO_VAL_20:0"  \
-"IO_VAL_21:0"  \
-"IO_VAL_22:0"  \
-"IO_VAL_23:0"  \
-"IO_VAL_24:0"  \
-"IO_VAL_25:0"  \
-"IO_VAL_26:0"  \
-"IO_VAL_27:0"  \
-"IO_VAL_28:0"  \
-"IO_VAL_29:0"  \
-"IO_VAL_30:0"  \
-"IO_VAL_31:0"  \
-"OE_TYPE:1"   }
-# Parameters for CoreGPIO_OUT
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND}
-
-
-
-# Creating the CoreTimer_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreTimer:2.0.103} -component_name {CoreTimer_0} -params {\
-"INTACTIVEH:1"  \
-"WIDTH:32"   }
-# Parameters for CoreTimer_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0}
-
-
-
-# Creating the CoreTimer_1 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreTimer:2.0.103} -component_name {CoreTimer_1} -params {\
-"INTACTIVEH:1"  \
-"WIDTH:32"   }
-# Parameters for CoreTimer_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1}
-
-
-
-# Creating the CoreUARTapb_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreUARTapb:5.6.102} -component_name {CoreUARTapb_0} -params {\
-"BAUD_VAL_FRCTN:0"  \
-"BAUD_VAL_FRCTN_EN:false"  \
-"BAUD_VALUE:1"  \
-"FIXEDMODE:0"  \
-"PRG_BIT8:0"  \
-"PRG_PARITY:0"  \
-"RX_FIFO:0"  \
-"RX_LEGACY_MODE:0"  \
-"TX_FIFO:0"  \
-"USE_SOFT_FIFO:0"   }
-# Parameters for CoreUARTapb_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR}
-
-
-
-# Creating the CoreJTAGDebug_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:COREJTAGDEBUG:3.1.100} -component_name {CoreJTAGDebug_0} -params {\
-"IR_CODE_TGT_0:0x55" \
-"IR_CODE_TGT_1:0x56" \
-"IR_CODE_TGT_2:0x57" \
-"IR_CODE_TGT_3:0x58" \
-"IR_CODE_TGT_4:0x59" \
-"IR_CODE_TGT_5:0x5a" \
-"IR_CODE_TGT_6:0x5b" \
-"IR_CODE_TGT_7:0x5c" \
-"IR_CODE_TGT_8:0x5d" \
-"IR_CODE_TGT_9:0x5e" \
-"IR_CODE_TGT_10:0x5f" \
-"IR_CODE_TGT_11:0x60" \
-"IR_CODE_TGT_12:0x61" \
-"IR_CODE_TGT_13:0x62" \
-"IR_CODE_TGT_14:0x63" \
-"IR_CODE_TGT_15:0x64" \
-"NUM_DEBUG_TGTS:1" \
-"Testbench:User" \
-"TGT_ACTIVE_HIGH_RESET_0:true" \
-"TGT_ACTIVE_HIGH_RESET_1:true" \
-"TGT_ACTIVE_HIGH_RESET_2:true" \
-"TGT_ACTIVE_HIGH_RESET_3:true" \
-"TGT_ACTIVE_HIGH_RESET_4:true" \
-"TGT_ACTIVE_HIGH_RESET_5:true" \
-"TGT_ACTIVE_HIGH_RESET_6:true" \
-"TGT_ACTIVE_HIGH_RESET_7:true" \
-"TGT_ACTIVE_HIGH_RESET_8:true" \
-"TGT_ACTIVE_HIGH_RESET_9:true" \
-"TGT_ACTIVE_HIGH_RESET_10:true" \
-"TGT_ACTIVE_HIGH_RESET_11:true" \
-"TGT_ACTIVE_HIGH_RESET_12:true" \
-"TGT_ACTIVE_HIGH_RESET_13:true" \
-"TGT_ACTIVE_HIGH_RESET_14:true" \
-"TGT_ACTIVE_HIGH_RESET_15:true" \
-"UJTAG_BYPASS:false" }
-# Parameters for CoreJTAGDebug_0 instance
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0}
-
-
-
-# Creating the RTG4_SRAM_0 instance
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.107} -component_name {RTG4_SRAM_0} -params {\
-"AXI4_AWIDTH:32" \
-"AXI4_DWIDTH:32" \
-"AXI4_IDWIDTH:8" \
-"AXI4_IFTYPE_RD:T" \
-"AXI4_IFTYPE_WR:T" \
-"AXI4_WRAP_SUPPORT:F" \
-"BYTEENABLES:1" \
-"BYTE_ENABLE_WIDTH:4" \
-"B_REN_POLARITY:2" \
-"CASCADE:1" \
-"ECC_OPTIONS:0" \
-"FABRIC_INTERFACE_TYPE:0" \
-"IMPORT_FILE:" \
-"INIT_RAM:F" \
-"LPM_HINT:0" \
-"PIPELINE_OPTIONS:1" \
-"RDEPTH:65536" \
-"RWIDTH:36" \
-"USE_NATIVE_INTERFACE:F" \
-"WDEPTH:65536" \
-"WWIDTH:36"} 
-# Instantiating the RTG4_SRAM_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0} 
-
-
-
-
-# Creating the MiV_RV32IMA_L1_AHB_0 instance
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -component_name {MiV_RV32IMA_L1_AHB_0} -params {\
-"ECC_EN:false" \
-"EXT_HALT:false" \
-"RESET_VECTOR_ADDR_0:0x0" \
-"RESET_VECTOR_ADDR_1:0x8000" }
-# Parameters for MiV_RV32IMA_L1_AHB_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {MiV_RV32IMA_L1_AHB_0} -instance_name {MiV_RV32IMA_L1_AHB_0}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AHB_0:IRQ} -pin_slices {[28:0]}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AHB_0:IRQ[28:0]} -value {GND}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AHB_0:IRQ} -pin_slices {[29]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AHB_0:IRQ} -pin_slices {[30]}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AHB_0:AHB_MST_MEM_HSEL}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AHB_0:AHB_MST_MMIO_HSEL}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AHB_0:EXT_RESETN}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AHB_0:DRV_TDO}
-
-
-
-# Create top level Ports
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN}
-sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_IN} -port_direction {IN} -port_range {[1:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT} -port_range {[3:0]}
-
-# Add scalar net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4FCCC_0:GL0" "reset_synchronizer_0:clock" "CoreAHBL_0:HCLK" "CoreGPIO_IN:PCLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "CoreUARTapb_0:PCLK" "CoreGPIO_OUT:PCLK" "COREAHBTOAPB3_0:HCLK" "MiV_RV32IMA_L1_AHB_0:CLK" "RTG4_SRAM_0:HCLK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVRST_N" "SYSRESET_0:DEVRST_N" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4FCCC_0:RCOSC_50MHZ" "RCOSC_50MHZ_0:CLKOUT" } 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:IRQ[29]" "CoreTimer_0:TIMINT" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:IRQ[30]" "CoreTimer_1:TIMINT" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:TCK" "CoreJTAGDebug_0:TGT_TCK_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:TDI" "CoreJTAGDebug_0:TGT_TDI_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:TMS" "CoreJTAGDebug_0:TGT_TMS_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:TRST" "CoreJTAGDebug_0:TGT_TRSTB_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MiV_RV32IMA_L1_AHB_0:TDO" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:reset_sync" "CoreAHBL_0:HRESETN" "CoreGPIO_IN:PRESETN" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "CoreUARTapb_0:PRESETN" "CoreGPIO_OUT:PRESETN" "COREAHBTOAPB3_0:HRESETN" "MiV_RV32IMA_L1_AHB_0:RESETN" "RTG4_SRAM_0:HRESETN" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"RX" "CoreUARTapb_0:RX" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TCK" "CoreJTAGDebug_0:TCK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TDI" "CoreJTAGDebug_0:TDI" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TDO" "CoreJTAGDebug_0:TDO" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TMS" "CoreJTAGDebug_0:TMS" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TRSTB" "CoreJTAGDebug_0:TRSTB" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TX" "CoreUARTapb_0:TX" }
-
-# Add bus net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_IN" "CoreGPIO_IN:GPIO_IN" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT" "GPIO_OUT" }
-
-# Add bus interface net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:APB_bif" "CoreAPB3_0:APBmslave1" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:APB_bif" "CoreAPB3_0:APBmslave2" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:APBslave" "CoreAPB3_0:APBmslave3" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:APBslave" "CoreAPB3_0:APBmslave4" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:APB_bif" "CoreAPB3_0:APBmslave5" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "COREAHBTOAPB3_0:APBmaster" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmslave8" "RTG4_SRAM_0:AHBSlaveInterface" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmslave7" "COREAHBTOAPB3_0:AHBslave" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:AHB_MST_MEM" "CoreAHBL_0:AHBmmaster1" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:AHB_MST_MMIO" "CoreAHBL_0:AHBmmaster0" }
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign BaseDesign
-generate_component -component_name ${sd_name} -recursive 1
-# ######################################################################################################################################
diff --git a/Libero_Projects/import/components/AXI/import_component_and_constraints_rtg4_dev_kit_axi.tcl b/Libero_Projects/import/components/AXI/import_component_and_constraints_rtg4_dev_kit_axi.tcl
deleted file mode 100644
index 1c3648d..0000000
--- a/Libero_Projects/import/components/AXI/import_component_and_constraints_rtg4_dev_kit_axi.tcl
+++ /dev/null
@@ -1,38 +0,0 @@
-set project_folder_name MiV_AXI_BD
-set project_dir2 "./$project_folder_name"
-
-
-puts "-------------------------------------------------------------------------"
-puts "-----------------------IMPORTING COMPONENTS------------------------------"
-puts "-------------------------------------------------------------------------"
-
-
-source ./import/components/AXI/top_level_rtg4_dev_kit_axi.tcl
-
-build_design_hierarchy
-set_root BaseDesign
-
-puts "-------------------------------------------------------------------------"
-puts "--------------------APPLYING DESIGN CONSTRAINTS--------------------------"
-puts "-------------------------------------------------------------------------"
-
-import_files -io_pdc ./import/constraints/io/io_constraints.pdc
-import_files -sdc    ./import/constraints/io_jtag_constraints.sdc
-
-## Associate SDC constraint file to Place and Route tool
-organize_tool_files -tool {PLACEROUTE} \
-    -file $project_dir2/constraint/io_jtag_constraints.sdc \
-    -file $project_dir2/constraint/io/io_constraints.pdc \
-    -module {BaseDesign::work} -input_type {constraint}
-
-organize_tool_files -tool {SYNTHESIZE} \
-    -file $project_dir2/constraint/io_jtag_constraints.sdc \
-    -module {BaseDesign::work} -input_type {constraint}
-
-organize_tool_files -tool {VERIFYTIMING} \
-    -file $project_dir2/constraint/io_jtag_constraints.sdc \
-    -module {BaseDesign::work} -input_type {constraint}
-set_root BaseDesign
-
-run_tool -name {CONSTRAINT_MANAGEMENT}
-derive_constraints_sdc
diff --git a/Libero_Projects/import/components/AXI/top_level_rtg4_dev_kit_axi.tcl b/Libero_Projects/import/components/AXI/top_level_rtg4_dev_kit_axi.tcl
deleted file mode 100644
index 3ca0c03..0000000
--- a/Libero_Projects/import/components/AXI/top_level_rtg4_dev_kit_axi.tcl
+++ /dev/null
@@ -1,829 +0,0 @@
-#RTG4 Dev Kit = RTG4150-1657CG
-#Libero's TCL top level script
-# Core: MiV_RV32IMA_L1_AXI
-#
-# Creating SmartDesign BaseDesign
-set sd_name {BaseDesign}
-create_smartdesign -sd_name ${sd_name}
-
-# Disable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 0
-
-# Creating the RTG4FCCC_0 instance
-create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:2.0.201} -component_name {RTG4FCCC_0} -params {\
-"ADVANCED_TAB_CHANGED:false" \
-"CLK0_IS_USED:false" \
-"CLK0_PAD_IS_USED:false" \
-"CLK1_IS_USED:false" \
-"CLK1_PAD_IS_USED:false" \
-"CLK2_IS_USED:false" \
-"CLK2_PAD_IS_USED:false" \
-"CLK3_IS_USED:false" \
-"CLK3_PAD_IS_USED:false" \
-"DYN_CONF_IS_USED:false" \
-"ENABLE_AUTO_RESET_LOGIC:false" \
-"EXPOSE_CGL_ENABLE_ARST_SIGNALS:false" \
-"GL0_BP_IN_0_FREQ:100" \
-"GL0_BP_IN_0_SRC:IO_HARDWIRED_0" \
-"GL0_BP_IN_1_FREQ:100" \
-"GL0_BP_IN_1_SRC:IO_HARDWIRED_0" \
-"GL0_FREQUENCY_LOCKED:false" \
-"GL0_IN_0_SRC:PLL" \
-"GL0_IN_1_SRC:UNUSED" \
-"GL0_IS_INVERTED:false" \
-"GL0_IS_USED:true" \
-"GL0_OUT_0_FREQ:50" \
-"GL0_OUT_1_FREQ:50" \
-"GL0_OUT_IS_GATED:false" \
-"GL0_PLL_IN_0_PHASE:0" \
-"GL0_PLL_IN_1_PHASE:0" \
-"GL1_BP_IN_0_FREQ:100" \
-"GL1_BP_IN_0_SRC:IO_HARDWIRED_0" \
-"GL1_BP_IN_1_FREQ:100" \
-"GL1_BP_IN_1_SRC:IO_HARDWIRED_0" \
-"GL1_FREQUENCY_LOCKED:false" \
-"GL1_IN_0_SRC:PLL" \
-"GL1_IN_1_SRC:UNUSED" \
-"GL1_IS_INVERTED:false" \
-"GL1_IS_USED:false" \
-"GL1_OUT_0_FREQ:50" \
-"GL1_OUT_1_FREQ:50" \
-"GL1_OUT_IS_GATED:false" \
-"GL1_PLL_IN_0_PHASE:0" \
-"GL1_PLL_IN_1_PHASE:0" \
-"GL2_BP_IN_0_FREQ:100" \
-"GL2_BP_IN_0_SRC:IO_HARDWIRED_0" \
-"GL2_BP_IN_1_FREQ:100" \
-"GL2_BP_IN_1_SRC:IO_HARDWIRED_0" \
-"GL2_FREQUENCY_LOCKED:false" \
-"GL2_IN_0_SRC:PLL" \
-"GL2_IN_1_SRC:UNUSED" \
-"GL2_IS_INVERTED:false" \
-"GL2_IS_USED:false" \
-"GL2_OUT_0_FREQ:100" \
-"GL2_OUT_1_FREQ:50" \
-"GL2_OUT_IS_GATED:false" \
-"GL2_PLL_IN_0_PHASE:0" \
-"GL2_PLL_IN_1_PHASE:0" \
-"GL3_BP_IN_0_FREQ:100" \
-"GL3_BP_IN_0_SRC:IO_HARDWIRED_0" \
-"GL3_BP_IN_1_FREQ:100" \
-"GL3_BP_IN_1_SRC:IO_HARDWIRED_0" \
-"GL3_FREQUENCY_LOCKED:false" \
-"GL3_IN_0_SRC:PLL" \
-"GL3_IN_1_SRC:UNUSED" \
-"GL3_IS_INVERTED:false" \
-"GL3_IS_USED:false" \
-"GL3_OUT_0_FREQ:100" \
-"GL3_OUT_1_FREQ:50" \
-"GL3_OUT_IS_GATED:false" \
-"GL3_PLL_IN_0_PHASE:0" \
-"GL3_PLL_IN_1_PHASE:0" \
-"GPD0_IS_USED:false" \
-"GPD0_NOPIPE_RSTSYNC:true" \
-"GPD0_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC" \
-"GPD1_IS_USED:false" \
-"GPD1_NOPIPE_RSTSYNC:true" \
-"GPD1_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC" \
-"GPD2_IS_USED:false" \
-"GPD2_NOPIPE_RSTSYNC:true" \
-"GPD2_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC" \
-"GPD3_IS_USED:false" \
-"GPD3_NOPIPE_RSTSYNC:true" \
-"GPD3_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC" \
-"GPD_EXPOSE_RESETS:false" \
-"GPD_SYNC_STYLE:G3STYLE_AND_LOCK_RSTSYNC" \
-"INCLUDE_RECONFIGURATION_LOGIC:true" \
-"INIT:088101249000020B80404040664C993186071C11C16C" \
-"IO_HARDWIRED_0_IS_DIFF:false" \
-"IO_HARDWIRED_1_IS_DIFF:false" \
-"IO_HARDWIRED_2_IS_DIFF:false" \
-"IO_HARDWIRED_3_IS_DIFF:false" \
-"MODE_10V:false" \
-"NGMUX0_HOLD_IS_USED:false" \
-"NGMUX1_HOLD_IS_USED:false" \
-"NGMUX2_HOLD_IS_USED:false" \
-"NGMUX3_HOLD_IS_USED:false" \
-"NGMUX_EXPOSE_HOLD:false" \
-"PLL_DELAY:0" \
-"PLL_EXPOSE_BYPASS:false" \
-"PLL_EXPOSE_READY_VDDPLL:false" \
-"PLL_EXPOSE_RESETS:false" \
-"PLL_EXT_FB_GL:EXT_FB_GL0" \
-"PLL_FB_SRC:CCC_INTERNAL" \
-"PLL_IN_FREQ:50.000" \
-"PLL_IN_SRC:OSC_50MHZ" \
-"PLL_IS_USED:true" \
-"PLL_LOCK_IND:1024" \
-"PLL_LOCK_WND:6000" \
-"PLL_SSM_DEPTH:0.5" \
-"PLL_SSM_ENABLE:false" \
-"PLL_SSM_FREQ:40" \
-"PLL_SUPPLY_VOLTAGE:25_V" \
-"PLL_VCO_TARGET:700" \
-"RCOSC_25_50MHZ_IS_USED:true" \
-"RX0_RECOVERY_BLOCK_DATA:Unused-Unused" \
-"RX0_RECOVERY_BLOCK_IS_USED:false" \
-"RX0_RECOVERY_BLOCK_STROBE:Unused" \
-"RX0_SPACE_WIRE_MODE_IS_USED:true" \
-"RX1_RECOVERY_BLOCK_DATA:Unused-Unused" \
-"RX1_RECOVERY_BLOCK_IS_USED:false" \
-"RX1_RECOVERY_BLOCK_STROBE:Unused" \
-"RX1_SPACE_WIRE_MODE_IS_USED:true" \
-"VCOFREQUENCY:800.000" \
-"Y0_IS_USED:false" \
-"Y1_IS_USED:false" \
-"Y2_IS_USED:false" \
-"Y3_IS_USED:false"	} 
-# Parameters for the RTG4FCCC_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0}
-
-
-
-# Add RCOSC_50MHZ_0 instance
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0}
-
-
-
-# Add reset_synchronizer_0 instance
-sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} 
-
-
-
-# Add SYSRESET_0 instance
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0}
-
-
-
-# Add AND2_0 instance
-sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} 
-
-
-
-# Creating the CoreAPB3_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.1.100} -component_name {CoreAPB3_0} -params {\
-"APB_DWIDTH:32"  \
-"APBSLOT0ENABLE:false"  \
-"APBSLOT1ENABLE:true"  \
-"APBSLOT2ENABLE:true"  \
-"APBSLOT3ENABLE:true"  \
-"APBSLOT4ENABLE:true"  \
-"APBSLOT5ENABLE:true"  \
-"APBSLOT6ENABLE:false"  \
-"APBSLOT7ENABLE:false"  \
-"APBSLOT8ENABLE:false"  \
-"APBSLOT9ENABLE:false"  \
-"APBSLOT10ENABLE:false"  \
-"APBSLOT11ENABLE:false"  \
-"APBSLOT12ENABLE:false"  \
-"APBSLOT13ENABLE:false"  \
-"APBSLOT14ENABLE:false"  \
-"APBSLOT15ENABLE:false"  \
-"IADDR_OPTION:0"  \
-"MADDR_BITS:16"  \
-"SC_0:false"  \
-"SC_1:false"  \
-"SC_2:false"  \
-"SC_3:false"  \
-"SC_4:false"  \
-"SC_5:false"  \
-"SC_6:false"  \
-"SC_7:false"  \
-"SC_8:false"  \
-"SC_9:false"  \
-"SC_10:false"  \
-"SC_11:false"  \
-"SC_12:false"  \
-"SC_13:false"  \
-"SC_14:false"  \
-"SC_15:false"  \
-"UPR_NIBBLE_POSN:6"   }
-# Parameters for CoreAPB3_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0}
-
-
-
-# Creating the COREAHBTOAPB3_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:COREAHBTOAPB3:3.1.100} -component_name {COREAHBTOAPB3_0} -params { }
-# Parameters for COREAHBTOAPB3_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0}
-
-
-
-# Creating the CoreAHBL_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.4.102} -component_name {CoreAHBL_0} -params {\
-"HADDR_SHG_CFG:1"  \
-"M0_AHBSLOT0ENABLE:false"  \
-"M0_AHBSLOT1ENABLE:false"  \
-"M0_AHBSLOT2ENABLE:false"  \
-"M0_AHBSLOT3ENABLE:false"  \
-"M0_AHBSLOT4ENABLE:false"  \
-"M0_AHBSLOT5ENABLE:false"  \
-"M0_AHBSLOT6ENABLE:false"  \
-"M0_AHBSLOT7ENABLE:true"  \
-"M0_AHBSLOT8ENABLE:false"  \
-"M0_AHBSLOT9ENABLE:false"  \
-"M0_AHBSLOT10ENABLE:false"  \
-"M0_AHBSLOT11ENABLE:false"  \
-"M0_AHBSLOT12ENABLE:false"  \
-"M0_AHBSLOT13ENABLE:false"  \
-"M0_AHBSLOT14ENABLE:false"  \
-"M0_AHBSLOT15ENABLE:false"  \
-"M0_AHBSLOT16ENABLE:false"  \
-"M1_AHBSLOT0ENABLE:false"  \
-"M1_AHBSLOT1ENABLE:false"  \
-"M1_AHBSLOT2ENABLE:false"  \
-"M1_AHBSLOT3ENABLE:false"  \
-"M1_AHBSLOT4ENABLE:false"  \
-"M1_AHBSLOT5ENABLE:false"  \
-"M1_AHBSLOT6ENABLE:false"  \
-"M1_AHBSLOT7ENABLE:false"  \
-"M1_AHBSLOT8ENABLE:true"  \
-"M1_AHBSLOT9ENABLE:false"  \
-"M1_AHBSLOT10ENABLE:false"  \
-"M1_AHBSLOT11ENABLE:false"  \
-"M1_AHBSLOT12ENABLE:false"  \
-"M1_AHBSLOT13ENABLE:false"  \
-"M1_AHBSLOT14ENABLE:false"  \
-"M1_AHBSLOT15ENABLE:false"  \
-"M1_AHBSLOT16ENABLE:false"  \
-"M2_AHBSLOT0ENABLE:false"  \
-"M2_AHBSLOT1ENABLE:false"  \
-"M2_AHBSLOT2ENABLE:false"  \
-"M2_AHBSLOT3ENABLE:false"  \
-"M2_AHBSLOT4ENABLE:false"  \
-"M2_AHBSLOT5ENABLE:false"  \
-"M2_AHBSLOT6ENABLE:false"  \
-"M2_AHBSLOT7ENABLE:false"  \
-"M2_AHBSLOT8ENABLE:false"  \
-"M2_AHBSLOT9ENABLE:false"  \
-"M2_AHBSLOT10ENABLE:false"  \
-"M2_AHBSLOT11ENABLE:false"  \
-"M2_AHBSLOT12ENABLE:false"  \
-"M2_AHBSLOT13ENABLE:false"  \
-"M2_AHBSLOT14ENABLE:false"  \
-"M2_AHBSLOT15ENABLE:false"  \
-"M2_AHBSLOT16ENABLE:false"  \
-"M3_AHBSLOT0ENABLE:false"  \
-"M3_AHBSLOT1ENABLE:false"  \
-"M3_AHBSLOT2ENABLE:false"  \
-"M3_AHBSLOT3ENABLE:false"  \
-"M3_AHBSLOT4ENABLE:false"  \
-"M3_AHBSLOT5ENABLE:false"  \
-"M3_AHBSLOT6ENABLE:false"  \
-"M3_AHBSLOT7ENABLE:false"  \
-"M3_AHBSLOT8ENABLE:false"  \
-"M3_AHBSLOT9ENABLE:false"  \
-"M3_AHBSLOT10ENABLE:false"  \
-"M3_AHBSLOT11ENABLE:false"  \
-"M3_AHBSLOT12ENABLE:false"  \
-"M3_AHBSLOT13ENABLE:false"  \
-"M3_AHBSLOT14ENABLE:false"  \
-"M3_AHBSLOT15ENABLE:false"  \
-"M3_AHBSLOT16ENABLE:false"  \
-"MASTER0_INTERFACE:1"	\
-"MASTER1_INTERFACE:1"	\
-"MASTER2_INTERFACE:1"	\
-"MASTER3_INTERFACE:1"	\
-"MEMSPACE:1"  \
-"SC_0:false"  \
-"SC_1:false"  \
-"SC_2:false"  \
-"SC_3:false"  \
-"SC_4:false"  \
-"SC_5:false"  \
-"SC_6:false"  \
-"SC_7:false"  \
-"SC_8:false"  \
-"SC_9:false"  \
-"SC_10:false"  \
-"SC_11:false"  \
-"SC_12:false"  \
-"SC_13:false"  \
-"SC_14:false"  \
-"SC_15:false"   \
-"SLAVE0_INTERFACE:1"	\
-"SLAVE1_INTERFACE:1"	\
-"SLAVE2_INTERFACE:1"	\
-"SLAVE3_INTERFACE:1"	\
-"SLAVE4_INTERFACE:1"	\
-"SLAVE5_INTERFACE:1"	\
-"SLAVE6_INTERFACE:1"	\
-"SLAVE7_INTERFACE:1"	\
-"SLAVE8_INTERFACE:1"	\
-"SLAVE9_INTERFACE:1"	\
-"SLAVE10_INTERFACE:1"	\
-"SLAVE11_INTERFACE:1"	\
-"SLAVE12_INTERFACE:1"	\
-"SLAVE13_INTERFACE:1"	\
-"SLAVE14_INTERFACE:1"	\
-"SLAVE15_INTERFACE:1"	\
-"SLAVE16_INTERFACE:1"	}
-# Parameters for CoreAHBL_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -instance_name {CoreAHBL_0}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND}
-
-
-
-# Creating the CoreGPIO_IN instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_IN} -params {\
-"APB_WIDTH:32"  \
-"FIXED_CONFIG_0:true"  \
-"FIXED_CONFIG_1:true"  \
-"FIXED_CONFIG_2:false"  \
-"FIXED_CONFIG_3:false"  \
-"FIXED_CONFIG_4:false"  \
-"FIXED_CONFIG_5:false"  \
-"FIXED_CONFIG_6:false"  \
-"FIXED_CONFIG_7:false"  \
-"FIXED_CONFIG_8:false"  \
-"FIXED_CONFIG_9:false"  \
-"FIXED_CONFIG_10:false"  \
-"FIXED_CONFIG_11:false"  \
-"FIXED_CONFIG_12:false"  \
-"FIXED_CONFIG_13:false"  \
-"FIXED_CONFIG_14:false"  \
-"FIXED_CONFIG_15:false"  \
-"FIXED_CONFIG_16:false"  \
-"FIXED_CONFIG_17:false"  \
-"FIXED_CONFIG_18:false"  \
-"FIXED_CONFIG_19:false"  \
-"FIXED_CONFIG_20:false"  \
-"FIXED_CONFIG_21:false"  \
-"FIXED_CONFIG_22:false"  \
-"FIXED_CONFIG_23:false"  \
-"FIXED_CONFIG_24:false"  \
-"FIXED_CONFIG_25:false"  \
-"FIXED_CONFIG_26:false"  \
-"FIXED_CONFIG_27:false"  \
-"FIXED_CONFIG_28:false"  \
-"FIXED_CONFIG_29:false"  \
-"FIXED_CONFIG_30:false"  \
-"FIXED_CONFIG_31:false"  \
-"INT_BUS:0"  \
-"IO_INT_TYPE_0:7"  \
-"IO_INT_TYPE_1:7"  \
-"IO_INT_TYPE_2:7"  \
-"IO_INT_TYPE_3:7"  \
-"IO_INT_TYPE_4:7"  \
-"IO_INT_TYPE_5:7"  \
-"IO_INT_TYPE_6:7"  \
-"IO_INT_TYPE_7:7"  \
-"IO_INT_TYPE_8:7"  \
-"IO_INT_TYPE_9:7"  \
-"IO_INT_TYPE_10:7"  \
-"IO_INT_TYPE_11:7"  \
-"IO_INT_TYPE_12:7"  \
-"IO_INT_TYPE_13:7"  \
-"IO_INT_TYPE_14:7"  \
-"IO_INT_TYPE_15:7"  \
-"IO_INT_TYPE_16:7"  \
-"IO_INT_TYPE_17:7"  \
-"IO_INT_TYPE_18:7"  \
-"IO_INT_TYPE_19:7"  \
-"IO_INT_TYPE_20:7"  \
-"IO_INT_TYPE_21:7"  \
-"IO_INT_TYPE_22:7"  \
-"IO_INT_TYPE_23:7"  \
-"IO_INT_TYPE_24:7"  \
-"IO_INT_TYPE_25:7"  \
-"IO_INT_TYPE_26:7"  \
-"IO_INT_TYPE_27:7"  \
-"IO_INT_TYPE_28:7"  \
-"IO_INT_TYPE_29:7"  \
-"IO_INT_TYPE_30:7"  \
-"IO_INT_TYPE_31:7"  \
-"IO_NUM:2"  \
-"IO_TYPE_0:0"  \
-"IO_TYPE_1:0"  \
-"IO_TYPE_2:0"  \
-"IO_TYPE_3:0"  \
-"IO_TYPE_4:0"  \
-"IO_TYPE_5:0"  \
-"IO_TYPE_6:0"  \
-"IO_TYPE_7:0"  \
-"IO_TYPE_8:0"  \
-"IO_TYPE_9:0"  \
-"IO_TYPE_10:0"  \
-"IO_TYPE_11:0"  \
-"IO_TYPE_12:0"  \
-"IO_TYPE_13:0"  \
-"IO_TYPE_14:0"  \
-"IO_TYPE_15:0"  \
-"IO_TYPE_16:0"  \
-"IO_TYPE_17:0"  \
-"IO_TYPE_18:0"  \
-"IO_TYPE_19:0"  \
-"IO_TYPE_20:0"  \
-"IO_TYPE_21:0"  \
-"IO_TYPE_22:0"  \
-"IO_TYPE_23:0"  \
-"IO_TYPE_24:0"  \
-"IO_TYPE_25:0"  \
-"IO_TYPE_26:0"  \
-"IO_TYPE_27:0"  \
-"IO_TYPE_28:0"  \
-"IO_TYPE_29:0"  \
-"IO_TYPE_30:0"  \
-"IO_TYPE_31:0"  \
-"IO_VAL_0:0"  \
-"IO_VAL_1:0"  \
-"IO_VAL_2:0"  \
-"IO_VAL_3:0"  \
-"IO_VAL_4:0"  \
-"IO_VAL_5:0"  \
-"IO_VAL_6:0"  \
-"IO_VAL_7:0"  \
-"IO_VAL_8:0"  \
-"IO_VAL_9:0"  \
-"IO_VAL_10:0"  \
-"IO_VAL_11:0"  \
-"IO_VAL_12:0"  \
-"IO_VAL_13:0"  \
-"IO_VAL_14:0"  \
-"IO_VAL_15:0"  \
-"IO_VAL_16:0"  \
-"IO_VAL_17:0"  \
-"IO_VAL_18:0"  \
-"IO_VAL_19:0"  \
-"IO_VAL_20:0"  \
-"IO_VAL_21:0"  \
-"IO_VAL_22:0"  \
-"IO_VAL_23:0"  \
-"IO_VAL_24:0"  \
-"IO_VAL_25:0"  \
-"IO_VAL_26:0"  \
-"IO_VAL_27:0"  \
-"IO_VAL_28:0"  \
-"IO_VAL_29:0"  \
-"IO_VAL_30:0"  \
-"IO_VAL_31:0"  \
-"OE_TYPE:1"   }
-# Parameters for CoreGPIO_IN
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT}
-
-
-
-# Creating CoreGPIO_OUT
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_OUT} -params {\
-"APB_WIDTH:32"  \
-"FIXED_CONFIG_0:true"  \
-"FIXED_CONFIG_1:true"  \
-"FIXED_CONFIG_2:true"  \
-"FIXED_CONFIG_3:true"  \
-"FIXED_CONFIG_4:false"  \
-"FIXED_CONFIG_5:false"  \
-"FIXED_CONFIG_6:false"  \
-"FIXED_CONFIG_7:false"  \
-"FIXED_CONFIG_8:false"  \
-"FIXED_CONFIG_9:false"  \
-"FIXED_CONFIG_10:false"  \
-"FIXED_CONFIG_11:false"  \
-"FIXED_CONFIG_12:false"  \
-"FIXED_CONFIG_13:false"  \
-"FIXED_CONFIG_14:false"  \
-"FIXED_CONFIG_15:false"  \
-"FIXED_CONFIG_16:false"  \
-"FIXED_CONFIG_17:false"  \
-"FIXED_CONFIG_18:false"  \
-"FIXED_CONFIG_19:false"  \
-"FIXED_CONFIG_20:false"  \
-"FIXED_CONFIG_21:false"  \
-"FIXED_CONFIG_22:false"  \
-"FIXED_CONFIG_23:false"  \
-"FIXED_CONFIG_24:false"  \
-"FIXED_CONFIG_25:false"  \
-"FIXED_CONFIG_26:false"  \
-"FIXED_CONFIG_27:false"  \
-"FIXED_CONFIG_28:false"  \
-"FIXED_CONFIG_29:false"  \
-"FIXED_CONFIG_30:false"  \
-"FIXED_CONFIG_31:false"  \
-"INT_BUS:0"  \
-"IO_INT_TYPE_0:7"  \
-"IO_INT_TYPE_1:7"  \
-"IO_INT_TYPE_2:7"  \
-"IO_INT_TYPE_3:7"  \
-"IO_INT_TYPE_4:7"  \
-"IO_INT_TYPE_5:7"  \
-"IO_INT_TYPE_6:7"  \
-"IO_INT_TYPE_7:7"  \
-"IO_INT_TYPE_8:7"  \
-"IO_INT_TYPE_9:7"  \
-"IO_INT_TYPE_10:7"  \
-"IO_INT_TYPE_11:7"  \
-"IO_INT_TYPE_12:7"  \
-"IO_INT_TYPE_13:7"  \
-"IO_INT_TYPE_14:7"  \
-"IO_INT_TYPE_15:7"  \
-"IO_INT_TYPE_16:7"  \
-"IO_INT_TYPE_17:7"  \
-"IO_INT_TYPE_18:7"  \
-"IO_INT_TYPE_19:7"  \
-"IO_INT_TYPE_20:7"  \
-"IO_INT_TYPE_21:7"  \
-"IO_INT_TYPE_22:7"  \
-"IO_INT_TYPE_23:7"  \
-"IO_INT_TYPE_24:7"  \
-"IO_INT_TYPE_25:7"  \
-"IO_INT_TYPE_26:7"  \
-"IO_INT_TYPE_27:7"  \
-"IO_INT_TYPE_28:7"  \
-"IO_INT_TYPE_29:7"  \
-"IO_INT_TYPE_30:7"  \
-"IO_INT_TYPE_31:7"  \
-"IO_NUM:4"  \
-"IO_TYPE_0:1"  \
-"IO_TYPE_1:1"  \
-"IO_TYPE_2:1"  \
-"IO_TYPE_3:1"  \
-"IO_TYPE_4:0"  \
-"IO_TYPE_5:0"  \
-"IO_TYPE_6:0"  \
-"IO_TYPE_7:0"  \
-"IO_TYPE_8:0"  \
-"IO_TYPE_9:0"  \
-"IO_TYPE_10:0"  \
-"IO_TYPE_11:0"  \
-"IO_TYPE_12:0"  \
-"IO_TYPE_13:0"  \
-"IO_TYPE_14:0"  \
-"IO_TYPE_15:0"  \
-"IO_TYPE_16:0"  \
-"IO_TYPE_17:0"  \
-"IO_TYPE_18:0"  \
-"IO_TYPE_19:0"  \
-"IO_TYPE_20:0"  \
-"IO_TYPE_21:0"  \
-"IO_TYPE_22:0"  \
-"IO_TYPE_23:0"  \
-"IO_TYPE_24:0"  \
-"IO_TYPE_25:0"  \
-"IO_TYPE_26:0"  \
-"IO_TYPE_27:0"  \
-"IO_TYPE_28:0"  \
-"IO_TYPE_29:0"  \
-"IO_TYPE_30:0"  \
-"IO_TYPE_31:0"  \
-"IO_VAL_0:0"  \
-"IO_VAL_1:0"  \
-"IO_VAL_2:0"  \
-"IO_VAL_3:0"  \
-"IO_VAL_4:0"  \
-"IO_VAL_5:0"  \
-"IO_VAL_6:0"  \
-"IO_VAL_7:0"  \
-"IO_VAL_8:0"  \
-"IO_VAL_9:0"  \
-"IO_VAL_10:0"  \
-"IO_VAL_11:0"  \
-"IO_VAL_12:0"  \
-"IO_VAL_13:0"  \
-"IO_VAL_14:0"  \
-"IO_VAL_15:0"  \
-"IO_VAL_16:0"  \
-"IO_VAL_17:0"  \
-"IO_VAL_18:0"  \
-"IO_VAL_19:0"  \
-"IO_VAL_20:0"  \
-"IO_VAL_21:0"  \
-"IO_VAL_22:0"  \
-"IO_VAL_23:0"  \
-"IO_VAL_24:0"  \
-"IO_VAL_25:0"  \
-"IO_VAL_26:0"  \
-"IO_VAL_27:0"  \
-"IO_VAL_28:0"  \
-"IO_VAL_29:0"  \
-"IO_VAL_30:0"  \
-"IO_VAL_31:0"  \
-"OE_TYPE:1"   }
-# Parameters for CoreGPIO_OUT
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND}
-
-
-
-# Creating the CoreTimer_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreTimer:2.0.103} -component_name {CoreTimer_0} -params {\
-"INTACTIVEH:1"  \
-"WIDTH:32"   }
-# Parameters for CoreTimer_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0}
-
-
-
-# Creating the CoreTimer_1 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreTimer:2.0.103} -component_name {CoreTimer_1} -params {\
-"INTACTIVEH:1"  \
-"WIDTH:32"   }
-# Parameters for CoreTimer_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1}
-
-
-
-# Creating the CoreUARTapb_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreUARTapb:5.6.102} -component_name {CoreUARTapb_0} -params {\
-"BAUD_VAL_FRCTN:0"  \
-"BAUD_VAL_FRCTN_EN:false"  \
-"BAUD_VALUE:1"  \
-"FIXEDMODE:0"  \
-"PRG_BIT8:0"  \
-"PRG_PARITY:0"  \
-"RX_FIFO:0"  \
-"RX_LEGACY_MODE:0"  \
-"TX_FIFO:0"  \
-"USE_SOFT_FIFO:0"   }
-# Parameters for CoreUARTapb_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR}
-
-
-
-# Creating the CoreJTAGDebug_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:COREJTAGDEBUG:3.1.100} -component_name {CoreJTAGDebug_0} -params {\
-"IR_CODE_TGT_0:0x55" \
-"IR_CODE_TGT_1:0x56" \
-"IR_CODE_TGT_2:0x57" \
-"IR_CODE_TGT_3:0x58" \
-"IR_CODE_TGT_4:0x59" \
-"IR_CODE_TGT_5:0x5a" \
-"IR_CODE_TGT_6:0x5b" \
-"IR_CODE_TGT_7:0x5c" \
-"IR_CODE_TGT_8:0x5d" \
-"IR_CODE_TGT_9:0x5e" \
-"IR_CODE_TGT_10:0x5f" \
-"IR_CODE_TGT_11:0x60" \
-"IR_CODE_TGT_12:0x61" \
-"IR_CODE_TGT_13:0x62" \
-"IR_CODE_TGT_14:0x63" \
-"IR_CODE_TGT_15:0x64" \
-"NUM_DEBUG_TGTS:1" \
-"Testbench:User" \
-"TGT_ACTIVE_HIGH_RESET_0:true" \
-"TGT_ACTIVE_HIGH_RESET_1:true" \
-"TGT_ACTIVE_HIGH_RESET_2:true" \
-"TGT_ACTIVE_HIGH_RESET_3:true" \
-"TGT_ACTIVE_HIGH_RESET_4:true" \
-"TGT_ACTIVE_HIGH_RESET_5:true" \
-"TGT_ACTIVE_HIGH_RESET_6:true" \
-"TGT_ACTIVE_HIGH_RESET_7:true" \
-"TGT_ACTIVE_HIGH_RESET_8:true" \
-"TGT_ACTIVE_HIGH_RESET_9:true" \
-"TGT_ACTIVE_HIGH_RESET_10:true" \
-"TGT_ACTIVE_HIGH_RESET_11:true" \
-"TGT_ACTIVE_HIGH_RESET_12:true" \
-"TGT_ACTIVE_HIGH_RESET_13:true" \
-"TGT_ACTIVE_HIGH_RESET_14:true" \
-"TGT_ACTIVE_HIGH_RESET_15:true" \
-"UJTAG_BYPASS:false" }
-# Parameters for CoreJTAGDebug_0 instance
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0}
-
-
-
-# Creating the RTG4_SRAM_0 instance
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.107} -component_name {RTG4_SRAM_0} -params {\
-"AXI4_AWIDTH:32" \
-"AXI4_DWIDTH:32" \
-"AXI4_IDWIDTH:8" \
-"AXI4_IFTYPE_RD:T" \
-"AXI4_IFTYPE_WR:T" \
-"AXI4_WRAP_SUPPORT:F" \
-"BYTEENABLES:1" \
-"BYTE_ENABLE_WIDTH:4" \
-"B_REN_POLARITY:2" \
-"CASCADE:1" \
-"ECC_OPTIONS:0" \
-"FABRIC_INTERFACE_TYPE:0" \
-"IMPORT_FILE:" \
-"INIT_RAM:F" \
-"LPM_HINT:0" \
-"PIPELINE_OPTIONS:1" \
-"RDEPTH:65536" \
-"RWIDTH:36" \
-"USE_NATIVE_INTERFACE:F" \
-"WDEPTH:65536" \
-"WWIDTH:36"} 
-# Instantiating the RTG4_SRAM_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0}
-
-
-
-# Creating the MiV_RV32IMA_L1_AXI_0 instance
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -component_name {MiV_RV32IMA_L1_AXI_0} -params {\
-"MASTER_TYPE:0" \
-"MEM_WID:5" \
-"MMIO_WID:5" \
-"RESET_VECTOR_ADDR_0:0x0" \
-"RESET_VECTOR_ADDR_1:0x8000"} 
-# Parameters for MiV_RV32IMA_L1_AXI_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {MiV_RV32IMA_L1_AXI_0} -instance_name {MiV_RV32IMA_L1_AXI_0}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AXI_0:IRQ} -pin_slices {[28:0]}
-sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AXI_0:IRQ[28:0]} -value {GND}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AXI_0:IRQ} -pin_slices {[29]}
-sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AXI_0:IRQ} -pin_slices {[30]}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AXI_0:MEM_MST_AXI}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AXI_0:MMIO_MST_AXI}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AXI_0:EXT_RESETN}
-sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AXI_0:DRV_TDO}
-
-
-
-# Creating the CoreAXITOAHBL_0 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXITOAHBL:3.5.100} -component_name {CoreAXITOAHBL_0} -params {\
-"ASYNC_CLOCKS:false" \
-"AXI_DWIDTH:64" \
-"AXI_SEL_MM_S:1" \
-"EXPOSE_WID:false" \
-"ID_WIDTH:5" \
-"NO_BURST_TRANS:false" \
-"WRAP_SUPPORT:false"}
-# Parameters for CoreAXITOAHBL_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAXITOAHBL_0} -instance_name {CoreAXITOAHBL_0}
-
-
-
-# Creating the CoreAXITOAHBL_1 instance
-create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXITOAHBL:3.5.100} -component_name {CoreAXITOAHBL_1} -params {\
-"ASYNC_CLOCKS:false" \
-"AXI_DWIDTH:64" \
-"AXI_SEL_MM_S:1" \
-"EXPOSE_WID:false" \
-"ID_WIDTH:5" \
-"NO_BURST_TRANS:false" \
-"WRAP_SUPPORT:false"}
-# Parameters for CoreAXITOAHBL_0
-sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAXITOAHBL_1} -instance_name {CoreAXITOAHBL_1}
-
-
-
-# Create top level Ports
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
-sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN}
-sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_IN} -port_direction {IN} -port_range {[1:0]}
-sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT} -port_range {[3:0]}
-
-
-# Add scalar net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4FCCC_0:GL0" "reset_synchronizer_0:clock" "CoreAXITOAHBL_0:ACLK" "CoreAXITOAHBL_1:ACLK" "CoreAXITOAHBL_0:HCLK" "CoreAXITOAHBL_1:HCLK" "CoreAHBL_0:HCLK" "CoreGPIO_IN:PCLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "CoreUARTapb_0:PCLK" "CoreGPIO_OUT:PCLK" "COREAHBTOAPB3_0:HCLK" "MiV_RV32IMA_L1_AXI_0:CLK" "RTG4_SRAM_0:HCLK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVRST_N" "SYSRESET_0:DEVRST_N" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4FCCC_0:RCOSC_50MHZ" "RCOSC_50MHZ_0:CLKOUT" } 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AXI_0:IRQ[29]" "CoreTimer_0:TIMINT" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AXI_0:IRQ[30]" "CoreTimer_1:TIMINT" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AXI_0:TCK" "CoreJTAGDebug_0:TGT_TCK_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AXI_0:TDI" "CoreJTAGDebug_0:TGT_TDI_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AXI_0:TMS" "CoreJTAGDebug_0:TGT_TMS_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AXI_0:TRST" "CoreJTAGDebug_0:TGT_TRSTB_0" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MiV_RV32IMA_L1_AXI_0:TDO" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:reset_sync" "CoreAXITOAHBL_0:ARESETN" "CoreAXITOAHBL_1:ARESETN" "CoreAXITOAHBL_0:HRESETN" "CoreAXITOAHBL_1:HRESETN" "CoreAHBL_0:HRESETN" "CoreGPIO_IN:PRESETN" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "CoreUARTapb_0:PRESETN" "CoreGPIO_OUT:PRESETN" "COREAHBTOAPB3_0:HRESETN" "MiV_RV32IMA_L1_AXI_0:RESETN" "RTG4_SRAM_0:HRESETN" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"RX" "CoreUARTapb_0:RX" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TCK" "CoreJTAGDebug_0:TCK" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TDI" "CoreJTAGDebug_0:TDI" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TDO" "CoreJTAGDebug_0:TDO" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TMS" "CoreJTAGDebug_0:TMS" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TRSTB" "CoreJTAGDebug_0:TRSTB" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"TX" "CoreUARTapb_0:TX" }
-
-# Add bus net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_IN" "CoreGPIO_IN:GPIO_IN" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT" "GPIO_OUT" }
-
-# Add bus interface net connections
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAXITOAHBL_0:AHBMasterIF" "CoreAHBL_0:AHBmmaster0"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAXITOAHBL_1:AHBMasterIF" "CoreAHBL_0:AHBmmaster1"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmslave7" "COREAHBTOAPB3_0:AHBslave"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmslave8" "RTG4_SRAM_0:AHBSlaveInterface"}
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AXI_0:MEM_MST_AXI" "CoreAXITOAHBL_1:AXI_MM_IF"} 
-sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AXI_0:MMIO_MST_AXI" "CoreAXITOAHBL_0:AXI_MM_IF"} 
-
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:APB_bif" "CoreAPB3_0:APBmslave1" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:APB_bif" "CoreAPB3_0:APBmslave2" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:APBslave" "CoreAPB3_0:APBmslave3" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:APBslave" "CoreAPB3_0:APBmslave4" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:APB_bif" "CoreAPB3_0:APBmslave5" }
-sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "COREAHBTOAPB3_0:APBmaster" }
-
-# Re-enable auto promotion of pins of type 'pad'
-auto_promote_pad_pins -promote_all 1
-# Save the smartDesign
-save_smartdesign -sd_name ${sd_name}
-# Generate SmartDesign BaseDesign
-generate_component -component_name ${sd_name} -recursive 1
-# ######################################################################################################################################
diff --git a/Libero_Projects/import/components/IMAF_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imaf_cfg1.tcl b/Libero_Projects/import/components/IMAF_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imaf_cfg1.tcl
new file mode 100644
index 0000000..c4b5ec3
--- /dev/null
+++ b/Libero_Projects/import/components/IMAF_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imaf_cfg1.tcl
@@ -0,0 +1,46 @@
+set project_folder_name MiV_CFG1_BD
+set project_dir2 "./$project_folder_name"
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Importing Components..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+source ./import/components/IMAF_CFG1/top_level_rtg4_dev_kit_rv32imaf_cfg1.tcl
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Components Imported."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+build_design_hierarchy
+set_root BaseDesign
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Applying Design Constraints..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+import_files -io_pdc ./import/constraints/io/io_constraints.pdc
+import_files -sdc ./import/constraints/io_jtag_constraints.sdc
+
+
+# #Associate SDC constraint file to Place and Route tool
+organize_tool_files -tool {PLACEROUTE} \
+    -file $project_dir2/constraint/io/io_constraints.pdc \
+    -file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {SYNTHESIZE} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {VERIFYTIMING} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+set_root BaseDesign
+run_tool -name {CONSTRAINT_MANAGEMENT}
+derive_constraints_sdc
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Design Constraints Applied."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
diff --git a/Libero_Projects/import/components/IMAF_CFG1/top_level_rtg4_dev_kit_rv32imaf_cfg1.tcl b/Libero_Projects/import/components/IMAF_CFG1/top_level_rtg4_dev_kit_rv32imaf_cfg1.tcl
new file mode 100644
index 0000000..7a2e62d
--- /dev/null
+++ b/Libero_Projects/import/components/IMAF_CFG1/top_level_rtg4_dev_kit_rv32imaf_cfg1.tcl
@@ -0,0 +1,201 @@
+#RTG4 Dev Kit = RTG4150-1657CG
+#Libero's TCL top level script
+# Core: MiV_RV32IMAF_L1_AHB
+#
+#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion
+
+#Importing and Linking all the HDL source files used in the design
+import_files -hdl_source ./import/hdl/reset_synchronizer.v
+build_design_hierarchy
+
+#Sourcing the Tcl files for creating individual components under the top level
+source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl 
+source ./import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl 
+source ./import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl 
+source ./import/components/SHARED_COMPONENTS/MIV_RV32IMAF_L1_AHB_0.tcl 
+
+# Creating SmartDesign BaseDesign
+set sd_name {BaseDesign}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT}
+
+# Add CoreAHBL_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -instance_name {CoreAHBL_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND}
+
+
+
+# Add COREAHBTOAPB3_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0}
+
+
+
+# Add CoreAPB3_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0}
+
+
+
+# Add CoreGPIO_IN instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} 
+
+
+
+# Add CoreGPIO_OUT instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} 
+
+
+
+# Add CoreJTAGDebug_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_1} -instance_name {CoreJTAGDebug_1}
+
+
+
+# Add CoreTimer_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0}
+
+
+
+# Add CoreTimer_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1}
+
+
+
+# Add CoreUARTapb_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR}
+
+
+
+# Add MiV_RV32IMAF_L1_AHB_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32IMAF_L1_AHB_0} -instance_name {MiV_RV32IMAF_L1_AHB_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMAF_L1_AHB_0:IRQ} -pin_slices {[28:0]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MiV_RV32IMAF_L1_AHB_0:IRQ[28:0]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMAF_L1_AHB_0:IRQ} -pin_slices {[29]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMAF_L1_AHB_0:IRQ} -pin_slices {[30]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMAF_L1_AHB_0:AHB_MST_MEM_HSEL}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMAF_L1_AHB_0:AHB_MST_MMIO_HSEL}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMAF_L1_AHB_0:DRV_TDO}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMAF_L1_AHB_0:EXT_RESETN}
+
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add RCOSC_50MHZ_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0}
+
+
+
+# Add reset_synchronizer_0 instance
+sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0}
+
+
+
+# Add RTG4_SRAM_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0}
+
+
+
+# Add RTG4FCCC_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0}
+
+
+
+# Add SYSRESET_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMAF_L1_AHB_0:TCK" "CoreJTAGDebug_1:TGT_TCK_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMAF_L1_AHB_0:TDI" "CoreJTAGDebug_1:TGT_TDI_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMAF_L1_AHB_0:TMS" "CoreJTAGDebug_1:TGT_TMS_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMAF_L1_AHB_0:TRST" "CoreJTAGDebug_1:TGT_TRSTB_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:reset_sync" "COREAHBTOAPB3_0:HRESETN" "CoreTimer_1:PRESETn" "MiV_RV32IMAF_L1_AHB_0:RESETN" "RTG4_SRAM_0:HRESETN" "CoreGPIO_IN:PRESETN" "CoreGPIO_OUT:PRESETN" "CoreAHBL_0:HRESETN" "CoreTimer_0:PRESETn" "CoreUARTapb_0:PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMAF_L1_AHB_0:IRQ[29]" "CoreTimer_0:TIMINT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MiV_RV32IMAF_L1_AHB_0:IRQ[30]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMAF_L1_AHB_0:TDO" "CoreJTAGDebug_1:TGT_TDO_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:clock" "COREAHBTOAPB3_0:HCLK" "RTG4FCCC_0:GL0" "CoreTimer_1:PCLK" "MiV_RV32IMAF_L1_AHB_0:CLK" "RTG4_SRAM_0:HCLK" "CoreUARTapb_0:PCLK" "CoreGPIO_IN:PCLK" "CoreGPIO_OUT:PCLK" "CoreAHBL_0:HCLK" "CoreTimer_0:PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TCK" "CoreJTAGDebug_1:TCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDI" "TDI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDO" "TDO" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TMS" "TMS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"TRSTB" "CoreJTAGDebug_1:TRSTB" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "PUSH_BTN_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "PUSH_BTN_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_0:AHBslave" "CoreAHBL_0:AHBmslave7" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4_SRAM_0:AHBSlaveInterface" "CoreAHBL_0:AHBmslave8" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "COREAHBTOAPB3_0:APBmaster" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave1" "CoreUARTapb_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave2" "CoreGPIO_IN:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave3" "CoreTimer_0:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave4" "CoreTimer_1:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave5" "CoreGPIO_OUT:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMAF_L1_AHB_0:AHB_MST_MEM" "CoreAHBL_0:AHBmmaster1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmmaster0" "MiV_RV32IMAF_L1_AHB_0:AHB_MST_MMIO" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign BaseDesign
+generate_component -component_name ${sd_name}
diff --git a/Libero_Projects/import/components/IMA_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg1.tcl b/Libero_Projects/import/components/IMA_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg1.tcl
new file mode 100644
index 0000000..5d01215
--- /dev/null
+++ b/Libero_Projects/import/components/IMA_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg1.tcl
@@ -0,0 +1,46 @@
+set project_folder_name MiV_CFG1_BD
+set project_dir2 "./$project_folder_name"
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Importing Components..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+source ./import/components/IMA_CFG1/top_level_rtg4_dev_kit_rv32ima_cfg1.tcl
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Components Imported."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+build_design_hierarchy
+set_root BaseDesign
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Applying Design Constraints..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+import_files -io_pdc ./import/constraints/io/io_constraints.pdc
+import_files -sdc ./import/constraints/io_jtag_constraints.sdc
+
+
+# #Associate SDC constraint file to Place and Route tool
+organize_tool_files -tool {PLACEROUTE} \
+    -file $project_dir2/constraint/io/io_constraints.pdc \
+    -file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {SYNTHESIZE} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {VERIFYTIMING} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+set_root BaseDesign
+run_tool -name {CONSTRAINT_MANAGEMENT}
+derive_constraints_sdc
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Design Constraints Applied."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
diff --git a/Libero_Projects/import/components/IMA_CFG1/top_level_rtg4_dev_kit_rv32ima_cfg1.tcl b/Libero_Projects/import/components/IMA_CFG1/top_level_rtg4_dev_kit_rv32ima_cfg1.tcl
new file mode 100644
index 0000000..a6a2f9b
--- /dev/null
+++ b/Libero_Projects/import/components/IMA_CFG1/top_level_rtg4_dev_kit_rv32ima_cfg1.tcl
@@ -0,0 +1,202 @@
+#RTG4 Dev Kit = RTG4150-1657CG
+#Libero's TCL top level script
+# Core: MiV_RV32IMA_L1_AHB
+#
+#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion
+
+#Importing and Linking all the HDL source files used in the design
+import_files -hdl_source ./import/hdl/reset_synchronizer.v
+build_design_hierarchy
+
+#Sourcing the Tcl files for creating individual components under the top level
+source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl 
+source ./import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl 
+source ./import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl 
+source ./import/components/SHARED_COMPONENTS/MiV_RV32IMA_L1_AHB_0.tcl 
+
+# Creating SmartDesign BaseDesign
+set sd_name {BaseDesign}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT}
+
+
+
+# Add CoreAHBL_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -instance_name {CoreAHBL_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND}
+
+
+
+# Add COREAHBTOAPB3_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0}
+
+
+
+# Add CoreAPB3_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0}
+
+
+
+# Add CoreGPIO_IN instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} 
+
+
+
+# Add CoreGPIO_OUT instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} 
+
+
+
+# Add CoreJTAGDebug_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_1} -instance_name {CoreJTAGDebug_1}
+
+
+
+# Add CoreTimer_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0}
+
+
+
+# Add CoreTimer_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1}
+
+
+
+# Add CoreUARTapb_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR}
+
+
+
+# Add MiV_RV32IMA_L1_AHB_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {MiV_RV32IMA_L1_AHB_0} -instance_name {MiV_RV32IMA_L1_AHB_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AHB_0:IRQ} -pin_slices {[28:0]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AHB_0:IRQ[28:0]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AHB_0:IRQ} -pin_slices {[29]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AHB_0:IRQ} -pin_slices {[30]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AHB_0:AHB_MST_MEM_HSEL}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AHB_0:AHB_MST_MMIO_HSEL}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AHB_0:EXT_RESETN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AHB_0:DRV_TDO}
+
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add RCOSC_50MHZ_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0}
+
+
+
+# Add reset_synchronizer_0 instance
+sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0}
+
+
+
+# Add RTG4_SRAM_AHBL_AXI_C0_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0}
+
+
+
+# Add RTG4FCCC_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0}
+
+
+
+# Add SYSRESET_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:TCK" "CoreJTAGDebug_1:TGT_TCK_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:TDI" "CoreJTAGDebug_1:TGT_TDI_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:TMS" "CoreJTAGDebug_1:TGT_TMS_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:TRST" "CoreJTAGDebug_1:TGT_TRSTB_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MiV_RV32IMA_L1_AHB_0:IRQ[29]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MiV_RV32IMA_L1_AHB_0:IRQ[30]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:TDO" "CoreJTAGDebug_1:TGT_TDO_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:PRESETN" "MiV_RV32IMA_L1_AHB_0:RESETN" "CoreAHBL_0:HRESETN" "CoreGPIO_OUT:PRESETN" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "CoreGPIO_IN:PRESETN" "reset_synchronizer_0:reset_sync" "RTG4_SRAM_0:HRESETN" "COREAHBTOAPB3_0:HRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:PCLK" "MiV_RV32IMA_L1_AHB_0:CLK" "CoreAHBL_0:HCLK" "CoreGPIO_OUT:PCLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "CoreGPIO_IN:PCLK" "reset_synchronizer_0:clock" "RTG4FCCC_0:GL0" "RTG4_SRAM_0:HCLK" "COREAHBTOAPB3_0:HCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TCK" "TCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDI" "TDI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDO" "TDO" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TMS" "TMS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TRSTB" "TRSTB" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "PUSH_BTN_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "PUSH_BTN_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" }
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_0:AHBslave" "CoreAHBL_0:AHBmslave7" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4_SRAM_0:AHBSlaveInterface" "CoreAHBL_0:AHBmslave8" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_0:APBmaster" "CoreAPB3_0:APB3mmaster" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:APB_bif" "CoreAPB3_0:APBmslave1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:APB_bif" "CoreAPB3_0:APBmslave2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:APBslave" "CoreAPB3_0:APBmslave3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:APBslave" "CoreAPB3_0:APBmslave4" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:APB_bif" "CoreAPB3_0:APBmslave5" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:AHB_MST_MEM" "CoreAHBL_0:AHBmmaster1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AHB_0:AHB_MST_MMIO" "CoreAHBL_0:AHBmmaster0" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign BaseDesign
+generate_component -component_name ${sd_name}
diff --git a/Libero_Projects/import/components/IMA_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg2.tcl b/Libero_Projects/import/components/IMA_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg2.tcl
new file mode 100644
index 0000000..bca96ea
--- /dev/null
+++ b/Libero_Projects/import/components/IMA_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg2.tcl
@@ -0,0 +1,46 @@
+set project_folder_name MiV_CFG2_BD
+set project_dir2 "./$project_folder_name"
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Importing Components..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+source ./import/components/IMA_CFG2/top_level_rtg4_dev_kit_rv32ima_cfg2.tcl
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Components Imported."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+build_design_hierarchy
+set_root BaseDesign
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Applying Design Constraints..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+import_files -io_pdc ./import/constraints/io/io_constraints.pdc
+import_files -sdc ./import/constraints/io_jtag_constraints.sdc
+
+
+# #Associate SDC constraint file to Place and Route tool
+organize_tool_files -tool {PLACEROUTE} \
+    -file $project_dir2/constraint/io/io_constraints.pdc \
+    -file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {SYNTHESIZE} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {VERIFYTIMING} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+set_root BaseDesign
+run_tool -name {CONSTRAINT_MANAGEMENT}
+derive_constraints_sdc
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Design Constraints Applied."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
diff --git a/Libero_Projects/import/components/IMA_CFG2/top_level_rtg4_dev_kit_rv32ima_cfg2.tcl b/Libero_Projects/import/components/IMA_CFG2/top_level_rtg4_dev_kit_rv32ima_cfg2.tcl
new file mode 100644
index 0000000..d513ba6
--- /dev/null
+++ b/Libero_Projects/import/components/IMA_CFG2/top_level_rtg4_dev_kit_rv32ima_cfg2.tcl
@@ -0,0 +1,213 @@
+#RTG4 Dev Kit = RTG4150-1657CG
+#Libero's TCL top level script
+# Core: MiV_RV32IMA_L1_AXI
+#
+#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion
+
+#Importing and Linking all the HDL source files used in the design
+import_files -hdl_source ./import/hdl/reset_synchronizer.v
+build_design_hierarchy
+
+#Sourcing the Tcl files for creating individual components under the top level
+source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl 
+source ./import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl 
+source ./import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAXITOAHBL_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAXITOAHBL_1.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl 
+source ./import/components/SHARED_COMPONENTS/MiV_RV32IMA_L1_AXI_0.tcl 
+
+# Creating SmartDesign BaseDesign
+set sd_name {BaseDesign}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT}
+
+# Add CoreAHBL_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -instance_name {CoreAHBL_0}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND}
+
+
+
+# Add COREAHBTOAPB3_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0}
+
+
+
+# Add CoreAPB3_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0}
+
+
+
+# Add CoreAXITOAHBL_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAXITOAHBL_0} -instance_name {CoreAXITOAHBL_0}
+
+
+
+# Add CoreAXITOAHBL_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAXITOAHBL_1} -instance_name {CoreAXITOAHBL_1}
+
+
+
+# Add CoreGPIO_IN instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} 
+
+
+
+# Add CoreGPIO_OUT instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} 
+
+
+
+# Add CoreJTAGDebug_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_1} -instance_name {CoreJTAGDebug_1}
+
+
+
+# Add CoreTimer_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0}
+
+
+
+# Add CoreTimer_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1}
+
+
+
+# Add CoreUARTapb_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR}
+
+
+
+# Add MiV_RV32IMA_L1_AXI_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {MiV_RV32IMA_L1_AXI_0} -instance_name {MiV_RV32IMA_L1_AXI_0}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AXI_0:IRQ} -pin_slices {[28:0]}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AXI_0:IRQ[28:0]} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AXI_0:IRQ} -pin_slices {[29]}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {MiV_RV32IMA_L1_AXI_0:IRQ} -pin_slices {[30]}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AXI_0:DRV_TDO}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32IMA_L1_AXI_0:EXT_RESETN}
+
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add RCOSC_50MHZ_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0}
+
+
+
+# Add reset_synchronizer_0 instance
+sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0}
+
+
+
+# Add RTG4_SRAM_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0}
+
+
+
+# Add RTG4FCCC_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0}
+
+
+
+# Add SYSRESET_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TGT_TCK_0" "MiV_RV32IMA_L1_AXI_0:TCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TGT_TDI_0" "MiV_RV32IMA_L1_AXI_0:TDI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TGT_TMS_0" "MiV_RV32IMA_L1_AXI_0:TMS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TGT_TRSTB_0" "MiV_RV32IMA_L1_AXI_0:TRST" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:reset_sync" "RTG4_SRAM_0:HRESETN" "CoreTimer_1:PRESETn" "COREAHBTOAPB3_0:HRESETN" "CoreGPIO_OUT:PRESETN" "CoreAHBL_0:HRESETN" "CoreTimer_0:PRESETn" "CoreUARTapb_0:PRESETN" "CoreGPIO_IN:PRESETN" "CoreAXITOAHBL_0:HRESETN" "CoreAXITOAHBL_0:ARESETN" "MiV_RV32IMA_L1_AXI_0:RESETN" "CoreAXITOAHBL_1:ARESETN" "CoreAXITOAHBL_1:HRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MiV_RV32IMA_L1_AXI_0:IRQ[29]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MiV_RV32IMA_L1_AXI_0:IRQ[30]" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TGT_TDO_0" "MiV_RV32IMA_L1_AXI_0:TDO" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:clock" "RTG4_SRAM_0:HCLK" "CoreTimer_1:PCLK" "COREAHBTOAPB3_0:HCLK" "CoreGPIO_OUT:PCLK" "CoreAHBL_0:HCLK" "CoreTimer_0:PCLK" "CoreUARTapb_0:PCLK" "CoreGPIO_IN:PCLK" "RTG4FCCC_0:GL0" "CoreAXITOAHBL_0:HCLK" "CoreAXITOAHBL_0:ACLK" "MiV_RV32IMA_L1_AXI_0:CLK" "CoreAXITOAHBL_1:ACLK" "CoreAXITOAHBL_1:HCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TCK" "TCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDI" "TDI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDO" "TDO" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TMS" "TMS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TRSTB" "TRSTB" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "PUSH_BTN_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "PUSH_BTN_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmslave7" "COREAHBTOAPB3_0:AHBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmslave8" "RTG4_SRAM_0:AHBSlaveInterface" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "COREAHBTOAPB3_0:APBmaster" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave1" "CoreUARTapb_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave2" "CoreGPIO_IN:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave3" "CoreTimer_0:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave4" "CoreTimer_1:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave5" "CoreGPIO_OUT:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmmaster0" "CoreAXITOAHBL_0:AHBMasterIF" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmmaster1" "CoreAXITOAHBL_1:AHBMasterIF" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AXI_0:MEM_MST_AXI" "CoreAXITOAHBL_1:AXI_MM_IF" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32IMA_L1_AXI_0:MMIO_MST_AXI" "CoreAXITOAHBL_0:AXI_MM_IF" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign BaseDesign
+generate_component -component_name ${sd_name}
diff --git a/Libero_Projects/import/components/IMC_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg1.tcl b/Libero_Projects/import/components/IMC_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg1.tcl
new file mode 100644
index 0000000..2765ad5
--- /dev/null
+++ b/Libero_Projects/import/components/IMC_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg1.tcl
@@ -0,0 +1,46 @@
+set project_folder_name MiV_CFG1_BD
+set project_dir2 "./$project_folder_name"
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Importing Components..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+source ./import/components/IMC_CFG1/top_level_rtg4_dev_kit_rv32imc_cfg1.tcl
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Components Imported."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+build_design_hierarchy
+set_root BaseDesign
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Applying Design Constraints..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+import_files -io_pdc ./import/constraints/io/io_constraints.pdc
+import_files -sdc ./import/constraints/io_jtag_constraints.sdc
+
+
+# #Associate SDC constraint file to Place and Route tool
+organize_tool_files -tool {PLACEROUTE} \
+    -file $project_dir2/constraint/io/io_constraints.pdc \
+    -file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {SYNTHESIZE} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {VERIFYTIMING} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+set_root BaseDesign
+run_tool -name {CONSTRAINT_MANAGEMENT}
+derive_constraints_sdc
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Design Constraints Applied."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
diff --git a/Libero_Projects/import/components/IMC_CFG1/top_level_rtg4_dev_kit_rv32imc_cfg1.tcl b/Libero_Projects/import/components/IMC_CFG1/top_level_rtg4_dev_kit_rv32imc_cfg1.tcl
new file mode 100644
index 0000000..a3aaa1b
--- /dev/null
+++ b/Libero_Projects/import/components/IMC_CFG1/top_level_rtg4_dev_kit_rv32imc_cfg1.tcl
@@ -0,0 +1,180 @@
+#RTG4 Dev Kit = RTG4150-1657CG
+#Libero's TCL top level script
+# Core: MiV_RV32IMC
+#
+#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion
+
+#Importing and Linking all the HDL source files used in the design
+import_files -hdl_source ./import/hdl/reset_synchronizer.v
+build_design_hierarchy
+
+#Sourcing the Tcl files for creating individual components under the top level
+source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl 
+source ./import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl 
+source ./import/components/SHARED_COMPONENTS/MiV_RV32_CFG1.tcl 
+
+# Creating SmartDesign BaseDesign
+set sd_name {BaseDesign}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT}
+
+# Add CoreAPB3_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0}
+
+
+
+# Add CoreGPIO_IN instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} 
+
+
+
+# Add CoreGPIO_OUT instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} 
+
+
+
+# Add CoreJTAGDebug_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0}
+
+
+
+# Add CoreTimer_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0}
+
+
+
+# Add CoreTimer_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1}
+
+
+
+# Add CoreUARTapb_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR}
+
+
+
+# Add MiV_RV32_CFG1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {MiV_RV32_CFG1} -instance_name {MiV_RV32_CFG1}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32_CFG1:TIME_COUNT_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32_CFG1:JTAG_TDO_DR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32_CFG1:EXT_RESETN}
+
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add RCOSC_50MHZ_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0}
+
+
+
+# Add reset_synchronizer_0 instance
+sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0}
+
+
+
+# Add RTG4_SRAM_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0}
+
+
+
+# Add RTG4FCCC_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0}
+
+
+
+# Add SYSRESET_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TCK_0" "MiV_RV32_CFG1:JTAG_TCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDI_0" "MiV_RV32_CFG1:JTAG_TDI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TMS_0" "MiV_RV32_CFG1:JTAG_TMS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TRSTB_0" "MiV_RV32_CFG1:JTAG_TRSTN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:reset_sync" "CoreGPIO_IN:PRESETN" "CoreGPIO_OUT:PRESETN" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "CoreUARTapb_0:PRESETN" "RTG4_SRAM_0:HRESETN" "MiV_RV32_CFG1:RESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MiV_RV32_CFG1:MSYS_EI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MiV_RV32_CFG1:EXT_IRQ" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MiV_RV32_CFG1:JTAG_TDO" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:clock" "RTG4FCCC_0:GL0" "CoreGPIO_IN:PCLK" "CoreGPIO_OUT:PCLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "CoreUARTapb_0:PCLK" "RTG4_SRAM_0:HCLK" "MiV_RV32_CFG1:CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TCK" "TCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDI" "TDI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDO" "TDO" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TMS" "TMS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TRSTB" "TRSTB" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "PUSH_BTN_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "PUSH_BTN_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave1" "CoreUARTapb_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:APB_bif" "CoreAPB3_0:APBmslave2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave3" "CoreTimer_0:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave4" "CoreTimer_1:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave5" "CoreGPIO_OUT:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4_SRAM_0:AHBSlaveInterface" "MiV_RV32_CFG1:AHBL_M_SLV" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "MiV_RV32_CFG1:APB_MSTR" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign BaseDesign
+generate_component -component_name ${sd_name}
diff --git a/Libero_Projects/import/components/IMC_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg2.tcl b/Libero_Projects/import/components/IMC_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg2.tcl
new file mode 100644
index 0000000..392a79c
--- /dev/null
+++ b/Libero_Projects/import/components/IMC_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg2.tcl
@@ -0,0 +1,46 @@
+set project_folder_name MiV_CFG2_BD
+set project_dir2 "./$project_folder_name"
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Importing Components..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+source ./import/components/IMC_CFG2/top_level_rtg4_dev_kit_rv32imc_cfg2.tcl
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Components Imported."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+build_design_hierarchy
+set_root BaseDesign
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Applying Design Constraints..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+import_files -io_pdc ./import/constraints/io/io_constraints.pdc
+import_files -sdc ./import/constraints/io_jtag_constraints.sdc
+
+
+# #Associate SDC constraint file to Place and Route tool
+organize_tool_files -tool {PLACEROUTE} \
+    -file $project_dir2/constraint/io/io_constraints.pdc \
+    -file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {SYNTHESIZE} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {VERIFYTIMING} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+set_root BaseDesign
+run_tool -name {CONSTRAINT_MANAGEMENT}
+derive_constraints_sdc
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Design Constraints Applied."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
diff --git a/Libero_Projects/import/components/IMC_CFG2/top_level_rtg4_dev_kit_rv32imc_cfg2.tcl b/Libero_Projects/import/components/IMC_CFG2/top_level_rtg4_dev_kit_rv32imc_cfg2.tcl
new file mode 100644
index 0000000..beb5713
--- /dev/null
+++ b/Libero_Projects/import/components/IMC_CFG2/top_level_rtg4_dev_kit_rv32imc_cfg2.tcl
@@ -0,0 +1,180 @@
+#RTG4 Dev Kit = RTG4150-1657CG
+#Libero's TCL top level script
+# Core: MiV_RV32IMC
+#
+#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion
+
+#Importing and Linking all the HDL source files used in the design
+import_files -hdl_source ./import/hdl/reset_synchronizer.v
+build_design_hierarchy
+
+#Sourcing the Tcl files for creating individual components under the top level
+source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl 
+source ./import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl 
+source ./import/components/SHARED_COMPONENTS/MiV_RV32_CFG2.tcl 
+
+# Creating SmartDesign BaseDesign
+set sd_name {BaseDesign}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT}
+
+# Add CoreAPB3_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0}
+
+
+
+# Add CoreGPIO_IN instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} 
+
+
+
+# Add CoreGPIO_OUT instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} 
+
+
+
+# Add CoreJTAGDebug_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0}
+
+
+
+# Add CoreTimer_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0}
+
+
+
+# Add CoreTimer_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1}
+
+
+
+# Add CoreUARTapb_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR}
+
+
+
+# Add MiV_RV32_CFG2 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {MiV_RV32_CFG2} -instance_name {MiV_RV32_CFG2}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32_CFG2:TIME_COUNT_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32_CFG2:JTAG_TDO_DR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32_CFG2:EXT_RESETN}
+
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add RCOSC_50MHZ_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0}
+
+
+
+# Add reset_synchronizer_0 instance
+sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0}
+
+
+
+# Add RTG4_SRAM_AXI4_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_AXI4_0} -instance_name {RTG4_SRAM_AXI4_0}
+
+
+
+# Add RTG4FCCC_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0}
+
+
+
+# Add SYSRESET_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TCK_0" "MiV_RV32_CFG2:JTAG_TCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDI_0" "MiV_RV32_CFG2:JTAG_TDI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TMS_0" "MiV_RV32_CFG2:JTAG_TMS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TRSTB_0" "MiV_RV32_CFG2:JTAG_TRSTN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:reset_sync" "CoreGPIO_IN:PRESETN" "CoreTimer_0:PRESETn" "CoreUARTapb_0:PRESETN" "CoreGPIO_OUT:PRESETN" "CoreTimer_1:PRESETn" "RTG4_SRAM_AXI4_0:ARESETN" "MiV_RV32_CFG2:RESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MiV_RV32_CFG2:MSYS_EI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MiV_RV32_CFG2:EXT_IRQ" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MiV_RV32_CFG2:JTAG_TDO" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:clock" "RTG4FCCC_0:GL0" "CoreGPIO_IN:PCLK" "CoreTimer_0:PCLK" "CoreUARTapb_0:PCLK" "CoreGPIO_OUT:PCLK" "CoreTimer_1:PCLK" "RTG4_SRAM_AXI4_0:ACLK" "MiV_RV32_CFG2:CLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TCK" "TCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDI" "TDI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDO" "TDO" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TMS" "TMS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TRSTB" "TRSTB" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "PUSH_BTN_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "PUSH_BTN_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave1" "CoreUARTapb_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave2" "CoreGPIO_IN:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave3" "CoreTimer_0:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave4" "CoreTimer_1:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave5" "CoreGPIO_OUT:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "MiV_RV32_CFG2:APB_MSTR" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4_SRAM_AXI4_0:AXI4_Slave" "MiV_RV32_CFG2:AXI4_M_SLV" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign BaseDesign
+generate_component -component_name ${sd_name}
diff --git a/Libero_Projects/import/components/IMC_CFG3/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg3.tcl b/Libero_Projects/import/components/IMC_CFG3/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg3.tcl
new file mode 100644
index 0000000..75a74fc
--- /dev/null
+++ b/Libero_Projects/import/components/IMC_CFG3/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg3.tcl
@@ -0,0 +1,46 @@
+set project_folder_name MiV_CFG3_BD
+set project_dir2 "./$project_folder_name"
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Importing Components..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+source ./import/components/IMC_CFG3/top_level_rtg4_dev_kit_rv32imc_cfg3.tcl
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Components Imported."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+build_design_hierarchy
+set_root BaseDesign
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Applying Design Constraints..."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
+import_files -io_pdc ./import/constraints/io/io_constraints.pdc
+import_files -sdc ./import/constraints/io_jtag_constraints.sdc
+
+
+# #Associate SDC constraint file to Place and Route tool
+organize_tool_files -tool {PLACEROUTE} \
+    -file $project_dir2/constraint/io/io_constraints.pdc \
+    -file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {SYNTHESIZE} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+organize_tool_files -tool {VERIFYTIMING} \
+	-file $project_dir2/constraint/io_jtag_constraints.sdc \
+    -module {BaseDesign::work} -input_type {constraint}
+
+set_root BaseDesign
+run_tool -name {CONSTRAINT_MANAGEMENT}
+derive_constraints_sdc
+
+puts "\n---------------------------------------------------------------------------------------------------------"
+puts "Design Constraints Applied."
+puts "---------------------------------------------------------------------------------------------------------\n"
+
diff --git a/Libero_Projects/import/components/IMC_CFG3/top_level_rtg4_dev_kit_rv32imc_cfg3.tcl b/Libero_Projects/import/components/IMC_CFG3/top_level_rtg4_dev_kit_rv32imc_cfg3.tcl
new file mode 100644
index 0000000..f3db15a
--- /dev/null
+++ b/Libero_Projects/import/components/IMC_CFG3/top_level_rtg4_dev_kit_rv32imc_cfg3.tcl
@@ -0,0 +1,173 @@
+#RTG4 Dev Kit = RTG4150-1657CG
+#Libero's TCL top level script
+# Core: MiV_RV32IMC
+#
+#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion
+
+#Importing and Linking all the HDL source files used in the design
+import_files -hdl_source ./import/hdl/reset_synchronizer.v
+build_design_hierarchy
+
+#Sourcing the Tcl files for creating individual components under the top level
+source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl 
+source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl 
+source ./import/components/SHARED_COMPONENTS/MiV_RV32_CFG3.tcl 
+
+# Creating SmartDesign BaseDesign
+set sd_name {BaseDesign}
+create_smartdesign -sd_name ${sd_name}
+
+# Disable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 0
+
+# Create top level Ports
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN}
+
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT}
+sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT}
+
+# Add CoreAPB3_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0}
+
+
+
+# Add CoreGPIO_IN instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} 
+
+
+
+# Add CoreGPIO_OUT instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT}
+sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND}
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} 
+sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} 
+
+
+
+# Add CoreJTAGDebug_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0}
+
+
+
+# Add CoreTimer_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0}
+
+
+
+# Add CoreTimer_1 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1}
+
+
+
+# Add CoreUARTapb_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR}
+
+
+
+# Add MiV_RV32_CFG3 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {MiV_RV32_CFG3} -instance_name {MiV_RV32_CFG3}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32_CFG3:TIME_COUNT_OUT}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32_CFG3:JTAG_TDO_DR}
+sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MiV_RV32_CFG3:EXT_RESETN}
+
+
+
+# Add AND2_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
+
+
+
+# Add RCOSC_50MHZ_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0}
+
+
+
+# Add reset_synchronizer_0 instance
+sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0}
+
+
+
+# Add RTG4FCCC_0 instance
+sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0}
+
+
+
+# Add SYSRESET_0 instance
+sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0}
+
+
+
+# Add scalar net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32_CFG3:JTAG_TCK" "CoreJTAGDebug_0:TGT_TCK_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32_CFG3:JTAG_TDI" "CoreJTAGDebug_0:TGT_TDI_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32_CFG3:JTAG_TMS" "CoreJTAGDebug_0:TGT_TMS_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32_CFG3:JTAG_TRSTN" "CoreJTAGDebug_0:TGT_TRSTB_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:reset_sync" "MiV_RV32_CFG3:RESETN" "CoreGPIO_IN:PRESETN" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "CoreUARTapb_0:PRESETN" "CoreGPIO_OUT:PRESETN" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MiV_RV32_CFG3:MSYS_EI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32_CFG3:EXT_IRQ" "CoreTimer_1:TIMINT" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32_CFG3:JTAG_TDO" "CoreJTAGDebug_0:TGT_TDO_0" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:clock" "RTG4FCCC_0:GL0" "MiV_RV32_CFG3:CLK" "CoreGPIO_IN:PCLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "CoreUARTapb_0:PCLK" "CoreGPIO_OUT:PCLK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TCK" "TCK" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDI" "TDI" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDO" "TDO" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TMS" "TMS" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TRSTB" "TRSTB" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" }
+
+# Add bus net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "PUSH_BTN_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "PUSH_BTN_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" }
+
+# Add bus interface net connections
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave1" "CoreUARTapb_0:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave2" "CoreGPIO_IN:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave3" "CoreTimer_0:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave4" "CoreTimer_1:APBslave" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave5" "CoreGPIO_OUT:APB_bif" }
+sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_RV32_CFG3:APB_MSTR" "CoreAPB3_0:APB3mmaster" }
+
+# Re-enable auto promotion of pins of type 'pad'
+auto_promote_pad_pins -promote_all 1
+# Save the smartDesign
+save_smartdesign -sd_name ${sd_name}
+# Generate SmartDesign BaseDesign
+generate_component -component_name ${sd_name}
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl
new file mode 100644
index 0000000..bf89e7c
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl
@@ -0,0 +1,4 @@
+# Exporting core COREAHBTOAPB3_0 to TCL
+# Exporting Create design command for core COREAHBTOAPB3_0
+create_and_configure_core -core_vlnv {Actel:DirectCore:COREAHBTOAPB3:3.1.100} -component_name {COREAHBTOAPB3_0} -params { }
+# Exporting core COREAHBTOAPB3_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl
new file mode 100644
index 0000000..12fdc29
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl
@@ -0,0 +1,111 @@
+# Exporting core CoreAHBL_0 to TCL
+# Exporting Create design command for core CoreAHBL_0
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.4.102} -component_name {CoreAHBL_0} -params {\
+"HADDR_SHG_CFG:1"  \
+"M0_AHBSLOT0ENABLE:false"  \
+"M0_AHBSLOT1ENABLE:false"  \
+"M0_AHBSLOT2ENABLE:false"  \
+"M0_AHBSLOT3ENABLE:false"  \
+"M0_AHBSLOT4ENABLE:false"  \
+"M0_AHBSLOT5ENABLE:false"  \
+"M0_AHBSLOT6ENABLE:false"  \
+"M0_AHBSLOT7ENABLE:true"  \
+"M0_AHBSLOT8ENABLE:false"  \
+"M0_AHBSLOT9ENABLE:false"  \
+"M0_AHBSLOT10ENABLE:false"  \
+"M0_AHBSLOT11ENABLE:false"  \
+"M0_AHBSLOT12ENABLE:false"  \
+"M0_AHBSLOT13ENABLE:false"  \
+"M0_AHBSLOT14ENABLE:false"  \
+"M0_AHBSLOT15ENABLE:false"  \
+"M0_AHBSLOT16ENABLE:false"  \
+"M1_AHBSLOT0ENABLE:false"  \
+"M1_AHBSLOT1ENABLE:false"  \
+"M1_AHBSLOT2ENABLE:false"  \
+"M1_AHBSLOT3ENABLE:false"  \
+"M1_AHBSLOT4ENABLE:false"  \
+"M1_AHBSLOT5ENABLE:false"  \
+"M1_AHBSLOT6ENABLE:false"  \
+"M1_AHBSLOT7ENABLE:false"  \
+"M1_AHBSLOT8ENABLE:true"  \
+"M1_AHBSLOT9ENABLE:false"  \
+"M1_AHBSLOT10ENABLE:false"  \
+"M1_AHBSLOT11ENABLE:false"  \
+"M1_AHBSLOT12ENABLE:false"  \
+"M1_AHBSLOT13ENABLE:false"  \
+"M1_AHBSLOT14ENABLE:false"  \
+"M1_AHBSLOT15ENABLE:false"  \
+"M1_AHBSLOT16ENABLE:false"  \
+"M2_AHBSLOT0ENABLE:false"  \
+"M2_AHBSLOT1ENABLE:false"  \
+"M2_AHBSLOT2ENABLE:false"  \
+"M2_AHBSLOT3ENABLE:false"  \
+"M2_AHBSLOT4ENABLE:false"  \
+"M2_AHBSLOT5ENABLE:false"  \
+"M2_AHBSLOT6ENABLE:false"  \
+"M2_AHBSLOT7ENABLE:false"  \
+"M2_AHBSLOT8ENABLE:false"  \
+"M2_AHBSLOT9ENABLE:false"  \
+"M2_AHBSLOT10ENABLE:false"  \
+"M2_AHBSLOT11ENABLE:false"  \
+"M2_AHBSLOT12ENABLE:false"  \
+"M2_AHBSLOT13ENABLE:false"  \
+"M2_AHBSLOT14ENABLE:false"  \
+"M2_AHBSLOT15ENABLE:false"  \
+"M2_AHBSLOT16ENABLE:false"  \
+"M3_AHBSLOT0ENABLE:false"  \
+"M3_AHBSLOT1ENABLE:false"  \
+"M3_AHBSLOT2ENABLE:false"  \
+"M3_AHBSLOT3ENABLE:false"  \
+"M3_AHBSLOT4ENABLE:false"  \
+"M3_AHBSLOT5ENABLE:false"  \
+"M3_AHBSLOT6ENABLE:false"  \
+"M3_AHBSLOT7ENABLE:false"  \
+"M3_AHBSLOT8ENABLE:false"  \
+"M3_AHBSLOT9ENABLE:false"  \
+"M3_AHBSLOT10ENABLE:false"  \
+"M3_AHBSLOT11ENABLE:false"  \
+"M3_AHBSLOT12ENABLE:false"  \
+"M3_AHBSLOT13ENABLE:false"  \
+"M3_AHBSLOT14ENABLE:false"  \
+"M3_AHBSLOT15ENABLE:false"  \
+"M3_AHBSLOT16ENABLE:false"  \
+"MASTER0_INTERFACE:1"  \
+"MASTER1_INTERFACE:1"  \
+"MASTER2_INTERFACE:1"  \
+"MASTER3_INTERFACE:1"  \
+"MEMSPACE:1"  \
+"SC_0:false"  \
+"SC_1:false"  \
+"SC_2:false"  \
+"SC_3:false"  \
+"SC_4:false"  \
+"SC_5:false"  \
+"SC_6:false"  \
+"SC_7:false"  \
+"SC_8:false"  \
+"SC_9:false"  \
+"SC_10:false"  \
+"SC_11:false"  \
+"SC_12:false"  \
+"SC_13:false"  \
+"SC_14:false"  \
+"SC_15:false"  \
+"SLAVE0_INTERFACE:1"  \
+"SLAVE1_INTERFACE:1"  \
+"SLAVE2_INTERFACE:1"  \
+"SLAVE3_INTERFACE:1"  \
+"SLAVE4_INTERFACE:1"  \
+"SLAVE5_INTERFACE:1"  \
+"SLAVE6_INTERFACE:1"  \
+"SLAVE7_INTERFACE:1"  \
+"SLAVE8_INTERFACE:1"  \
+"SLAVE9_INTERFACE:1"  \
+"SLAVE10_INTERFACE:1"  \
+"SLAVE11_INTERFACE:1"  \
+"SLAVE12_INTERFACE:1"  \
+"SLAVE13_INTERFACE:1"  \
+"SLAVE14_INTERFACE:1"  \
+"SLAVE15_INTERFACE:1"  \
+"SLAVE16_INTERFACE:1"   }
+# Exporting core CoreAHBL_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl
new file mode 100644
index 0000000..e87609a
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl
@@ -0,0 +1,41 @@
+# Exporting core CoreAPB3_0 to TCL
+# Exporting Create design command for core CoreAPB3_0
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.1.100} -component_name {CoreAPB3_0} -params {\
+"APB_DWIDTH:32" \
+"APBSLOT0ENABLE:false" \
+"APBSLOT1ENABLE:true" \
+"APBSLOT2ENABLE:true" \
+"APBSLOT3ENABLE:true" \
+"APBSLOT4ENABLE:true" \
+"APBSLOT5ENABLE:true" \
+"APBSLOT6ENABLE:false" \
+"APBSLOT7ENABLE:false" \
+"APBSLOT8ENABLE:false" \
+"APBSLOT9ENABLE:false" \
+"APBSLOT10ENABLE:false" \
+"APBSLOT11ENABLE:false" \
+"APBSLOT12ENABLE:false" \
+"APBSLOT13ENABLE:false" \
+"APBSLOT14ENABLE:false" \
+"APBSLOT15ENABLE:false" \
+"IADDR_OPTION:0" \
+"MADDR_BITS:16" \
+"SC_0:false" \
+"SC_1:false" \
+"SC_2:false" \
+"SC_3:false" \
+"SC_4:false" \
+"SC_5:false" \
+"SC_6:false" \
+"SC_7:false" \
+"SC_8:false" \
+"SC_9:false" \
+"SC_10:false" \
+"SC_11:false" \
+"SC_12:false" \
+"SC_13:false" \
+"SC_14:false" \
+"SC_15:false" \
+"UPR_NIBBLE_POSN:6"} 
+# Exporting core CoreAPB3_0 to TCL done
+
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_0.tcl
new file mode 100644
index 0000000..6177894
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_0.tcl
@@ -0,0 +1,11 @@
+# Exporting core CoreAXITOAHBL_0 to TCL
+# Exporting Create design command for core CoreAXITOAHBL_0
+create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXITOAHBL:3.5.100} -component_name {CoreAXITOAHBL_0} -params {\
+"ASYNC_CLOCKS:false"  \
+"AXI_DWIDTH:64"  \
+"AXI_SEL_MM_S:1"  \
+"EXPOSE_WID:false"  \
+"ID_WIDTH:5"  \
+"NO_BURST_TRANS:false"  \
+"WRAP_SUPPORT:false"   }
+# Exporting core CoreAXITOAHBL_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_1.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_1.tcl
new file mode 100644
index 0000000..2ab4745
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_1.tcl
@@ -0,0 +1,11 @@
+# Exporting core CoreAXITOAHBL_1 to TCL
+# Exporting Create design command for core CoreAXITOAHBL_1
+create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXITOAHBL:3.5.100} -component_name {CoreAXITOAHBL_1} -params {\
+"ASYNC_CLOCKS:false"  \
+"AXI_DWIDTH:64"  \
+"AXI_SEL_MM_S:1"  \
+"EXPOSE_WID:false"  \
+"ID_WIDTH:5"  \
+"NO_BURST_TRANS:false"  \
+"WRAP_SUPPORT:false"   }
+# Exporting core CoreAXITOAHBL_1 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl
new file mode 100644
index 0000000..a1c824d
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl
@@ -0,0 +1,136 @@
+# Exporting core CoreGPIO_IN to TCL
+# Exporting Create design command for core CoreGPIO_IN
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_IN} -params {\
+"APB_WIDTH:32"  \
+"FIXED_CONFIG_0:true"  \
+"FIXED_CONFIG_1:true"  \
+"FIXED_CONFIG_2:false"  \
+"FIXED_CONFIG_3:false"  \
+"FIXED_CONFIG_4:false"  \
+"FIXED_CONFIG_5:false"  \
+"FIXED_CONFIG_6:false"  \
+"FIXED_CONFIG_7:false"  \
+"FIXED_CONFIG_8:false"  \
+"FIXED_CONFIG_9:false"  \
+"FIXED_CONFIG_10:false"  \
+"FIXED_CONFIG_11:false"  \
+"FIXED_CONFIG_12:false"  \
+"FIXED_CONFIG_13:false"  \
+"FIXED_CONFIG_14:false"  \
+"FIXED_CONFIG_15:false"  \
+"FIXED_CONFIG_16:false"  \
+"FIXED_CONFIG_17:false"  \
+"FIXED_CONFIG_18:false"  \
+"FIXED_CONFIG_19:false"  \
+"FIXED_CONFIG_20:false"  \
+"FIXED_CONFIG_21:false"  \
+"FIXED_CONFIG_22:false"  \
+"FIXED_CONFIG_23:false"  \
+"FIXED_CONFIG_24:false"  \
+"FIXED_CONFIG_25:false"  \
+"FIXED_CONFIG_26:false"  \
+"FIXED_CONFIG_27:false"  \
+"FIXED_CONFIG_28:false"  \
+"FIXED_CONFIG_29:false"  \
+"FIXED_CONFIG_30:false"  \
+"FIXED_CONFIG_31:false"  \
+"INT_BUS:0"  \
+"IO_INT_TYPE_0:7"  \
+"IO_INT_TYPE_1:7"  \
+"IO_INT_TYPE_2:7"  \
+"IO_INT_TYPE_3:7"  \
+"IO_INT_TYPE_4:7"  \
+"IO_INT_TYPE_5:7"  \
+"IO_INT_TYPE_6:7"  \
+"IO_INT_TYPE_7:7"  \
+"IO_INT_TYPE_8:7"  \
+"IO_INT_TYPE_9:7"  \
+"IO_INT_TYPE_10:7"  \
+"IO_INT_TYPE_11:7"  \
+"IO_INT_TYPE_12:7"  \
+"IO_INT_TYPE_13:7"  \
+"IO_INT_TYPE_14:7"  \
+"IO_INT_TYPE_15:7"  \
+"IO_INT_TYPE_16:7"  \
+"IO_INT_TYPE_17:7"  \
+"IO_INT_TYPE_18:7"  \
+"IO_INT_TYPE_19:7"  \
+"IO_INT_TYPE_20:7"  \
+"IO_INT_TYPE_21:7"  \
+"IO_INT_TYPE_22:7"  \
+"IO_INT_TYPE_23:7"  \
+"IO_INT_TYPE_24:7"  \
+"IO_INT_TYPE_25:7"  \
+"IO_INT_TYPE_26:7"  \
+"IO_INT_TYPE_27:7"  \
+"IO_INT_TYPE_28:7"  \
+"IO_INT_TYPE_29:7"  \
+"IO_INT_TYPE_30:7"  \
+"IO_INT_TYPE_31:7"  \
+"IO_NUM:2"  \
+"IO_TYPE_0:0"  \
+"IO_TYPE_1:0"  \
+"IO_TYPE_2:0"  \
+"IO_TYPE_3:0"  \
+"IO_TYPE_4:0"  \
+"IO_TYPE_5:0"  \
+"IO_TYPE_6:0"  \
+"IO_TYPE_7:0"  \
+"IO_TYPE_8:0"  \
+"IO_TYPE_9:0"  \
+"IO_TYPE_10:0"  \
+"IO_TYPE_11:0"  \
+"IO_TYPE_12:0"  \
+"IO_TYPE_13:0"  \
+"IO_TYPE_14:0"  \
+"IO_TYPE_15:0"  \
+"IO_TYPE_16:0"  \
+"IO_TYPE_17:0"  \
+"IO_TYPE_18:0"  \
+"IO_TYPE_19:0"  \
+"IO_TYPE_20:0"  \
+"IO_TYPE_21:0"  \
+"IO_TYPE_22:0"  \
+"IO_TYPE_23:0"  \
+"IO_TYPE_24:0"  \
+"IO_TYPE_25:0"  \
+"IO_TYPE_26:0"  \
+"IO_TYPE_27:0"  \
+"IO_TYPE_28:0"  \
+"IO_TYPE_29:0"  \
+"IO_TYPE_30:0"  \
+"IO_TYPE_31:0"  \
+"IO_VAL_0:0"  \
+"IO_VAL_1:0"  \
+"IO_VAL_2:0"  \
+"IO_VAL_3:0"  \
+"IO_VAL_4:0"  \
+"IO_VAL_5:0"  \
+"IO_VAL_6:0"  \
+"IO_VAL_7:0"  \
+"IO_VAL_8:0"  \
+"IO_VAL_9:0"  \
+"IO_VAL_10:0"  \
+"IO_VAL_11:0"  \
+"IO_VAL_12:0"  \
+"IO_VAL_13:0"  \
+"IO_VAL_14:0"  \
+"IO_VAL_15:0"  \
+"IO_VAL_16:0"  \
+"IO_VAL_17:0"  \
+"IO_VAL_18:0"  \
+"IO_VAL_19:0"  \
+"IO_VAL_20:0"  \
+"IO_VAL_21:0"  \
+"IO_VAL_22:0"  \
+"IO_VAL_23:0"  \
+"IO_VAL_24:0"  \
+"IO_VAL_25:0"  \
+"IO_VAL_26:0"  \
+"IO_VAL_27:0"  \
+"IO_VAL_28:0"  \
+"IO_VAL_29:0"  \
+"IO_VAL_30:0"  \
+"IO_VAL_31:0"  \
+"OE_TYPE:1"   }
+# Exporting core CoreGPIO_IN to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl
new file mode 100644
index 0000000..cecf205
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl
@@ -0,0 +1,136 @@
+# Exporting core CoreGPIO_OUT to TCL
+# Exporting Create design command for core CoreGPIO_OUT
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_OUT} -params {\
+"APB_WIDTH:32"  \
+"FIXED_CONFIG_0:true"  \
+"FIXED_CONFIG_1:true"  \
+"FIXED_CONFIG_2:true"  \
+"FIXED_CONFIG_3:true"  \
+"FIXED_CONFIG_4:false"  \
+"FIXED_CONFIG_5:false"  \
+"FIXED_CONFIG_6:false"  \
+"FIXED_CONFIG_7:false"  \
+"FIXED_CONFIG_8:false"  \
+"FIXED_CONFIG_9:false"  \
+"FIXED_CONFIG_10:false"  \
+"FIXED_CONFIG_11:false"  \
+"FIXED_CONFIG_12:false"  \
+"FIXED_CONFIG_13:false"  \
+"FIXED_CONFIG_14:false"  \
+"FIXED_CONFIG_15:false"  \
+"FIXED_CONFIG_16:false"  \
+"FIXED_CONFIG_17:false"  \
+"FIXED_CONFIG_18:false"  \
+"FIXED_CONFIG_19:false"  \
+"FIXED_CONFIG_20:false"  \
+"FIXED_CONFIG_21:false"  \
+"FIXED_CONFIG_22:false"  \
+"FIXED_CONFIG_23:false"  \
+"FIXED_CONFIG_24:false"  \
+"FIXED_CONFIG_25:false"  \
+"FIXED_CONFIG_26:false"  \
+"FIXED_CONFIG_27:false"  \
+"FIXED_CONFIG_28:false"  \
+"FIXED_CONFIG_29:false"  \
+"FIXED_CONFIG_30:false"  \
+"FIXED_CONFIG_31:false"  \
+"INT_BUS:0"  \
+"IO_INT_TYPE_0:7"  \
+"IO_INT_TYPE_1:7"  \
+"IO_INT_TYPE_2:7"  \
+"IO_INT_TYPE_3:7"  \
+"IO_INT_TYPE_4:7"  \
+"IO_INT_TYPE_5:7"  \
+"IO_INT_TYPE_6:7"  \
+"IO_INT_TYPE_7:7"  \
+"IO_INT_TYPE_8:7"  \
+"IO_INT_TYPE_9:7"  \
+"IO_INT_TYPE_10:7"  \
+"IO_INT_TYPE_11:7"  \
+"IO_INT_TYPE_12:7"  \
+"IO_INT_TYPE_13:7"  \
+"IO_INT_TYPE_14:7"  \
+"IO_INT_TYPE_15:7"  \
+"IO_INT_TYPE_16:7"  \
+"IO_INT_TYPE_17:7"  \
+"IO_INT_TYPE_18:7"  \
+"IO_INT_TYPE_19:7"  \
+"IO_INT_TYPE_20:7"  \
+"IO_INT_TYPE_21:7"  \
+"IO_INT_TYPE_22:7"  \
+"IO_INT_TYPE_23:7"  \
+"IO_INT_TYPE_24:7"  \
+"IO_INT_TYPE_25:7"  \
+"IO_INT_TYPE_26:7"  \
+"IO_INT_TYPE_27:7"  \
+"IO_INT_TYPE_28:7"  \
+"IO_INT_TYPE_29:7"  \
+"IO_INT_TYPE_30:7"  \
+"IO_INT_TYPE_31:7"  \
+"IO_NUM:4"  \
+"IO_TYPE_0:1"  \
+"IO_TYPE_1:1"  \
+"IO_TYPE_2:1"  \
+"IO_TYPE_3:1"  \
+"IO_TYPE_4:0"  \
+"IO_TYPE_5:0"  \
+"IO_TYPE_6:0"  \
+"IO_TYPE_7:0"  \
+"IO_TYPE_8:0"  \
+"IO_TYPE_9:0"  \
+"IO_TYPE_10:0"  \
+"IO_TYPE_11:0"  \
+"IO_TYPE_12:0"  \
+"IO_TYPE_13:0"  \
+"IO_TYPE_14:0"  \
+"IO_TYPE_15:0"  \
+"IO_TYPE_16:0"  \
+"IO_TYPE_17:0"  \
+"IO_TYPE_18:0"  \
+"IO_TYPE_19:0"  \
+"IO_TYPE_20:0"  \
+"IO_TYPE_21:0"  \
+"IO_TYPE_22:0"  \
+"IO_TYPE_23:0"  \
+"IO_TYPE_24:0"  \
+"IO_TYPE_25:0"  \
+"IO_TYPE_26:0"  \
+"IO_TYPE_27:0"  \
+"IO_TYPE_28:0"  \
+"IO_TYPE_29:0"  \
+"IO_TYPE_30:0"  \
+"IO_TYPE_31:0"  \
+"IO_VAL_0:0"  \
+"IO_VAL_1:0"  \
+"IO_VAL_2:0"  \
+"IO_VAL_3:0"  \
+"IO_VAL_4:0"  \
+"IO_VAL_5:0"  \
+"IO_VAL_6:0"  \
+"IO_VAL_7:0"  \
+"IO_VAL_8:0"  \
+"IO_VAL_9:0"  \
+"IO_VAL_10:0"  \
+"IO_VAL_11:0"  \
+"IO_VAL_12:0"  \
+"IO_VAL_13:0"  \
+"IO_VAL_14:0"  \
+"IO_VAL_15:0"  \
+"IO_VAL_16:0"  \
+"IO_VAL_17:0"  \
+"IO_VAL_18:0"  \
+"IO_VAL_19:0"  \
+"IO_VAL_20:0"  \
+"IO_VAL_21:0"  \
+"IO_VAL_22:0"  \
+"IO_VAL_23:0"  \
+"IO_VAL_24:0"  \
+"IO_VAL_25:0"  \
+"IO_VAL_26:0"  \
+"IO_VAL_27:0"  \
+"IO_VAL_28:0"  \
+"IO_VAL_29:0"  \
+"IO_VAL_30:0"  \
+"IO_VAL_31:0"  \
+"OE_TYPE:1"   }
+# Exporting core CoreGPIO_OUT to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl
new file mode 100644
index 0000000..e03bcf6
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl
@@ -0,0 +1,38 @@
+# Exporting core CoreJTAGDebug_0 to TCL
+# Exporting Create design command for core CoreJTAGDebug_0
+create_and_configure_core -core_vlnv {Actel:DirectCore:COREJTAGDEBUG:3.1.100} -component_name {CoreJTAGDebug_0} -params {\
+"IR_CODE_TGT_0:0x55"  \
+"IR_CODE_TGT_1:0x56"  \
+"IR_CODE_TGT_2:0x57"  \
+"IR_CODE_TGT_3:0x58"  \
+"IR_CODE_TGT_4:0x59"  \
+"IR_CODE_TGT_5:0x5a"  \
+"IR_CODE_TGT_6:0x5b"  \
+"IR_CODE_TGT_7:0x5c"  \
+"IR_CODE_TGT_8:0x5d"  \
+"IR_CODE_TGT_9:0x5e"  \
+"IR_CODE_TGT_10:0x5f"  \
+"IR_CODE_TGT_11:0x60"  \
+"IR_CODE_TGT_12:0x61"  \
+"IR_CODE_TGT_13:0x62"  \
+"IR_CODE_TGT_14:0x63"  \
+"IR_CODE_TGT_15:0x64"  \
+"NUM_DEBUG_TGTS:1"  \
+"TGT_ACTIVE_HIGH_RESET_0:false"  \
+"TGT_ACTIVE_HIGH_RESET_1:true"  \
+"TGT_ACTIVE_HIGH_RESET_2:true"  \
+"TGT_ACTIVE_HIGH_RESET_3:true"  \
+"TGT_ACTIVE_HIGH_RESET_4:true"  \
+"TGT_ACTIVE_HIGH_RESET_5:true"  \
+"TGT_ACTIVE_HIGH_RESET_6:true"  \
+"TGT_ACTIVE_HIGH_RESET_7:true"  \
+"TGT_ACTIVE_HIGH_RESET_8:true"  \
+"TGT_ACTIVE_HIGH_RESET_9:true"  \
+"TGT_ACTIVE_HIGH_RESET_10:true"  \
+"TGT_ACTIVE_HIGH_RESET_11:true"  \
+"TGT_ACTIVE_HIGH_RESET_12:true"  \
+"TGT_ACTIVE_HIGH_RESET_13:true"  \
+"TGT_ACTIVE_HIGH_RESET_14:true"  \
+"TGT_ACTIVE_HIGH_RESET_15:true"  \
+"UJTAG_BYPASS:false"   }
+# Exporting core CoreJTAGDebug_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl
new file mode 100644
index 0000000..a55adca
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl
@@ -0,0 +1,38 @@
+# Exporting core CoreJTAGDebug_0 to TCL
+# Exporting Create design command for core CoreJTAGDebug_0
+create_and_configure_core -core_vlnv {Actel:DirectCore:COREJTAGDEBUG:3.1.100} -component_name {CoreJTAGDebug_1} -params {\
+"IR_CODE_TGT_0:0x55"  \
+"IR_CODE_TGT_1:0x56"  \
+"IR_CODE_TGT_2:0x57"  \
+"IR_CODE_TGT_3:0x58"  \
+"IR_CODE_TGT_4:0x59"  \
+"IR_CODE_TGT_5:0x5a"  \
+"IR_CODE_TGT_6:0x5b"  \
+"IR_CODE_TGT_7:0x5c"  \
+"IR_CODE_TGT_8:0x5d"  \
+"IR_CODE_TGT_9:0x5e"  \
+"IR_CODE_TGT_10:0x5f"  \
+"IR_CODE_TGT_11:0x60"  \
+"IR_CODE_TGT_12:0x61"  \
+"IR_CODE_TGT_13:0x62"  \
+"IR_CODE_TGT_14:0x63"  \
+"IR_CODE_TGT_15:0x64"  \
+"NUM_DEBUG_TGTS:1"  \
+"TGT_ACTIVE_HIGH_RESET_0:true"  \
+"TGT_ACTIVE_HIGH_RESET_1:true"  \
+"TGT_ACTIVE_HIGH_RESET_2:true"  \
+"TGT_ACTIVE_HIGH_RESET_3:true"  \
+"TGT_ACTIVE_HIGH_RESET_4:true"  \
+"TGT_ACTIVE_HIGH_RESET_5:true"  \
+"TGT_ACTIVE_HIGH_RESET_6:true"  \
+"TGT_ACTIVE_HIGH_RESET_7:true"  \
+"TGT_ACTIVE_HIGH_RESET_8:true"  \
+"TGT_ACTIVE_HIGH_RESET_9:true"  \
+"TGT_ACTIVE_HIGH_RESET_10:true"  \
+"TGT_ACTIVE_HIGH_RESET_11:true"  \
+"TGT_ACTIVE_HIGH_RESET_12:true"  \
+"TGT_ACTIVE_HIGH_RESET_13:true"  \
+"TGT_ACTIVE_HIGH_RESET_14:true"  \
+"TGT_ACTIVE_HIGH_RESET_15:true"  \
+"UJTAG_BYPASS:false"   }
+# Exporting core CoreJTAGDebug_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_0.tcl
new file mode 100644
index 0000000..fda5b3b
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_0.tcl
@@ -0,0 +1,6 @@
+# Exporting core CoreTimer_0 to TCL
+# Exporting Create design command for core CoreTimer_0
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreTimer:2.0.103} -component_name {CoreTimer_0} -params {\
+"INTACTIVEH:1"  \
+"WIDTH:32"   }
+# Exporting core CoreTimer_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_1.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_1.tcl
new file mode 100644
index 0000000..6a598ae
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_1.tcl
@@ -0,0 +1,6 @@
+# Exporting core CoreTimer_1 to TCL
+# Exporting Create design command for core CoreTimer_1
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreTimer:2.0.103} -component_name {CoreTimer_1} -params {\
+"INTACTIVEH:1"  \
+"WIDTH:32"   }
+# Exporting core CoreTimer_1 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl
new file mode 100644
index 0000000..6e4baa2
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl
@@ -0,0 +1,14 @@
+# Exporting core CoreUARTapb_0 to TCL
+# Exporting Create design command for core CoreUARTapb_0
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreUARTapb:5.6.102} -component_name {CoreUARTapb_0} -params {\
+"BAUD_VAL_FRCTN:0"  \
+"BAUD_VAL_FRCTN_EN:false"  \
+"BAUD_VALUE:1"  \
+"FIXEDMODE:0"  \
+"PRG_BIT8:0"  \
+"PRG_PARITY:0"  \
+"RX_FIFO:0"  \
+"RX_LEGACY_MODE:0"  \
+"TX_FIFO:0"  \
+"USE_SOFT_FIFO:0"   }
+# Exporting core CoreUARTapb_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMAF_L1_AHB_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMAF_L1_AHB_0.tcl
new file mode 100644
index 0000000..378a8ad
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMAF_L1_AHB_0.tcl
@@ -0,0 +1,7 @@
+# Exporting core MIV_RV32IMAF_L1_AHB_0 to TCL
+# Exporting Create design command for core MIV_RV32IMAF_L1_AHB_0
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -component_name {MIV_RV32IMAF_L1_AHB_0} -params {\
+"ECC_EN:false"  \
+"RESET_VECTOR_ADDR_0:0x0"  \
+"RESET_VECTOR_ADDR_1:0x8000"   }
+# Exporting core MIV_RV32IMAF_L1_AHB_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32IMA_L1_AHB_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32IMA_L1_AHB_0.tcl
new file mode 100644
index 0000000..e802e9a
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32IMA_L1_AHB_0.tcl
@@ -0,0 +1,8 @@
+# Exporting core MiV_RV32IMA_L1_AHB_0 to TCL
+# Exporting Create design command for core MiV_RV32IMA_L1_AHB_0
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -component_name {MiV_RV32IMA_L1_AHB_0} -params {\
+"ECC_EN:false"  \
+"EXT_HALT:false"  \
+"RESET_VECTOR_ADDR_0:0x0"  \
+"RESET_VECTOR_ADDR_1:0x8000"   }
+# Exporting core MiV_RV32IMA_L1_AHB_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32IMA_L1_AXI_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32IMA_L1_AXI_0.tcl
new file mode 100644
index 0000000..9baf0ee
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32IMA_L1_AXI_0.tcl
@@ -0,0 +1,9 @@
+# Exporting core MiV_RV32IMA_L1_AXI_0 to TCL
+# Exporting Create design command for core MiV_RV32IMA_L1_AXI_0
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -component_name {MiV_RV32IMA_L1_AXI_0} -params {\
+"MASTER_TYPE:0"  \
+"MEM_WID:5"  \
+"MMIO_WID:5"  \
+"RESET_VECTOR_ADDR_0:0x0"  \
+"RESET_VECTOR_ADDR_1:0x8000"   }
+# Exporting core MiV_RV32IMA_L1_AXI_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32_CFG1.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32_CFG1.tcl
new file mode 100644
index 0000000..8f9bff6
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32_CFG1.tcl
@@ -0,0 +1,53 @@
+# Exporting core MIV_RV32_CFG1_0 to TCL
+# Exporting Create design command for core MIV_RV32_CFG1_0
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component_name {MIV_RV32_CFG1} -params {\
+"AHB_END_ADDR_0:0x7fff"  \
+"AHB_END_ADDR_1:0x8fff"  \
+"AHB_MASTER_TYPE:1"  \
+"AHB_SLAVE_MIRROR:true"  \
+"AHB_START_ADDR_0:0x0"  \
+"AHB_START_ADDR_1:0x8000"  \
+"APB_END_ADDR_0:0xffff"  \
+"APB_END_ADDR_1:0x7fff"  \
+"APB_MASTER_TYPE:1"  \
+"APB_SLAVE_MIRROR:false"  \
+"APB_START_ADDR_0:0x0"  \
+"APB_START_ADDR_1:0x7000"  \
+"AXI_END_ADDR_0:0xffff"  \
+"AXI_END_ADDR_1:0x6fff"  \
+"AXI_MASTER_TYPE:0"  \
+"AXI_SLAVE_MIRROR:false"  \
+"AXI_START_ADDR_0:0x0"  \
+"AXI_START_ADDR_1:0x6000"  \
+"BOOTROM_DEST_ADDR_LOWER:0x0"  \
+"BOOTROM_DEST_ADDR_UPPER:0x4000"  \
+"BOOTROM_PRESENT:false"  \
+"BOOTROM_SRC_END_ADDR_LOWER:0x3fff"  \
+"BOOTROM_SRC_END_ADDR_UPPER:0x8000"  \
+"BOOTROM_SRC_START_ADDR_LOWER:0x0"  \
+"BOOTROM_SRC_START_ADDR_UPPER:0x8000"  \
+"DEBUGGER:true"  \
+"ECC_ENABLE:false"  \
+"FWD_REGS:false"  \
+"GEN_DECODE_RV32:3"  \
+"GEN_MUL_TYPE:2"  \
+"GPR_REGS:false"  \
+"INTERNAL_MTIME:true"  \
+"INTERNAL_MTIME_IRQ:true"  \
+"MTIME_PRESCALER:100"  \
+"NUM_EXT_IRQS:1"  \
+"RECONFIG_BOOTROM:false"  \
+"RESET_VECTOR_ADDR_0:0x0"  \
+"RESET_VECTOR_ADDR_1:0x8000"  \
+"TAS_END_ADDR_0:0x3fff"  \
+"TAS_END_ADDR_1:0x4000"  \
+"TAS_START_ADDR_0:0x0"  \
+"TAS_START_ADDR_1:0x4000"  \
+"TCM_END_ADDR_0:0x3fff"  \
+"TCM_END_ADDR_1:0x4000"  \
+"TCM_PRESENT:false"  \
+"TCM_START_ADDR_0:0x0"  \
+"TCM_START_ADDR_1:0x4000"  \
+"TCM_TAS_PRESENT:false"  \
+"VECTORED_INTERRUPTS:false"   }
+# Exporting core MIV_RV32_CFG1_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32_CFG2.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32_CFG2.tcl
new file mode 100644
index 0000000..00bb0c9
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32_CFG2.tcl
@@ -0,0 +1,53 @@
+# Exporting core MIV_RV32_CFG2_0 to TCL
+# Exporting Create design command for core MIV_RV32_CFG2_0
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component_name {MIV_RV32_CFG2} -params {\
+"AHB_END_ADDR_0:0xffff"  \
+"AHB_END_ADDR_1:0x8fff"  \
+"AHB_MASTER_TYPE:0"  \
+"AHB_SLAVE_MIRROR:false"  \
+"AHB_START_ADDR_0:0x0"  \
+"AHB_START_ADDR_1:0x8000"  \
+"APB_END_ADDR_0:0xffff"  \
+"APB_END_ADDR_1:0x7fff"  \
+"APB_MASTER_TYPE:1"  \
+"APB_SLAVE_MIRROR:false"  \
+"APB_START_ADDR_0:0x0"  \
+"APB_START_ADDR_1:0x7000"  \
+"AXI_END_ADDR_0:0x7fff"  \
+"AXI_END_ADDR_1:0x8fff"  \
+"AXI_MASTER_TYPE:2"  \
+"AXI_SLAVE_MIRROR:true"  \
+"AXI_START_ADDR_0:0x0"  \
+"AXI_START_ADDR_1:0x8000"  \
+"BOOTROM_DEST_ADDR_LOWER:0x0"  \
+"BOOTROM_DEST_ADDR_UPPER:0x4000"  \
+"BOOTROM_PRESENT:false"  \
+"BOOTROM_SRC_END_ADDR_LOWER:0x3fff"  \
+"BOOTROM_SRC_END_ADDR_UPPER:0x8000"  \
+"BOOTROM_SRC_START_ADDR_LOWER:0x0"  \
+"BOOTROM_SRC_START_ADDR_UPPER:0x8000"  \
+"DEBUGGER:true"  \
+"ECC_ENABLE:false"  \
+"FWD_REGS:false"  \
+"GEN_DECODE_RV32:2"  \
+"GEN_MUL_TYPE:0"  \
+"GPR_REGS:false"  \
+"INTERNAL_MTIME:true"  \
+"INTERNAL_MTIME_IRQ:true"  \
+"MTIME_PRESCALER:100"  \
+"NUM_EXT_IRQS:1"  \
+"RECONFIG_BOOTROM:false"  \
+"RESET_VECTOR_ADDR_0:0x0"  \
+"RESET_VECTOR_ADDR_1:0x8000"  \
+"TAS_END_ADDR_0:0x3fff"  \
+"TAS_END_ADDR_1:0x4000"  \
+"TAS_START_ADDR_0:0x0"  \
+"TAS_START_ADDR_1:0x4000"  \
+"TCM_END_ADDR_0:0x3fff"  \
+"TCM_END_ADDR_1:0x4000"  \
+"TCM_PRESENT:false"  \
+"TCM_START_ADDR_0:0x0"  \
+"TCM_START_ADDR_1:0x4000"  \
+"TCM_TAS_PRESENT:false"  \
+"VECTORED_INTERRUPTS:false"   }
+# Exporting core MIV_RV32_CFG2_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32_CFG3.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32_CFG3.tcl
new file mode 100644
index 0000000..e5b9363
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/MiV_RV32_CFG3.tcl
@@ -0,0 +1,54 @@
+# Exporting core MIV_RV32_CFG3_0 to TCL
+# Exporting Create design command for core MIV_RV32_CFG3_0
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component_name {MIV_RV32_CFG3} -params {\
+"AHB_END_ADDR_0:0xffff"  \
+"AHB_END_ADDR_1:0x8fff"  \
+"AHB_MASTER_TYPE:0"  \
+"AHB_SLAVE_MIRROR:false"  \
+"AHB_START_ADDR_0:0x0"  \
+"AHB_START_ADDR_1:0x8000"  \
+"APB_END_ADDR_0:0xffff"  \
+"APB_END_ADDR_1:0x7fff"  \
+"APB_MASTER_TYPE:1"  \
+"APB_SLAVE_MIRROR:false"  \
+"APB_START_ADDR_0:0x0"  \
+"APB_START_ADDR_1:0x7000"  \
+"AXI_END_ADDR_0:0xffff"  \
+"AXI_END_ADDR_1:0x6fff"  \
+"AXI_MASTER_TYPE:0"  \
+"AXI_SLAVE_MIRROR:false"  \
+"AXI_START_ADDR_0:0x0"  \
+"AXI_START_ADDR_1:0x6000"  \
+"BOOTROM_DEST_ADDR_LOWER:0x0"  \
+"BOOTROM_DEST_ADDR_UPPER:0x4000"  \
+"BOOTROM_PRESENT:false"  \
+"BOOTROM_SRC_END_ADDR_LOWER:0x3fff"  \
+"BOOTROM_SRC_END_ADDR_UPPER:0x8000"  \
+"BOOTROM_SRC_START_ADDR_LOWER:0x0"  \
+"BOOTROM_SRC_START_ADDR_UPPER:0x8000"  \
+"DEBUGGER:true"  \
+"ECC_ENABLE:false"  \
+"FWD_REGS:false"  \
+"GEN_DECODE_RV32:0"  \
+"GEN_MUL_TYPE:2"  \
+"GPR_REGS:false"  \
+"INTERNAL_MTIME:true"  \
+"INTERNAL_MTIME_IRQ:true"  \
+"MTIME_PRESCALER:100"  \
+"NUM_EXT_IRQS:1"  \
+"RECONFIG_BOOTROM:false"  \
+"RESET_VECTOR_ADDR_0:0x0"  \
+"RESET_VECTOR_ADDR_1:0x8000"  \
+"TAS_END_ADDR_0:0x3fff"  \
+"TAS_END_ADDR_1:0x4000"  \
+"TAS_START_ADDR_0:0x0"  \
+"TAS_START_ADDR_1:0x4000"  \
+"TCM_END_ADDR_0:0x7fff"  \
+"TCM_END_ADDR_1:0x8000"  \
+"TCM_PRESENT:true"  \
+"TCM_START_ADDR_0:0x0"  \
+"TCM_START_ADDR_1:0x8000"  \
+"TCM_TAS_PRESENT:false"  \
+"VECTORED_INTERRUPTS:false"   }
+# Exporting core MIV_RV32_CFG3_0 to TCL done
+
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl
new file mode 100644
index 0000000..10a4f62
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl
@@ -0,0 +1,128 @@
+# Exporting core RTG4FCCC_0 to TCL
+# Exporting Create design command for core RTG4FCCC_0
+create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:2.0.201} -component_name {RTG4FCCC_0} -params {\
+"ADVANCED_TAB_CHANGED:false"  \
+"CLK0_IS_USED:false"  \
+"CLK0_PAD_IS_USED:false"  \
+"CLK1_IS_USED:false"  \
+"CLK1_PAD_IS_USED:false"  \
+"CLK2_IS_USED:false"  \
+"CLK2_PAD_IS_USED:false"  \
+"CLK3_IS_USED:false"  \
+"CLK3_PAD_IS_USED:false"  \
+"DYN_CONF_IS_USED:false"  \
+"ENABLE_AUTO_RESET_LOGIC:false"  \
+"EXPOSE_CGL_ENABLE_ARST_SIGNALS:false"  \
+"GL0_BP_IN_0_FREQ:100"  \
+"GL0_BP_IN_0_SRC:IO_HARDWIRED_0"  \
+"GL0_BP_IN_1_FREQ:100"  \
+"GL0_BP_IN_1_SRC:IO_HARDWIRED_0"  \
+"GL0_FREQUENCY_LOCKED:false"  \
+"GL0_IN_0_SRC:PLL"  \
+"GL0_IN_1_SRC:UNUSED"  \
+"GL0_IS_INVERTED:false"  \
+"GL0_IS_USED:true"  \
+"GL0_OUT_0_FREQ:50"  \
+"GL0_OUT_1_FREQ:50"  \
+"GL0_OUT_IS_GATED:false"  \
+"GL0_PLL_IN_0_PHASE:0"  \
+"GL0_PLL_IN_1_PHASE:0"  \
+"GL1_BP_IN_0_FREQ:100"  \
+"GL1_BP_IN_0_SRC:IO_HARDWIRED_0"  \
+"GL1_BP_IN_1_FREQ:100"  \
+"GL1_BP_IN_1_SRC:IO_HARDWIRED_0"  \
+"GL1_FREQUENCY_LOCKED:false"  \
+"GL1_IN_0_SRC:PLL"  \
+"GL1_IN_1_SRC:UNUSED"  \
+"GL1_IS_INVERTED:false"  \
+"GL1_IS_USED:false"  \
+"GL1_OUT_0_FREQ:50"  \
+"GL1_OUT_1_FREQ:50"  \
+"GL1_OUT_IS_GATED:false"  \
+"GL1_PLL_IN_0_PHASE:0"  \
+"GL1_PLL_IN_1_PHASE:0"  \
+"GL2_BP_IN_0_FREQ:100"  \
+"GL2_BP_IN_0_SRC:IO_HARDWIRED_0"  \
+"GL2_BP_IN_1_FREQ:100"  \
+"GL2_BP_IN_1_SRC:IO_HARDWIRED_0"  \
+"GL2_FREQUENCY_LOCKED:false"  \
+"GL2_IN_0_SRC:PLL"  \
+"GL2_IN_1_SRC:UNUSED"  \
+"GL2_IS_INVERTED:false"  \
+"GL2_IS_USED:false"  \
+"GL2_OUT_0_FREQ:100"  \
+"GL2_OUT_1_FREQ:50"  \
+"GL2_OUT_IS_GATED:false"  \
+"GL2_PLL_IN_0_PHASE:0"  \
+"GL2_PLL_IN_1_PHASE:0"  \
+"GL3_BP_IN_0_FREQ:100"  \
+"GL3_BP_IN_0_SRC:IO_HARDWIRED_0"  \
+"GL3_BP_IN_1_FREQ:100"  \
+"GL3_BP_IN_1_SRC:IO_HARDWIRED_0"  \
+"GL3_FREQUENCY_LOCKED:false"  \
+"GL3_IN_0_SRC:PLL"  \
+"GL3_IN_1_SRC:UNUSED"  \
+"GL3_IS_INVERTED:false"  \
+"GL3_IS_USED:false"  \
+"GL3_OUT_0_FREQ:100"  \
+"GL3_OUT_1_FREQ:50"  \
+"GL3_OUT_IS_GATED:false"  \
+"GL3_PLL_IN_0_PHASE:0"  \
+"GL3_PLL_IN_1_PHASE:0"  \
+"GPD0_IS_USED:false"  \
+"GPD0_NOPIPE_RSTSYNC:true"  \
+"GPD0_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC"  \
+"GPD1_IS_USED:false"  \
+"GPD1_NOPIPE_RSTSYNC:true"  \
+"GPD1_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC"  \
+"GPD2_IS_USED:false"  \
+"GPD2_NOPIPE_RSTSYNC:true"  \
+"GPD2_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC"  \
+"GPD3_IS_USED:false"  \
+"GPD3_NOPIPE_RSTSYNC:true"  \
+"GPD3_SYNC_STYLE:G3STYLE_AND_NO_LOCK_RSTSYNC"  \
+"GPD_EXPOSE_RESETS:false"  \
+"GPD_SYNC_STYLE:G3STYLE_AND_LOCK_RSTSYNC"  \
+"INCLUDE_RECONFIGURATION_LOGIC:true"  \
+"INIT:088101249000020B80404040664C993186071C11C16C"  \
+"IO_HARDWIRED_0_IS_DIFF:false"  \
+"IO_HARDWIRED_1_IS_DIFF:false"  \
+"IO_HARDWIRED_2_IS_DIFF:false"  \
+"IO_HARDWIRED_3_IS_DIFF:false"  \
+"MODE_10V:false"  \
+"NGMUX0_HOLD_IS_USED:false"  \
+"NGMUX1_HOLD_IS_USED:false"  \
+"NGMUX2_HOLD_IS_USED:false"  \
+"NGMUX3_HOLD_IS_USED:false"  \
+"NGMUX_EXPOSE_HOLD:false"  \
+"PLL_DELAY:0"  \
+"PLL_EXPOSE_BYPASS:false"  \
+"PLL_EXPOSE_READY_VDDPLL:false"  \
+"PLL_EXPOSE_RESETS:false"  \
+"PLL_EXT_FB_GL:EXT_FB_GL0"  \
+"PLL_FB_SRC:CCC_INTERNAL"  \
+"PLL_IN_FREQ:50.000"  \
+"PLL_IN_SRC:OSC_50MHZ"  \
+"PLL_IS_USED:true"  \
+"PLL_LOCK_IND:1024"  \
+"PLL_LOCK_WND:6000"  \
+"PLL_SSM_DEPTH:0.5"  \
+"PLL_SSM_ENABLE:false"  \
+"PLL_SSM_FREQ:40"  \
+"PLL_SUPPLY_VOLTAGE:25_V"  \
+"PLL_VCO_TARGET:700"  \
+"RCOSC_25_50MHZ_IS_USED:true"  \
+"RX0_RECOVERY_BLOCK_DATA:Unused-Unused"  \
+"RX0_RECOVERY_BLOCK_IS_USED:false"  \
+"RX0_RECOVERY_BLOCK_STROBE:Unused"  \
+"RX0_SPACE_WIRE_MODE_IS_USED:true"  \
+"RX1_RECOVERY_BLOCK_DATA:Unused-Unused"  \
+"RX1_RECOVERY_BLOCK_IS_USED:false"  \
+"RX1_RECOVERY_BLOCK_STROBE:Unused"  \
+"RX1_SPACE_WIRE_MODE_IS_USED:true"  \
+"VCOFREQUENCY:800.000"  \
+"Y0_IS_USED:false"  \
+"Y1_IS_USED:false"  \
+"Y2_IS_USED:false"  \
+"Y3_IS_USED:false"   }
+# Exporting core RTG4FCCC_0 to TCL done
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl
new file mode 100644
index 0000000..3b2c17e
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl
@@ -0,0 +1,25 @@
+# Exporting core RTG4_SRAM_0 to TCL
+# Create design TCL command for core RTG4_SRAM_0
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.115} -component_name {RTG4_SRAM_0} -params {\
+"AXI4_AWIDTH:32" \
+"AXI4_DWIDTH:32" \
+"AXI4_IDWIDTH:8" \
+"AXI4_IFTYPE_RD:T" \
+"AXI4_IFTYPE_WR:T" \
+"AXI4_WRAP_SUPPORT:F" \
+"BYTEENABLES:1" \
+"BYTE_ENABLE_WIDTH:4" \
+"B_REN_POLARITY:2" \
+"CASCADE:1" \
+"ECC_OPTIONS:0" \
+"FABRIC_INTERFACE_TYPE:0" \
+"IMPORT_FILE:" \
+"INIT_RAM:F" \
+"LPM_HINT:0" \
+"PIPELINE_OPTIONS:1" \
+"RDEPTH:32768" \
+"RWIDTH:36" \
+"USE_NATIVE_INTERFACE:F" \
+"WDEPTH:32768" \
+"WWIDTH:36" }
+# Exporting core RTG4_SRAM_0 to TCL done 
diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl
new file mode 100644
index 0000000..458fd67
--- /dev/null
+++ b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl
@@ -0,0 +1,25 @@
+# Exporting core RTG4_SRAM_AXI4_0 to TCL
+# Create design TCL command for core RTG4_SRAM_AXI4_0
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.115} -component_name {RTG4_SRAM_AXI4_0} -params {\
+"AXI4_AWIDTH:32" \
+"AXI4_DWIDTH:32" \
+"AXI4_IDWIDTH:8" \
+"AXI4_IFTYPE_RD:T" \
+"AXI4_IFTYPE_WR:T" \
+"AXI4_WRAP_SUPPORT:F" \
+"BYTEENABLES:1" \
+"BYTE_ENABLE_WIDTH:4" \
+"B_REN_POLARITY:2" \
+"CASCADE:1" \
+"ECC_OPTIONS:0" \
+"FABRIC_INTERFACE_TYPE:1" \
+"IMPORT_FILE:" \
+"INIT_RAM:F" \
+"LPM_HINT:0" \
+"PIPELINE_OPTIONS:1" \
+"RDEPTH:32768" \
+"RWIDTH:36" \
+"USE_NATIVE_INTERFACE:F" \
+"WDEPTH:32768" \
+"WWIDTH:36" }
+# Exporting core RTG4_SRAM_AXI4_0 to TCL done
diff --git a/Libero_Projects/import/constraints/io/io_constraints.pdc b/Libero_Projects/import/constraints/io/io_constraints.pdc
index 6ce4e6f..f9e6036 100644
--- a/Libero_Projects/import/constraints/io/io_constraints.pdc
+++ b/Libero_Projects/import/constraints/io/io_constraints.pdc
@@ -25,125 +25,129 @@
 # User Locked I/O settings
 # 
 
-set_io {GPIO_IN[0]}   \
-    -pinname V33      \
+
+# -- User PushButtons I/O -- #
+
+set_io {PUSH_BTN_1}   \
+    -pinname AA30      \
     -fixed yes        \
     -DIRECTION INPUT
 
+set_io {PUSH_BTN_2}   \
+    -pinname AB31      \
+    -fixed yes        \
+    -DIRECTION INPUT
+
+
+# -- LEDs I/O --#
+
+set_io {LED_1}   \
+    -pinname W35       \
+    -fixed yes         \
+    -DIRECTION OUTPUT
+
+set_io {LED_2}   \
+    -pinname W34       \
+    -fixed yes         \
+    -DIRECTION OUTPUT
 
-set_io {GPIO_IN[1]}   \
-    -pinname V34      \
+set_io {LED_3}   \
+    -pinname V30       \
+    -fixed yes         \
+    -DIRECTION OUTPUT
+
+set_io {LED_4}   \
+    -pinname W33       \
+    -fixed yes         \
+    -DIRECTION OUTPUT
+
+
+# -- UART RX/TX -- #
+
+set_io RX             \
+    -pinname E27      \
     -fixed yes        \
     -DIRECTION INPUT
 
+set_io TX              \
+    -pinname E28       \
+    -fixed yes         \
+    -DIRECTION OUTPUT
+
+
+# 
+# Dedicated Peripheral I/O Settings
+# 
+
+
+# 
+# Unlocked I/O settings
+# The I/Os in this section are unplaced or placed but are not locked
+# the other listed attributes have been applied
+# 
+
+
+# Additional GPIOs IN
+
+# set_io {GPIO_IN[0]}   \
+    # -pinname V33      \
+    # -fixed yes        \
+    # -DIRECTION INPUT
+
+# set_io {GPIO_IN[1]}   \
+    # -pinname V34      \
+    # -fixed yes        \
+    # -DIRECTION INPUT
 
-# Additional GPIOs
 # set_io {GPIO_IN[2]}   \
     # -pinname U34      \
     # -fixed yes        \
     # -DIRECTION INPUT
 
-
 # set_io {GPIO_IN[3]}   \
     # -pinname W36      \
     # -fixed yes        \
     # -DIRECTION INPUT
 
-
 # set_io {GPIO_IN[4]}   \
     # -pinname AA30     \
     # -fixed yes        \
     # -DIRECTION INPUT
 
-
 # set_io {GPIO_IN[5]}   \
     # -pinname AB31     \
     # -fixed yes        \
     # -DIRECTION INPUT
 
-
 # set_io {GPIO_IN[6]}   \
     # -pinname AB30     \
     # -fixed yes        \
     # -DIRECTION INPUT
 
-
 # set_io {GPIO_IN[7]}   \
     # -pinname AB32     \
     # -fixed yes        \
     # -DIRECTION INPUT
+	
+	
+# Additional GPIOs OUT
 
-
-set_io {GPIO_OUT[0]}   \
-    -pinname W35       \
-    -fixed yes         \
-    -DIRECTION OUTPUT
-
-
-set_io {GPIO_OUT[1]}   \
-    -pinname W34       \
-    -fixed yes         \
-    -DIRECTION OUTPUT
-
-
-set_io {GPIO_OUT[2]}   \
-    -pinname V30       \
-    -fixed yes         \
-    -DIRECTION OUTPUT
-
-
-set_io {GPIO_OUT[3]}   \
-    -pinname W33       \
-    -fixed yes         \
-    -DIRECTION OUTPUT
-
-
-# Additional GPIOs
 # set_io {GPIO_OUT[4]}   \
     # -pinname T33       \
     # -fixed yes         \
     # -DIRECTION OUTPUT
 
-
 # set_io {GPIO_OUT[5]}   \
     # -pinname U35       \
     # -fixed yes         \
     # -DIRECTION OUTPUT
 
-
 # set_io {GPIO_OUT[6]}   \
     # -pinname R36       \
     # -fixed yes         \
     # -DIRECTION OUTPUT
 
-
 # set_io {GPIO_OUT[7]}   \
     # -pinname T34       \
     # -fixed yes         \
     # -DIRECTION OUTPUT
-
-
-set_io RX             \
-    -pinname E27      \
-    -fixed yes        \
-    -DIRECTION INPUT
-
-
-set_io TX              \
-    -pinname E28       \
-    -fixed yes         \
-    -DIRECTION OUTPUT
-
-
-
-# 
-# Dedicated Peripheral I/O Settings
-# 
-
-
-# 
-# Unlocked I/O settings
-# The I/Os in this section are unplaced or placed but are not locked
-# the other listed attributes have been applied
-# 
-
diff --git a/README.md b/README.md
index 5fea2b2..6138ef0 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,11 @@
 # RTG4 Development Kit Mi-V Sample Designs
 
-This repository contains Libero projects for the MIV_RV32IMA_L1_AHB and MIV_RV32IMA_L1_AXI soft core RISC-V processors.
+This repository contains Libero projects for the following soft core RISC-V processors:
+* MIV_RV32
+* MIV_RV32IMA_L1_AHB
+* MIV_RV32IMA_L1_AXI
+* MIV_RV32IMAF_L1_AHB
+
 FlashPro Express projects containing pre-generated programming files are also available for each of the designs.
 
 To download or clone the repository:
@@ -8,24 +13,24 @@ To download or clone the repository:
     $ git clone https://github.com/RISCV-on-Microsemi-FPGA/RTG4-Development-Kit.git
 
     $ Running from the zipped sources
-    1. Download the zipped sources via the "Clone or download" button using "Download Zip" button
+    1. Download the zipped sources via the "Code" button using "Download Zip" button
     2. Unzip the sources
 
 
 # Libero Projects
-The Libero_Projects folder contains sample Mi-V Libero designs.
+The Libero_Projects folder contains sample Mi-V Libero designs for Libero v12.6. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/RISCV-on-Microsemi-FPGA/Future-Avalanche-Board/releases) in this repository.
 
 ## Design Features
 The Libero designs include the following features:
-* A MIV_RV32IMA_L1_AHB or MIV_RV32IMA_L1_AXI soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
-* RISC-V debug block allowing on-target debug using SoftConsole
+* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
+* A RISC-V debug block allowing on-target debug using SoftConsole
 * The operating frequency of the design is 50MHz
-* Target memory is LSRAM
-* User peripherals (GPIO, Timers, UART)
+* Target memory is SRAM (32kB)
+* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)
 
 ## Target Hardware
 Details of the RTG4 Development kit and it's features can be found:
-* RTG4-DEV-KIT [here](https://www.microsemi.com/product-directory/dev-kits-solutions/3865-rtg4-kits)
+* [RTG4-DEV-KIT](https://www.microsemi.com/product-directory/dev-kits-solutions/3865-rtg4-kits)
 
 # FlashPro Express
 The FlashPro_Express_Projects folder contains the pre-generated programming files, which can be downloaded directly to the target board using FlashPro Express.
@@ -33,17 +38,13 @@ The FlashPro_Express_Projects folder contains the pre-generated programming file
 # Design Tools
 The following design tools are required.
 
-## Libero SoC v12.3
-Libero SoC is Microsemi's FPGA design software.
-It is available from [here](https://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc#downloads).
+## Libero SoC v12.6
+[Libero SoC](https://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc#downloads) is Microchip's FPGA design software.
 
 ## FlashPro Express
-FlashPro Express is Microsemi's Programming and debug tool. It is included in the Libero SoC software and is also
-available as a standalone application found [here](http://www.microsemi.com/products/fpga-soc/design-resources/programming/flashpro#software). Please note, that if Libero SoC is already on your system, you do not need
+[FlashPro Express](http://www.microsemi.com/products/fpga-soc/design-resources/programming/flashpro#software) is Microchip's Programming and debug tool. It is included in the Libero SoC software and is also
+available as a standalone application. Please note, that if Libero SoC is already on your system, you do not need
 the standalone version.
 
 ## SoftConsole
-SoftConsole is Microsemi’s free software development environment facilitating the rapid development of bare-metal and RTOS based C/C++ software for Microsemi CPU and SoC based FPGAs. It provides development and debug support for all Microsemi SoC FPGAs and 32-bit soft IP CPUs. SoftConsole can be downloaded [here](https://www.microsemi.com/product-directory/design-tools/4879-softconsole).  
-
-### SoftConsole Projects
-A set of RISC-V example software projects are also available for these designs from the SoftConsole [page](https://github.com/RISCV-on-Microsemi-FPGA/SoftConsole).
+[SoftConsole](https://www.microsemi.com/product-directory/design-tools/4879-softconsole) is Microchip’s free software development environment facilitating the rapid development of bare-metal and RTOS based C/C++ software for Microchip CPU and SoC based FPGAs. It provides development and debug support for all Microchip SoC FPGAs and 32-bit soft IP CPUs. SoftConsole can be downloaded.