3rd party validation of port!

[Riesi]

For now only I tried to validate the entire design to match the Altium version myself. I found many mismatches over the last days, but I cant guarantee that I didn't overlook something.

It would be much appreciated if somebody else could also take a look at validating this port to the original Altium version. This way we could increase the plausibility of this port being correct.

Thanks in advance!