From d49f82c800782082119dd87e9ae4dacc8b34524b Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Wed, 27 Mar 2024 16:35:36 -0400
Subject: [PATCH 01/48] Display RISC-V stages on the visual datapath

---
 src/agent/datapath_reducer.rs        |  7 +++++++
 src/emulation_core/riscv/datapath.rs | 12 ++++++++++++
 src/ui/visual_datapath/mod.rs        | 10 ++--------
 src/ui/visual_datapath/utils.rs      |  2 ++
 4 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/src/agent/datapath_reducer.rs b/src/agent/datapath_reducer.rs
index 04c4dd9b3..a47535967 100644
--- a/src/agent/datapath_reducer.rs
+++ b/src/agent/datapath_reducer.rs
@@ -159,4 +159,11 @@ impl DatapathReducer {
             RISCV => &self.riscv.memory,
         }
     }
+
+    pub fn get_current_stage(&self) -> String {
+        match self.current_architecture {
+            MIPS => self.mips.current_stage.into(),
+            RISCV => self.riscv.current_stage.into(),
+        }
+    }
 }
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index bf145f799..8f7325d03 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -192,6 +192,18 @@ impl RiscStage {
     }
 }
 
+impl From<RiscStage> for String {
+    fn from(val: RiscStage) -> String {
+        String::from(match val {
+            RiscStage::InstructionFetch => "writeback",
+            RiscStage::InstructionDecode => "instruction_fetch",
+            RiscStage::Execute => "instruction_decode",
+            RiscStage::Memory => "execute",
+            RiscStage::WriteBack => "memory",
+        })
+    }
+}
+
 impl Default for RiscDatapath {
     fn default() -> Self {
         let mut datapath = RiscDatapath {
diff --git a/src/ui/visual_datapath/mod.rs b/src/ui/visual_datapath/mod.rs
index 67ffb541d..e0117732a 100644
--- a/src/ui/visual_datapath/mod.rs
+++ b/src/ui/visual_datapath/mod.rs
@@ -36,7 +36,7 @@ use yew::prelude::*;
 use consts::*;
 use utils::*;
 
-use crate::{agent::datapath_reducer::DatapathReducer, emulation_core::mips::datapath::Stage};
+use crate::agent::datapath_reducer::DatapathReducer;
 
 #[derive(PartialEq, Properties)]
 pub struct VisualDatapathProps {
@@ -130,13 +130,7 @@ impl Component for VisualDatapath {
         // there is actual data to view. A better way to see this is "when stage X is
         // set on the datapath, highlight the lines for stage Y." The datapath stage
         // tells where it will start the next time "execute" is pressed.
-        let current_stage = String::from(match ctx.props().datapath_state.mips.current_stage {
-            Stage::InstructionFetch => "writeback",
-            Stage::InstructionDecode => "instruction_fetch",
-            Stage::Execute => "instruction_decode",
-            Stage::Memory => "execute",
-            Stage::WriteBack => "memory",
-        });
+        let current_stage = ctx.props().datapath_state.get_current_stage();
 
         debug!("Current stage: {:?}", current_stage);
         if first_render || self.should_reinitialize {
diff --git a/src/ui/visual_datapath/utils.rs b/src/ui/visual_datapath/utils.rs
index d265a7cd6..f9a1eded7 100644
--- a/src/ui/visual_datapath/utils.rs
+++ b/src/ui/visual_datapath/utils.rs
@@ -1,6 +1,7 @@
 //! Helpful common functions used for the visual datapath.
 
 use gloo::utils::{document, window};
+use gloo_console::log;
 use wasm_bindgen::JsCast;
 use web_sys::{Element, HtmlCollection, HtmlElement, HtmlObjectElement, MouseEvent};
 use yew::UseReducerHandle;
@@ -181,6 +182,7 @@ pub fn visual_line_to_data(
     variable: &str,
     datapath_state: &UseReducerHandle<DatapathReducer>,
 ) -> LineInformation {
+    log!("Calling here");
     match datapath_state.current_architecture {
         AvailableDatapaths::MIPS => {
             match variable {

From 818804dcd3050bce7bb0c984776acfd1ca924588 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Wed, 27 Mar 2024 17:12:04 -0400
Subject: [PATCH 02/48] Fix visual datapath popup overflowing window

---
 src/bin/main.rs                 | 4 ++--
 src/ui/visual_datapath/mod.rs   | 2 +-
 src/ui/visual_datapath/utils.rs | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/bin/main.rs b/src/bin/main.rs
index dee719dd2..a9f53a4ca 100644
--- a/src/bin/main.rs
+++ b/src/bin/main.rs
@@ -491,7 +491,7 @@ fn app(props: &AppProps) -> Html {
 
     log::debug!("{:?}", datapath_state.executing);
     html! {
-        <>
+        <div class="overflow-hidden">
             // button tied to the input file element, which is hidden to be more clean
             <input type="file" class="hidden" id="file_input" accept=".txt,.asm,.mips" onchange={file_picked_callback} />
             <div class="flex flex-row flex-no-wrap h-screen p-2 gap-2">
@@ -573,7 +573,7 @@ fn app(props: &AppProps) -> Html {
                 // Right column
                 <Regview gp={datapath_state.get_dyn_gp_registers()} fp={datapath_state.mips.coprocessor_registers.get_dyn_register_list()} pc_limit={*pc_limit} communicator={props.communicator}/>
             </div>
-        </>
+        </div>
     }
 }
 
diff --git a/src/ui/visual_datapath/mod.rs b/src/ui/visual_datapath/mod.rs
index e0117732a..59a1e033e 100644
--- a/src/ui/visual_datapath/mod.rs
+++ b/src/ui/visual_datapath/mod.rs
@@ -84,7 +84,7 @@ impl Component for VisualDatapath {
         let zoom_out_size = Rc::clone(&self.size);
         html! {
             <div id="datapath-wrapper" class="max-h-[50%] relative">
-                <div class="overflow-auto w-full h-full basis-1/2 bg-primary-100 z-10 relative">
+                <div id="datapath-scrollbox" class="overflow-auto w-full h-full basis-1/2 bg-primary-100 z-10 relative">
                     <object data={ctx.props().svg_path.clone()} type="image/svg+xml" id={DATAPATH_ID} class={classes!("datapath", format!("size-{}", self.size.borrow()))}></object>
                 </div>
                 <div id="popup">
diff --git a/src/ui/visual_datapath/utils.rs b/src/ui/visual_datapath/utils.rs
index f9a1eded7..522d833b5 100644
--- a/src/ui/visual_datapath/utils.rs
+++ b/src/ui/visual_datapath/utils.rs
@@ -68,7 +68,7 @@ pub fn get_datapath_iframe_mouse_position(event: MouseEvent) -> (i32, i32) {
     let datapath_position = get_datapath_position();
 
     let datapath_wrapper = gloo::utils::document()
-        .get_element_by_id("datapath-wrapper")
+        .get_element_by_id("datapath-scrollbox")
         .unwrap()
         .unchecked_into::<HtmlElement>();
     let scroll_position = (

From d77288e5b119f7953b6664189636e81ad31e832f Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Wed, 27 Mar 2024 18:28:53 -0400
Subject: [PATCH 03/48] Updated with ECALL fix from SWIM-v2

---
 src/emulation_core/riscv/datapath.rs | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index bf145f799..d8d052c54 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -671,7 +671,8 @@ impl RiscDatapath {
                             0 => SysOp::ECALL,
                             1 => SysOp::EBREAK,
                             _ => SysOp::None,
-                        }
+                        };
+                        self.signals.reg_write_en = RegWriteEn::NoWrite;
                     }
                     1 => self.signals.sys_op = SysOp::CSRReadWrite,
                     2 => self.signals.sys_op = SysOp::CSRReadSet,
@@ -879,7 +880,8 @@ impl RiscDatapath {
                     self.registers.gpr[self.state.imm as usize] &= !self.state.alu_input1;
                 }
             }
-            _ => self.error("Impossible/Unsupported Instruction!"),
+            SysOp::None => self.error("Impossible/Unsupported Instruction!"),
+            _ => self.state.alu_result = 0,
         }
     }
 

From af693bd3cd2339ef33dd83e156fcaa468591a10a Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Wed, 27 Mar 2024 18:59:32 -0400
Subject: [PATCH 04/48] Added Coprocessor. Implemented instruction_decode.
 Moving on to FPU control signals.

---
 src/emulation_core/riscv.rs                 |   1 +
 src/emulation_core/riscv/constants.rs       |  10 +
 src/emulation_core/riscv/control_signals.rs | 249 ++++++++++++
 src/emulation_core/riscv/coprocessor.rs     | 429 ++++++++++++++++++++
 src/emulation_core/riscv/datapath.rs        |   4 +-
 src/emulation_core/riscv/instruction.rs     |  31 +-
 src/emulation_core/riscv/registers.rs       | 164 ++++++++
 7 files changed, 877 insertions(+), 11 deletions(-)
 create mode 100644 src/emulation_core/riscv/coprocessor.rs

diff --git a/src/emulation_core/riscv.rs b/src/emulation_core/riscv.rs
index a937a8c28..8085e380a 100644
--- a/src/emulation_core/riscv.rs
+++ b/src/emulation_core/riscv.rs
@@ -3,6 +3,7 @@
 
 pub mod constants;
 pub mod control_signals;
+// pub mod coprocessor;
 pub mod datapath;
 pub mod datapath_signals;
 pub mod instruction;
diff --git a/src/emulation_core/riscv/constants.rs b/src/emulation_core/riscv/constants.rs
index de2208061..b9f29eeaa 100644
--- a/src/emulation_core/riscv/constants.rs
+++ b/src/emulation_core/riscv/constants.rs
@@ -70,6 +70,16 @@ pub const OPCODE_AUIPC: u8 = 0b0010111;
 /// Used for J-type instructions.
 pub const OPCODE_JAL: u8 = 0b1101111;
 
+/// Used for R4-type instructions.
+// FMADD.S
+pub const OPCODE_MADD: u8 = 0b1000011;
+// FMSUB.S
+pub const OPCODE_MSUB: u8 = 0b1000111;
+// FNMSUB.S
+pub const OPCODE_NMSUB: u8 = 0b1001011;
+// FNMADD.S
+pub const OPCODE_NMADD: u8 = 0b1001111;
+
 // "ENC" is short for encoding. There is no formal name for this field
 // in the MIPS64 specification, other than the "shamt"/"sa" field that it
 // replaces, so this was chosen as the mnemonic for this project.
diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index dd9a1717b..c315f7a23 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -201,3 +201,252 @@ pub enum RegWriteEn {
     NoWrite = 0,
     YesWrite = 1,
 }
+
+pub mod floating_point {
+    use super::super::constants::*;
+    use serde::{Deserialize, Serialize};
+
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub struct FpuControlSignals {
+        pub cc: Cc,
+        pub cc_write: CcWrite,
+        pub data_src: DataSrc,
+        pub data_write: DataWrite,
+        pub fpu_alu_op: FpuAluOp,
+        pub fpu_branch: FpuBranch,
+        pub fpu_mem_to_reg: FpuMemToReg,
+        pub fpu_reg_dst: FpuRegDst,
+        pub fpu_reg_width: FpuRegWidth,
+        pub fpu_reg_write: FpuRegWrite,
+        pub fpu_take_branch: FpuTakeBranch,
+    }
+
+    /// Determines, given that [`CcWrite`] is set, which condition code register
+    /// should be written to or read from for a given operation.
+    ///
+    /// For the sake of this project, it will usually be assumed that this will
+    /// be 0, however the functionality is available to be extended.
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub enum Cc {
+        /// Use condition code register 0. Default in most operations. Can be
+        /// additionally used in the case where the condition code register is
+        /// irrelevant to the current instruction.
+        #[default]
+        Cc0 = 0,
+    }
+
+    /// Determines if the condition code register file should be written to.
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub enum CcWrite {
+        #[default]
+        NoWrite = 0,
+        YesWrite = 1,
+    }
+
+    /// Determines the source of the `Data` register in the floating-point unit.
+    ///
+    /// This is a special intermediary register that facilitates passing data between
+    /// the main processing unit and the floating-point unit.
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub enum DataSrc {
+        /// Use data from the main processing unit. Specifically, the data from register
+        /// `rt` from a given instruction. This value can additionally be used in the cases
+        /// where this register is not written to.
+        MainProcessorUnit = 0,
+
+        /// Use data from the floating-point unit. Specifically, the data from register `fs`
+        /// from a given instruction.
+        #[default]
+        FloatingPointUnit = 1,
+    }
+
+    /// Determines whether to write to the `Data` register in the floating-point unit.
+    ///
+    /// This acts as a toggle for the source of data to the main processing unit register
+    /// file. Additionally, it acts as a toggle for a source to the floating-point unit
+    /// register file (this could be overridden by the [`FpuMemToReg`] control signal).
+    /// For the latter two functions, it is imperative to unset the [`RegWrite`](super::RegWrite) and
+    /// [`FpuRegWrite`] control signals in cases where registers should not be modified
+    /// with unintended data.
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub enum DataWrite {
+        /// - Do not write to the data register.
+        /// - Source data to write to the main processing unit register file from the main
+        ///   processing unit. This implies either the ALU result or the data read from memory
+        /// - Source data to write to the floating-point register file from the floating-point
+        ///   ALU.
+        #[default]
+        NoWrite = 0,
+
+        /// - Write to the data register.
+        /// - Source data to write to the main processing unit register file from the
+        ///   floating-point unit. Specifically, this is the data stored in the `Data` register
+        ///   in the FPU, likely from register `fs` from a given instruction. This data source
+        ///   overrides the decision given by the [`MemToReg`](super::MemToReg) control signal.
+        /// - Source data to write to the floating-point register file from the `Data` register
+        ///   in the FPU, likely from register `rt` from a given instruction.
+        YesWrite = 1,
+    }
+
+    /// This doubly determines the operations sent to the floating-point ALU and the
+    /// floating-point comparator.
+    ///
+    /// Only one of these units are effectively utilized in any given instruction.
+    ///
+    /// The fifth bit of the control signal represents either a single-precision
+    /// floating-point operation (0), or a double-precision floating-point operation (1).
+    /// This fifth bit is determined by [`FpuRegWidth`].
+    ///
+    /// *Implementation note:* The bits set for the comparator are intended to match
+    /// the bits used in the `cond` field of a `c.cond.fmt` instruction.
+    #[derive(Clone, Debug, Default, PartialEq, Serialize, Deserialize)]
+    pub enum FpuAluOp {
+        #[default]
+        /// `_0000` (0):
+        /// - ALU: Perform an addition.
+        Addition = 0,
+
+        /// `_0001` (1):
+        /// - ALU: Perform a subtraction.
+        Subtraction = 1,
+
+        /// `_0010` (2):
+        /// - ALU: Perform a multiplication.
+        /// - Comparator: Set if equal.
+        MultiplicationOrEqual = 2,
+
+        /// `_0011` (3):
+        /// - ALU: Perform a division.
+        Division = 3,
+
+        /// `_0100` (4):
+        /// - ALU: Perform an "AND" operation.
+        And = 4,
+
+        /// `_0101` (5):
+        /// - ALU: Perform an "OR" operation.
+        Or = 5,
+
+        /// `_1100` (12):
+        /// - Comparator: Set if less than.
+        Slt = 12,
+
+        /// `_1101` (13):
+        /// - Comparator: Set if not greater than or equal.
+        Snge = 13,
+
+        /// `_1110` (14):
+        /// - Comparator: Set if less than or equal.
+        Sle = 14,
+
+        /// `_1111` (15):
+        /// - Comparator: Set if not greater than.
+        Sngt = 15,
+    }
+
+    impl FpuAluOp {
+        /// Get the corresponding control signal given a function code.
+        pub fn from_function(function: u8) -> Result<Self, String> {
+            match function {
+                FUNCTION_C_EQ => Ok(Self::MultiplicationOrEqual),
+                FUNCTION_C_LT => Ok(Self::Slt),
+                FUNCTION_C_NGE => Ok(Self::Snge),
+                FUNCTION_C_LE => Ok(Self::Sle),
+                FUNCTION_C_NGT => Ok(Self::Sngt),
+                _ => Err(format!("Unsupported function code `{function}`")),
+            }
+        }
+    }
+
+    /// Determines if the floating-point unit should consider branching, based on the
+    /// contents of the condition code register.
+    ///
+    /// This directly overrides any branch decisions decided by the main processing unit.
+    /// The [`Branch`](super::Branch) control signal should not be set in addition to this signal.
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub enum FpuBranch {
+        /// Do not consider branching.
+        #[default]
+        NoBranch = 0,
+
+        /// Consider branching.
+        YesBranch = 1,
+    }
+
+    /// Determines, given that [`FpuRegWrite`] is set, what the source of a floating-point
+    /// register's new data will be.
+    ///
+    /// This decision, if set, overrides the decision from the [`DataWrite`] control signal.
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub enum FpuMemToReg {
+        /// Do not use data from memory. Use the result of the [`DataWrite`] control signal.
+        #[default]
+        UseDataWrite = 0,
+
+        /// Use data from memory.
+        UseMemory = 1,
+    }
+
+    /// Determines, given that [`FpuRegWrite`] is set, which destination register to write
+    /// to, which largely depends on the instruction format.
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub enum FpuRegDst {
+        /// Use register `ft`.
+        Reg1 = 0,
+
+        /// Use register `fs`.
+        Reg2 = 1,
+
+        /// Use register `fd`.
+        #[default]
+        Reg3 = 2,
+    }
+
+    /// Determines the amount of data to be sent or received from registers and the ALU.
+    ///
+    /// While all buses carrying information are 64-bits wide, some bits of the bus may be
+    /// ignored in the case of this control signal.
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub enum FpuRegWidth {
+        /// Use words (32 bits). Equivalent to a single-precision floating-point value.
+        Word = 0,
+
+        /// Use doublewords (64 bits). Equivalent to a double-precision floating-point value.
+        #[default]
+        DoubleWord = 1,
+    }
+
+    impl FpuRegWidth {
+        /// Get the corresponding [`FpuRegWidth`] control signal based on
+        /// the `fmt` field in an instruction.
+        pub fn from_fmt(fmt: u8) -> Result<Self, String> {
+            match fmt {
+                FMT_SINGLE => Ok(Self::Word),
+                FMT_DOUBLE => Ok(Self::DoubleWord),
+                _ => Err(format!("`{fmt}` is an invalid fmt value")),
+            }
+        }
+    }
+
+    /// Determines if the floating-point register file should be written to.
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub enum FpuRegWrite {
+        /// Do not write to the floating-point register file.
+        #[default]
+        NoWrite = 0,
+
+        /// Write to the floating-point register file.
+        YesWrite = 1,
+    }
+
+    /// After checking the [`FpuBranch`] and condition code, this signal determines whether
+    /// to follow through with a branch.
+    ///
+    /// This signal is what is sent to the main processor.
+    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+    pub enum FpuTakeBranch {
+        #[default]
+        NoBranch = 0,
+        YesBranch = 1,
+    }
+}
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
new file mode 100644
index 000000000..54f019272
--- /dev/null
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -0,0 +1,429 @@
+//! Implementation of a RISC-V floating-point coprocessor.
+
+use super::constants::*;
+use super::control_signals::floating_point::*;
+use super::registers::FpRegisters;
+use super::instruction::Instruction;
+use serde::{Deserialize, Serialize};
+
+/// An implementation of a floating-point coprocessor for the RISC-V ISA.
+///
+/// Different from the main processor, much of the functionality of the coprocessor
+/// is controlled remotely using its available API calls.
+#[derive(Clone, PartialEq, Default, Debug, Serialize, Deserialize)]
+pub struct RiscFpCoprocessor {
+    instruction: Instruction,
+    pub signals: FpuControlSignals,
+    pub state: RiscFpuState,
+    pub is_halted: bool,
+    pub registers: FpRegisters,
+    pub condition_code: u64,
+    pub data: u64,
+}
+
+#[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
+pub struct RiscFpuState {
+    pub instruction: u32,
+    pub rs1: u32,
+    pub rs2: u32,
+    pub rs3: u32,
+    pub rd: u32,
+    pub shamt: u32,
+    pub funct2: u32,
+    pub funct3: u32,
+    pub funct7: u32,
+    pub imm: u32,
+    pub imm1: u32,
+    pub imm2: u32,
+    pub branch_flag: bool,
+
+    /// The line that comes out of the condition code register file. Should contain
+    /// 1 for true or 0 for false.
+    pub condition_code_bit: u8,
+    /// The inversion of `condition_code_bit`.
+    pub condition_code_bit_inverted: u8,
+    /// The result of the multiplexer with `condition_code_bit` and `condition_code_bit_inverted`.
+    pub condition_code_mux: u8,
+
+    pub data_from_main_processor: u64,
+    pub data_writeback: u64,
+    pub destination: usize,
+    pub fp_register_data_from_main_processor: u64,
+    pub read_data_1: u64,
+    pub read_data_2: u64,
+    pub register_write_data: u64,
+    pub register_write_mux_to_mux: u64,
+    pub sign_extend_data: u64,
+
+    /// Data line that goes from `Read Data 2` to the multiplexer in the main processor
+    /// controlled by [`MemWriteSrc`](super::control_signals::MemWriteSrc).
+    /// This variable in a way in just a copy of read_data_2
+    pub fp_register_to_memory: u64,
+
+    pub alu_result: u64,
+    pub comparator_result: u64,
+}
+
+impl RiscFpCoprocessor {
+    // ========================== Stages ==========================
+    pub fn stage_instruction_decode(&mut self) {
+        self.instruction_decode();
+        self.set_control_signals();
+        self.read_registers();
+    }
+
+    pub fn stage_execute(&mut self) {
+        self.alu();
+        self.comparator();
+        self.write_condition_code();
+        self.write_fp_register_to_memory();
+        self.set_condition_code_line();
+    }
+
+    pub fn stage_memory(&mut self) {
+        self.write_data();
+        self.set_data_writeback();
+        self.set_fpu_branch();
+    }
+
+    pub fn stage_writeback(&mut self) {
+        self.register_write();
+    }
+
+    // ===================== General Functions =====================
+    /// Handle an otherwise irrecoverable error within the datapath.
+    pub fn error(&mut self, _message: &str) {
+        self.is_halted = true;
+    }
+
+    // =================== API For Main Processor ===================
+    /// Set the internally-stored copy of the current instruction. This effectively
+    /// operates in lieu of any "instruction fetch" functionality since the coprocessor
+    /// does not fetch instructions.
+    pub fn set_instruction(&mut self, instruction_bits: u32) {
+        self.state.instruction = instruction_bits;
+        if let Ok(instruction) = Instruction::try_from(self.state.instruction) {
+            self.instruction = instruction;
+        }
+    }
+
+    /// Sets the data line between the main processor and the `Data` register. This
+    /// is then used if deciding data from the main processor should go into the `Data`
+    /// register.
+    pub fn set_data_from_main_processor(&mut self, data: u64) {
+        self.state.data_from_main_processor = data;
+    }
+
+    /// Gets the contents of the data line between the `Data` register and the multiplexer
+    /// in the main processor controlled by the [`DataWrite`] control signal.
+    pub fn get_data_writeback(&mut self) -> u64 {
+        self.state.data_writeback
+    }
+
+    /// Sets the data line between the multiplexer controlled by [`MemToReg`](super::control_signals::MemToReg)
+    /// in the main processor and the multiplexer controlled by [`FpuMemToReg`] in the
+    /// floating-point coprocessor.
+    pub fn set_fp_register_data_from_main_processor(&mut self, data: u64) {
+        self.state.fp_register_data_from_main_processor = data;
+    }
+
+    /// Gets the contents of the data line that goes from `Read Data 2` to the multiplexer
+    /// in the main processor controlled by [`MemWriteSrc`](super::control_signals::MemWriteSrc).
+    pub fn get_fp_register_to_memory(&mut self) -> u64 {
+        self.state.fp_register_to_memory
+    }
+
+    pub fn set_register(&mut self, _register: usize, _data: u64) -> Result<(), String> {
+        if _register >= 32 {
+            return Err(format!("Register index out of bounds: {}", _register));
+        }
+
+        let register = &mut self.registers.fpr[_register];
+        *register = _data;
+
+        Ok(())
+    }
+
+    pub fn register_from_str(&self, _register: &str) -> Option<usize> {
+        // Check if register matches a register between f0 and f31
+        if _register.len() >= 2 && &_register[0..1] == "f" && _register.len() <= 3 {
+            let register = &_register[1..];
+            if let Ok(register) = register.parse::<usize>() {
+                if register < 32 {
+                    return Some(register);
+                }
+            }
+        }
+        None
+    }
+
+    // ================== Instruction Decode (ID) ==================
+    /// Decode an instruction into its individual fields.
+    fn instruction_decode(&mut self) {
+        // Set the data lines based on the contents of the instruction.
+        // Some lines will hold uninitialized values as a result.
+        match self.instruction {
+            Instruction::RType(r) => {
+                self.state.rs1 = r.rs1 as u32;
+                self.state.rs2 = r.rs2 as u32;
+                self.state.rd = r.rd as u32;
+                self.state.shamt = r.rs2 as u32;
+                self.state.funct3 = r.funct3 as u32;
+                self.state.funct7 = r.funct7 as u32;
+            }
+            Instruction::IType(i) => {
+                self.state.rs1 = i.rs1 as u32;
+                self.state.funct3 = i.funct3 as u32;
+                self.state.rd = i.rd as u32;
+                self.state.imm = i.imm as u32;
+                self.state.shamt = (i.imm & 0x003f) as u32;
+            }
+            Instruction::SType(s) => {
+                self.state.rs2 = s.rs2 as u32;
+                self.state.rs1 = s.rs1 as u32;
+                self.state.funct3 = s.funct3 as u32;
+                self.state.imm1 = s.imm1 as u32;
+                self.state.imm2 = s.imm2 as u32;
+            }
+            Instruction::R4Type(r4) => {
+                self.state.rs3 = r4.rs3 as u32;
+                self.state.funct2 = r4.funct2 as u32;
+                self.state.rs2 = r4.rs2 as u32;
+                self.state.rs1 = r4.rs1 as u32;
+                self.state.funct3 = r4.funct3 as u32;
+                self.state.rd = r4.rd as u32;
+            }
+            _ => (),
+        }
+    }
+
+    /// Set the control signals of the processor based on the instruction opcode and function
+    /// control signals.
+    fn set_control_signals(&mut self) {
+        
+    }
+
+    /// Read the registers as specified from the instruction and pass
+    /// the data into the datapath.
+    fn read_registers(&mut self) {
+        let reg1 = self.state.fs as usize;
+        let reg2 = self.state.ft as usize;
+
+        self.state.read_data_1 = self.registers.fpr[reg1];
+        self.state.read_data_2 = self.registers.fpr[reg2];
+
+        // Truncate the variable data if a 32-bit word is requested.
+        if let FpuRegWidth::Word = self.signals.fpu_reg_width {
+            self.state.read_data_1 = self.registers.fpr[reg1] as u32 as u64;
+            self.state.read_data_2 = self.registers.fpr[reg2] as u32 as u64;
+        }
+    }
+
+    // ======================= Execute (EX) =======================
+    /// Perform an ALU operation.
+    fn alu(&mut self) {
+        let input1 = self.state.read_data_1;
+        let input2 = self.state.read_data_2;
+
+        let mut input1_f32 = 0f32;
+        let mut input2_f32 = 0f32;
+        let mut input1_f64 = 0f64;
+        let mut input2_f64 = 0f64;
+
+        // Truncate the inputs if 32-bit operations are expected.
+        if let FpuRegWidth::Word = self.signals.fpu_reg_width {
+            input1_f32 = f32::from_bits(input1 as u32);
+            input2_f32 = f32::from_bits(input2 as u32);
+        } else {
+            input1_f64 = f64::from_bits(input1);
+            input2_f64 = f64::from_bits(input2);
+        }
+
+        self.state.alu_result = match self.signals.fpu_alu_op {
+            FpuAluOp::Addition => match self.signals.fpu_reg_width {
+                FpuRegWidth::Word => f32::to_bits(input1_f32 + input2_f32) as u64,
+                FpuRegWidth::DoubleWord => f64::to_bits(input1_f64 + input2_f64),
+            },
+            FpuAluOp::Subtraction => match self.signals.fpu_reg_width {
+                FpuRegWidth::Word => f32::to_bits(input1_f32 - input2_f32) as u64,
+                FpuRegWidth::DoubleWord => f64::to_bits(input1_f64 - input2_f64),
+            },
+            FpuAluOp::MultiplicationOrEqual => match self.signals.fpu_reg_width {
+                FpuRegWidth::Word => f32::to_bits(input1_f32 * input2_f32) as u64,
+                FpuRegWidth::DoubleWord => f64::to_bits(input1_f64 * input2_f64),
+            },
+            FpuAluOp::Division => match self.signals.fpu_reg_width {
+                FpuRegWidth::Word => {
+                    if input2_f32 == 0f32 {
+                        f32::to_bits(0f32) as u64
+                    } else {
+                        f32::to_bits(input1_f32 / input2_f32) as u64
+                    }
+                }
+                FpuRegWidth::DoubleWord => {
+                    if input2_f64 == 0.0 {
+                        f64::to_bits(0.0)
+                    } else {
+                        f64::to_bits(input1_f64 / input2_f64)
+                    }
+                }
+            },
+            // No operation.
+            FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0,
+            _ => {
+                self.error(&format!(
+                    "Unsupported operation in FPU `{:?}`",
+                    self.signals.fpu_alu_op
+                ));
+                0
+            }
+        };
+    }
+
+    /// Perform a comparison.
+    fn comparator(&mut self) {
+        let input1 = self.state.read_data_1;
+        let input2 = self.state.read_data_2;
+
+        let input1_f32 = f32::from_bits(input1 as u32);
+        let input2_f32 = f32::from_bits(input2 as u32);
+        let input1_f64 = f64::from_bits(input1);
+        let input2_f64 = f64::from_bits(input2);
+
+        self.state.comparator_result = match self.signals.fpu_alu_op {
+            FpuAluOp::MultiplicationOrEqual => match self.signals.fpu_reg_width {
+                FpuRegWidth::Word => (input1_f32 == input2_f32) as u64,
+                FpuRegWidth::DoubleWord => (input1_f64 == input2_f64) as u64,
+            },
+            FpuAluOp::Slt => match self.signals.fpu_reg_width {
+                FpuRegWidth::Word => (input1_f32 < input2_f32) as u64,
+                FpuRegWidth::DoubleWord => (input1_f64 < input2_f64) as u64,
+            },
+            FpuAluOp::Sle => match self.signals.fpu_reg_width {
+                FpuRegWidth::Word => (input1_f32 <= input2_f32) as u64,
+                FpuRegWidth::DoubleWord => (input1_f64 <= input2_f64) as u64,
+            },
+            FpuAluOp::Sngt => match self.signals.fpu_reg_width {
+                FpuRegWidth::Word => !input1_f32.gt(&input2_f32) as u64,
+                FpuRegWidth::DoubleWord => !input1_f64.gt(&input2_f64) as u64,
+            },
+            FpuAluOp::Snge => match self.signals.fpu_reg_width {
+                FpuRegWidth::Word => !input1_f32.ge(&input2_f32) as u64,
+                FpuRegWidth::DoubleWord => !input1_f64.ge(&input2_f64) as u64,
+            },
+            FpuAluOp::Addition | FpuAluOp::Subtraction | FpuAluOp::Division => 0, // No operation
+            _ => {
+                self.error(&format!(
+                    "Unsupported operation in comparator `{:?}`",
+                    self.signals.fpu_alu_op
+                ));
+                0
+            }
+        }
+    }
+
+    /// Write to the `Data` register. This register is used to transfer data between
+    /// the main processor and the coprocessor.
+    fn write_data(&mut self) {
+        if let DataWrite::NoWrite = self.signals.data_write {
+            return;
+        }
+
+        self.data = match self.signals.data_src {
+            DataSrc::FloatingPointUnit => self.state.read_data_1,
+            DataSrc::MainProcessorUnit => self.state.data_from_main_processor,
+        };
+    }
+
+    /// Set the condition code (CC) register based on the result from the comparator.
+    fn write_condition_code(&mut self) {
+        if let CcWrite::YesWrite = self.signals.cc_write {
+            self.condition_code = self.state.comparator_result;
+        }
+    }
+
+    /// Set the data line that goes from `Read Data 2` to the multiplexer in the main processor
+    /// controlled by [`MemWriteSrc`](super::control_signals::MemWriteSrc).
+    fn write_fp_register_to_memory(&mut self) {
+        self.state.fp_register_to_memory = self.state.read_data_2;
+    }
+
+    // ======================= Memory (MEM) =======================
+    /// Set the data line that goes out of the condition code register file.
+    fn set_condition_code_line(&mut self) {
+        // The MIPS architecture supports more than one condition code, but SWIM
+        // manually uses only one. This stubs the possible use of more than one
+        // for future development.
+        let selected_register_data = match self.signals.cc {
+            Cc::Cc0 => self.condition_code,
+        };
+
+        // This only considers one bit of the selected condition code register.
+        self.state.condition_code_bit = match selected_register_data % 2 {
+            0 => 0,
+            _ => 1,
+        };
+    }
+
+    /// Set the data line between the multiplexer after the `Data` register and the
+    /// multiplexer in the main processor controlled by the [`DataWrite`] control signal.
+    fn set_data_writeback(&mut self) {
+        self.state.sign_extend_data = self.data as i32 as i64 as u64;
+        self.state.data_writeback = match self.signals.fpu_reg_width {
+            FpuRegWidth::Word => self.state.sign_extend_data,
+            FpuRegWidth::DoubleWord => self.data,
+        }
+    }
+
+    /// Simulate the logic between `self.state.condition_code_bit` and the FPU branch
+    /// AND gate.
+    fn set_fpu_branch(&mut self) {
+        // Invert the condition code. (In this case, instead of using a bitwise NOT, this
+        // will invert only the last digit and leave the rest as 0.)
+        self.state.condition_code_bit_inverted = match self.state.condition_code_bit % 2 {
+            0 => 1,
+            _ => 0,
+        };
+
+        // Run the multiplexer.
+        self.state.condition_code_mux = match self.state.branch_flag {
+            // 0 - Use inverted condition code.
+            false => self.state.condition_code_bit_inverted,
+            // 1 - Use condition code value as-is.
+            true => self.state.condition_code_bit,
+        };
+
+        // Set the result of the AND gate.
+        self.signals.fpu_take_branch = if self.signals.fpu_branch == FpuBranch::YesBranch
+            && self.state.condition_code_mux == 1
+        {
+            FpuTakeBranch::YesBranch
+        } else {
+            FpuTakeBranch::NoBranch
+        };
+    }
+
+    // ====================== Writeback (WB) ======================
+    /// Write data to the floating-point register file.
+    fn register_write(&mut self) {
+        if let FpuRegWrite::NoWrite = self.signals.fpu_reg_write {
+            return;
+        }
+
+        self.state.destination = match self.signals.fpu_reg_dst {
+            FpuRegDst::Reg1 => self.state.ft as usize,
+            FpuRegDst::Reg2 => self.state.fs as usize,
+            FpuRegDst::Reg3 => self.state.fd as usize,
+        };
+
+        self.state.register_write_mux_to_mux = match self.signals.data_write {
+            DataWrite::NoWrite => self.state.alu_result,
+            DataWrite::YesWrite => self.data,
+        };
+        self.state.register_write_data = match self.signals.fpu_mem_to_reg {
+            FpuMemToReg::UseDataWrite => self.state.register_write_mux_to_mux,
+            FpuMemToReg::UseMemory => self.state.fp_register_data_from_main_processor,
+        };
+        self.registers.fpr[self.state.destination] = self.state.register_write_data;
+    }
+}
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index d8d052c54..b69860bc5 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -506,9 +506,7 @@ impl RiscDatapath {
                 self.state.imm = j.imm;
                 self.state.rd = j.rd as u32;
             }
-            Instruction::R4Type(r) => {
-                self.state.rd = r.rd as u32;
-            }
+            _ => (),
         }
     }
 
diff --git a/src/emulation_core/riscv/instruction.rs b/src/emulation_core/riscv/instruction.rs
index 5007a9445..57bd1ede8 100644
--- a/src/emulation_core/riscv/instruction.rs
+++ b/src/emulation_core/riscv/instruction.rs
@@ -1,5 +1,7 @@
 //! Abstract representation of an instruction.
 
+use serde::{Deserialize, Serialize};
+
 use super::constants::*;
 
 /// Register (R-Type) Instruction
@@ -20,7 +22,7 @@ use super::constants::*;
 /// - funct3:
 /// - rd: CPU register - can be used as a destination for the result of executed instructions.
 /// - opcode: Determines the type of instruction executed. This is typically 0110011 in R-type instructions.
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct RType {
     pub funct7: u8,
     pub rs2: u8,
@@ -30,7 +32,7 @@ pub struct RType {
     pub op: u8,
 }
 
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct IType {
     pub imm: u16,
     pub rs1: u8,
@@ -39,7 +41,7 @@ pub struct IType {
     pub op: u8,
 }
 
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct SType {
     pub imm1: u8,
     pub rs2: u8,
@@ -49,7 +51,7 @@ pub struct SType {
     pub op: u8,
 }
 
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct BType {
     pub imm1: u8,
     pub rs2: u8,
@@ -59,21 +61,21 @@ pub struct BType {
     pub op: u8,
 }
 
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct UType {
     pub imm: u32,
     pub rd: u8,
     pub op: u8,
 }
 
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct JType {
     pub imm: u32,
     pub rd: u8,
     pub op: u8,
 }
 
-#[derive(Clone, Copy, Debug, Default, PartialEq)]
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
 pub struct R4Type {
     pub rs3: u8,
     pub funct2: u8,
@@ -84,7 +86,7 @@ pub struct R4Type {
     pub op: u8,
 }
 
-#[derive(Clone, Debug, PartialEq)]
+#[derive(Clone, Debug, PartialEq, Serialize, Deserialize)]
 pub enum Instruction {
     RType(RType),
     IType(IType),
@@ -163,6 +165,19 @@ impl TryFrom<u32> for Instruction {
                 op: (value & 0x7f) as u8,
             })),
 
+            // R4-type instruction:
+            OPCODE_MADD | OPCODE_MSUB | OPCODE_NMSUB | OPCODE_NMADD => {
+                Ok(Instruction::R4Type(R4Type {
+                    rs3: (value >> 27) as u8,
+                    funct2: ((value >> 25) & 0x3) as u8,
+                    rs2: ((value >> 20) & 0x1f) as u8,
+                    rs1: ((value >> 15) & 0x1f) as u8,
+                    funct3: ((value >> 12) & 0x07) as u8,
+                    rd: ((value >> 7) & 0x1f) as u8,
+                    op: (value & 0x7f) as u8,
+                }))
+            }
+
             _ => Err(format!("opcode `{op}` not supported")),
         }
     }
diff --git a/src/emulation_core/riscv/registers.rs b/src/emulation_core/riscv/registers.rs
index 77f092d8e..d69c76366 100644
--- a/src/emulation_core/riscv/registers.rs
+++ b/src/emulation_core/riscv/registers.rs
@@ -257,3 +257,167 @@ impl IntoIterator for RiscGpRegisters {
         }
     }
 }
+
+/// Collection of general-purpose registers used by the datapath.
+#[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
+pub struct FpRegisters {
+    pub fpr: [u64; 32],
+}
+
+/// Specifies all of the valid registers accessible in an instance
+/// of [`FpRegisters`].
+#[derive(Clone, Copy, Debug, Display, EnumIter, EnumString, Eq, PartialEq)]
+#[strum(ascii_case_insensitive)]
+#[strum(serialize_all = "lowercase")]
+pub enum FpRegisterType {
+    F0 = 0,
+    F1 = 1,
+    F2 = 2,
+    F3 = 3,
+    F4 = 4,
+    F5 = 5,
+    F6 = 6,
+    F7 = 7,
+    F8 = 8,
+    F9 = 9,
+    F10 = 10,
+    F11 = 11,
+    F12 = 12,
+    F13 = 13,
+    F14 = 14,
+    F15 = 15,
+    F16 = 16,
+    F17 = 17,
+    F18 = 18,
+    F19 = 19,
+    F20 = 20,
+    F21 = 21,
+    F22 = 22,
+    F23 = 23,
+    F24 = 24,
+    F25 = 25,
+    F26 = 26,
+    F27 = 27,
+    F28 = 28,
+    F29 = 29,
+    F30 = 30,
+    F31 = 31,
+    FCSR = 32,
+}
+
+impl RegisterType for FpRegisterType {
+    fn get_register_name(&self) -> String {
+        format!("f{}", *self as u32)
+    }
+    fn is_valid_register_value(&self, _value: u64, _pc_limit: usize) -> bool {
+        true
+    }
+}
+
+impl Registers for FpRegisters {
+    fn get_dyn_register_list(&self) -> Vec<(Rc<dyn RegisterType>, u64)> {
+        self.into_iter()
+            .map(|(register, val)| {
+                let register: Rc<dyn RegisterType> = Rc::new(register);
+                (register, val)
+            })
+            .collect()
+    }
+}
+
+impl ToString for FpRegisters {
+    fn to_string(&self) -> String {
+        let mut output = String::new();
+
+        let fpr_registers = self
+            .fpr
+            .iter()
+            .enumerate()
+            .map(|(i, inst)| format!("fpr[{i}] = {inst}"))
+            .collect::<Vec<String>>()
+            .join("\n");
+        output.push_str(&fpr_registers);
+
+        output
+    }
+}
+
+impl Index<&str> for FpRegisters {
+    type Output = u64;
+
+    // Convert string to the corresponding RegistersEnum value and use this to index.
+    // If this is an invalid string, no enum will be returned, causing a panic as desired.
+    fn index(&self, index: &str) -> &Self::Output {
+        match FpRegisterType::from_str(index) {
+            Ok(register) => &self[register],
+            _ => panic!("{index} is not a valid register"),
+        }
+    }
+}
+
+impl IndexMut<&str> for FpRegisters {
+    // Convert string to the corresponding RegistersEnum value and use this to index.
+    // If this is an invalid string, no enum will be returned, causing a panic as desired.
+    fn index_mut(&mut self, index: &str) -> &mut Self::Output {
+        match FpRegisterType::from_str(index) {
+            Ok(register) => &mut self[register],
+            _ => panic!("{index} is not a valid register"),
+        }
+    }
+}
+
+impl Index<FpRegisterType> for FpRegisters {
+    type Output = u64;
+
+    fn index(&self, index: FpRegisterType) -> &Self::Output {
+        &self.fpr[index as usize]
+    }
+}
+
+impl IndexMut<FpRegisterType> for FpRegisters {
+    fn index_mut(&mut self, index: FpRegisterType) -> &mut Self::Output {
+        &mut self.fpr[index as usize]
+    }
+}
+
+/// Iterator that is used to view each register in the register file.
+///
+/// This contains a copy of all the registers and their values, and a [`FpRegisterTypeIter`],
+/// as generated by [`strum::IntoEnumIterator`]. In other iterator implementations,
+/// the internal state might be data like a [`FpRegisterType`]. However, since we can't
+/// normally just "add 1" to get to the next register, we use an internal iterator
+/// that can track the progression of one [`FpRegisterType`] to the next.
+pub struct FpRegistersIter {
+    registers: FpRegisters,
+    register_iter: FpRegisterTypeIter,
+}
+
+/// This implementation of the [`Iterator`] trait essentially wraps the existing
+/// [`FpRegisterTypeIter`] so that the register type can be paired with register data.
+impl Iterator for FpRegistersIter {
+    type Item = (FpRegisterType, u64);
+
+    fn next(&mut self) -> Option<Self::Item> {
+        match self.register_iter.next() {
+            Some(register_type) => Some((register_type, self.registers[register_type])),
+            None => None,
+        }
+    }
+}
+
+/// [`IntoIterator`] is a standard library trait that can convert any type into
+/// an [`Iterator`]. In this case, this is an instance of [`FpRegistersIter`] with all the
+/// data in the registers and a new [`FpRegisterTypeIter`].
+impl IntoIterator for FpRegisters {
+    type Item = (FpRegisterType, u64);
+    type IntoIter = FpRegistersIter;
+
+    /// Consumes the [`FpRegisters`] struct to create a new [`FpRegistersIter`] that can
+    /// be iterated over.
+    fn into_iter(self) -> Self::IntoIter {
+        FpRegistersIter {
+            registers: self,
+            register_iter: FpRegisterType::iter(),
+        }
+    }
+}

From 23213e5edcf17ce69e5a7c58d6337bebca64da7b Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Wed, 27 Mar 2024 20:17:30 -0400
Subject: [PATCH 05/48] Updated Datapath logic for FPU and implemented FLW the
 entire way through.

---
 src/emulation_core/riscv.rs                 |  2 +-
 src/emulation_core/riscv/constants.rs       |  5 ++
 src/emulation_core/riscv/control_signals.rs | 59 ++---------------
 src/emulation_core/riscv/coprocessor.rs     | 45 +++++++++----
 src/emulation_core/riscv/datapath.rs        | 71 +++++++++++++++++++--
 5 files changed, 109 insertions(+), 73 deletions(-)

diff --git a/src/emulation_core/riscv.rs b/src/emulation_core/riscv.rs
index 8085e380a..8e83c2b45 100644
--- a/src/emulation_core/riscv.rs
+++ b/src/emulation_core/riscv.rs
@@ -3,7 +3,7 @@
 
 pub mod constants;
 pub mod control_signals;
-// pub mod coprocessor;
+pub mod coprocessor;
 pub mod datapath;
 pub mod datapath_signals;
 pub mod instruction;
diff --git a/src/emulation_core/riscv/constants.rs b/src/emulation_core/riscv/constants.rs
index b9f29eeaa..bdf49f599 100644
--- a/src/emulation_core/riscv/constants.rs
+++ b/src/emulation_core/riscv/constants.rs
@@ -52,11 +52,13 @@ pub const OPCODE_IMM_32: u8 = 0b0011011;
 pub const OPCODE_JALR: u8 = 0b1100111;
 // LOAD
 pub const OPCODE_LOAD: u8 = 0b0000011;
+pub const OPCODE_LOAD_FP: u8 = 0b0000111;
 // SYSTEM
 pub const OPCODE_SYSTEM: u8 = 0b1110011;
 
 /// Used for S-type instructions.
 pub const OPCODE_STORE: u8 = 0b0100011;
+pub const OPCODE_STORE_FP: u8 = 0b0100111;
 
 /// Used for B-type instructions.
 pub const OPCODE_BRANCH: u8 = 0b1100011;
@@ -80,6 +82,9 @@ pub const OPCODE_NMSUB: u8 = 0b1001011;
 // FNMADD.S
 pub const OPCODE_NMADD: u8 = 0b1001111;
 
+/// Not a Number
+pub const NAN: u8 = 0x7fc00000;
+
 // "ENC" is short for encoding. There is no formal name for this field
 // in the MIPS64 specification, other than the "shamt"/"sa" field that it
 // replaces, so this was chosen as the mnemonic for this project.
diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index c315f7a23..5181aafbb 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -208,41 +208,16 @@ pub mod floating_point {
 
     #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub struct FpuControlSignals {
-        pub cc: Cc,
-        pub cc_write: CcWrite,
         pub data_src: DataSrc,
         pub data_write: DataWrite,
         pub fpu_alu_op: FpuAluOp,
         pub fpu_branch: FpuBranch,
         pub fpu_mem_to_reg: FpuMemToReg,
         pub fpu_reg_dst: FpuRegDst,
-        pub fpu_reg_width: FpuRegWidth,
         pub fpu_reg_write: FpuRegWrite,
         pub fpu_take_branch: FpuTakeBranch,
     }
 
-    /// Determines, given that [`CcWrite`] is set, which condition code register
-    /// should be written to or read from for a given operation.
-    ///
-    /// For the sake of this project, it will usually be assumed that this will
-    /// be 0, however the functionality is available to be extended.
-    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
-    pub enum Cc {
-        /// Use condition code register 0. Default in most operations. Can be
-        /// additionally used in the case where the condition code register is
-        /// irrelevant to the current instruction.
-        #[default]
-        Cc0 = 0,
-    }
-
-    /// Determines if the condition code register file should be written to.
-    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
-    pub enum CcWrite {
-        #[default]
-        NoWrite = 0,
-        YesWrite = 1,
-    }
-
     /// Determines the source of the `Data` register in the floating-point unit.
     ///
     /// This is a special intermediary register that facilitates passing data between
@@ -265,7 +240,7 @@ pub mod floating_point {
     /// This acts as a toggle for the source of data to the main processing unit register
     /// file. Additionally, it acts as a toggle for a source to the floating-point unit
     /// register file (this could be overridden by the [`FpuMemToReg`] control signal).
-    /// For the latter two functions, it is imperative to unset the [`RegWrite`](super::RegWrite) and
+    /// For the latter two functions, it is imperative to unset the [`RegWriteEn`](super::RegWriteEn) and
     /// [`FpuRegWrite`] control signals in cases where registers should not be modified
     /// with unintended data.
     #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
@@ -391,43 +366,17 @@ pub mod floating_point {
     /// to, which largely depends on the instruction format.
     #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum FpuRegDst {
-        /// Use register `ft`.
+        /// Use register `rs1`.
         Reg1 = 0,
 
-        /// Use register `fs`.
+        /// Use register `rs2`.
         Reg2 = 1,
 
-        /// Use register `fd`.
+        /// Use register `rd`.
         #[default]
         Reg3 = 2,
     }
 
-    /// Determines the amount of data to be sent or received from registers and the ALU.
-    ///
-    /// While all buses carrying information are 64-bits wide, some bits of the bus may be
-    /// ignored in the case of this control signal.
-    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
-    pub enum FpuRegWidth {
-        /// Use words (32 bits). Equivalent to a single-precision floating-point value.
-        Word = 0,
-
-        /// Use doublewords (64 bits). Equivalent to a double-precision floating-point value.
-        #[default]
-        DoubleWord = 1,
-    }
-
-    impl FpuRegWidth {
-        /// Get the corresponding [`FpuRegWidth`] control signal based on
-        /// the `fmt` field in an instruction.
-        pub fn from_fmt(fmt: u8) -> Result<Self, String> {
-            match fmt {
-                FMT_SINGLE => Ok(Self::Word),
-                FMT_DOUBLE => Ok(Self::DoubleWord),
-                _ => Err(format!("`{fmt}` is an invalid fmt value")),
-            }
-        }
-    }
-
     /// Determines if the floating-point register file should be written to.
     #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum FpuRegWrite {
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 54f019272..777990a03 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -200,23 +200,44 @@ impl RiscFpCoprocessor {
     /// Set the control signals of the processor based on the instruction opcode and function
     /// control signals.
     fn set_control_signals(&mut self) {
-        
+        match self.instruction {
+            Instruction::RType(r) => {
+                self.set_rtype_control_signals(r);
+            }
+            Instruction::IType(i) => {
+                self.signals = FpuControlSignals {
+                    data_write: DataWrite::NoWrite,
+                    fpu_branch: FpuBranch::NoBranch,
+                    fpu_mem_to_reg: FpuMemToReg::UseMemory,
+                    fpu_reg_dst: FpuRegDst::Reg3,
+                    fpu_reg_write: FpuRegWrite::YesWrite,
+                    ..Default::default()
+                }
+            }
+            Instruction::SType(s) => {
+                self.set_stype_control_signals(s);
+            }
+            Instruction::BType(b) => {
+                self.set_btype_control_signals(b);
+            }
+            Instruction::UType(u) => {
+                self.set_utype_control_signals(u);
+            }
+            Instruction::JType(j) => {
+                self.set_jtype_control_signals(j);
+            }
+            _ => self.error("Unsupported Instruction!"),
+        }
     }
 
     /// Read the registers as specified from the instruction and pass
     /// the data into the datapath.
     fn read_registers(&mut self) {
-        let reg1 = self.state.fs as usize;
-        let reg2 = self.state.ft as usize;
+        let reg1 = self.state.rs1 as usize;
+        let reg2 = self.state.rs2 as usize;
 
         self.state.read_data_1 = self.registers.fpr[reg1];
         self.state.read_data_2 = self.registers.fpr[reg2];
-
-        // Truncate the variable data if a 32-bit word is requested.
-        if let FpuRegWidth::Word = self.signals.fpu_reg_width {
-            self.state.read_data_1 = self.registers.fpr[reg1] as u32 as u64;
-            self.state.read_data_2 = self.registers.fpr[reg2] as u32 as u64;
-        }
     }
 
     // ======================= Execute (EX) =======================
@@ -411,9 +432,9 @@ impl RiscFpCoprocessor {
         }
 
         self.state.destination = match self.signals.fpu_reg_dst {
-            FpuRegDst::Reg1 => self.state.ft as usize,
-            FpuRegDst::Reg2 => self.state.fs as usize,
-            FpuRegDst::Reg3 => self.state.fd as usize,
+            FpuRegDst::Reg1 => self.state.rs1 as usize,
+            FpuRegDst::Reg2 => self.state.rs2 as usize,
+            FpuRegDst::Reg3 => self.state.rd as usize,
         };
 
         self.state.register_write_mux_to_mux = match self.signals.data_write {
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index b69860bc5..f5d16091c 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -50,8 +50,10 @@
 use super::super::datapath::Datapath;
 use super::constants::*;
 use super::control_signals::*;
+use super::control_signals::floating_point::*;
 use super::datapath_signals::*;
 use super::instruction::*;
+use super::coprocessor::RiscFpCoprocessor;
 use super::{super::mips::memory::Memory, registers::RiscGpRegisters};
 use crate::emulation_core::architectures::DatapathRef;
 use crate::emulation_core::datapath::{DatapathUpdateSignal, Syscall};
@@ -63,6 +65,7 @@ use serde::{Deserialize, Serialize};
 pub struct RiscDatapath {
     pub registers: RiscGpRegisters,
     pub memory: Memory,
+    pub coprocessor: RiscFpCoprocessor,
 
     pub instruction: Instruction,
     pub signals: ControlSignals,
@@ -87,8 +90,10 @@ pub struct RiscDatapathState {
     pub instruction: u32,
     pub rs1: u32,
     pub rs2: u32,
+    pub rs3: u32,
     pub rd: u32,
     pub shamt: u32,
+    pub funct2: u32,
     pub funct3: u32,
     pub funct7: u32,
     pub imm: u32,
@@ -197,6 +202,7 @@ impl Default for RiscDatapath {
         let mut datapath = RiscDatapath {
             registers: RiscGpRegisters::default(),
             memory: Memory::default(),
+            coprocessor: RiscFpCoprocessor::default(),
             instruction: Instruction::default(),
             signals: ControlSignals::default(),
             datapath_signals: DatapathSignals::default(),
@@ -260,6 +266,11 @@ impl Datapath for RiscDatapath {
             RiscStage::WriteBack => self.stage_writeback(),
         };
 
+        // If the FPU has halted, reflect this in the main unit.
+        if self.coprocessor.is_halted {
+            self.is_halted = true;
+        }
+
         self.current_stage = RiscStage::get_next_stage(self.current_stage);
         res
     }
@@ -289,8 +300,9 @@ impl Datapath for RiscDatapath {
         DatapathRef::RISCV(self)
     }
 
-    fn set_fp_register_by_str(&mut self, _register: &str, _data: Self::RegisterData) {
-        todo!()
+    fn set_fp_register_by_str(&mut self, register: &str, data: Self::RegisterData) {
+        let register = &mut self.coprocessor.registers[register];
+        *register = data;
     }
 
     fn get_memory_mut(&mut self) -> &mut Memory {
@@ -339,10 +351,12 @@ impl RiscDatapath {
 
         // Upper part of datapath, PC calculation
         self.pc_plus_4();
+        self.coprocessor.set_instruction(self.state.instruction);
 
         // Both state and coprocessor state always update
         DatapathUpdateSignal {
             changed_state: true,
+            changed_coprocessor_state: true,
             ..Default::default()
         }
     }
@@ -359,6 +373,10 @@ impl RiscDatapath {
         self.set_immediate();
         self.read_registers();
 
+        self.coprocessor.stage_instruction_decode();
+        self.coprocessor
+            .set_data_from_main_processor(self.state.read_data_1);
+
         // Check if we hit a syscall or breakpoint and signal it to the caller.
         let (hit_syscall, hit_breakpoint) = (
             self.signals.sys_op == SysOp::ECALL,
@@ -368,6 +386,7 @@ impl RiscDatapath {
         // Instruction decode always involves a state update
         DatapathUpdateSignal {
             changed_state: true,
+            changed_coprocessor_state: true,
             hit_syscall,
             hit_breakpoint,
             ..Default::default()
@@ -381,9 +400,11 @@ impl RiscDatapath {
         self.alu();
         self.calc_relative_pc_branch();
         self.calc_cpu_branch_signal();
+        self.coprocessor.stage_execute();
 
         DatapathUpdateSignal {
             changed_state: true,
+            changed_coprocessor_state: true,
             ..Default::default()
         }
     }
@@ -407,6 +428,8 @@ impl RiscDatapath {
             ReadWrite::StoreDouble => self.memory_write(),
         }
 
+        self.coprocessor.stage_memory();
+
         // PC calculation stuff from upper part of datapath
         self.calc_general_branch_signal();
         self.pick_pc_plus_4_or_relative_branch_addr_mux1();
@@ -418,6 +441,7 @@ impl RiscDatapath {
                 | (self.signals.read_write == ReadWrite::StoreDouble)
                 | (self.signals.read_write == ReadWrite::StoreHalf)
                 | (self.signals.read_write == ReadWrite::StoreWord)),
+            changed_coprocessor_state: true,
             ..Default::default()
         }
     }
@@ -428,11 +452,17 @@ impl RiscDatapath {
     /// if desired. Additionally, set the PC for the next instruction.
     fn stage_writeback(&mut self) -> DatapathUpdateSignal {
         self.register_write();
+        self.coprocessor
+            .set_fp_register_data_from_main_processor(self.state.data_result);
         self.set_pc();
+        self.coprocessor.stage_writeback();
 
         DatapathUpdateSignal {
             changed_state: true,
+            changed_coprocessor_state: true,
             changed_registers: true, // Always true because pc always gets updated
+            changed_coprocessor_registers: self.coprocessor.signals.fpu_reg_write
+                == FpuRegWrite::YesWrite,
             ..Default::default()
         }
     }
@@ -506,7 +536,14 @@ impl RiscDatapath {
                 self.state.imm = j.imm;
                 self.state.rd = j.rd as u32;
             }
-            _ => (),
+            Instruction::R4Type(r4) => {
+                self.state.rs3 = r4.rs3 as u32;
+                self.state.funct2 = r4.funct2 as u32;
+                self.state.rs2 = r4.rs2 as u32;
+                self.state.rs1 = r4.rs1 as u32;
+                self.state.funct3 = r4.funct3 as u32;
+                self.state.rd = r4.rd as u32;
+            }
         }
     }
 
@@ -659,6 +696,20 @@ impl RiscDatapath {
                     _ => (),
                 }
             }
+            OPCODE_LOAD_FP => {
+                self.signals.wb_sel = WBSel::UseMemory;
+                self.signals.reg_write_en = RegWriteEn::NoWrite;
+                match i.funct3 {
+                    0 => self.signals.read_write = ReadWrite::LoadByte,
+                    1 => self.signals.read_write = ReadWrite::LoadHalf,
+                    2 => self.signals.read_write = ReadWrite::LoadWord,
+                    3 => self.signals.read_write = ReadWrite::LoadDouble,
+                    4 => self.signals.read_write = ReadWrite::LoadByteUnsigned,
+                    5 => self.signals.read_write = ReadWrite::LoadHalfUnsigned,
+                    6 => self.signals.read_write = ReadWrite::LoadWordUnsigned,
+                    _ => (),
+                }
+            }
             OPCODE_SYSTEM => {
                 self.signals.imm_select = ImmSelect::IUnsigned;
                 self.signals.wb_sel = WBSel::UseAlu;
@@ -955,7 +1006,10 @@ impl RiscDatapath {
     fn memory_write(&mut self) {
         let address = self.state.alu_result;
 
-        self.state.write_data = self.state.read_data_2;
+        self.state.write_data = match self.signals.mem_write_src {
+            MemWriteSrc::PrimaryUnit => self.state.read_data_2,
+            MemWriteSrc::FloatingPointUnit => self.coprocessor.get_fp_register_to_memory(),
+        };
 
         // Choose the correct store function based on the RegWidth
         // control signal.
@@ -991,6 +1045,10 @@ impl RiscDatapath {
         if let CpuBranch::YesBranch = self.datapath_signals.cpu_branch {
             self.datapath_signals.general_branch = GeneralBranch::YesBranch;
         }
+
+        if let FpuTakeBranch::YesBranch = self.coprocessor.signals.fpu_take_branch {
+            self.datapath_signals.general_branch = GeneralBranch::YesBranch;
+        }
     }
 
     fn pick_pc_plus_4_or_relative_branch_addr_mux1(&mut self) {
@@ -1022,7 +1080,10 @@ impl RiscDatapath {
         };
 
         // Decide to retrieve data either from the main processor or the coprocessor.
-        self.state.register_write_data = self.state.data_result;
+        self.state.register_write_data = match self.coprocessor.signals.data_write {
+            DataWrite::NoWrite => self.state.data_result,
+            DataWrite::YesWrite => self.coprocessor.get_data_writeback(),
+        };
 
         // Abort if the RegWrite signal is not set.
         if self.signals.reg_write_en == RegWriteEn::NoWrite {

From 7dbadebb4b1582ce19dde07cac8f8aa29730662b Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Wed, 27 Mar 2024 20:37:06 -0400
Subject: [PATCH 06/48] Implemented FSW all the way. Still errors.

---
 src/emulation_core/riscv/coprocessor.rs | 11 ++++++++---
 src/emulation_core/riscv/datapath.rs    |  4 ++++
 src/emulation_core/riscv/instruction.rs |  2 +-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 777990a03..4edd22d35 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -215,7 +215,12 @@ impl RiscFpCoprocessor {
                 }
             }
             Instruction::SType(s) => {
-                self.set_stype_control_signals(s);
+                self.signals = FpuControlSignals {
+                    data_write: DataWrite::NoWrite,
+                    fpu_branch: FpuBranch::NoBranch,
+                    fpu_reg_write: FpuRegWrite::NoWrite,
+                    ..Default::default()
+                }
             }
             Instruction::BType(b) => {
                 self.set_btype_control_signals(b);
@@ -363,10 +368,10 @@ impl RiscFpCoprocessor {
         }
     }
 
-    /// Set the data line that goes from `Read Data 2` to the multiplexer in the main processor
+    /// Set the data line that goes from `Read Data 1` to the multiplexer in the main processor
     /// controlled by [`MemWriteSrc`](super::control_signals::MemWriteSrc).
     fn write_fp_register_to_memory(&mut self) {
-        self.state.fp_register_to_memory = self.state.read_data_2;
+        self.state.fp_register_to_memory = self.state.read_data_1;
     }
 
     // ======================= Memory (MEM) =======================
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index f5d16091c..af8c40583 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -756,6 +756,10 @@ impl RiscDatapath {
             ..Default::default()
         };
 
+        if s.op == OPCODE_STORE_FP {
+            self.signals.mem_write_src = MemWriteSrc::FloatingPointUnit;
+        }
+
         match s.funct3 {
             0 => self.signals.read_write = ReadWrite::StoreByte,
             1 => self.signals.read_write = ReadWrite::StoreHalf,
diff --git a/src/emulation_core/riscv/instruction.rs b/src/emulation_core/riscv/instruction.rs
index 57bd1ede8..e53e947b0 100644
--- a/src/emulation_core/riscv/instruction.rs
+++ b/src/emulation_core/riscv/instruction.rs
@@ -132,7 +132,7 @@ impl TryFrom<u32> for Instruction {
             }
 
             // S-type instruction:
-            OPCODE_STORE => Ok(Instruction::SType(SType {
+            OPCODE_STORE | OPCODE_STORE_FP => Ok(Instruction::SType(SType {
                 imm1: (value >> 25) as u8,
                 rs2: ((value >> 20) & 0x1f) as u8,
                 rs1: ((value >> 15) & 0x1f) as u8,

From 4e993b878bac5b285a67cc258e9ed673ed28ba8d Mon Sep 17 00:00:00 2001
From: Geetis <capiix1@gmail.com>
Date: Wed, 27 Mar 2024 20:44:57 -0400
Subject: [PATCH 07/48] RV32M and RV64M support

---
 src/emulation_core/riscv/control_signals.rs | 10 ++++
 src/emulation_core/riscv/datapath.rs        | 63 +++++++++++++++++++--
 static/assembly_examples/riscv_test.asm     |  6 +-
 3 files changed, 70 insertions(+), 9 deletions(-)

diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index dd9a1717b..fe0b494b1 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -99,6 +99,16 @@ pub enum AluOp {
 
     /// `_1110` (14) - Perform unsigned integer division. (Returns the integer quotient.)
     DivisionUnsigned,
+
+    MultiplicationSignedUpper,
+
+    MultiplicationSignedUnsignedUpper,
+
+    MultiplicationUnsignedSignedUpper,
+
+    RemainderSigned,
+
+    RemainderUnsigned,
 }
 
 #[derive(Clone, Default, PartialEq)]
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index a49751390..00287aa29 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -636,19 +636,45 @@ impl RiscDatapath {
             0 => match r.funct7 {
                 0b0000000 => self.signals.alu_op = AluOp::Addition,
                 0b0100000 => self.signals.alu_op = AluOp::Subtraction,
+                0b0000001 => self.signals.alu_op = AluOp::MultiplicationSigned,
+                _ => (),
+            },
+            1 => match r.funct7 {
+                0b0000000 => self.signals.alu_op = AluOp::ShiftLeftLogical(self.state.rs2),
+                0b0000001 => self.signals.alu_op = AluOp::MultiplicationSignedUpper,
+                _ => (),
+            },
+            2 => match r.funct7 {
+                0b0000000 => self.signals.alu_op = AluOp::SetOnLessThanSigned,
+                0b0000001 => self.signals.alu_op = AluOp::MultiplicationSignedUnsignedUpper,
+                _ => (),
+            },
+            3 => match r.funct7 {
+                0b0000000 => self.signals.alu_op = AluOp::SetOnLessThanUnsigned,
+                0b0000001 => self.signals.alu_op = AluOp::MultiplicationUnsignedSignedUpper,
+                _ => (),
+            },
+            4 => match r.funct7 {
+                0b0000000 => self.signals.alu_op = AluOp::Xor,
+                0b0000001 => self.signals.alu_op = AluOp::DivisionSigned,
                 _ => (),
             },
-            1 => self.signals.alu_op = AluOp::ShiftLeftLogical(self.state.rs2),
-            2 => self.signals.alu_op = AluOp::SetOnLessThanSigned,
-            3 => self.signals.alu_op = AluOp::SetOnLessThanUnsigned,
-            4 => self.signals.alu_op = AluOp::Xor,
             5 => match r.funct7 {
                 0b0000000 => self.signals.alu_op = AluOp::ShiftRightLogical(self.state.rs2),
                 0b0100000 => self.signals.alu_op = AluOp::ShiftRightArithmetic(self.state.rs2),
+                0b0000001 => self.signals.alu_op = AluOp::DivisionUnsigned,
+                _ => (),
+            },
+            6 => match r.funct7 {
+                0b0000000 => self.signals.alu_op = AluOp::Or,
+                0b0000001 => self.signals.alu_op = AluOp::RemainderSigned,
+                _ => (),
+            },
+            7 => match r.funct7 {
+                0b0000000 => self.signals.alu_op = AluOp::And,
+                0b0000001 => self.signals.alu_op = AluOp::RemainderUnsigned,
                 _ => (),
             },
-            6 => self.signals.alu_op = AluOp::Or,
-            7 => self.signals.alu_op = AluOp::And,
             _ => (),
         }
     }
@@ -875,6 +901,17 @@ impl RiscDatapath {
             AluOp::MultiplicationUnsigned => {
                 ((self.state.alu_input1 as u128) * (self.state.alu_input2 as u128)) as u64
             }
+            AluOp::MultiplicationSignedUpper => {
+                (((self.state.alu_input1 as i128) * (self.state.alu_input2 as i128)) >> 64) as u64
+            }
+            AluOp::MultiplicationSignedUnsignedUpper => {
+                (((self.state.alu_input1 as i128) * (self.state.alu_input2 as u128 as i128)) >> 64)
+                    as u64
+            }
+            AluOp::MultiplicationUnsignedSignedUpper => {
+                (((self.state.alu_input1 as u128 as i128) * (self.state.alu_input2 as i128)) >> 64)
+                    as u64
+            }
             AluOp::DivisionSigned => {
                 if self.state.alu_input2 == 0 {
                     0
@@ -889,6 +926,20 @@ impl RiscDatapath {
                     self.state.alu_input1 / self.state.alu_input2
                 }
             }
+            AluOp::RemainderSigned => {
+                if self.state.alu_input2 == 0 {
+                    0
+                } else {
+                    ((self.state.alu_input1 as i64) % (self.state.alu_input2 as i64)) as u64
+                }
+            }
+            AluOp::RemainderUnsigned => {
+                if self.state.alu_input2 == 0 {
+                    0
+                } else {
+                    self.state.alu_input1 % self.state.alu_input2
+                }
+            }
             _ => 0,
         };
 
diff --git a/static/assembly_examples/riscv_test.asm b/static/assembly_examples/riscv_test.asm
index ef828b552..f1f6791c4 100644
--- a/static/assembly_examples/riscv_test.asm
+++ b/static/assembly_examples/riscv_test.asm
@@ -1,4 +1,4 @@
 main:
-    jal x1, 2044
-    fmv.s f1, f2
-    ret
\ No newline at end of file
+        addi x1, x0, 50
+        addi x2, x0, 2
+        mul x3, x1, x2
\ No newline at end of file

From f5c369a24d78ea9616d551c407af8f7524254783 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Wed, 27 Mar 2024 21:35:00 -0400
Subject: [PATCH 08/48] Added logic for Floating Point Addition, Subtraction,
 Multiplication, and Division. Fixed errors. SWIM_v2 once again compiles and
 works. FPU support still rudimentary, will continue to add instructions until
 the end of Thursday.

---
 src/emulation_core/riscv/constants.rs       |   3 +-
 src/emulation_core/riscv/control_signals.rs |  12 ++
 src/emulation_core/riscv/coprocessor.rs     | 143 +++++++-------------
 src/emulation_core/riscv/datapath.rs        |   8 +-
 src/emulation_core/riscv/instruction.rs     |   2 +-
 5 files changed, 73 insertions(+), 95 deletions(-)

diff --git a/src/emulation_core/riscv/constants.rs b/src/emulation_core/riscv/constants.rs
index bdf49f599..7f3647ab5 100644
--- a/src/emulation_core/riscv/constants.rs
+++ b/src/emulation_core/riscv/constants.rs
@@ -44,6 +44,7 @@ pub const FUNCT_SOP37: u8 = 0b011111;
 /// Used for R-type instructions.
 pub const OPCODE_OP: u8 = 0b0110011;
 pub const OPCODE_OP_32: u8 = 0b0111011;
+pub const OPCODE_OP_FP: u8 = 0b1010011;
 
 /// Used for I-type instructions.
 pub const OPCODE_IMM: u8 = 0b0010011;
@@ -83,7 +84,7 @@ pub const OPCODE_NMSUB: u8 = 0b1001011;
 pub const OPCODE_NMADD: u8 = 0b1001111;
 
 /// Not a Number
-pub const NAN: u8 = 0x7fc00000;
+pub const NAN: u32 = 0x7fc00000;
 
 // "ENC" is short for encoding. There is no formal name for this field
 // in the MIPS64 specification, other than the "shamt"/"sa" field that it
diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index 5181aafbb..77abfdd4c 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -203,11 +203,13 @@ pub enum RegWriteEn {
 }
 
 pub mod floating_point {
+
     use super::super::constants::*;
     use serde::{Deserialize, Serialize};
 
     #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub struct FpuControlSignals {
+        pub round_mode: RoundingMode,
         pub data_src: DataSrc,
         pub data_write: DataWrite,
         pub fpu_alu_op: FpuAluOp,
@@ -332,6 +334,16 @@ pub mod floating_point {
             }
         }
     }
+    #[derive(Clone, Debug, Default, PartialEq, Serialize, Deserialize)]
+    pub enum RoundingMode {
+        RNE = 0,
+        RTZ = 1,
+        RDN = 2,
+        RUP = 3,
+        RMM = 4,
+        #[default]
+        DRM = 7,
+    }
 
     /// Determines if the floating-point unit should consider branching, based on the
     /// contents of the condition code register.
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 4edd22d35..a711a6dcf 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -1,9 +1,9 @@
 //! Implementation of a RISC-V floating-point coprocessor.
 
-use super::constants::*;
+// use super::constants::*;
 use super::control_signals::floating_point::*;
-use super::registers::FpRegisters;
 use super::instruction::Instruction;
+use super::registers::FpRegisters;
 use serde::{Deserialize, Serialize};
 
 /// An implementation of a floating-point coprocessor for the RISC-V ISA.
@@ -202,9 +202,34 @@ impl RiscFpCoprocessor {
     fn set_control_signals(&mut self) {
         match self.instruction {
             Instruction::RType(r) => {
-                self.set_rtype_control_signals(r);
+                self.signals = FpuControlSignals {
+                    data_write: DataWrite::NoWrite,
+                    fpu_branch: FpuBranch::NoBranch,
+                    fpu_mem_to_reg: FpuMemToReg::UseDataWrite,
+                    fpu_reg_dst: FpuRegDst::Reg3,
+                    fpu_reg_write: FpuRegWrite::YesWrite,
+                    ..Default::default()
+                };
+
+                match r.funct7 >> 2 {
+                    0 => self.signals.fpu_alu_op = FpuAluOp::Addition,
+                    4 => self.signals.fpu_alu_op = FpuAluOp::Subtraction,
+                    8 => self.signals.fpu_alu_op = FpuAluOp::MultiplicationOrEqual,
+                    12 => self.signals.fpu_alu_op = FpuAluOp::Division,
+                    _ => self.error("Unsupported Instruction!"),
+                }
+
+                match r.funct3 {
+                    0 => self.signals.round_mode = RoundingMode::RNE,
+                    1 => self.signals.round_mode = RoundingMode::RTZ,
+                    2 => self.signals.round_mode = RoundingMode::RDN,
+                    3 => self.signals.round_mode = RoundingMode::RUP,
+                    4 => self.signals.round_mode = RoundingMode::RMM,
+                    7 => self.signals.round_mode = RoundingMode::DRM,
+                    _ => self.error("Unsupported Rounding Mode!"),
+                }
             }
-            Instruction::IType(i) => {
+            Instruction::IType(_i) => {
                 self.signals = FpuControlSignals {
                     data_write: DataWrite::NoWrite,
                     fpu_branch: FpuBranch::NoBranch,
@@ -214,7 +239,7 @@ impl RiscFpCoprocessor {
                     ..Default::default()
                 }
             }
-            Instruction::SType(s) => {
+            Instruction::SType(_s) => {
                 self.signals = FpuControlSignals {
                     data_write: DataWrite::NoWrite,
                     fpu_branch: FpuBranch::NoBranch,
@@ -222,15 +247,6 @@ impl RiscFpCoprocessor {
                     ..Default::default()
                 }
             }
-            Instruction::BType(b) => {
-                self.set_btype_control_signals(b);
-            }
-            Instruction::UType(u) => {
-                self.set_utype_control_signals(u);
-            }
-            Instruction::JType(j) => {
-                self.set_jtype_control_signals(j);
-            }
             _ => self.error("Unsupported Instruction!"),
         }
     }
@@ -250,50 +266,21 @@ impl RiscFpCoprocessor {
     fn alu(&mut self) {
         let input1 = self.state.read_data_1;
         let input2 = self.state.read_data_2;
+        let input1_f64 = f64::from_bits(input1);
+        let input2_f64 = f64::from_bits(input2);
 
-        let mut input1_f32 = 0f32;
-        let mut input2_f32 = 0f32;
-        let mut input1_f64 = 0f64;
-        let mut input2_f64 = 0f64;
-
-        // Truncate the inputs if 32-bit operations are expected.
-        if let FpuRegWidth::Word = self.signals.fpu_reg_width {
-            input1_f32 = f32::from_bits(input1 as u32);
-            input2_f32 = f32::from_bits(input2 as u32);
-        } else {
-            input1_f64 = f64::from_bits(input1);
-            input2_f64 = f64::from_bits(input2);
-        }
-
+        // REMINDER: IMPLEMENT ROUNDING MODE!!!
         self.state.alu_result = match self.signals.fpu_alu_op {
-            FpuAluOp::Addition => match self.signals.fpu_reg_width {
-                FpuRegWidth::Word => f32::to_bits(input1_f32 + input2_f32) as u64,
-                FpuRegWidth::DoubleWord => f64::to_bits(input1_f64 + input2_f64),
-            },
-            FpuAluOp::Subtraction => match self.signals.fpu_reg_width {
-                FpuRegWidth::Word => f32::to_bits(input1_f32 - input2_f32) as u64,
-                FpuRegWidth::DoubleWord => f64::to_bits(input1_f64 - input2_f64),
-            },
-            FpuAluOp::MultiplicationOrEqual => match self.signals.fpu_reg_width {
-                FpuRegWidth::Word => f32::to_bits(input1_f32 * input2_f32) as u64,
-                FpuRegWidth::DoubleWord => f64::to_bits(input1_f64 * input2_f64),
-            },
-            FpuAluOp::Division => match self.signals.fpu_reg_width {
-                FpuRegWidth::Word => {
-                    if input2_f32 == 0f32 {
-                        f32::to_bits(0f32) as u64
-                    } else {
-                        f32::to_bits(input1_f32 / input2_f32) as u64
-                    }
-                }
-                FpuRegWidth::DoubleWord => {
-                    if input2_f64 == 0.0 {
-                        f64::to_bits(0.0)
-                    } else {
-                        f64::to_bits(input1_f64 / input2_f64)
-                    }
+            FpuAluOp::Addition => f64::to_bits(input1_f64 + input2_f64),
+            FpuAluOp::Subtraction => f64::to_bits(input1_f64 - input2_f64),
+            FpuAluOp::MultiplicationOrEqual => f64::to_bits(input1_f64 * input2_f64),
+            FpuAluOp::Division => {
+                if input2_f64 == 0.0 {
+                    f64::to_bits(0.0)
+                } else {
+                    f64::to_bits(input1_f64 / input2_f64)
                 }
-            },
+            }
             // No operation.
             FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0,
             _ => {
@@ -310,33 +297,15 @@ impl RiscFpCoprocessor {
     fn comparator(&mut self) {
         let input1 = self.state.read_data_1;
         let input2 = self.state.read_data_2;
-
-        let input1_f32 = f32::from_bits(input1 as u32);
-        let input2_f32 = f32::from_bits(input2 as u32);
         let input1_f64 = f64::from_bits(input1);
         let input2_f64 = f64::from_bits(input2);
 
         self.state.comparator_result = match self.signals.fpu_alu_op {
-            FpuAluOp::MultiplicationOrEqual => match self.signals.fpu_reg_width {
-                FpuRegWidth::Word => (input1_f32 == input2_f32) as u64,
-                FpuRegWidth::DoubleWord => (input1_f64 == input2_f64) as u64,
-            },
-            FpuAluOp::Slt => match self.signals.fpu_reg_width {
-                FpuRegWidth::Word => (input1_f32 < input2_f32) as u64,
-                FpuRegWidth::DoubleWord => (input1_f64 < input2_f64) as u64,
-            },
-            FpuAluOp::Sle => match self.signals.fpu_reg_width {
-                FpuRegWidth::Word => (input1_f32 <= input2_f32) as u64,
-                FpuRegWidth::DoubleWord => (input1_f64 <= input2_f64) as u64,
-            },
-            FpuAluOp::Sngt => match self.signals.fpu_reg_width {
-                FpuRegWidth::Word => !input1_f32.gt(&input2_f32) as u64,
-                FpuRegWidth::DoubleWord => !input1_f64.gt(&input2_f64) as u64,
-            },
-            FpuAluOp::Snge => match self.signals.fpu_reg_width {
-                FpuRegWidth::Word => !input1_f32.ge(&input2_f32) as u64,
-                FpuRegWidth::DoubleWord => !input1_f64.ge(&input2_f64) as u64,
-            },
+            FpuAluOp::MultiplicationOrEqual => (input1_f64 == input2_f64) as u64,
+            FpuAluOp::Slt => (input1_f64 < input2_f64) as u64,
+            FpuAluOp::Sle => (input1_f64 <= input2_f64) as u64,
+            FpuAluOp::Sngt => !input1_f64.gt(&input2_f64) as u64,
+            FpuAluOp::Snge => !input1_f64.ge(&input2_f64) as u64,
             FpuAluOp::Addition | FpuAluOp::Subtraction | FpuAluOp::Division => 0, // No operation
             _ => {
                 self.error(&format!(
@@ -363,9 +332,9 @@ impl RiscFpCoprocessor {
 
     /// Set the condition code (CC) register based on the result from the comparator.
     fn write_condition_code(&mut self) {
-        if let CcWrite::YesWrite = self.signals.cc_write {
-            self.condition_code = self.state.comparator_result;
-        }
+        // if let CcWrite::YesWrite = self.signals.cc_write {
+        self.condition_code = self.state.comparator_result;
+        // }
     }
 
     /// Set the data line that goes from `Read Data 1` to the multiplexer in the main processor
@@ -377,12 +346,7 @@ impl RiscFpCoprocessor {
     // ======================= Memory (MEM) =======================
     /// Set the data line that goes out of the condition code register file.
     fn set_condition_code_line(&mut self) {
-        // The MIPS architecture supports more than one condition code, but SWIM
-        // manually uses only one. This stubs the possible use of more than one
-        // for future development.
-        let selected_register_data = match self.signals.cc {
-            Cc::Cc0 => self.condition_code,
-        };
+        let selected_register_data = self.condition_code;
 
         // This only considers one bit of the selected condition code register.
         self.state.condition_code_bit = match selected_register_data % 2 {
@@ -395,10 +359,7 @@ impl RiscFpCoprocessor {
     /// multiplexer in the main processor controlled by the [`DataWrite`] control signal.
     fn set_data_writeback(&mut self) {
         self.state.sign_extend_data = self.data as i32 as i64 as u64;
-        self.state.data_writeback = match self.signals.fpu_reg_width {
-            FpuRegWidth::Word => self.state.sign_extend_data,
-            FpuRegWidth::DoubleWord => self.data,
-        }
+        self.state.data_writeback = self.data;
     }
 
     /// Simulate the logic between `self.state.condition_code_bit` and the FPU branch
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index af8c40583..3c48d75bf 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -49,11 +49,11 @@
 
 use super::super::datapath::Datapath;
 use super::constants::*;
-use super::control_signals::*;
 use super::control_signals::floating_point::*;
+use super::control_signals::*;
+use super::coprocessor::RiscFpCoprocessor;
 use super::datapath_signals::*;
 use super::instruction::*;
-use super::coprocessor::RiscFpCoprocessor;
 use super::{super::mips::memory::Memory, registers::RiscGpRegisters};
 use crate::emulation_core::architectures::DatapathRef;
 use crate::emulation_core::datapath::{DatapathUpdateSignal, Syscall};
@@ -618,6 +618,10 @@ impl RiscDatapath {
             self.datapath_signals.reg_width = RegisterWidth::HalfWidth;
         }
 
+        if r.op == OPCODE_OP_FP {
+            self.signals.reg_write_en = RegWriteEn::NoWrite;
+        }
+
         match r.funct3 {
             0 => match r.funct7 {
                 0b0000000 => self.signals.alu_op = AluOp::Addition,
diff --git a/src/emulation_core/riscv/instruction.rs b/src/emulation_core/riscv/instruction.rs
index e53e947b0..7cad14a46 100644
--- a/src/emulation_core/riscv/instruction.rs
+++ b/src/emulation_core/riscv/instruction.rs
@@ -111,7 +111,7 @@ impl TryFrom<u32> for Instruction {
         let op = (value & 0x7f) as u8;
         match op {
             // R-type instructions:
-            OPCODE_OP | OPCODE_OP_32 => Ok(Instruction::RType(RType {
+            OPCODE_OP | OPCODE_OP_32 | OPCODE_OP_FP => Ok(Instruction::RType(RType {
                 funct7: (value >> 25) as u8,
                 rs2: ((value >> 20) & 0x1f) as u8,
                 rs1: ((value >> 15) & 0x1f) as u8,

From e1532c94bcd82fd40b2abb3760cccfcef5a28186 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 13:19:59 -0400
Subject: [PATCH 09/48] Implemented Sqrt function and fixed funct7 match
 statement.

---
 src/emulation_core/riscv/control_signals.rs | 4 ++--
 src/emulation_core/riscv/coprocessor.rs     | 8 +++++---
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index 77abfdd4c..bad24c925 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -297,8 +297,8 @@ pub mod floating_point {
         Division = 3,
 
         /// `_0100` (4):
-        /// - ALU: Perform an "AND" operation.
-        And = 4,
+        /// - ALU: Perform a Square Root.
+        Sqrt = 4,
 
         /// `_0101` (5):
         /// - ALU: Perform an "OR" operation.
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index a711a6dcf..c609e082c 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -213,9 +213,10 @@ impl RiscFpCoprocessor {
 
                 match r.funct7 >> 2 {
                     0 => self.signals.fpu_alu_op = FpuAluOp::Addition,
-                    4 => self.signals.fpu_alu_op = FpuAluOp::Subtraction,
-                    8 => self.signals.fpu_alu_op = FpuAluOp::MultiplicationOrEqual,
-                    12 => self.signals.fpu_alu_op = FpuAluOp::Division,
+                    1 => self.signals.fpu_alu_op = FpuAluOp::Subtraction,
+                    2 => self.signals.fpu_alu_op = FpuAluOp::MultiplicationOrEqual,
+                    3 => self.signals.fpu_alu_op = FpuAluOp::Division,
+                    11 => self.signals.fpu_alu_op = FpuAluOp::Sqrt,
                     _ => self.error("Unsupported Instruction!"),
                 }
 
@@ -281,6 +282,7 @@ impl RiscFpCoprocessor {
                     f64::to_bits(input1_f64 / input2_f64)
                 }
             }
+            FpuAluOp::Sqrt => f64::to_bits(input1_f64.sqrt()),
             // No operation.
             FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0,
             _ => {

From 4d753d10b335c71ddb18b3b8238bd959b5db7472 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 15:42:50 -0400
Subject: [PATCH 10/48] Implemented FMIN and FMAX. Remaining FP Operations: *
 R4 Types * Conversion + Move * Comparisons * Classify * 64-Bits

---
 src/emulation_core/riscv/control_signals.rs |  8 ++++++--
 src/emulation_core/riscv/coprocessor.rs     | 21 ++++++++++++++++++++-
 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index bad24c925..70a01c198 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -301,8 +301,12 @@ pub mod floating_point {
         Sqrt = 4,
 
         /// `_0101` (5):
-        /// - ALU: Perform an "OR" operation.
-        Or = 5,
+        /// - ALU: Take the Minimum value.
+        Min = 5,
+
+        /// `_0110` (6):
+        /// - ALU: Take the Maximum value.
+        Max = 6,
 
         /// `_1100` (12):
         /// - Comparator: Set if less than.
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index c609e082c..fd178bfad 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -216,6 +216,11 @@ impl RiscFpCoprocessor {
                     1 => self.signals.fpu_alu_op = FpuAluOp::Subtraction,
                     2 => self.signals.fpu_alu_op = FpuAluOp::MultiplicationOrEqual,
                     3 => self.signals.fpu_alu_op = FpuAluOp::Division,
+                    5 => match r.funct3 {
+                        0 => self.signals.fpu_alu_op = FpuAluOp::Min,
+                        1 => self.signals.fpu_alu_op = FpuAluOp::Max,
+                        _ => self.error("Unsupported Instruction!"),
+                    },
                     11 => self.signals.fpu_alu_op = FpuAluOp::Sqrt,
                     _ => self.error("Unsupported Instruction!"),
                 }
@@ -283,8 +288,22 @@ impl RiscFpCoprocessor {
                 }
             }
             FpuAluOp::Sqrt => f64::to_bits(input1_f64.sqrt()),
+            FpuAluOp::Min => {
+                if input1_f64 < input2_f64 {
+                    f64::to_bits(input1_f64)
+                } else {
+                    f64::to_bits(input2_f64)
+                }
+            }
+            FpuAluOp::Max => {
+                if input1_f64 > input2_f64 {
+                    f64::to_bits(input1_f64)
+                } else {
+                    f64::to_bits(input2_f64)
+                }
+            }
             // No operation.
-            FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0,
+            // FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0,
             _ => {
                 self.error(&format!(
                     "Unsupported operation in FPU `{:?}`",

From d436914e1cf0a7d3e6f2c6b64b76e7b1d6001fac Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 17:46:37 -0400
Subject: [PATCH 11/48] Implemented Conversion from Float Registers to Integer
 Registers.

---
 src/emulation_core/riscv/constants.rs       |   2 +-
 src/emulation_core/riscv/control_signals.rs |   8 +-
 src/emulation_core/riscv/coprocessor.rs     | 150 ++++++++++++++++++--
 src/emulation_core/riscv/datapath.rs        |   5 +-
 4 files changed, 144 insertions(+), 21 deletions(-)

diff --git a/src/emulation_core/riscv/constants.rs b/src/emulation_core/riscv/constants.rs
index 7f3647ab5..022dfd788 100644
--- a/src/emulation_core/riscv/constants.rs
+++ b/src/emulation_core/riscv/constants.rs
@@ -84,7 +84,7 @@ pub const OPCODE_NMSUB: u8 = 0b1001011;
 pub const OPCODE_NMADD: u8 = 0b1001111;
 
 /// Not a Number
-pub const NAN: u32 = 0x7fc00000;
+pub const RISC_NAN: u32 = 0x7fc00000;
 
 // "ENC" is short for encoding. There is no formal name for this field
 // in the MIPS64 specification, other than the "shamt"/"sa" field that it
diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index 70a01c198..661de1674 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -227,11 +227,11 @@ pub mod floating_point {
     #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
     pub enum DataSrc {
         /// Use data from the main processing unit. Specifically, the data from register
-        /// `rt` from a given instruction. This value can additionally be used in the cases
+        /// `rs1` from a given instruction. This value can additionally be used in the cases
         /// where this register is not written to.
         MainProcessorUnit = 0,
 
-        /// Use data from the floating-point unit. Specifically, the data from register `fs`
+        /// Use data from the floating-point unit. Specifically, the data from register `rs1`
         /// from a given instruction.
         #[default]
         FloatingPointUnit = 1,
@@ -258,10 +258,10 @@ pub mod floating_point {
         /// - Write to the data register.
         /// - Source data to write to the main processing unit register file from the
         ///   floating-point unit. Specifically, this is the data stored in the `Data` register
-        ///   in the FPU, likely from register `fs` from a given instruction. This data source
+        ///   in the FPU, likely from register `rs1` from a given instruction. This data source
         ///   overrides the decision given by the [`MemToReg`](super::MemToReg) control signal.
         /// - Source data to write to the floating-point register file from the `Data` register
-        ///   in the FPU, likely from register `rt` from a given instruction.
+        ///   in the FPU, likely from register `rs1` from a given instruction.
         YesWrite = 1,
     }
 
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index fd178bfad..042c9e128 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -1,9 +1,9 @@
 //! Implementation of a RISC-V floating-point coprocessor.
 
 // use super::constants::*;
-use super::control_signals::floating_point::*;
 use super::instruction::Instruction;
 use super::registers::FpRegisters;
+use super::{constants::RISC_NAN, control_signals::floating_point::*};
 use serde::{Deserialize, Serialize};
 
 /// An implementation of a floating-point coprocessor for the RISC-V ISA.
@@ -222,6 +222,10 @@ impl RiscFpCoprocessor {
                         _ => self.error("Unsupported Instruction!"),
                     },
                     11 => self.signals.fpu_alu_op = FpuAluOp::Sqrt,
+                    24 => {
+                        self.signals.data_write = DataWrite::YesWrite;
+                        self.signals.fpu_reg_write = FpuRegWrite::NoWrite;
+                    }
                     _ => self.error("Unsupported Instruction!"),
                 }
 
@@ -275,35 +279,65 @@ impl RiscFpCoprocessor {
         let input1_f64 = f64::from_bits(input1);
         let input2_f64 = f64::from_bits(input2);
 
-        // REMINDER: IMPLEMENT ROUNDING MODE!!!
-        self.state.alu_result = match self.signals.fpu_alu_op {
-            FpuAluOp::Addition => f64::to_bits(input1_f64 + input2_f64),
-            FpuAluOp::Subtraction => f64::to_bits(input1_f64 - input2_f64),
-            FpuAluOp::MultiplicationOrEqual => f64::to_bits(input1_f64 * input2_f64),
+        let result_f64: f64 = match self.signals.fpu_alu_op {
+            FpuAluOp::Addition => input1_f64 + input2_f64,
+            FpuAluOp::Subtraction => input1_f64 - input2_f64,
+            FpuAluOp::MultiplicationOrEqual => input1_f64 * input2_f64,
             FpuAluOp::Division => {
                 if input2_f64 == 0.0 {
-                    f64::to_bits(0.0)
+                    0.0
                 } else {
-                    f64::to_bits(input1_f64 / input2_f64)
+                    input1_f64 / input2_f64
                 }
             }
-            FpuAluOp::Sqrt => f64::to_bits(input1_f64.sqrt()),
+            FpuAluOp::Sqrt => input1_f64.sqrt(),
             FpuAluOp::Min => {
                 if input1_f64 < input2_f64 {
-                    f64::to_bits(input1_f64)
+                    input1_f64
                 } else {
-                    f64::to_bits(input2_f64)
+                    input2_f64
                 }
             }
             FpuAluOp::Max => {
                 if input1_f64 > input2_f64 {
-                    f64::to_bits(input1_f64)
+                    input1_f64
                 } else {
-                    f64::to_bits(input2_f64)
+                    input2_f64
                 }
             }
             // No operation.
             // FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0,
+            _ => {
+                self.error(&format!(
+                    "Unsupported operation in FPU `{:?}`",
+                    self.signals.fpu_alu_op
+                ));
+                0.0
+            }
+        };
+
+        if result_f64.is_nan() {
+            self.state.alu_result = RISC_NAN as u64;
+            return;
+        }
+
+        self.state.alu_result = match self.signals.round_mode {
+            RoundingMode::RNE => f64::to_bits(
+                if (result_f64.ceil() - result_f64).abs() == (result_f64 - result_f64.floor()).abs()
+                {
+                    if result_f64.ceil() % 2.0 == 0.0 {
+                        result_f64.ceil()
+                    } else {
+                        result_f64.floor()
+                    }
+                } else {
+                    result_f64.round()
+                },
+            ),
+            RoundingMode::RTZ => f64::to_bits(result_f64.trunc()),
+            RoundingMode::RDN => f64::to_bits(result_f64.floor()),
+            RoundingMode::RUP => f64::to_bits(result_f64.ceil()),
+            RoundingMode::RMM => f64::to_bits(result_f64.round()),
             _ => {
                 self.error(&format!(
                     "Unsupported operation in FPU `{:?}`",
@@ -379,8 +413,94 @@ impl RiscFpCoprocessor {
     /// Set the data line between the multiplexer after the `Data` register and the
     /// multiplexer in the main processor controlled by the [`DataWrite`] control signal.
     fn set_data_writeback(&mut self) {
-        self.state.sign_extend_data = self.data as i32 as i64 as u64;
-        self.state.data_writeback = self.data;
+        let data_unrounded = f64::from_bits(self.data);
+
+        let data_rounded = match self.signals.round_mode {
+            RoundingMode::RNE => {
+                if (data_unrounded.ceil() - data_unrounded).abs()
+                    == (data_unrounded - data_unrounded.floor()).abs()
+                {
+                    if data_unrounded.ceil() % 2.0 == 0.0 {
+                        data_unrounded.ceil()
+                    } else {
+                        data_unrounded.floor()
+                    }
+                } else {
+                    data_unrounded.round()
+                }
+            }
+            RoundingMode::RTZ => data_unrounded.trunc(),
+            RoundingMode::RDN => data_unrounded.floor(),
+            RoundingMode::RUP => data_unrounded.ceil(),
+            RoundingMode::RMM => data_unrounded.round(),
+            _ => {
+                self.error(&format!(
+                    "Unsupported Rounding Mode `{:?}`",
+                    self.signals.round_mode
+                ));
+                0.0
+            }
+        };
+
+        self.state.data_writeback = match self.state.rs2 {
+            0 => {
+                if (data_rounded <= (-(2_i32.pow(31))).into()) | (data_rounded == f64::NEG_INFINITY)
+                {
+                    -(2_i32.pow(31)) as u64
+                } else if (data_rounded >= (2_i32.pow(31) - 1).into())
+                    | (data_rounded == f64::INFINITY)
+                    | (data_rounded.is_nan())
+                {
+                    (2_i32.pow(31) - 1) as u64
+                } else {
+                    data_rounded as i32 as u64
+                }
+            }
+            1 => {
+                if (data_rounded <= 0.0) | (data_rounded == f64::NEG_INFINITY) {
+                    0
+                } else if (data_rounded >= (2_u32.pow(32) - 1).into())
+                    | (data_rounded == f64::INFINITY)
+                    | (data_rounded.is_nan())
+                {
+                    (2_u32.pow(32) - 1) as u64
+                } else {
+                    data_rounded as u32 as u64
+                }
+            }
+            2 => {
+                if (data_rounded <= (-(2_i64.pow(63))) as f64) | (data_rounded == f64::NEG_INFINITY)
+                {
+                    -(2_i64.pow(63)) as u64
+                } else if (data_rounded >= (2_i64.pow(63) - 1) as f64)
+                    | (data_rounded == f64::INFINITY)
+                    | (data_rounded.is_nan())
+                {
+                    (2_i64.pow(63) - 1) as u64
+                } else {
+                    data_rounded as i64 as u64
+                }
+            }
+            3 => {
+                if (data_rounded <= 0.0) | (data_rounded == f64::NEG_INFINITY) {
+                    0
+                } else if (data_rounded >= (2_u64.pow(64) - 1) as f64)
+                    | (data_rounded == f64::INFINITY)
+                    | (data_rounded.is_nan())
+                {
+                    2_u64.pow(64) - 1
+                } else {
+                    data_rounded as u64
+                }
+            }
+            _ => {
+                self.error(&format!(
+                    "Unsupported Register Width `{:?}`",
+                    self.state.rs2
+                ));
+                0
+            }
+        }
     }
 
     /// Simulate the logic between `self.state.condition_code_bit` and the FPU branch
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 3c48d75bf..6214721b7 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -619,7 +619,10 @@ impl RiscDatapath {
         }
 
         if r.op == OPCODE_OP_FP {
-            self.signals.reg_write_en = RegWriteEn::NoWrite;
+            match r.funct7 >> 2 {
+                24 => self.signals.reg_write_en = RegWriteEn::YesWrite,
+                _ => self.signals.reg_write_en = RegWriteEn::NoWrite,
+            }
         }
 
         match r.funct3 {

From bfac4a20cb8ddcfe6fa0afff40d1165ee33bcf83 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 18:02:23 -0400
Subject: [PATCH 12/48] Implemented conversion from Integer Registers to FP
 Registers.

---
 src/emulation_core/riscv/coprocessor.rs | 186 +++++++++++++-----------
 1 file changed, 103 insertions(+), 83 deletions(-)

diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 042c9e128..0a0194af1 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -226,6 +226,10 @@ impl RiscFpCoprocessor {
                         self.signals.data_write = DataWrite::YesWrite;
                         self.signals.fpu_reg_write = FpuRegWrite::NoWrite;
                     }
+                    26 => {
+                        self.signals.data_write = DataWrite::YesWrite;
+                        self.signals.data_src = DataSrc::MainProcessorUnit;
+                    }
                     _ => self.error("Unsupported Instruction!"),
                 }
 
@@ -413,93 +417,109 @@ impl RiscFpCoprocessor {
     /// Set the data line between the multiplexer after the `Data` register and the
     /// multiplexer in the main processor controlled by the [`DataWrite`] control signal.
     fn set_data_writeback(&mut self) {
-        let data_unrounded = f64::from_bits(self.data);
-
-        let data_rounded = match self.signals.round_mode {
-            RoundingMode::RNE => {
-                if (data_unrounded.ceil() - data_unrounded).abs()
-                    == (data_unrounded - data_unrounded.floor()).abs()
-                {
-                    if data_unrounded.ceil() % 2.0 == 0.0 {
-                        data_unrounded.ceil()
-                    } else {
-                        data_unrounded.floor()
-                    }
-                } else {
-                    data_unrounded.round()
-                }
-            }
-            RoundingMode::RTZ => data_unrounded.trunc(),
-            RoundingMode::RDN => data_unrounded.floor(),
-            RoundingMode::RUP => data_unrounded.ceil(),
-            RoundingMode::RMM => data_unrounded.round(),
-            _ => {
-                self.error(&format!(
-                    "Unsupported Rounding Mode `{:?}`",
-                    self.signals.round_mode
-                ));
-                0.0
-            }
-        };
-
-        self.state.data_writeback = match self.state.rs2 {
-            0 => {
-                if (data_rounded <= (-(2_i32.pow(31))).into()) | (data_rounded == f64::NEG_INFINITY)
-                {
-                    -(2_i32.pow(31)) as u64
-                } else if (data_rounded >= (2_i32.pow(31) - 1).into())
-                    | (data_rounded == f64::INFINITY)
-                    | (data_rounded.is_nan())
-                {
-                    (2_i32.pow(31) - 1) as u64
-                } else {
-                    data_rounded as i32 as u64
-                }
-            }
-            1 => {
-                if (data_rounded <= 0.0) | (data_rounded == f64::NEG_INFINITY) {
+        self.state.data_writeback = match self.signals.data_src {
+            DataSrc::MainProcessorUnit => match self.state.rs2 {
+                0 => f64::to_bits(self.data as i32 as f64),
+                1 => f64::to_bits(self.data as u32 as f64),
+                2 => f64::to_bits(self.data as i64 as f64),
+                3 => f64::to_bits(self.data as f64),
+                _ => {
+                    self.error(&format!(
+                        "Unsupported Register Width `{:?}`",
+                        self.state.rs2
+                    ));
                     0
-                } else if (data_rounded >= (2_u32.pow(32) - 1).into())
-                    | (data_rounded == f64::INFINITY)
-                    | (data_rounded.is_nan())
-                {
-                    (2_u32.pow(32) - 1) as u64
-                } else {
-                    data_rounded as u32 as u64
-                }
-            }
-            2 => {
-                if (data_rounded <= (-(2_i64.pow(63))) as f64) | (data_rounded == f64::NEG_INFINITY)
-                {
-                    -(2_i64.pow(63)) as u64
-                } else if (data_rounded >= (2_i64.pow(63) - 1) as f64)
-                    | (data_rounded == f64::INFINITY)
-                    | (data_rounded.is_nan())
-                {
-                    (2_i64.pow(63) - 1) as u64
-                } else {
-                    data_rounded as i64 as u64
                 }
             }
-            3 => {
-                if (data_rounded <= 0.0) | (data_rounded == f64::NEG_INFINITY) {
-                    0
-                } else if (data_rounded >= (2_u64.pow(64) - 1) as f64)
-                    | (data_rounded == f64::INFINITY)
-                    | (data_rounded.is_nan())
-                {
-                    2_u64.pow(64) - 1
-                } else {
-                    data_rounded as u64
+            DataSrc::FloatingPointUnit => {
+                let data_unrounded = f64::from_bits(self.data);
+                let data_rounded = match self.signals.round_mode {
+                    RoundingMode::RNE => {
+                        if (data_unrounded.ceil() - data_unrounded).abs()
+                            == (data_unrounded - data_unrounded.floor()).abs()
+                        {
+                            if data_unrounded.ceil() % 2.0 == 0.0 {
+                                data_unrounded.ceil()
+                            } else {
+                                data_unrounded.floor()
+                            }
+                        } else {
+                            data_unrounded.round()
+                        }
+                    }
+                    RoundingMode::RTZ => data_unrounded.trunc(),
+                    RoundingMode::RDN => data_unrounded.floor(),
+                    RoundingMode::RUP => data_unrounded.ceil(),
+                    RoundingMode::RMM => data_unrounded.round(),
+                    _ => {
+                        self.error(&format!(
+                            "Unsupported Rounding Mode `{:?}`",
+                            self.signals.round_mode
+                        ));
+                        0.0
+                    }
+                };
+        
+                match self.state.rs2 {
+                    0 => {
+                        if (data_rounded <= (-(2_i32.pow(31))).into()) | (data_rounded == f64::NEG_INFINITY)
+                        {
+                            -(2_i32.pow(31)) as u64
+                        } else if (data_rounded >= (2_i32.pow(31) - 1).into())
+                            | (data_rounded == f64::INFINITY)
+                            | (data_rounded.is_nan())
+                        {
+                            (2_i32.pow(31) - 1) as u64
+                        } else {
+                            data_rounded as i32 as u64
+                        }
+                    }
+                    1 => {
+                        if (data_rounded <= 0.0) | (data_rounded == f64::NEG_INFINITY) {
+                            0
+                        } else if (data_rounded >= (2_u32.pow(32) - 1).into())
+                            | (data_rounded == f64::INFINITY)
+                            | (data_rounded.is_nan())
+                        {
+                            (2_u32.pow(32) - 1) as u64
+                        } else {
+                            data_rounded as u32 as u64
+                        }
+                    }
+                    2 => {
+                        if (data_rounded <= (-(2_i64.pow(63))) as f64) | (data_rounded == f64::NEG_INFINITY)
+                        {
+                            -(2_i64.pow(63)) as u64
+                        } else if (data_rounded >= (2_i64.pow(63) - 1) as f64)
+                            | (data_rounded == f64::INFINITY)
+                            | (data_rounded.is_nan())
+                        {
+                            (2_i64.pow(63) - 1) as u64
+                        } else {
+                            data_rounded as i64 as u64
+                        }
+                    }
+                    3 => {
+                        if (data_rounded <= 0.0) | (data_rounded == f64::NEG_INFINITY) {
+                            0
+                        } else if (data_rounded >= (2_u64.pow(64) - 1) as f64)
+                            | (data_rounded == f64::INFINITY)
+                            | (data_rounded.is_nan())
+                        {
+                            2_u64.pow(64) - 1
+                        } else {
+                            data_rounded as u64
+                        }
+                    }
+                    _ => {
+                        self.error(&format!(
+                            "Unsupported Register Width `{:?}`",
+                            self.state.rs2
+                        ));
+                        0
+                    }
                 }
             }
-            _ => {
-                self.error(&format!(
-                    "Unsupported Register Width `{:?}`",
-                    self.state.rs2
-                ));
-                0
-            }
         }
     }
 
@@ -546,7 +566,7 @@ impl RiscFpCoprocessor {
 
         self.state.register_write_mux_to_mux = match self.signals.data_write {
             DataWrite::NoWrite => self.state.alu_result,
-            DataWrite::YesWrite => self.data,
+            DataWrite::YesWrite => self.state.data_writeback,
         };
         self.state.register_write_data = match self.signals.fpu_mem_to_reg {
             FpuMemToReg::UseDataWrite => self.state.register_write_mux_to_mux,

From 4de6fa935baa39bc8616ad1061b1df426d28958e Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 18:03:13 -0400
Subject: [PATCH 13/48] Fixed formatting.

---
 src/emulation_core/riscv/coprocessor.rs | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 0a0194af1..0f416fbc3 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -430,7 +430,7 @@ impl RiscFpCoprocessor {
                     ));
                     0
                 }
-            }
+            },
             DataSrc::FloatingPointUnit => {
                 let data_unrounded = f64::from_bits(self.data);
                 let data_rounded = match self.signals.round_mode {
@@ -459,10 +459,11 @@ impl RiscFpCoprocessor {
                         0.0
                     }
                 };
-        
+
                 match self.state.rs2 {
                     0 => {
-                        if (data_rounded <= (-(2_i32.pow(31))).into()) | (data_rounded == f64::NEG_INFINITY)
+                        if (data_rounded <= (-(2_i32.pow(31))).into())
+                            | (data_rounded == f64::NEG_INFINITY)
                         {
                             -(2_i32.pow(31)) as u64
                         } else if (data_rounded >= (2_i32.pow(31) - 1).into())
@@ -487,7 +488,8 @@ impl RiscFpCoprocessor {
                         }
                     }
                     2 => {
-                        if (data_rounded <= (-(2_i64.pow(63))) as f64) | (data_rounded == f64::NEG_INFINITY)
+                        if (data_rounded <= (-(2_i64.pow(63))) as f64)
+                            | (data_rounded == f64::NEG_INFINITY)
                         {
                             -(2_i64.pow(63)) as u64
                         } else if (data_rounded >= (2_i64.pow(63) - 1) as f64)

From 7356d31dffba7373e01a58a1612d5b0b94f120e9 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 18:29:23 -0400
Subject: [PATCH 14/48] Implemented Sign-Injection functions.

---
 src/emulation_core/riscv/control_signals.rs | 12 ++++++++++++
 src/emulation_core/riscv/coprocessor.rs     | 19 +++++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index 661de1674..f7d574dd2 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -308,6 +308,18 @@ pub mod floating_point {
         /// - ALU: Take the Maximum value.
         Max = 6,
 
+        /// `_0111` (7):
+        /// - ALU: Sign-Injection.
+        SGNJ = 7,
+
+        /// `_1000` (8):
+        /// - ALU: Negative Sign-Injection.
+        SGNJN = 8,
+
+        /// `_1001` (9):
+        /// - ALU: Xor Sign-Injection.
+        SGNJX = 9,
+
         /// `_1100` (12):
         /// - Comparator: Set if less than.
         Slt = 12,
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 0f416fbc3..eed32f204 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -216,6 +216,12 @@ impl RiscFpCoprocessor {
                     1 => self.signals.fpu_alu_op = FpuAluOp::Subtraction,
                     2 => self.signals.fpu_alu_op = FpuAluOp::MultiplicationOrEqual,
                     3 => self.signals.fpu_alu_op = FpuAluOp::Division,
+                    4 => match r.funct3 {
+                        0 => self.signals.fpu_alu_op = FpuAluOp::SGNJ,
+                        1 => self.signals.fpu_alu_op = FpuAluOp::SGNJN,
+                        2 => self.signals.fpu_alu_op = FpuAluOp::SGNJX,
+                        _ => self.error("Unsupported Instruction!"),
+                    },
                     5 => match r.funct3 {
                         0 => self.signals.fpu_alu_op = FpuAluOp::Min,
                         1 => self.signals.fpu_alu_op = FpuAluOp::Max,
@@ -309,6 +315,11 @@ impl RiscFpCoprocessor {
                     input2_f64
                 }
             }
+            FpuAluOp::SGNJ => f64::from_bits((input1 & 0x01111111) | (input2 >> 63 << 63)),
+            FpuAluOp::SGNJN => f64::from_bits((input1 & 0x01111111) | (!(input2 >> 63) << 63)),
+            FpuAluOp::SGNJX => {
+                f64::from_bits((input1 & 0x01111111) | (((input2 >> 63) ^ (input1 >> 63)) << 63))
+            }
             // No operation.
             // FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0,
             _ => {
@@ -325,6 +336,14 @@ impl RiscFpCoprocessor {
             return;
         }
 
+        if (self.signals.fpu_alu_op == FpuAluOp::SGNJ)
+            | (self.signals.fpu_alu_op == FpuAluOp::SGNJN)
+            | (self.signals.fpu_alu_op == FpuAluOp::SGNJX)
+        {
+            self.state.alu_result = f64::to_bits(result_f64);
+            return;
+        }
+
         self.state.alu_result = match self.signals.round_mode {
             RoundingMode::RNE => f64::to_bits(
                 if (result_f64.ceil() - result_f64).abs() == (result_f64 - result_f64.floor()).abs()

From e578a955acc1ba2c5ff6016d17ef28d45c5b758a Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 18:53:54 -0400
Subject: [PATCH 15/48] Implemented FCMP instructions.

---
 src/emulation_core/riscv/control_signals.rs |  2 +-
 src/emulation_core/riscv/coprocessor.rs     | 17 ++++++++++++++++-
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index f7d574dd2..28eec2736 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -333,7 +333,7 @@ pub mod floating_point {
         Sle = 14,
 
         /// `_1111` (15):
-        /// - Comparator: Set if not greater than.
+        /// - Comparator: Set if equal.
         Sngt = 15,
     }
 
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index eed32f204..5c39fed3e 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -228,6 +228,16 @@ impl RiscFpCoprocessor {
                         _ => self.error("Unsupported Instruction!"),
                     },
                     11 => self.signals.fpu_alu_op = FpuAluOp::Sqrt,
+                    20 => {
+                        self.signals.fpu_reg_write = FpuRegWrite::NoWrite;
+                        self.signals.data_write = DataWrite::YesWrite;
+                        match r.funct3 {
+                            0 => self.signals.fpu_alu_op = FpuAluOp::Sle,
+                            1 => self.signals.fpu_alu_op = FpuAluOp::Slt,
+                            2 => self.signals.fpu_alu_op = FpuAluOp::MultiplicationOrEqual,
+                            _ => self.error("Unsupported Instruction!"),
+                        }
+                    }
                     24 => {
                         self.signals.data_write = DataWrite::YesWrite;
                         self.signals.fpu_reg_write = FpuRegWrite::NoWrite;
@@ -321,7 +331,7 @@ impl RiscFpCoprocessor {
                 f64::from_bits((input1 & 0x01111111) | (((input2 >> 63) ^ (input1 >> 63)) << 63))
             }
             // No operation.
-            // FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0,
+            FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0.0,
             _ => {
                 self.error(&format!(
                     "Unsupported operation in FPU `{:?}`",
@@ -436,6 +446,11 @@ impl RiscFpCoprocessor {
     /// Set the data line between the multiplexer after the `Data` register and the
     /// multiplexer in the main processor controlled by the [`DataWrite`] control signal.
     fn set_data_writeback(&mut self) {
+        if self.state.funct7 >> 2 == 20 {
+            self.state.data_writeback = self.state.comparator_result;
+            return;
+        }
+
         self.state.data_writeback = match self.signals.data_src {
             DataSrc::MainProcessorUnit => match self.state.rs2 {
                 0 => f64::to_bits(self.data as i32 as f64),

From 53af4bf6656b5303189935563bf1e780a3e462fa Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 19:32:54 -0400
Subject: [PATCH 16/48] Added FCLASS.

---
 src/emulation_core/riscv/control_signals.rs | 12 +++-
 src/emulation_core/riscv/coprocessor.rs     | 62 ++++++++++++++++++---
 src/emulation_core/riscv/datapath.rs        |  2 +
 3 files changed, 68 insertions(+), 8 deletions(-)

diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index 28eec2736..90757f688 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -234,7 +234,13 @@ pub mod floating_point {
         /// Use data from the floating-point unit. Specifically, the data from register `rs1`
         /// from a given instruction.
         #[default]
-        FloatingPointUnit = 1,
+        FloatingPointUnitRS1 = 1,
+
+        /// Use data from the floating-point unit. Specifically, the data from the comparator.
+        FloatingPointUnitComp = 2,
+
+        /// Use data from the floating-point unit. Specifically, the Classify Mask.
+        FloatingPointUnitMask = 3,
     }
 
     /// Determines whether to write to the `Data` register in the floating-point unit.
@@ -320,6 +326,10 @@ pub mod floating_point {
         /// - ALU: Xor Sign-Injection.
         SGNJX = 9,
 
+        /// `_1010` (10):
+        /// - ALU: Classification Mask.
+        Class = 10,
+
         /// `_1100` (12):
         /// - Comparator: Set if less than.
         Slt = 12,
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 5c39fed3e..ddc60fc17 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -231,6 +231,7 @@ impl RiscFpCoprocessor {
                     20 => {
                         self.signals.fpu_reg_write = FpuRegWrite::NoWrite;
                         self.signals.data_write = DataWrite::YesWrite;
+                        self.signals.data_src = DataSrc::FloatingPointUnitComp;
                         match r.funct3 {
                             0 => self.signals.fpu_alu_op = FpuAluOp::Sle,
                             1 => self.signals.fpu_alu_op = FpuAluOp::Slt,
@@ -246,6 +247,12 @@ impl RiscFpCoprocessor {
                         self.signals.data_write = DataWrite::YesWrite;
                         self.signals.data_src = DataSrc::MainProcessorUnit;
                     }
+                    28 => {
+                        self.signals.data_write = DataWrite::YesWrite;
+                        self.signals.data_src = DataSrc::FloatingPointUnitMask;
+                        self.signals.fpu_reg_write = FpuRegWrite::NoWrite;
+                        self.signals.fpu_alu_op = FpuAluOp::Class;
+                    }
                     _ => self.error("Unsupported Instruction!"),
                 }
 
@@ -298,6 +305,7 @@ impl RiscFpCoprocessor {
         let input2 = self.state.read_data_2;
         let input1_f64 = f64::from_bits(input1);
         let input2_f64 = f64::from_bits(input2);
+        let mut input_mask = 0b0000000000;
 
         let result_f64: f64 = match self.signals.fpu_alu_op {
             FpuAluOp::Addition => input1_f64 + input2_f64,
@@ -330,6 +338,43 @@ impl RiscFpCoprocessor {
             FpuAluOp::SGNJX => {
                 f64::from_bits((input1 & 0x01111111) | (((input2 >> 63) ^ (input1 >> 63)) << 63))
             }
+            FpuAluOp::Class => {
+                if input1_f64.is_sign_negative() {
+                    if input1_f64.is_infinite() {
+                        input_mask = 0b1;
+                    }
+                    else if input1_f64.is_normal() {
+                        input_mask = 0b10;
+                    }
+                    else if input1_f64.is_subnormal() {
+                        input_mask = 0b100;
+                    }
+                    else {
+                        input_mask = 0b1000;
+                    }
+                }
+                else if input1_f64.is_sign_positive() {
+                    if input1_f64.is_infinite() {
+                        input_mask = 0b10000000;
+                    }
+                    else if input1_f64.is_normal() {
+                        input_mask = 0b1000000;
+                    }
+                    else if input1_f64.is_subnormal() {
+                        input_mask = 0b100000;
+                    }
+                    else {
+                        input_mask = 0b10000;
+                    }
+                }
+                else if input1_f64.is_nan() {
+                    input_mask = 0b100000000;
+                }
+                else {
+                    input_mask = 0b1000000000;
+                }
+                0.0
+            }
             // No operation.
             FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0.0,
             _ => {
@@ -354,6 +399,11 @@ impl RiscFpCoprocessor {
             return;
         }
 
+        if self.signals.fpu_alu_op == FpuAluOp::Class {
+            self.state.alu_result = input_mask as u64;
+            return;
+        }
+
         self.state.alu_result = match self.signals.round_mode {
             RoundingMode::RNE => f64::to_bits(
                 if (result_f64.ceil() - result_f64).abs() == (result_f64 - result_f64.floor()).abs()
@@ -413,7 +463,9 @@ impl RiscFpCoprocessor {
         }
 
         self.data = match self.signals.data_src {
-            DataSrc::FloatingPointUnit => self.state.read_data_1,
+            DataSrc::FloatingPointUnitRS1 => self.state.read_data_1,
+            DataSrc::FloatingPointUnitComp => self.state.comparator_result,
+            DataSrc::FloatingPointUnitMask => self.state.alu_result,
             DataSrc::MainProcessorUnit => self.state.data_from_main_processor,
         };
     }
@@ -446,11 +498,6 @@ impl RiscFpCoprocessor {
     /// Set the data line between the multiplexer after the `Data` register and the
     /// multiplexer in the main processor controlled by the [`DataWrite`] control signal.
     fn set_data_writeback(&mut self) {
-        if self.state.funct7 >> 2 == 20 {
-            self.state.data_writeback = self.state.comparator_result;
-            return;
-        }
-
         self.state.data_writeback = match self.signals.data_src {
             DataSrc::MainProcessorUnit => match self.state.rs2 {
                 0 => f64::to_bits(self.data as i32 as f64),
@@ -465,7 +512,7 @@ impl RiscFpCoprocessor {
                     0
                 }
             },
-            DataSrc::FloatingPointUnit => {
+            DataSrc::FloatingPointUnitRS1 => {
                 let data_unrounded = f64::from_bits(self.data);
                 let data_rounded = match self.signals.round_mode {
                     RoundingMode::RNE => {
@@ -556,6 +603,7 @@ impl RiscFpCoprocessor {
                     }
                 }
             }
+            _ => self.data,
         }
     }
 
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 6214721b7..89b936ed2 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -620,7 +620,9 @@ impl RiscDatapath {
 
         if r.op == OPCODE_OP_FP {
             match r.funct7 >> 2 {
+                20 => self.signals.reg_write_en = RegWriteEn::YesWrite,
                 24 => self.signals.reg_write_en = RegWriteEn::YesWrite,
+                28 => self.signals.reg_write_en = RegWriteEn:: YesWrite,
                 _ => self.signals.reg_write_en = RegWriteEn::NoWrite,
             }
         }

From 9d78bd11e77daa47d82a421da3dcd55533f2c3a7 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 20:02:11 -0400
Subject: [PATCH 17/48] Implemented Fused Multiplication Instructions (R4s)

---
 src/emulation_core/riscv/control_signals.rs | 56 ++++++++++++---------
 src/emulation_core/riscv/coprocessor.rs     | 44 ++++++++++++----
 src/emulation_core/riscv/datapath.rs        | 17 ++++++-
 3 files changed, 81 insertions(+), 36 deletions(-)

diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index 90757f688..d0d400c82 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -285,66 +285,74 @@ pub mod floating_point {
     #[derive(Clone, Debug, Default, PartialEq, Serialize, Deserialize)]
     pub enum FpuAluOp {
         #[default]
-        /// `_0000` (0):
+        /// `_00000` (0):
         /// - ALU: Perform an addition.
         Addition = 0,
 
-        /// `_0001` (1):
+        /// `_00001` (1):
         /// - ALU: Perform a subtraction.
         Subtraction = 1,
 
-        /// `_0010` (2):
+        /// `_00010` (2):
         /// - ALU: Perform a multiplication.
         /// - Comparator: Set if equal.
         MultiplicationOrEqual = 2,
 
-        /// `_0011` (3):
+        /// `_00011` (3):
         /// - ALU: Perform a division.
         Division = 3,
 
-        /// `_0100` (4):
+        /// `_00100` (4):
         /// - ALU: Perform a Square Root.
         Sqrt = 4,
 
-        /// `_0101` (5):
+        /// `_00101` (5):
         /// - ALU: Take the Minimum value.
         Min = 5,
 
-        /// `_0110` (6):
+        /// `_00110` (6):
         /// - ALU: Take the Maximum value.
         Max = 6,
 
-        /// `_0111` (7):
+        /// `_00111` (7):
         /// - ALU: Sign-Injection.
         SGNJ = 7,
 
-        /// `_1000` (8):
+        /// `_01000` (8):
         /// - ALU: Negative Sign-Injection.
         SGNJN = 8,
 
-        /// `_1001` (9):
+        /// `_01001` (9):
         /// - ALU: Xor Sign-Injection.
         SGNJX = 9,
 
-        /// `_1010` (10):
+        /// `_01010` (10):
         /// - ALU: Classification Mask.
         Class = 10,
 
-        /// `_1100` (12):
-        /// - Comparator: Set if less than.
-        Slt = 12,
+        /// `_01011` (11):
+        /// - ALU: Fused Multiplication-Addition.
+        MAdd = 11,
 
-        /// `_1101` (13):
-        /// - Comparator: Set if not greater than or equal.
-        Snge = 13,
+        /// `_01100` (12):
+        /// - ALU: Fused Multiplication-Subtraction.
+        MSub = 12,
 
-        /// `_1110` (14):
-        /// - Comparator: Set if less than or equal.
-        Sle = 14,
+        /// `_01101` (13):
+        /// - ALU: Fused Negated Multiplication-Subtraction.
+        NMSub = 13,
 
-        /// `_1111` (15):
-        /// - Comparator: Set if equal.
-        Sngt = 15,
+        /// `_01110` (14):
+        /// - ALU: Fused Negated Multiplication-Addition.
+        NMAdd = 14,
+
+        /// `_10000` (16):
+        /// - Comparator: Set if less than.
+        Slt = 16,
+
+        /// `_10001` (17):
+        /// - Comparator: Set if less than or equal.
+        Sle = 17,
     }
 
     impl FpuAluOp {
@@ -353,9 +361,7 @@ pub mod floating_point {
             match function {
                 FUNCTION_C_EQ => Ok(Self::MultiplicationOrEqual),
                 FUNCTION_C_LT => Ok(Self::Slt),
-                FUNCTION_C_NGE => Ok(Self::Snge),
                 FUNCTION_C_LE => Ok(Self::Sle),
-                FUNCTION_C_NGT => Ok(Self::Sngt),
                 _ => Err(format!("Unsupported function code `{function}`")),
             }
         }
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index ddc60fc17..9fa374ac3 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -1,5 +1,8 @@
 //! Implementation of a RISC-V floating-point coprocessor.
 
+use std::ops::Neg;
+
+use super::constants::{OPCODE_MADD, OPCODE_MSUB, OPCODE_NMADD, OPCODE_NMSUB};
 // use super::constants::*;
 use super::instruction::Instruction;
 use super::registers::FpRegisters;
@@ -51,6 +54,7 @@ pub struct RiscFpuState {
     pub fp_register_data_from_main_processor: u64,
     pub read_data_1: u64,
     pub read_data_2: u64,
+    pub read_data_3: u64,
     pub register_write_data: u64,
     pub register_write_mux_to_mux: u64,
     pub sign_extend_data: u64,
@@ -284,6 +288,27 @@ impl RiscFpCoprocessor {
                     ..Default::default()
                 }
             }
+            Instruction::R4Type(r4) => {
+                self.signals = FpuControlSignals {
+                    data_write: DataWrite::NoWrite,
+                    fpu_branch: FpuBranch::NoBranch,
+                    fpu_mem_to_reg: FpuMemToReg::UseDataWrite,
+                    fpu_reg_dst: FpuRegDst::Reg3,
+                    fpu_reg_write: FpuRegWrite::YesWrite,
+                    ..Default::default()
+                };
+
+                self.signals.fpu_alu_op = match r4.op {
+                    OPCODE_MADD => FpuAluOp::MAdd,
+                    OPCODE_MSUB => FpuAluOp::MSub,
+                    OPCODE_NMSUB => FpuAluOp::NMSub,
+                    OPCODE_NMADD => FpuAluOp::NMAdd,
+                    _ => {
+                        self.error("Unsupported Instruction!");
+                        FpuAluOp::Addition
+                    }
+                };
+            }
             _ => self.error("Unsupported Instruction!"),
         }
     }
@@ -293,9 +318,11 @@ impl RiscFpCoprocessor {
     fn read_registers(&mut self) {
         let reg1 = self.state.rs1 as usize;
         let reg2 = self.state.rs2 as usize;
+        let reg3 = self.state.rs3 as usize;
 
         self.state.read_data_1 = self.registers.fpr[reg1];
         self.state.read_data_2 = self.registers.fpr[reg2];
+        self.state.read_data_3 = self.registers.fpr[reg3];
     }
 
     // ======================= Execute (EX) =======================
@@ -303,8 +330,10 @@ impl RiscFpCoprocessor {
     fn alu(&mut self) {
         let input1 = self.state.read_data_1;
         let input2 = self.state.read_data_2;
+        let input3 = self.state.read_data_3;
         let input1_f64 = f64::from_bits(input1);
         let input2_f64 = f64::from_bits(input2);
+        let input3_f64 = f64::from_bits(input3);
         let mut input_mask = 0b0000000000;
 
         let result_f64: f64 = match self.signals.fpu_alu_op {
@@ -375,15 +404,12 @@ impl RiscFpCoprocessor {
                 }
                 0.0
             }
+            FpuAluOp::MAdd => input1_f64 * input2_f64 + input3_f64,
+            FpuAluOp::MSub => input1_f64 * input2_f64 - input3_f64,
+            FpuAluOp::NMSub => input1_f64.neg() * input2_f64 + input3_f64,
+            FpuAluOp::NMAdd => input1_f64.neg() * input2_f64 - input3_f64,
             // No operation.
-            FpuAluOp::Slt | FpuAluOp::Snge | FpuAluOp::Sle | FpuAluOp::Sngt => 0.0,
-            _ => {
-                self.error(&format!(
-                    "Unsupported operation in FPU `{:?}`",
-                    self.signals.fpu_alu_op
-                ));
-                0.0
-            }
+            FpuAluOp::Slt | FpuAluOp::Sle => 0.0,
         };
 
         if result_f64.is_nan() {
@@ -442,8 +468,6 @@ impl RiscFpCoprocessor {
             FpuAluOp::MultiplicationOrEqual => (input1_f64 == input2_f64) as u64,
             FpuAluOp::Slt => (input1_f64 < input2_f64) as u64,
             FpuAluOp::Sle => (input1_f64 <= input2_f64) as u64,
-            FpuAluOp::Sngt => !input1_f64.gt(&input2_f64) as u64,
-            FpuAluOp::Snge => !input1_f64.ge(&input2_f64) as u64,
             FpuAluOp::Addition | FpuAluOp::Subtraction | FpuAluOp::Division => 0, // No operation
             _ => {
                 self.error(&format!(
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 89b936ed2..8a6bac23d 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -597,7 +597,9 @@ impl RiscDatapath {
             Instruction::JType(j) => {
                 self.set_jtype_control_signals(j);
             }
-            _ => self.error("Unsupported Instruction!"),
+            Instruction::R4Type(r4) => {
+                self.set_r4type_control_signals(r4);
+            }
         }
     }
 
@@ -828,6 +830,19 @@ impl RiscDatapath {
         };
     }
 
+    /// Set the control signals for the datapath, specifically in the
+    /// case where the instruction is an R$-type.
+    fn set_r4type_control_signals(&mut self, _r4: R4Type) {
+        self.signals = ControlSignals {
+            op2_select: OP2Select::DATA2,
+            branch_jump: BranchJump::NoBranch,
+            read_write: ReadWrite::NoLoadStore,
+            wb_sel: WBSel::UseAlu,
+            reg_write_en: RegWriteEn::NoWrite,
+            ..Default::default()
+        };
+    }
+
     /// Read the registers as specified from the instruction and pass
     /// the data into the datapath.
     fn read_registers(&mut self) {

From 7b28864bac815a1f65c4aa6093d92f24b36145d2 Mon Sep 17 00:00:00 2001
From: Geetis <capiix1@gmail.com>
Date: Thu, 28 Mar 2024 20:16:19 -0400
Subject: [PATCH 18/48] Merged risc-v-parser and fixed branching and jumping
 instructions

---
 src/parser/assembling.rs                  |   8 +-
 src/parser/parser_assembler_main.rs       |  69 ++++----
 src/parser/parser_structs_and_enums.rs    |   1 +
 src/parser/pseudo_instruction_parsing.rs  | 189 ++++++++++++++++++----
 src/tests/parser/parser_assembler_main.rs |  30 ++--
 static/assembly_examples/riscv_fib.asm    |  53 ++++++
 static/assembly_examples/riscv_test.asm   |   9 +-
 7 files changed, 271 insertions(+), 88 deletions(-)
 create mode 100644 static/assembly_examples/riscv_fib.asm

diff --git a/src/parser/assembling.rs b/src/parser/assembling.rs
index 67d504fe3..8bed34368 100644
--- a/src/parser/assembling.rs
+++ b/src/parser/assembling.rs
@@ -255,9 +255,7 @@ pub fn read_operands_riscv(
                     instruction.errors.push(immediate_results.1.unwrap());
                 }
             }
-            UpperImmediate =>
-            // Can be used to represent offsets for J-type instructions
-            {
+            UpperImmediate => {
                 instruction.operands[i].token_type = TokenType::Immediate;
                 bit_lengths.push(20); // 20 bits to represent upper immediates
 
@@ -310,7 +308,7 @@ pub fn read_operands_riscv(
             LabelAbsolute => {
                 instruction.operands[i].token_type = TokenType::LabelOperand;
 
-                bit_lengths.push(26);
+                bit_lengths.push(20);
                 let label_absolute_results = read_label_absolute(
                     &instruction.operands[i].token_name,
                     instruction.operands[i].start_end_columns,
@@ -325,7 +323,7 @@ pub fn read_operands_riscv(
             LabelRelative => {
                 instruction.operands[i].token_type = TokenType::LabelOperand;
 
-                bit_lengths.push(16);
+                bit_lengths.push(12);
                 let label_relative_results = read_label_relative(
                     &instruction.operands[i].token_name,
                     instruction.operands[i].start_end_columns,
diff --git a/src/parser/parser_assembler_main.rs b/src/parser/parser_assembler_main.rs
index 84335da72..96333bc65 100644
--- a/src/parser/parser_assembler_main.rs
+++ b/src/parser/parser_assembler_main.rs
@@ -88,7 +88,6 @@ pub fn parser(
             (program_info.instructions, program_info.data) =
                 separate_data_and_text(&mut program_info.monaco_line_info);
 
-            // Implement a RISC-V version
             expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 &mut program_info.instructions,
                 &program_info.data,
@@ -1551,7 +1550,7 @@ pub fn read_instructions(
 
 pub fn read_instructions_riscv(
     instruction_list: &mut [Instruction],
-    _labels: &HashMap<String, usize>,
+    labels: &HashMap<String, usize>,
     monaco_line_info: &mut [MonacoLineInfo],
 ) {
     for instruction in &mut instruction_list.iter_mut() {
@@ -2291,9 +2290,9 @@ pub fn read_instructions_riscv(
                 // Read as U-type instruction and reorder immediate value after
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, UpperImmediate],
+                    vec![RegisterGP, LabelAbsolute],
                     vec![1, 2],
-                    None,
+                    Some(labels.clone()),
                     None,
                     None,
                 );
@@ -2302,9 +2301,10 @@ pub fn read_instructions_riscv(
                 instruction.binary = append_binary(instruction.binary, 0b1101111, 7);
 
                 // Reorder immediate
-                instruction.binary = upper_to_jump(instruction.binary);
+                //instruction.binary = upper_to_jump(instruction.binary);
+
+                // This isn't accurate to the risc-v spec, but we can make the user aware of this change in the instruction description. Unsure how useful this may be to the end user.
 
-                //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb
                 if monaco_line_info[instruction.line_number]
                     .mouse_hover_string
                     .is_empty()
@@ -2319,8 +2319,8 @@ pub fn read_instructions_riscv(
             "jalr" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, MemoryAddress],
-                    vec![1, 3, 2],
+                    vec![RegisterGP, RegisterGP, Immediate],
+                    vec![1, 2, 3],
                     None,
                     Some(0b000),
                     None,
@@ -2344,9 +2344,9 @@ pub fn read_instructions_riscv(
             "beq" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, Immediate],
+                    vec![RegisterGP, RegisterGP, LabelRelative],
                     vec![1, 2, 3],
-                    None,
+                    Some(labels.clone()),
                     Some(0b000),
                     None,
                 );
@@ -2354,7 +2354,10 @@ pub fn read_instructions_riscv(
                 // Opcode
                 instruction.binary = append_binary(instruction.binary, 0b1100011, 7);
 
-                instruction.binary = immediate_to_branch(instruction.binary);
+                // May be easier to treat branch instructions as i-type instructions due to how labels get resolved
+                // This isn't accurate to the risc-v spec, but we can make the user aware of this change in the instruction description
+
+                //instruction.binary = immediate_to_branch(instruction.binary);
 
                 //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb
                 if monaco_line_info[instruction.line_number]
@@ -2362,7 +2365,7 @@ pub fn read_instructions_riscv(
                     .is_empty()
                 {
                     let info = InstructionDescription {
-                        syntax: "beq rs1, rs2, offset".to_string(),
+                        syntax: "beq rs1, rs2, label".to_string(),
                         description: "Take the branch if registers rs1 and rs2 are equal."
                             .to_string(),
                     };
@@ -2372,9 +2375,9 @@ pub fn read_instructions_riscv(
             "bne" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, Immediate],
+                    vec![RegisterGP, RegisterGP, LabelRelative],
                     vec![1, 2, 3],
-                    None,
+                    Some(labels.clone()),
                     Some(0b001),
                     None,
                 );
@@ -2382,7 +2385,7 @@ pub fn read_instructions_riscv(
                 // Opcode
                 instruction.binary = append_binary(instruction.binary, 0b1100011, 7);
 
-                instruction.binary = immediate_to_branch(instruction.binary);
+                //instruction.binary = immediate_to_branch(instruction.binary);
 
                 //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb
                 if monaco_line_info[instruction.line_number]
@@ -2390,7 +2393,7 @@ pub fn read_instructions_riscv(
                     .is_empty()
                 {
                     let info = InstructionDescription {
-                        syntax: "bne rs1, rs2, offset".to_string(),
+                        syntax: "bne rs1, rs2, label".to_string(),
                         description: "Take the branch if registers rs1 and rs2 are not equal."
                             .to_string(),
                     };
@@ -2400,9 +2403,9 @@ pub fn read_instructions_riscv(
             "blt" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, Immediate],
+                    vec![RegisterGP, RegisterGP, LabelRelative],
                     vec![1, 2, 3],
-                    None,
+                    Some(labels.clone()),
                     Some(0b100),
                     None,
                 );
@@ -2410,7 +2413,7 @@ pub fn read_instructions_riscv(
                 // Opcode
                 instruction.binary = append_binary(instruction.binary, 0b1100011, 7);
 
-                instruction.binary = immediate_to_branch(instruction.binary);
+                //instruction.binary = immediate_to_branch(instruction.binary);
 
                 //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb
                 if monaco_line_info[instruction.line_number]
@@ -2418,7 +2421,7 @@ pub fn read_instructions_riscv(
                     .is_empty()
                 {
                     let info = InstructionDescription{
-                        syntax: "blt rs1, rs2, offset".to_string(),
+                        syntax: "blt rs1, rs2, label".to_string(),
                         description: "Take the branch if registers rs1 is less than rs2, using signed comparison.".to_string(),
                     };
                     monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string();
@@ -2427,9 +2430,9 @@ pub fn read_instructions_riscv(
             "bge" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, Immediate],
+                    vec![RegisterGP, RegisterGP, LabelRelative],
                     vec![1, 2, 3],
-                    None,
+                    Some(labels.clone()),
                     Some(0b101),
                     None,
                 );
@@ -2437,7 +2440,7 @@ pub fn read_instructions_riscv(
                 // Opcode
                 instruction.binary = append_binary(instruction.binary, 0b1100011, 7);
 
-                instruction.binary = immediate_to_branch(instruction.binary);
+                //instruction.binary = immediate_to_branch(instruction.binary);
 
                 //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb
                 if monaco_line_info[instruction.line_number]
@@ -2454,9 +2457,9 @@ pub fn read_instructions_riscv(
             "bltu" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, Immediate],
+                    vec![RegisterGP, RegisterGP, LabelRelative],
                     vec![1, 2, 3],
-                    None,
+                    Some(labels.clone()),
                     Some(0b110),
                     None,
                 );
@@ -2464,7 +2467,7 @@ pub fn read_instructions_riscv(
                 // Opcode
                 instruction.binary = append_binary(instruction.binary, 0b1100011, 7);
 
-                instruction.binary = immediate_to_branch(instruction.binary);
+                //instruction.binary = immediate_to_branch(instruction.binary);
 
                 //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb
                 if monaco_line_info[instruction.line_number]
@@ -2472,7 +2475,7 @@ pub fn read_instructions_riscv(
                     .is_empty()
                 {
                     let info = InstructionDescription{
-                        syntax: "bltu rs1, rs2, offset".to_string(),
+                        syntax: "bltu rs1, rs2, label".to_string(),
                         description: "Take the branch if registers rs1 is less than rs2, using unsigned comparison.".to_string(),
                     };
                     monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string();
@@ -2481,9 +2484,9 @@ pub fn read_instructions_riscv(
             "bgeu" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, Immediate],
+                    vec![RegisterGP, RegisterGP, LabelRelative],
                     vec![1, 2, 3],
-                    None,
+                    Some(labels.clone()),
                     Some(0b111),
                     None,
                 );
@@ -2491,7 +2494,7 @@ pub fn read_instructions_riscv(
                 // Opcode
                 instruction.binary = append_binary(instruction.binary, 0b1100011, 7);
 
-                instruction.binary = immediate_to_branch(instruction.binary);
+                //instruction.binary = immediate_to_branch(instruction.binary);
 
                 //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb
                 if monaco_line_info[instruction.line_number]
@@ -2499,7 +2502,7 @@ pub fn read_instructions_riscv(
                     .is_empty()
                 {
                     let info = InstructionDescription{
-                        syntax: "bgeu rs1, rs2, offset".to_string(),
+                        syntax: "bgeu rs1, rs2, label".to_string(),
                         description: "Take the branch if registers rs1 is greater than or equal to rs2, using unsigned comparison.".to_string(),
                     };
                     monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string();
@@ -4968,7 +4971,7 @@ fn immediate_to_stored(mut bin: u32) -> u32 {
 
 // Converts an I-type instruction to B-type instruction
 // Easier to encode in this manner
-fn immediate_to_branch(mut bin: u32) -> u32 {
+fn _immediate_to_branch(mut bin: u32) -> u32 {
     // Extract bits imm[4:1] from the immediate, last bit is ignored
     let lower_imm = (bin >> 21) & 0b1111;
 
@@ -5008,7 +5011,7 @@ fn immediate_to_branch(mut bin: u32) -> u32 {
 }
 
 // Reorder the immediate value to comply with J-type format
-fn upper_to_jump(mut bin: u32) -> u32 {
+fn _upper_to_jump(mut bin: u32) -> u32 {
     // Extract bits immediate
     let imm = bin >> 12;
 
diff --git a/src/parser/parser_structs_and_enums.rs b/src/parser/parser_structs_and_enums.rs
index 2b8b52ad9..32d55817a 100644
--- a/src/parser/parser_structs_and_enums.rs
+++ b/src/parser/parser_structs_and_enums.rs
@@ -235,6 +235,7 @@ pub enum ErrorType {
     NonASCIIString, //One or multiple characters within the given string cannot be represented in ASCII
     NonASCIIChar,   //The given char cannot be represented in ASCII
     JALRRDRegisterZero, //The destination address for JALR cannot be the zero register
+    IncorrectImmediateValue, //Ensure immediate value for li is valid
 }
 
 impl fmt::Display for ErrorType {
diff --git a/src/parser/pseudo_instruction_parsing.rs b/src/parser/pseudo_instruction_parsing.rs
index b3ecffb25..e01c15b70 100644
--- a/src/parser/pseudo_instruction_parsing.rs
+++ b/src/parser/pseudo_instruction_parsing.rs
@@ -1,4 +1,6 @@
-use crate::parser::parser_structs_and_enums::ErrorType::IncorrectNumberOfOperands;
+use crate::parser::parser_structs_and_enums::ErrorType::{
+    IncorrectImmediateValue, IncorrectNumberOfOperands,
+};
 use crate::parser::parser_structs_and_enums::TokenType::Operator;
 use crate::parser::parser_structs_and_enums::{
     Data, Error, Instruction, MonacoLineInfo, PseudoDescription, Token,
@@ -1260,7 +1262,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
 
     //vec_of_added_instructions is needed because of rust ownership rules. It will not let us
     //insert into instruction_list while instruction_list is being iterated over.
-    let vec_of_added_instructions: Vec<Instruction> = Vec::new();
+    let mut vec_of_added_instructions: Vec<Instruction> = Vec::new();
 
     //iterate through every instruction and check if the operator is a pseudo-instruction
     for (i, instruction) in &mut instructions.iter_mut().enumerate() {
@@ -1310,7 +1312,79 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+            }
+            "li" => {
+                let info = PseudoDescription {
+                    name: "li".to_string(),
+                    syntax: "li rd, imm".to_string(),
+                    translation_lines: vec![
+                        "lui rd, imm[31:12]".to_string(),
+                        "addi rd, rd, imm[11:0]".to_string(),
+                    ],
+                };
+                monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string();
+
+                // Change to function implementation
+                if !check_operands(instruction, 2) {
+                    continue;
+                }
+
+                // Parse the immediate value from the second operand
+                let imm_value: i32 = match instruction.operands[1].token_name.parse() {
+                    Ok(val) => val,
+                    Err(_) => {
+                        instruction.errors.push(Error {
+                            error_name: IncorrectImmediateValue,
+                            token_causing_error: instruction.operands[1].token_name.clone(),
+                            start_end_columns: instruction.operands[1].start_end_columns,
+                            message: "Invalid immediate value".to_string(),
+                        });
+                        continue;
+                    }
+                };
+
+                // Extract the upper and lower parts of the immediate value
+                let upper_imm = imm_value >> 12;
+                let lower_imm = imm_value & 0xFFF;
+
+                // lui instruction
+                instruction.operator.token_name = "lui".to_string();
+                instruction.operator.start_end_columns = (0, 0);
+                instruction.operator.token_type = Default::default();
+                instruction.operands[1].token_name = upper_imm.to_string();
+                instruction.operands[1].start_end_columns = (0, 0);
+                instruction.operands[1].token_type = Default::default();
+                instruction.binary = 0;
+                instruction.errors = vec![];
+                instruction.labels = Vec::new();
+
+                // addi instruction
+                let mut addi_instruction = Instruction {
+                    operator: Token {
+                        token_name: "addi".to_string(),
+                        start_end_columns: (0, 0),
+                        token_type: Default::default(),
+                    },
+                    operands: vec![
+                        instruction.operands[0].clone(),
+                        instruction.operands[0].clone(),
+                        Token {
+                            token_name: lower_imm.to_string(),
+                            start_end_columns: (0, 0),
+                            token_type: Default::default(),
+                        },
+                    ],
+                    binary: 0,
+                    instruction_number: instruction.instruction_number + 1,
+                    line_number: instruction.line_number,
+                    errors: vec![],
+                    labels: Vec::new(),
+                };
+                vec_of_added_instructions.push(addi_instruction.clone());
+
+                monaco_line_info[instruction.line_number]
+                    .update_pseudo_string(vec![instruction, &mut addi_instruction]);
             }
             "mv" => {
                 // Set Pseudo Description
@@ -1340,7 +1414,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "not" => {
                 // Set Pseudo Description
@@ -1370,7 +1444,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "neg" => {
                 // Set Pseudo Description
@@ -1400,7 +1474,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "negw" => {
                 // Set Pseudo Description
@@ -1430,7 +1504,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "sext.w" => {
                 // Set Pseudo Description
@@ -1460,7 +1534,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "seqz" => {
                 // Set Pseudo Description
@@ -1490,7 +1564,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "snez" => {
                 // Set Pseudo Description
@@ -1520,7 +1594,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "sltz" => {
                 // Set Pseudo Description
@@ -1550,7 +1624,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "sgtz" => {
                 // Set Pseudo Description
@@ -1580,7 +1654,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "beqz" => {
                 // Set Pseudo Description
@@ -1610,7 +1684,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "bnez" => {
                 // Set Pseudo Description
@@ -1640,7 +1714,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "blez" => {
                 // Set Pseudo Description
@@ -1670,7 +1744,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "bgez" => {
                 // Set Pseudo Description
@@ -1700,7 +1774,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "bltz" => {
                 // Set Pseudo Description
@@ -1730,7 +1804,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "bgtz" => {
                 // Set Pseudo Description
@@ -1760,7 +1834,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "bgt" => {
                 // Set Pseudo Description
@@ -1785,7 +1859,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 instruction.operands[1].token_name = tmp;
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "ble" => {
                 // Set Pseudo Description
@@ -1810,7 +1884,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 instruction.operands[1].token_name = tmp;
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "bgtu" => {
                 // Set Pseudo Description
@@ -1835,7 +1909,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 instruction.operands[1].token_name = tmp;
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "bleu" => {
                 // Set Pseudo Description
@@ -1860,7 +1934,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 instruction.operands[1].token_name = tmp;
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             // Start of Jump Pseudo-Instructions
             "j" => {
@@ -1891,14 +1965,14 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "jr" => {
                 // Set Pseudo Description
                 let info = PseudoDescription {
                     name: "jr".to_string(),
                     syntax: "jr offset".to_string(),
-                    translation_lines: vec!["jal x1, offset".to_string()],
+                    translation_lines: vec!["jalr x0, rs, 0".to_string()],
                 };
                 monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string();
 
@@ -1921,14 +1995,57 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+            }
+            "jalr" => {
+                // Account for default jal instruction
+                if instruction.operands.len() != 1 {
+                    continue;
+                }
+
+                // Set Pseudo Description
+                let info = PseudoDescription {
+                    name: "jalr".to_string(),
+                    syntax: "jalr rs".to_string(),
+                    translation_lines: vec!["jalr x1, rs, 0".to_string()],
+                };
+                monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string();
+
+                // Check operands
+                if !check_operands(instruction, 1) {
+                    continue;
+                }
+
+                // Replace Instruction
+                instruction.operator.token_name = "jalr".to_string();
+
+                // Replace Operands
+                instruction.operands.insert(
+                    0,
+                    Token {
+                        token_name: "x1".to_string(),
+                        start_end_columns: (0, 0),
+                        token_type: Default::default(),
+                    },
+                );
+                instruction.operands.insert(
+                    2,
+                    Token {
+                        token_name: "0".to_string(),
+                        start_end_columns: (0, 0),
+                        token_type: Default::default(),
+                    },
+                );
+
+                // Update Line Info
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "ret" => {
                 // Set Pseudo Description
                 let info = PseudoDescription {
                     name: "ret".to_string(),
                     syntax: "ret".to_string(),
-                    translation_lines: vec!["jalr x1, 0(x0)".to_string()],
+                    translation_lines: vec!["jalr x0, x1, 0".to_string()],
                 };
                 monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string();
 
@@ -1944,7 +2061,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 instruction.operands.insert(
                     0,
                     Token {
-                        token_name: "x1".to_string(),
+                        token_name: "x0".to_string(),
                         start_end_columns: (0, 0),
                         token_type: Default::default(),
                     },
@@ -1952,14 +2069,22 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 instruction.operands.insert(
                     1,
                     Token {
-                        token_name: "0(x0)".to_string(),
+                        token_name: "x1".to_string(),
+                        start_end_columns: (0, 0),
+                        token_type: Default::default(),
+                    },
+                );
+                instruction.operands.insert(
+                    2,
+                    Token {
+                        token_name: "0".to_string(),
                         start_end_columns: (0, 0),
                         token_type: Default::default(),
                     },
                 );
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             // Start of F extension pseudo-instructions
             "fmv.s" => {
@@ -1985,7 +2110,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                     .insert(2, instruction.operands[1].clone());
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "fabs.s" => {
                 // Set Pseudo Description
@@ -2010,7 +2135,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                     .insert(2, instruction.operands[1].clone());
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             "fneg.s" => {
                 // Set Pseudo Description
@@ -2035,7 +2160,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                     .insert(2, instruction.operands[1].clone());
 
                 // Update Line Info
-                //monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
+                monaco_line_info[instruction.line_number].update_pseudo_string(vec![instruction]);
             }
             _ => {}
         }
diff --git a/src/tests/parser/parser_assembler_main.rs b/src/tests/parser/parser_assembler_main.rs
index 398b0acf4..824f3cde0 100644
--- a/src/tests/parser/parser_assembler_main.rs
+++ b/src/tests/parser/parser_assembler_main.rs
@@ -357,19 +357,19 @@ mod read_riscv_instructions_tests {
 
     #[test]
     fn read_instructions_jal() {
-        let file_string = "jal x1, 2044".to_string();
+        let file_string = "main:\njal x1, L1\nret\nL1:\nadd x1, x2, x3".to_string();
 
         let instruction_list = instruction_parser_riscv(file_string);
 
         assert_eq!(
             instruction_list[0].binary,
-            0b01111111110000000000000011101111
+            0b00000000000000000010000011101111
         );
     }
 
     #[test]
     fn read_instructions_jalr() {
-        let file_string = "jalr x2, 128(x3)".to_string();
+        let file_string = "jalr x2, x3, 128".to_string();
 
         let instruction_list = instruction_parser_riscv(file_string);
 
@@ -381,73 +381,73 @@ mod read_riscv_instructions_tests {
 
     #[test]
     fn read_instructions_beq() {
-        let file_string = "beq x4, x5, 256".to_string();
+        let file_string = "main:\nbeq x1, x2, L1\nret\nL1:\nadd x1, x2, x3".to_string();
 
         let instruction_list = instruction_parser_riscv(file_string);
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00010000010100100000000001100011
+            0b00000000000100010000000011100011
         );
     }
 
     #[test]
     fn read_instructions_bne() {
-        let file_string = "bne x6, x7, 512".to_string();
+        let file_string = "main:\nbne x1, x2, L1\nret\nL1:\nadd x1, x2, x3".to_string();
 
         let instruction_list = instruction_parser_riscv(file_string);
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00100000011100110001000001100011
+            0b00000000000100010001000011100011
         );
     }
 
     #[test]
     fn read_instructions_blt() {
-        let file_string = "blt x8, x9, 1024".to_string();
+        let file_string = "main:\nblt x1, x2, L1\nret\nL1:\nadd x1, x2, x3".to_string();
 
         let instruction_list = instruction_parser_riscv(file_string);
 
         assert_eq!(
             instruction_list[0].binary,
-            0b01000000100101000100000011100011
+            0b00000000000100010100000011100011
         );
     }
 
     #[test]
     fn read_instructions_bge() {
-        let file_string = "bge x10, x11, 256".to_string();
+        let file_string = "main:\nbge x1, x2, L1\nret\nL1:\nadd x1, x2, x3".to_string();
 
         let instruction_list = instruction_parser_riscv(file_string);
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00010000101101010101000001100011
+            0b00000000000100010101000011100011
         );
     }
 
     #[test]
     fn read_instructions_bltu() {
-        let file_string = "bltu x12, x13, 64".to_string();
+        let file_string = "main:\nbltu x1, x2, L1\nret\nL1:\nadd x1, x2, x3".to_string();
 
         let instruction_list = instruction_parser_riscv(file_string);
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00000100110101100110000001100011
+            0b00000000000100010110000011100011
         );
     }
 
     #[test]
     fn read_instructions_bgeu() {
-        let file_string = "bgeu x14, x15, 32".to_string();
+        let file_string = "main:\nbgeu x1, x2, L1\nret\nL1:\nadd x1, x2, x3".to_string();
 
         let instruction_list = instruction_parser_riscv(file_string);
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00000010111101110111000001100011
+            0b00000000000100010111000011100011
         );
     }
 
diff --git a/static/assembly_examples/riscv_fib.asm b/static/assembly_examples/riscv_fib.asm
new file mode 100644
index 000000000..424c2c231
--- /dev/null
+++ b/static/assembly_examples/riscv_fib.asm
@@ -0,0 +1,53 @@
+fib:
+ addi sp,sp,-32
+ sw ra,28(sp)
+ sw s0,24(sp)
+ sw s1,20(sp)
+ addi s0,sp,32
+ sw a0,-20(s0)
+ lw a4,-20(s0)
+ li a5,1
+ blt a5,a4,L2
+ lw a5,-20(s0)
+ j L3
+
+L2:
+ lw a5,-20(s0)
+ addi a5,a5,-1
+ mv a0,a5
+ auipc ra,0
+ jalr ra # 26 <.L2+0x8>
+ mv s1,a0
+ lw a5,-20(s0)
+ addi a5,a5,-2
+ mv a0,a5
+ auipc ra,0
+ jalr ra # 38 <.L2+0x1a>
+ mv a5,a0
+ add a5,a5,s1
+
+L3:
+ mv a0,a5
+ lw ra,28(sp)
+ lw s0,24(sp)
+ lw s1,20(sp)
+ addi sp,sp,32
+ ret
+
+main:
+ addi sp,sp,-32
+ sw ra,28(sp)
+ sw s0,24(sp)
+ addi s0,sp,32
+ li a5,5
+ sw a5,-20(s0)
+ lw a0,-20(s0)
+ auipc ra,0
+ jalr ra # 62 <main+0x12>
+ sw a0,-24(s0)
+ lw a5,-24(s0)
+ mv a0,a5
+ lw ra,28(sp)
+ lw s0,24(sp)
+ addi sp,sp,32
+ ret
\ No newline at end of file
diff --git a/static/assembly_examples/riscv_test.asm b/static/assembly_examples/riscv_test.asm
index f1f6791c4..36e2a59bf 100644
--- a/static/assembly_examples/riscv_test.asm
+++ b/static/assembly_examples/riscv_test.asm
@@ -1,4 +1,7 @@
 main:
-        addi x1, x0, 50
-        addi x2, x0, 2
-        mul x3, x1, x2
\ No newline at end of file
+    jal x1, L1
+    bgeu x1, x2, L1
+    ret
+
+L1:
+    add x1, x2, x3

From 992048513370acbd3ee9af00433c1a8591e52031 Mon Sep 17 00:00:00 2001
From: Geetis <capiix1@gmail.com>
Date: Thu, 28 Mar 2024 20:16:42 -0400
Subject: [PATCH 19/48] Fixed branching and jump instructions

---
 src/emulation_core/riscv/datapath.rs    | 27 +++++++------------------
 src/emulation_core/riscv/instruction.rs | 10 ++++-----
 src/parser/parser_assembler_main.rs     | 12 +++++------
 static/assembly_examples/riscv_test.asm |  8 ++++----
 4 files changed, 21 insertions(+), 36 deletions(-)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 00287aa29..158f57113 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -541,11 +541,10 @@ impl RiscDatapath {
                 self.state.imm2 = s.imm2 as u32;
             }
             Instruction::BType(b) => {
-                self.state.rs2 = b.rs2 as u32;
                 self.state.rs1 = b.rs1 as u32;
+                self.state.rs2 = b.rs2 as u32;
                 self.state.funct3 = b.funct3 as u32;
-                self.state.imm1 = b.imm1 as u32;
-                self.state.imm2 = b.imm2 as u32;
+                self.state.imm = b.imm as u32;
             }
             Instruction::UType(u) => {
                 self.state.imm = u.imm;
@@ -572,18 +571,9 @@ impl RiscDatapath {
             ImmSelect::IShamt => (signed_imm << 12) | self.state.imm,
             ImmSelect::IUnsigned => self.state.imm,
             ImmSelect::SType => ((signed_imm << 7) | self.state.imm1) << 5 | self.state.imm2,
-            ImmSelect::BType => {
-                ((((signed_imm << 1) | (self.state.imm2 & 0x01)) << 6) | (self.state.imm1 & 0x3f))
-                    << 5
-                    | (self.state.imm2 & 0x1e)
-            }
+            ImmSelect::BType => self.state.imm,
             ImmSelect::UType => ((signed_imm << 20) | self.state.imm) << 12,
-            ImmSelect::JType => {
-                (((((signed_imm << 8) | (self.state.imm & 0xff)) << 1)
-                    | (self.state.imm >> 8 & 0x01))
-                    << 11)
-                    | (self.state.imm >> 8 & 0x7fe)
-            }
+            ImmSelect::JType => self.state.imm,
         };
 
         self.state.imm = signed_imm;
@@ -986,18 +976,15 @@ impl RiscDatapath {
     }
 
     fn construct_jump_address(&mut self) {
-        self.state.rd = self.state.pc_plus_4 as u32;
         self.state.jump_address = match self.instruction {
-            Instruction::IType(_i) => {
-                (self.state.imm as u64 + self.state.read_data_1) & 0xfffffffffffffff0
-            }
-            Instruction::JType(_j) => self.state.imm as u64 + self.registers.pc,
+            Instruction::IType(_i) => self.state.imm as u64 + self.state.read_data_1,
+            Instruction::JType(_j) => self.state.imm as u64 * 4,
             _ => self.state.jump_address,
         }
     }
 
     fn calc_relative_pc_branch(&mut self) {
-        self.state.relative_pc_branch = ((self.state.imm & 0x00000fff) as u64) + self.registers.pc;
+        self.state.relative_pc_branch = self.state.imm as u64 * 4;
     }
 
     /// Determine the value of the [`CpuBranch`] signal.
diff --git a/src/emulation_core/riscv/instruction.rs b/src/emulation_core/riscv/instruction.rs
index 5007a9445..795949d69 100644
--- a/src/emulation_core/riscv/instruction.rs
+++ b/src/emulation_core/riscv/instruction.rs
@@ -51,11 +51,10 @@ pub struct SType {
 
 #[derive(Clone, Copy, Debug, Default, PartialEq)]
 pub struct BType {
-    pub imm1: u8,
+    pub imm: u16,
     pub rs2: u8,
     pub rs1: u8,
     pub funct3: u8,
-    pub imm2: u8,
     pub op: u8,
 }
 
@@ -141,11 +140,10 @@ impl TryFrom<u32> for Instruction {
 
             // B-type instruction:
             OPCODE_BRANCH => Ok(Instruction::BType(BType {
-                imm1: (value >> 25) as u8,
-                rs2: ((value >> 20) & 0x1f) as u8,
-                rs1: ((value >> 15) & 0x1f) as u8,
+                imm: (value >> 20) as u16,
+                rs1: ((value >> 7) & 0x1f) as u8,
                 funct3: ((value >> 12) & 0x07) as u8,
-                imm2: ((value >> 7) & 0x1f) as u8,
+                rs2: ((value >> 15) & 0x1f) as u8,
                 op: (value & 0x7f) as u8,
             })),
 
diff --git a/src/parser/parser_assembler_main.rs b/src/parser/parser_assembler_main.rs
index 96333bc65..106fbcad6 100644
--- a/src/parser/parser_assembler_main.rs
+++ b/src/parser/parser_assembler_main.rs
@@ -2344,7 +2344,7 @@ pub fn read_instructions_riscv(
             "beq" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, LabelRelative],
+                    vec![RegisterGP, RegisterGP, LabelAbsolute],
                     vec![1, 2, 3],
                     Some(labels.clone()),
                     Some(0b000),
@@ -2375,7 +2375,7 @@ pub fn read_instructions_riscv(
             "bne" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, LabelRelative],
+                    vec![RegisterGP, RegisterGP, LabelAbsolute],
                     vec![1, 2, 3],
                     Some(labels.clone()),
                     Some(0b001),
@@ -2403,7 +2403,7 @@ pub fn read_instructions_riscv(
             "blt" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, LabelRelative],
+                    vec![RegisterGP, RegisterGP, LabelAbsolute],
                     vec![1, 2, 3],
                     Some(labels.clone()),
                     Some(0b100),
@@ -2430,7 +2430,7 @@ pub fn read_instructions_riscv(
             "bge" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, LabelRelative],
+                    vec![RegisterGP, RegisterGP, LabelAbsolute],
                     vec![1, 2, 3],
                     Some(labels.clone()),
                     Some(0b101),
@@ -2457,7 +2457,7 @@ pub fn read_instructions_riscv(
             "bltu" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, LabelRelative],
+                    vec![RegisterGP, RegisterGP, LabelAbsolute],
                     vec![1, 2, 3],
                     Some(labels.clone()),
                     Some(0b110),
@@ -2484,7 +2484,7 @@ pub fn read_instructions_riscv(
             "bgeu" => {
                 read_operands_riscv(
                     instruction,
-                    vec![RegisterGP, RegisterGP, LabelRelative],
+                    vec![RegisterGP, RegisterGP, LabelAbsolute],
                     vec![1, 2, 3],
                     Some(labels.clone()),
                     Some(0b111),
diff --git a/static/assembly_examples/riscv_test.asm b/static/assembly_examples/riscv_test.asm
index 36e2a59bf..7cbfc3705 100644
--- a/static/assembly_examples/riscv_test.asm
+++ b/static/assembly_examples/riscv_test.asm
@@ -1,7 +1,7 @@
 main:
-    jal x1, L1
-    bgeu x1, x2, L1
-    ret
+        addi x1, x0, 1
+        addi x2, x0, 1
+        beq x3, x1, L1
 
 L1:
-    add x1, x2, x3
+    addi x1, x0, 100
\ No newline at end of file

From 5fd4c731cd2365b0762ad04d8c67852fc3b8ed05 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 20:17:16 -0400
Subject: [PATCH 20/48] Fixed the Floating Point inputs and outputs to 32 bits,
 compliant with RV64F (In spite of its confusing name).

---
 src/emulation_core/riscv/coprocessor.rs | 144 ++++++++++++------------
 1 file changed, 72 insertions(+), 72 deletions(-)

diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 9fa374ac3..eac2e52fb 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -328,75 +328,75 @@ impl RiscFpCoprocessor {
     // ======================= Execute (EX) =======================
     /// Perform an ALU operation.
     fn alu(&mut self) {
-        let input1 = self.state.read_data_1;
-        let input2 = self.state.read_data_2;
-        let input3 = self.state.read_data_3;
-        let input1_f64 = f64::from_bits(input1);
-        let input2_f64 = f64::from_bits(input2);
-        let input3_f64 = f64::from_bits(input3);
+        let input1 = self.state.read_data_1 as u32;
+        let input2 = self.state.read_data_2 as u32;
+        let input3 = self.state.read_data_3 as u32;
+        let input1_f32 = f32::from_bits(input1);
+        let input2_f32 = f32::from_bits(input2);
+        let input3_f32 = f32::from_bits(input3);
         let mut input_mask = 0b0000000000;
 
-        let result_f64: f64 = match self.signals.fpu_alu_op {
-            FpuAluOp::Addition => input1_f64 + input2_f64,
-            FpuAluOp::Subtraction => input1_f64 - input2_f64,
-            FpuAluOp::MultiplicationOrEqual => input1_f64 * input2_f64,
+        let result_f32: f32 = match self.signals.fpu_alu_op {
+            FpuAluOp::Addition => input1_f32 + input2_f32,
+            FpuAluOp::Subtraction => input1_f32 - input2_f32,
+            FpuAluOp::MultiplicationOrEqual => input1_f32 * input2_f32,
             FpuAluOp::Division => {
-                if input2_f64 == 0.0 {
+                if input2_f32 == 0.0 {
                     0.0
                 } else {
-                    input1_f64 / input2_f64
+                    input1_f32 / input2_f32
                 }
             }
-            FpuAluOp::Sqrt => input1_f64.sqrt(),
+            FpuAluOp::Sqrt => input1_f32.sqrt(),
             FpuAluOp::Min => {
-                if input1_f64 < input2_f64 {
-                    input1_f64
+                if input1_f32 < input2_f32 {
+                    input1_f32
                 } else {
-                    input2_f64
+                    input2_f32
                 }
             }
             FpuAluOp::Max => {
-                if input1_f64 > input2_f64 {
-                    input1_f64
+                if input1_f32 > input2_f32 {
+                    input1_f32
                 } else {
-                    input2_f64
+                    input2_f32
                 }
             }
-            FpuAluOp::SGNJ => f64::from_bits((input1 & 0x01111111) | (input2 >> 63 << 63)),
-            FpuAluOp::SGNJN => f64::from_bits((input1 & 0x01111111) | (!(input2 >> 63) << 63)),
+            FpuAluOp::SGNJ => f32::from_bits((input1 & 0x01111111) | (input2 >> 31 << 31)),
+            FpuAluOp::SGNJN => f32::from_bits((input1 & 0x01111111) | (!(input2 >> 31) << 31)),
             FpuAluOp::SGNJX => {
-                f64::from_bits((input1 & 0x01111111) | (((input2 >> 63) ^ (input1 >> 63)) << 63))
+                f32::from_bits((input1 & 0x01111111) | (((input2 >> 31) ^ (input1 >> 31)) << 31))
             }
             FpuAluOp::Class => {
-                if input1_f64.is_sign_negative() {
-                    if input1_f64.is_infinite() {
+                if input1_f32.is_sign_negative() {
+                    if input1_f32.is_infinite() {
                         input_mask = 0b1;
                     }
-                    else if input1_f64.is_normal() {
+                    else if input1_f32.is_normal() {
                         input_mask = 0b10;
                     }
-                    else if input1_f64.is_subnormal() {
+                    else if input1_f32.is_subnormal() {
                         input_mask = 0b100;
                     }
                     else {
                         input_mask = 0b1000;
                     }
                 }
-                else if input1_f64.is_sign_positive() {
-                    if input1_f64.is_infinite() {
+                else if input1_f32.is_sign_positive() {
+                    if input1_f32.is_infinite() {
                         input_mask = 0b10000000;
                     }
-                    else if input1_f64.is_normal() {
+                    else if input1_f32.is_normal() {
                         input_mask = 0b1000000;
                     }
-                    else if input1_f64.is_subnormal() {
+                    else if input1_f32.is_subnormal() {
                         input_mask = 0b100000;
                     }
                     else {
                         input_mask = 0b10000;
                     }
                 }
-                else if input1_f64.is_nan() {
+                else if input1_f32.is_nan() {
                     input_mask = 0b100000000;
                 }
                 else {
@@ -404,15 +404,15 @@ impl RiscFpCoprocessor {
                 }
                 0.0
             }
-            FpuAluOp::MAdd => input1_f64 * input2_f64 + input3_f64,
-            FpuAluOp::MSub => input1_f64 * input2_f64 - input3_f64,
-            FpuAluOp::NMSub => input1_f64.neg() * input2_f64 + input3_f64,
-            FpuAluOp::NMAdd => input1_f64.neg() * input2_f64 - input3_f64,
+            FpuAluOp::MAdd => input1_f32 * input2_f32 + input3_f32,
+            FpuAluOp::MSub => input1_f32 * input2_f32 - input3_f32,
+            FpuAluOp::NMSub => input1_f32.neg() * input2_f32 + input3_f32,
+            FpuAluOp::NMAdd => input1_f32.neg() * input2_f32 - input3_f32,
             // No operation.
             FpuAluOp::Slt | FpuAluOp::Sle => 0.0,
         };
 
-        if result_f64.is_nan() {
+        if result_f32.is_nan() {
             self.state.alu_result = RISC_NAN as u64;
             return;
         }
@@ -421,7 +421,7 @@ impl RiscFpCoprocessor {
             | (self.signals.fpu_alu_op == FpuAluOp::SGNJN)
             | (self.signals.fpu_alu_op == FpuAluOp::SGNJX)
         {
-            self.state.alu_result = f64::to_bits(result_f64);
+            self.state.alu_result = f32::to_bits(result_f32) as u64;
             return;
         }
 
@@ -431,22 +431,22 @@ impl RiscFpCoprocessor {
         }
 
         self.state.alu_result = match self.signals.round_mode {
-            RoundingMode::RNE => f64::to_bits(
-                if (result_f64.ceil() - result_f64).abs() == (result_f64 - result_f64.floor()).abs()
+            RoundingMode::RNE => f32::to_bits(
+                if (result_f32.ceil() - result_f32).abs() == (result_f32 - result_f32.floor()).abs()
                 {
-                    if result_f64.ceil() % 2.0 == 0.0 {
-                        result_f64.ceil()
+                    if result_f32.ceil() % 2.0 == 0.0 {
+                        result_f32.ceil()
                     } else {
-                        result_f64.floor()
+                        result_f32.floor()
                     }
                 } else {
-                    result_f64.round()
+                    result_f32.round()
                 },
-            ),
-            RoundingMode::RTZ => f64::to_bits(result_f64.trunc()),
-            RoundingMode::RDN => f64::to_bits(result_f64.floor()),
-            RoundingMode::RUP => f64::to_bits(result_f64.ceil()),
-            RoundingMode::RMM => f64::to_bits(result_f64.round()),
+            ) as u64,
+            RoundingMode::RTZ => f32::to_bits(result_f32.trunc()) as u64,
+            RoundingMode::RDN => f32::to_bits(result_f32.floor()) as u64,
+            RoundingMode::RUP => f32::to_bits(result_f32.ceil()) as u64,
+            RoundingMode::RMM => f32::to_bits(result_f32.round()) as u64,
             _ => {
                 self.error(&format!(
                     "Unsupported operation in FPU `{:?}`",
@@ -461,13 +461,13 @@ impl RiscFpCoprocessor {
     fn comparator(&mut self) {
         let input1 = self.state.read_data_1;
         let input2 = self.state.read_data_2;
-        let input1_f64 = f64::from_bits(input1);
-        let input2_f64 = f64::from_bits(input2);
+        let input1_f32 = f32::from_bits(input1 as u32);
+        let input2_f32 = f32::from_bits(input2 as u32);
 
         self.state.comparator_result = match self.signals.fpu_alu_op {
-            FpuAluOp::MultiplicationOrEqual => (input1_f64 == input2_f64) as u64,
-            FpuAluOp::Slt => (input1_f64 < input2_f64) as u64,
-            FpuAluOp::Sle => (input1_f64 <= input2_f64) as u64,
+            FpuAluOp::MultiplicationOrEqual => (input1_f32 == input2_f32) as u64,
+            FpuAluOp::Slt => (input1_f32 < input2_f32) as u64,
+            FpuAluOp::Sle => (input1_f32 <= input2_f32) as u64,
             FpuAluOp::Addition | FpuAluOp::Subtraction | FpuAluOp::Division => 0, // No operation
             _ => {
                 self.error(&format!(
@@ -524,10 +524,10 @@ impl RiscFpCoprocessor {
     fn set_data_writeback(&mut self) {
         self.state.data_writeback = match self.signals.data_src {
             DataSrc::MainProcessorUnit => match self.state.rs2 {
-                0 => f64::to_bits(self.data as i32 as f64),
-                1 => f64::to_bits(self.data as u32 as f64),
-                2 => f64::to_bits(self.data as i64 as f64),
-                3 => f64::to_bits(self.data as f64),
+                0 => f32::to_bits(self.data as i32 as f32) as u64,
+                1 => f32::to_bits(self.data as u32 as f32) as u64,
+                2 => f32::to_bits(self.data as i64 as f32) as u64,
+                3 => f32::to_bits(self.data as f32) as u64,
                 _ => {
                     self.error(&format!(
                         "Unsupported Register Width `{:?}`",
@@ -537,7 +537,7 @@ impl RiscFpCoprocessor {
                 }
             },
             DataSrc::FloatingPointUnitRS1 => {
-                let data_unrounded = f64::from_bits(self.data);
+                let data_unrounded = f32::from_bits(self.data as u32);
                 let data_rounded = match self.signals.round_mode {
                     RoundingMode::RNE => {
                         if (data_unrounded.ceil() - data_unrounded).abs()
@@ -567,12 +567,12 @@ impl RiscFpCoprocessor {
 
                 match self.state.rs2 {
                     0 => {
-                        if (data_rounded <= (-(2_i32.pow(31))).into())
-                            | (data_rounded == f64::NEG_INFINITY)
+                        if (data_rounded <= ((-(2_i32.pow(31)))) as f32)
+                            | (data_rounded == f32::NEG_INFINITY)
                         {
                             -(2_i32.pow(31)) as u64
-                        } else if (data_rounded >= (2_i32.pow(31) - 1).into())
-                            | (data_rounded == f64::INFINITY)
+                        } else if (data_rounded >= ((2_i32.pow(31) - 1)) as f32)
+                            | (data_rounded == f32::INFINITY)
                             | (data_rounded.is_nan())
                         {
                             (2_i32.pow(31) - 1) as u64
@@ -581,10 +581,10 @@ impl RiscFpCoprocessor {
                         }
                     }
                     1 => {
-                        if (data_rounded <= 0.0) | (data_rounded == f64::NEG_INFINITY) {
+                        if (data_rounded <= 0.0) | (data_rounded == f32::NEG_INFINITY) {
                             0
-                        } else if (data_rounded >= (2_u32.pow(32) - 1).into())
-                            | (data_rounded == f64::INFINITY)
+                        } else if (data_rounded >= ((2_u32.pow(32) - 1)) as f32)
+                            | (data_rounded == f32::INFINITY)
                             | (data_rounded.is_nan())
                         {
                             (2_u32.pow(32) - 1) as u64
@@ -593,12 +593,12 @@ impl RiscFpCoprocessor {
                         }
                     }
                     2 => {
-                        if (data_rounded <= (-(2_i64.pow(63))) as f64)
-                            | (data_rounded == f64::NEG_INFINITY)
+                        if (data_rounded <= (-(2_i64.pow(63))) as f32)
+                            | (data_rounded == f32::NEG_INFINITY)
                         {
                             -(2_i64.pow(63)) as u64
-                        } else if (data_rounded >= (2_i64.pow(63) - 1) as f64)
-                            | (data_rounded == f64::INFINITY)
+                        } else if (data_rounded >= (2_i64.pow(63) - 1) as f32)
+                            | (data_rounded == f32::INFINITY)
                             | (data_rounded.is_nan())
                         {
                             (2_i64.pow(63) - 1) as u64
@@ -607,10 +607,10 @@ impl RiscFpCoprocessor {
                         }
                     }
                     3 => {
-                        if (data_rounded <= 0.0) | (data_rounded == f64::NEG_INFINITY) {
+                        if (data_rounded <= 0.0) | (data_rounded == f32::NEG_INFINITY) {
                             0
-                        } else if (data_rounded >= (2_u64.pow(64) - 1) as f64)
-                            | (data_rounded == f64::INFINITY)
+                        } else if (data_rounded >= (2_u64.pow(64) - 1) as f32)
+                            | (data_rounded == f32::INFINITY)
                             | (data_rounded.is_nan())
                         {
                             2_u64.pow(64) - 1

From 918a83142d9461183ce221e6caba056b2c6cb2f7 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Thu, 28 Mar 2024 20:22:42 -0400
Subject: [PATCH 21/48] Add an imm_input field for displaying the part of the
 instruction imm is extracted from in the visual datapath

---
 src/emulation_core/riscv/datapath.rs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 8f7325d03..dd65a7af9 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -165,6 +165,8 @@ pub struct RiscDatapathState {
 
     /// *Data line.* The data that will be written to memory.
     pub write_data: u64,
+
+    pub imm_input: u64,
 }
 
 /// The possible stages the datapath could be in during execution.
@@ -522,6 +524,9 @@ impl RiscDatapath {
                 self.state.rd = r.rd as u32;
             }
         }
+
+        // Extract the first 20 bits from the instruction for the imm decoding input
+        self.state.imm_input = ((self.state.instruction as u64) & (0xfffff << 12)) >> 12;
     }
 
     fn set_immediate(&mut self) {

From dc7adcf0b0acd30917b76079f28c52b84d60c864 Mon Sep 17 00:00:00 2001
From: Geetis <capiix1@gmail.com>
Date: Thu, 28 Mar 2024 20:35:31 -0400
Subject: [PATCH 22/48] Updated test cases to reflect branch instruction
 changes

---
 src/tests/parser/parser_assembler_main.rs | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/tests/parser/parser_assembler_main.rs b/src/tests/parser/parser_assembler_main.rs
index 824f3cde0..a38a24224 100644
--- a/src/tests/parser/parser_assembler_main.rs
+++ b/src/tests/parser/parser_assembler_main.rs
@@ -387,7 +387,7 @@ mod read_riscv_instructions_tests {
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00000000000100010000000011100011
+            0b00000000001000010000000011100011
         );
     }
 
@@ -399,7 +399,7 @@ mod read_riscv_instructions_tests {
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00000000000100010001000011100011
+            0b00000000001000010001000011100011
         );
     }
 
@@ -411,7 +411,7 @@ mod read_riscv_instructions_tests {
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00000000000100010100000011100011
+            0b00000000001000010100000011100011
         );
     }
 
@@ -423,7 +423,7 @@ mod read_riscv_instructions_tests {
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00000000000100010101000011100011
+            0b00000000001000010101000011100011
         );
     }
 
@@ -435,7 +435,7 @@ mod read_riscv_instructions_tests {
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00000000000100010110000011100011
+            0b00000000001000010110000011100011
         );
     }
 
@@ -447,7 +447,7 @@ mod read_riscv_instructions_tests {
 
         assert_eq!(
             instruction_list[0].binary,
-            0b00000000000100010111000011100011
+            0b00000000001000010111000011100011
         );
     }
 

From 05ea41441e40111175fa2d2581f5341cc1a474a2 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 20:38:14 -0400
Subject: [PATCH 23/48] Implemented Final Float Instructions.

---
 src/emulation_core/riscv/control_signals.rs |  6 +++
 src/emulation_core/riscv/coprocessor.rs     | 55 ++++++++++-----------
 src/emulation_core/riscv/datapath.rs        |  2 +-
 3 files changed, 34 insertions(+), 29 deletions(-)

diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index d0d400c82..33f426399 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -241,6 +241,12 @@ pub mod floating_point {
 
         /// Use data from the floating-point unit. Specifically, the Classify Mask.
         FloatingPointUnitMask = 3,
+
+        /// Use the un-altered bits from the floating-point unit.
+        FloatingPointBits = 4,
+
+        /// Use the un-altered bits from the main unit.
+        MainProcessorBits = 5,
     }
 
     /// Determines whether to write to the `Data` register in the floating-point unit.
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index eac2e52fb..3e70fc4fa 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -253,9 +253,15 @@ impl RiscFpCoprocessor {
                     }
                     28 => {
                         self.signals.data_write = DataWrite::YesWrite;
-                        self.signals.data_src = DataSrc::FloatingPointUnitMask;
                         self.signals.fpu_reg_write = FpuRegWrite::NoWrite;
-                        self.signals.fpu_alu_op = FpuAluOp::Class;
+                        match r.funct3 {
+                            0 => self.signals.data_src = DataSrc::FloatingPointBits,
+                            1 => {
+                                self.signals.fpu_alu_op = FpuAluOp::Class;
+                                self.signals.data_src = DataSrc::FloatingPointUnitMask;
+                            }
+                            _ => self.error("Unsupported Instruction!"),
+                        }
                     }
                     _ => self.error("Unsupported Instruction!"),
                 }
@@ -371,35 +377,26 @@ impl RiscFpCoprocessor {
                 if input1_f32.is_sign_negative() {
                     if input1_f32.is_infinite() {
                         input_mask = 0b1;
-                    }
-                    else if input1_f32.is_normal() {
+                    } else if input1_f32.is_normal() {
                         input_mask = 0b10;
-                    }
-                    else if input1_f32.is_subnormal() {
+                    } else if input1_f32.is_subnormal() {
                         input_mask = 0b100;
-                    }
-                    else {
+                    } else {
                         input_mask = 0b1000;
                     }
-                }
-                else if input1_f32.is_sign_positive() {
+                } else if input1_f32.is_sign_positive() {
                     if input1_f32.is_infinite() {
                         input_mask = 0b10000000;
-                    }
-                    else if input1_f32.is_normal() {
+                    } else if input1_f32.is_normal() {
                         input_mask = 0b1000000;
-                    }
-                    else if input1_f32.is_subnormal() {
+                    } else if input1_f32.is_subnormal() {
                         input_mask = 0b100000;
-                    }
-                    else {
+                    } else {
                         input_mask = 0b10000;
                     }
-                }
-                else if input1_f32.is_nan() {
+                } else if input1_f32.is_nan() {
                     input_mask = 0b100000000;
-                }
-                else {
+                } else {
                     input_mask = 0b1000000000;
                 }
                 0.0
@@ -459,10 +456,10 @@ impl RiscFpCoprocessor {
 
     /// Perform a comparison.
     fn comparator(&mut self) {
-        let input1 = self.state.read_data_1;
-        let input2 = self.state.read_data_2;
-        let input1_f32 = f32::from_bits(input1 as u32);
-        let input2_f32 = f32::from_bits(input2 as u32);
+        let input1 = self.state.read_data_1 as u32;
+        let input2 = self.state.read_data_2 as u32;
+        let input1_f32 = f32::from_bits(input1);
+        let input2_f32 = f32::from_bits(input2);
 
         self.state.comparator_result = match self.signals.fpu_alu_op {
             FpuAluOp::MultiplicationOrEqual => (input1_f32 == input2_f32) as u64,
@@ -490,7 +487,8 @@ impl RiscFpCoprocessor {
             DataSrc::FloatingPointUnitRS1 => self.state.read_data_1,
             DataSrc::FloatingPointUnitComp => self.state.comparator_result,
             DataSrc::FloatingPointUnitMask => self.state.alu_result,
-            DataSrc::MainProcessorUnit => self.state.data_from_main_processor,
+            DataSrc::FloatingPointBits => self.state.read_data_1 as u32 as i64 as u64,
+            _ => self.state.data_from_main_processor,
         };
     }
 
@@ -567,11 +565,11 @@ impl RiscFpCoprocessor {
 
                 match self.state.rs2 {
                     0 => {
-                        if (data_rounded <= ((-(2_i32.pow(31)))) as f32)
+                        if (data_rounded <= (-(2_i32.pow(31))) as f32)
                             | (data_rounded == f32::NEG_INFINITY)
                         {
                             -(2_i32.pow(31)) as u64
-                        } else if (data_rounded >= ((2_i32.pow(31) - 1)) as f32)
+                        } else if (data_rounded >= (2_i32.pow(31) - 1) as f32)
                             | (data_rounded == f32::INFINITY)
                             | (data_rounded.is_nan())
                         {
@@ -583,7 +581,7 @@ impl RiscFpCoprocessor {
                     1 => {
                         if (data_rounded <= 0.0) | (data_rounded == f32::NEG_INFINITY) {
                             0
-                        } else if (data_rounded >= ((2_u32.pow(32) - 1)) as f32)
+                        } else if (data_rounded >= (2_u32.pow(32) - 1) as f32)
                             | (data_rounded == f32::INFINITY)
                             | (data_rounded.is_nan())
                         {
@@ -627,6 +625,7 @@ impl RiscFpCoprocessor {
                     }
                 }
             }
+            DataSrc::MainProcessorBits => self.data as u32 as u64,
             _ => self.data,
         }
     }
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 8a6bac23d..c740029ce 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -624,7 +624,7 @@ impl RiscDatapath {
             match r.funct7 >> 2 {
                 20 => self.signals.reg_write_en = RegWriteEn::YesWrite,
                 24 => self.signals.reg_write_en = RegWriteEn::YesWrite,
-                28 => self.signals.reg_write_en = RegWriteEn:: YesWrite,
+                28 => self.signals.reg_write_en = RegWriteEn::YesWrite,
                 _ => self.signals.reg_write_en = RegWriteEn::NoWrite,
             }
         }

From 23821d2e1dd45b50fe346cb6ba7d10f40de5d768 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 20:42:38 -0400
Subject: [PATCH 24/48] Removed pointless functions and control signals.
 Notable FPU branching logic which doesn't exist in RISC-V.

---
 src/emulation_core/riscv/control_signals.rs | 28 -----------
 src/emulation_core/riscv/coprocessor.rs     | 53 ---------------------
 src/emulation_core/riscv/datapath.rs        |  4 --
 3 files changed, 85 deletions(-)

diff --git a/src/emulation_core/riscv/control_signals.rs b/src/emulation_core/riscv/control_signals.rs
index 33f426399..3908a5bcf 100644
--- a/src/emulation_core/riscv/control_signals.rs
+++ b/src/emulation_core/riscv/control_signals.rs
@@ -213,11 +213,9 @@ pub mod floating_point {
         pub data_src: DataSrc,
         pub data_write: DataWrite,
         pub fpu_alu_op: FpuAluOp,
-        pub fpu_branch: FpuBranch,
         pub fpu_mem_to_reg: FpuMemToReg,
         pub fpu_reg_dst: FpuRegDst,
         pub fpu_reg_write: FpuRegWrite,
-        pub fpu_take_branch: FpuTakeBranch,
     }
 
     /// Determines the source of the `Data` register in the floating-point unit.
@@ -383,21 +381,6 @@ pub mod floating_point {
         DRM = 7,
     }
 
-    /// Determines if the floating-point unit should consider branching, based on the
-    /// contents of the condition code register.
-    ///
-    /// This directly overrides any branch decisions decided by the main processing unit.
-    /// The [`Branch`](super::Branch) control signal should not be set in addition to this signal.
-    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
-    pub enum FpuBranch {
-        /// Do not consider branching.
-        #[default]
-        NoBranch = 0,
-
-        /// Consider branching.
-        YesBranch = 1,
-    }
-
     /// Determines, given that [`FpuRegWrite`] is set, what the source of a floating-point
     /// register's new data will be.
     ///
@@ -437,15 +420,4 @@ pub mod floating_point {
         /// Write to the floating-point register file.
         YesWrite = 1,
     }
-
-    /// After checking the [`FpuBranch`] and condition code, this signal determines whether
-    /// to follow through with a branch.
-    ///
-    /// This signal is what is sent to the main processor.
-    #[derive(Clone, Default, PartialEq, Serialize, Deserialize, Debug)]
-    pub enum FpuTakeBranch {
-        #[default]
-        NoBranch = 0,
-        YesBranch = 1,
-    }
 }
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 3e70fc4fa..6d73cf351 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -79,15 +79,12 @@ impl RiscFpCoprocessor {
     pub fn stage_execute(&mut self) {
         self.alu();
         self.comparator();
-        self.write_condition_code();
         self.write_fp_register_to_memory();
-        self.set_condition_code_line();
     }
 
     pub fn stage_memory(&mut self) {
         self.write_data();
         self.set_data_writeback();
-        self.set_fpu_branch();
     }
 
     pub fn stage_writeback(&mut self) {
@@ -208,7 +205,6 @@ impl RiscFpCoprocessor {
             Instruction::RType(r) => {
                 self.signals = FpuControlSignals {
                     data_write: DataWrite::NoWrite,
-                    fpu_branch: FpuBranch::NoBranch,
                     fpu_mem_to_reg: FpuMemToReg::UseDataWrite,
                     fpu_reg_dst: FpuRegDst::Reg3,
                     fpu_reg_write: FpuRegWrite::YesWrite,
@@ -279,7 +275,6 @@ impl RiscFpCoprocessor {
             Instruction::IType(_i) => {
                 self.signals = FpuControlSignals {
                     data_write: DataWrite::NoWrite,
-                    fpu_branch: FpuBranch::NoBranch,
                     fpu_mem_to_reg: FpuMemToReg::UseMemory,
                     fpu_reg_dst: FpuRegDst::Reg3,
                     fpu_reg_write: FpuRegWrite::YesWrite,
@@ -289,7 +284,6 @@ impl RiscFpCoprocessor {
             Instruction::SType(_s) => {
                 self.signals = FpuControlSignals {
                     data_write: DataWrite::NoWrite,
-                    fpu_branch: FpuBranch::NoBranch,
                     fpu_reg_write: FpuRegWrite::NoWrite,
                     ..Default::default()
                 }
@@ -297,7 +291,6 @@ impl RiscFpCoprocessor {
             Instruction::R4Type(r4) => {
                 self.signals = FpuControlSignals {
                     data_write: DataWrite::NoWrite,
-                    fpu_branch: FpuBranch::NoBranch,
                     fpu_mem_to_reg: FpuMemToReg::UseDataWrite,
                     fpu_reg_dst: FpuRegDst::Reg3,
                     fpu_reg_write: FpuRegWrite::YesWrite,
@@ -492,13 +485,6 @@ impl RiscFpCoprocessor {
         };
     }
 
-    /// Set the condition code (CC) register based on the result from the comparator.
-    fn write_condition_code(&mut self) {
-        // if let CcWrite::YesWrite = self.signals.cc_write {
-        self.condition_code = self.state.comparator_result;
-        // }
-    }
-
     /// Set the data line that goes from `Read Data 1` to the multiplexer in the main processor
     /// controlled by [`MemWriteSrc`](super::control_signals::MemWriteSrc).
     fn write_fp_register_to_memory(&mut self) {
@@ -506,17 +492,6 @@ impl RiscFpCoprocessor {
     }
 
     // ======================= Memory (MEM) =======================
-    /// Set the data line that goes out of the condition code register file.
-    fn set_condition_code_line(&mut self) {
-        let selected_register_data = self.condition_code;
-
-        // This only considers one bit of the selected condition code register.
-        self.state.condition_code_bit = match selected_register_data % 2 {
-            0 => 0,
-            _ => 1,
-        };
-    }
-
     /// Set the data line between the multiplexer after the `Data` register and the
     /// multiplexer in the main processor controlled by the [`DataWrite`] control signal.
     fn set_data_writeback(&mut self) {
@@ -630,34 +605,6 @@ impl RiscFpCoprocessor {
         }
     }
 
-    /// Simulate the logic between `self.state.condition_code_bit` and the FPU branch
-    /// AND gate.
-    fn set_fpu_branch(&mut self) {
-        // Invert the condition code. (In this case, instead of using a bitwise NOT, this
-        // will invert only the last digit and leave the rest as 0.)
-        self.state.condition_code_bit_inverted = match self.state.condition_code_bit % 2 {
-            0 => 1,
-            _ => 0,
-        };
-
-        // Run the multiplexer.
-        self.state.condition_code_mux = match self.state.branch_flag {
-            // 0 - Use inverted condition code.
-            false => self.state.condition_code_bit_inverted,
-            // 1 - Use condition code value as-is.
-            true => self.state.condition_code_bit,
-        };
-
-        // Set the result of the AND gate.
-        self.signals.fpu_take_branch = if self.signals.fpu_branch == FpuBranch::YesBranch
-            && self.state.condition_code_mux == 1
-        {
-            FpuTakeBranch::YesBranch
-        } else {
-            FpuTakeBranch::NoBranch
-        };
-    }
-
     // ====================== Writeback (WB) ======================
     /// Write data to the floating-point register file.
     fn register_write(&mut self) {
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index c740029ce..da08d1d2d 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -1073,10 +1073,6 @@ impl RiscDatapath {
         if let CpuBranch::YesBranch = self.datapath_signals.cpu_branch {
             self.datapath_signals.general_branch = GeneralBranch::YesBranch;
         }
-
-        if let FpuTakeBranch::YesBranch = self.coprocessor.signals.fpu_take_branch {
-            self.datapath_signals.general_branch = GeneralBranch::YesBranch;
-        }
     }
 
     fn pick_pc_plus_4_or_relative_branch_addr_mux1(&mut self) {

From 30b4886e63498bc3ea5692ee8a83b0c1e2e1dcf2 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Thu, 28 Mar 2024 21:20:13 -0400
Subject: [PATCH 25/48] Add RISC-V datapath drawio/svg files

---
 media/datapath-riscv.drawio | 1110 +++++++++++++++++++++++++++++++++++
 static/datapath_riscv.svg   |    4 +
 2 files changed, 1114 insertions(+)
 create mode 100644 media/datapath-riscv.drawio
 create mode 100644 static/datapath_riscv.svg

diff --git a/media/datapath-riscv.drawio b/media/datapath-riscv.drawio
new file mode 100644
index 000000000..edf78be1f
--- /dev/null
+++ b/media/datapath-riscv.drawio
@@ -0,0 +1,1110 @@
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color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;"><div style="font-size: 9px;"><font style="font-size: 9px;">Instruction [31-25] (funct7)</font></div></div></div></div></foreignObject><image x="318.5" y="845" width="103" height="13.25" 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KNJS6OyO/RNiN1e5R15ppWHhP5vM/q4eI+yKQR8ZvUE8cYAkhqv8YTxHrxRn1m9n6bb9rjizdorgqxLWSDjpgw9hVEaDC1BpZ45iUSiNJHzHUjys3f5uPe9g1H9I1EqdNKy6EO6RvU/QKx30pYu++5+ggnY+GWA/EWhqrjXqs/Un9By0FByGMmnEqIoit6vpPVJk8kGZfJRyjksAls934jid3BvdKd+5ok94lZxi8uxWzBobrEOQ2KacI409cr8fm+wDFMqeMCOqmWTraSWb6uGLKrvSbAtlBc6LjPuAViCBhspusctGhgbDpZJRaLj020/6h5jERqR1zUjzpkLoHou4+ui1uuPqYSiOIAXakG6OT+1H6WOhGkEoigcIgmyiFbC186gBKB4IlJn8/kHGex/Ba0c6zb9tXjzDVLfwdymM8jyGYDgZVtefsT7Bk+1GZs0Sba+A11EHQMhdgWigsbJxA7PqkmNQ4YFJxOj642DLUzt2BEHTKXQAzZE9Lmm6uPqQRiLpElHT9IuVxtj30fKHhGFOXIarH08RLUF6HoXPdEDPHBobJgLoh123CBCGyTChERZUwDxKg0P8Qer22gkM8HLDbFdgg0V4U8uQhlNOoVxBCnRxzeOIBTIFaDCDgoG/CqpWAs1AfNA8CBKgaLog4pDQArAxYIMuW1EZNurj6mEIjo5CMkYMTyqcOrD/HfLu5qZ+yEE7s+KVvk0ZitUzIeQxOBuO32gP9CvyEtL2m7tC7fcmAu8L2N9DpRrkHzTUiuRAWi9O361OMLealPulVDasSQcpuUqygQK0uLBi362rivE9lVAzPg396aqWuST/e47pPLIdFAHBrUmv3O1ccUAjFn212+4vP71Ilg0aaY90H3AsYUOuiEwPVWZAqf7PODTfRVNC7FtLXPePLx95D7oNdK43bM8Zpjwohy8C2fcwyFThwpEAGBCAdiXw+qr1u86GJWFV9zfSlj6Fa5HBINxDFXwnL1EfYBwaONFCtKga4HXZ46EfgkTFcSy+kvOZJbaCKQGnzd3KTtbJZD4xIFoouy7MXClHEh5xvMLhro78ExJFq86mtDaFwYtUAMGahgUBAbAT19HnWe3vLm7bEtNbvos6IIOqTokVZn0gMfMYfYt33/XH1MIRBBX/W2TzRfbFWUMhEcSvQRN72D/iKOD1LGsZkhicAlnscw2ZRylJTbxPEF+qcEQ7wygklvHSdFR/TYsqhPonzQ+uPBWq0JbHtQ7EHiQtfb0hSIlf0gI6xLJNpHz5Lvv65LPK0zEIODLkhkhQ66tn3WyS1GIIwtdgZmw9ESDugvUHyQMIWYCY66QXwyJFmC3ILGmYSjpMwmji+Us4RDtDIUiEEoQdsGxR4kLlAg9psVNkK5xK3nO6LP7wW50+GL0W9J2qtBh/QO6lAgFnySCMGWq4/1zFj+NQlBMIW4mQbEXHlFGOcQbkPtgUSV47xF0F/g+ODiGrMvqE9SIA5bZwzjC/RPl7vF/b0gptU+GW1CF7roEeLzceHB+Tgo9lAg9lgPTLreRqg2u2+9YE6zPBHbkfrqkx59sbgeDTa+ATIX8y4uufqIJmPJIacgNwpEwUBzJQTQX7zjQy5RjSQCF5shvCC3UfjqJo4vlLNgSMQrQoEYxBK0bVDsQeICVxAjriC2q6pWFPVzWutt89z+3iAPklwsHKSjXUEEH+u7kICDLihxhQ66ldnwpZM/MH7zY1cfF7/3FfDS+tFysVfDcoiqnP7S1Z/YzBCfpEAc/woi+pY9OmaDygtzT2wfb7aZL6nILIjEBQrEhAKxWXW9qviYWVV81Pz/h2SmBEsBj2hzJUNwph40M1oRWRnPZwsddOtsO+hlouIpE0GzAbHvg9QXU5Tjx9zMH3GdYoD4JAXi+AWibeG6/FM06AWFkPb7+GTq+gVd9CoC5uOgPInEBQrETAKxUwDo+YPmYOjj5ndf9/Kqjosk56PZy0CH9F5do0DsNNKbuxf3zgzZHBUMPsE0ls911ZMrUMe+T+z6pIxTHGuEJIIQ/8kVS6QsJeXAuOQd/yRtQcog/hlzAoO0cags0n4fn0QOypZs9YnVb1c94BiiQOwDGuL0YFAIMoLLIZIJRuGXSFAB4st9nczBQReUBJDAJw1MUJ0Bn6BEfVVSHgnUPolg0QaEkeQ+iKiK+dUf5FN7pu+i2IT0RcKmz+45x5nE9yRlwLgUFBsk7ZGWQWwqXSyQ3jtGudRxAeET87OuoWzAMSQa/31tghht2reYfYWKhQUGhSAjxHGY4gn4RRfhXpCSB3CGnC/3dTIHB11QEkBYSgWiCaZ3xHtXzZmYu+dvPOnrdwtW1Rd7iv8p69H64/LP2exPShf/Vf1VfSA5dxMJQiHiBOEuuQ8o1G6acfGwL/PmdSlsncsGOcdZDNYeuSAoNsRqcxWzT96Q5oQxfUquMaETn/YgGa9ttsj4RV/s7LJjGX/M1i5zaOOn5e9VcaeY6y/Kv6rZ7+yfc71/27UdBBxDQdoEiQt8xNw/eoOMECsooCt9UvFBgbhqId8Zdyob5Qx2py+dvGx853mR3wrEKBKEfBJBI+FEPTYDfdQb48s/qP9IeeWyAZjcRiG2wInrKNpcC8QfGYH4kmicFmpv98L1bVnZPKVS+2TO8YuMW5cYBcdQkDZBbECBGCAQrYPMVPFntgrzsfIHy6pm6i4zo7iv/Lsu7jEzirulHzLvawoya6RAPKCIDOBq8qfOXr1w/QoaKiFxVTmLcw+iLYYGuxA/Q1awJCsTSBDy5Y5OcqT3QR6DSW055FPY+C4+371445jER3PZAExuoxBbmyoQkTeZ7fm4X5rNjktW/Nv+ZHyyFKKuJwqS1bFm3al9En2T2UT9l42I/qFkPK0wurT9jvjMY8ekGhxDFIh9BvN91FkmE+yzb4NGQB5thSYRqN1C8YEmV1/uUNuFe6uQwQzZSbh/cyVQ7Gx/ZicC4nYBNoLEiueKAZJ0bB8lvpA6ESxYI/aVCkREsFWH1M9PuB4h9fkGOolBYkkuG4DJTeQ/4rHkWRCMS6No86KryGQO8ZeWkPuN+bfotA3X6lhOgVjnNXHb7eNh6YQrJO67Yg84higQN0Agip0wZCZXObx83wkyI0KSq0QUdNkMDMRBjt95f2CfJRLolgIFm3RUlwECEbO9rVp9562L13+J5E3sHrLHVrnECeLDriC9YAYGa5Njik/MSs3j6EpNudqxP78pnVygcSSXDVBevrEE8WlXWTAujUogIk8sfL6yBU9agFW4HD65WP10+cDy9x4LA9A9BCIUHENBeRKxAR8x93vRoBHQx3/mNl4b2u3qTqFme+bFgbskDo88ZkSSq4/wKMUtJqCCHL9HIIo3RVfXyx85QEGi2ThAIKKre2hCQP1YKrKgIOQRoJcCHZgASNter0JAfoOKRK9vtwN+g/YBYdMeZ2ByG4XYAuPSKNq84F77zsfinABOYJAVypSTlpBTAk6jT3WAuI/mZMmCADiGgvIkFJv5FnOv7HIaAXfC4pYRcOekj6NKp9H6ZekKg+mJs83N3iICUeLko1xBRPaJ2MU988hwptQ/Xj1//Sd9nlGt/Oy/aALYsxLRvlIGTvTICnLdh0Kdc+2ntALXvIJ3TppoEP+CghDot74+jIggfBWl5P5JodWLrhVcj3FtK4cfhSE2QNhQIHqN+qgXoQLX+o/ZO/zSUEyo9+/93DRU9Gi57BAcy7aRiReUzw7HhWoPJQRdMFEt40Kh/1mak6UCmgJxwFKIUAl5PAEOKqdzgkZtEFB7NtlqXfxnO5mUdaria2bg2eMzwAO05atf6ApD2XgzgLaU+ql9lFYl0OIvyi/DmFf8+45Yic0cGvCmMLpCdlC/2jP9+8CIxfcWjw6r4DB/3IA4IQ0Qne0Fgyo8Yz246S2TFN6ez/d/v5iUNL7oY78TDvkXIiJAu1vn2tN6/zXbTtvG2WzrL834eNT41zEz5h/oszsSO5D2l+MDnFy0fScW9yoP+2wdkCdjlE3THmgcDInh6Pjv9RvsycaoVhBtn9BVxAaHmyYm/Golrs2Kb5rzWJ6E4poRnVtbs4eQrRW54oLtL7ISuuRTHlmj3mjmZst6rvUTdTyycVP+I4z14BhyapOhBiITRz5i7icpMoKBLd6LKPcqr5Ki9jZrjtj23nuDAQHug4QU9qKHpMbAMsKgcchWyDE0gc3ruRzaIoHsk3I1d0hQpBSI3knG1SH499jEb1E9kggoEIeNMgZR226h/+QXdsDOC3x8JldcKMduuYihfxGntx61AAKaAnGALxLkQwZqCrHitZfIw9eGLvF9kzLiYB21QATt7mWdxnEQ7lU5D4FoG4W9TOLVjc6L0P11sYPzOgXi2se34MzJPktTIPaPATQmhOSdeCNxtSb/Ve7AVnn6ZUzRJrGJ9z7xQDzwXnD75LDQbwhvG7SQgsQFriD2W0RshIDlfqE/DBfzefxUJfFvPWxOe/8wtBF2MLx14cZXuuoBA7GYOdJm9G1RpG5bdiGg9ufzd80/kwnEdYhENNA12Xns0e0WqAOPV5HJpc+Kh23Q2kSiZxJeQEQSgS8bey9w9WMUj2vBuDSKNvdPBLA9ymh8Wy0vO8mgt73wCyTdNUnz3npEIrbqD46hoDyJxAUKxAgCcV1JRPJChSsYxFqV6pvNgYE4yPGH+mpnroXSu8ALGS505e+bq2vigee5gniQ+PMkhBBxWItZfKN4B/Uh8ZJDIC7Gt5kAYBv4RR7UVwhLMF21iP3RXEyBOGwsyWpVkLkDL44Vx93NCBOHueJCux95RSI+dikQBzwPCfIhAzW1WClXqvR8R3y6uns09paQvjHpukXACxCHqu775Fhq5q7+NX+fQCTeMv0+tdikLU7IgQKxDLJmT6J5w/1MbMHb4HWobwjnQ8yR70n33GToyy1I7AgRQUtxnph7rHFdJWK+pNLnt2BcGvUK4tI3wRdv4DEdIW4t7un1AkmrwZIvOjUv8To9AIFk9hzqQn3fdY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ded8ziQgrHv8zyPwO9hiLRknUZs+dOjz6KyIoEBpAoq8KJE5jaO+KsNV9rnvxA+40ERW1OkKNIFPTWCYjFxRTGbqM/4HwAHROqYrNLYK4CMGvMvdGbEwdB2cfG2ldSLkDEOtnSR3DzYGg83SnT8iyaEEcVRFNezGZZeYxtGJJvGbD8SNqHFK+R1wFHeVH9RfTDwo6SsF4u8M+mmnNVN1wQ5RKZ39UuEkPjtkoSJ40HegK/kCzo7/WpXPu/NIvMdWjgFpuFNY+v/DLok6MXMUsf+bSTp/P0E8rEbyBsWyLT2brhj9MkikdwlgdPQDFERnlB/UySwKzfmrFPxMyzxnxLHke0xzXZnHJx5u65K/et6kfYI/4Y0S1tAtNvEqSMB1vMXRxlLqFvmiH9VsxdlW32J5ydrj+cxIcn9IPieLBhe5b5h12kLyniN2SsxP2qK1WNqVQeUB+jZUlmp9YdzOf7k+Wy+gfjqluLXUi9FptjjLgVCUzFnQqD88zv6nxisbgbSQweduzVF2Yhgyad/BvlnOG2hfmm1KEhgYFOnv5daMHu/6rJymCpk5fulMQL569c35Qf7TcSFLU5QY4iQQCeNBDoGnRAx0DHhKrYrBKY3mCX1n4fCVqgDidMqIh1MjIoG+qfD9hcAuOM1FZBrCIKi9ks24ixDSExz1w85a9yuCFUbr1IbW3USJ/z5bxNLAv7dBb9bS1IEbmGyqYPRDtayyA74Pu0qLJtEJy5dOrlhAlu1z/zhD8xA/rkqEUM/DqwcBSWJxueTnkCSNi0qtgDT576aGi+a5M2KmF6HoJiiATxU5/s8JyNkCXrYQcgfkPGMbX/aK67ENuA+GNEt9C5oF2vIMx9WY3NQfqNyuPKQ7bZ+/DCLJ7TvqkUkM9dCbe4N2btLo4Hl/Ndk7xc9mHUj9OI+1ULB40pojPI3F7WGyXLNvn+1LmsvnHxNmRRmLOpNuvnGiPOPoEJX7QtnGnembokmLt3Bv+T2rGHJEASAwrjEWp+8/eEJzD1Y3v41Uq030hQ1AYEOYqIoNe3q2cEDmv96lxwoTZloIS0jQanh8cYvOAfwy2eU9JqxTq51MdcjrS2VeXJ1Lt/Ug5d5cRslg/H2IaQnHAgoPzyba7xbfYvxUZgs76IhUIIe9fv0QshX+lYi1rfVhWUGvODlK/C5/Mv5gkXXP7RXVPyM+HgqBcx+frQlDzddQ5CHnAxyd1jOW2bVGDEj6d8bbsjjhs+rXqoQ3ViXtrPVbnxbIROvm6fCX+IQ4RltZZZmOIzUtuA6CyiW0iMqPkQnwjIYCH5eCL9Vsglts1j+HBkPRwVD7pY2b8l9deyfE2XjJWPn2JMDj0CxrniMUVlwxOKet+6Tb4f3jBDwXeUT3GPfj7G8THirBOY1ti70p4MaI2wIrk0hoHu0ltpYgBN5MFzJFEC002sl9zrBeLXKTflPOwY0H4jQVFH4Pu2+zfZa2oKHVu1l89w9I96+9X8jr47Vcz2Z/ITmOMtNtoM9U7c1yQOXpw++o+b6OeeaOyzBUei1luFxGyWz8XYhpB86Gvk7rTmxqt3ofprXciz+OzxS9FvM/h6J/KrUSckJpLZ0UqzMMrvX8we8Dq9ymbk70NT6+NstGTuxpQRLBxVjGNk6noWSrZExE9DckuSve3nQ7FRV3vjxxPxtiG7//BvnizMv0pjEMQfI7olTWCOP4YHmiRNQCD9Vsxnkd0Y0x/GJDHF8aCzPcXCXKfNQbjXeE+MuZEv7letAKIxRXVFlejXb9JfAeILtCut8nG+P7tN7emdNG/UByd/fBUXI842genvHxpDOVEj417RcV8KLT4XORu0jweNDprIgwVJkMD0J3dcuzdoX210rxDc1H6FAO03EhS1GUGOQhmA5zcc3SPvDZ67XuGWvlc0pgyUkLalwWnU2MKTJ/SA3kkCOnm1+fXEkET63+MXUvq2N58E2FQPxtiGkMyKhXPQ5jfbhBOkIYFlv0Mytqscc+FzqDtK+7xc1L6j9WEyrEOl4ubXFKcBAn2GdQg+zRwPPck9iCnE6KrD2bnZ33/p5Ub8eI4TmJqElPY+uynWC9rYx4+Nwj+p1Hn5ldrrJA8j/hjRLSmnSezMEkwoHl/xQ/otYd4qE7TNy9fG98b0h1I2ETH+Nfes7KBKq5GYNzwV41M9Asa5wTHVyKFZt2o2hiaZk8pYcYq5sTl2unXlNsSIM05gaqaP4hnghMtUWfSWMg6+xoIm8mBiCRKYcJubD3SemkH7jQRFEQ5QteARnKSIRBh8vPdk0pSBEtK2NDhtktA43yBJtABgjzZlPyU/FYzKpCg/RQDXJyYY2GVNYC4DTfEpZmThPGmgpAzuVDv2Cn0cegQNoDUJkMQiV9VJT+e020Z9ZQ7ZO+qEFlQTJepr7oV5JNXdUinZBu+/NOaxlNcPaGVH/HjqBKb+Awr4InCSRbYbFG1iZw62uEunkFgd0S3JPF7eyfymVtfTPBfWPaTfCpmCtnmKRP2yH0HZotZvClhL5/zM7rnLZ7WPa54D41yY25BM6o+ButPYuxeu3Ij0d9t8PzguCApx2a5DX0MPb0uMuI0JTLcrUn0h6vXV8exq17Ao71Z9GQ6YQNAHGPxX0wq7574c/dvS7r/bPkpeKYgp/q4o7X3IRx38l1SHJnx2xZs8gdl98gTtNxIURTlAcGGvT0IYp2vFG+6OtFdXpyeXX8W9a3mSGdpJ7AvupgyUkLYlwWlzXPVOseZelvu/O7BH/ovxOyru2sREtJP09mphXrZl8ZvVR3jW+mPtI5CNWoJFT7eLvTFYEGUTYxskokF+xFUolQftZ3UKxhR7xprXVwkZH4i6D1fdY21xJ/oGhGa8VYv8Dl313Gufau9ysp8ET4JAwbxG5ibrxcK8cWCjXeyyKL4ExwHLRIXmvln9YrPLx+jlb80V8RioTr8O2bfCnnSyyP0jEDNK7EGKMpKTc+giJoVcXXUgfjwmgentQZ1MKD5ty/LzLuN/CzTODeHRTQ40Hl021b22UdmHcNLrUFzrvq7tGD2Ej3tWuyD2f15uRLckMSKyqb228YX5j7Is/rP9McN6jhZ/r4nHQ74V6Tc+vsOvG+tOah3WGb3/xt5GQOMkBS9ntsZ9fXyp+8ghBrG/bfff67G/w9b/u+vnF90Hm9xHKSsfiv8BXx/fNt8P+4Ge2HYd3xbF32jsB7rZvS0x4vYkMAVf7NWejJAEJ5IAcT17wUmJn7jDDDY6iaQL5nQBkNzu9QXhY/URdhRgAhMJmCoH4l/Ht+VDobtWFB+eEjs4JHiSBI192pCrHY1TrLmbx0Nf3K700tonkASg5gSFNiirg27zbGi3GNXLeuFoRt+F7lkwI4EdtGCSW66DkuhYSRIPircDrrp6/2noa56K00pim+FpqE63CHRK88VfqV1C/cxy1IOsK79y6fTTzlY8nDX5qrgfVWLrKua2vKi9L8x1X6w7sC0S+GC/geUS998XsxfUqbEN2mdCMeTMTsSLT6BreSR+Tqybq3aRTSrpx7nQRJHUpnmZc8ZAqNztsUPWI6ljxNCp5gNZzd7Owjwq/To2Ho8rEtJPnhLPM0RXmuOD+nCxLynLn7t2bpfMYzReRuMviQzNMlPZ2tz9QjmEyqPjVq+9wY+rCvx0Tt+PySuf43C8L+Cw9l1bFCNuRQLTGwR3L9/dEuegew0inBAEnDAc7KwWL24749HQpF8tiJxTv0NYtj6ZIv8aqHoBDzCSit4u1/tq81h9rI0o8LouYDg0wYB0Xni5oSS8Ky8NalIHjX3KkasdVG8Re9RYHIBfMpQ7M1gnl4DRi9CDd6wdGjisD1qjEHoOmq+uMmTBFGq763dUHsk8RBbM/g0G9zXdUxLZ0U1ByWZgI1ACL2EP++lmn0B9FfltdOwQ1isbXRi7K06kVR2Wc0HlR20dHFgfDJiIP+ojETbIXazI1Q6SeRZbJqjryqtJYuXqsX/ixEqO9pE6ax9ZngxtEG/aHflH1HAfLK/byST+SFnuGCjCLkD+OGWMKF1TaBIxaDyusTcpWfTH5PKEksKXyOMDwcbmQdwBrN8QY7EqC8iiqX5gfQRt1KdsW1MXfCrwon+zbQFc5yCPi3L4/uVr9e8J2Yht9VqPL516GdgwFsVXvu5tihFnn8DMHUBUyiBIMolfGxPUlcIASU7lrNqROuJVee0CHg2CNjisj07v/7L/aoB+gzRWH+EJDugDslujDZqwMZIlOsYIlJbcxQsfSdLH14mePECDsJWOazZWkNdQUKfj5cofQMhPVQmdvKoYykZr/6TCofKEdBm5/kBzOgC71kJmM+BEFGBHm3Pur2Up/tBOaL6hPgZNXq7kRjeaQtfKHNQLLgCcT97ZWdwu2Thu6j7ixxrPiQJscRxWGbjild1zV+6TzktfDplLSHIUkUFTNnRSDLX1GhmkzyDxgrTOfOXki+D1PAM+9KkZF2QOhGzaSmZkA0yzJqviN+Ur6og/RnQroV8V2a4uHUWYoLqSkkWX7EiCRqsz4ldZgWs90Pir1ffqmgd32vbFlV+s44LintVr1NI5l9pmRfYrtTiB+mRx4kZcgSTsZuD7pZs22rU8GCeKbBQel08bI84+gal9DREx3qIEpvzUnUhROp3ZwdFd//Uz/+cvTrZ3q1h8sfiDW6j8t/87eoE8uvBCAoYNA6MMUEJJoTr5s//4zs7OU32LqbH6WAVicl0QJccbge9H8pM3eGDt20EMlHTXF5lroaBxyOvlaAcJILVB2Hp8qzuQ7C/kkYLcyUM6WQsA7/jBug+8FipngpdE2Wjtn1QyVJ7QnAmevmoIFqqrrw/SeSK2Ge51afEbB8DipC0/lEwLnJxAxk2TKN4M1gE+1YNhfxB6zbjNTqsr6KbQsl1R3BRK1K36oF0UgDZOZUOldkJaTuLTkQ1vabvacogf17aR5DnFIjjHorLdF2h+CU6DgTJDMW1bdnFCqvEg4o8R3QrZN8TnuTehbkE3enwXV3PX+wsX+39Yddvad2qTvviT+7c/+r82702W6nZKFl1tQv5EsQHp20TWddK3PxA/vtnv4Xi8GsvC3L97Ya++e3fkP/p+jSuoNjbaRt9f3Slf2juraV1986S83n1r4DqXy7mp+reiuNnfQ49utK5GTDrHs8Tl3kQpP2gI+bAD9TwUI84+gakNvMDJHAyesfqw+1Bymw/ECXhZkIChKbvU4W/0V3nKo81srD76diFdEDpu5ORHzOLMy++DSPefG9zkr5Ljzgq95z4i8XH1V/fRKf/f0hb/FbrfETWidVP6L7hKjTXSDnLyQLLREZrLSEJF6nRgnazGWfdFWnSOa21JiCPyOzRfI+yfVCZUntCckc4LbeBY2Qzg9R2JbkELWaEN7eK/squNBeJ6UxBZICL9R+zPkM5AtkmwIQHqXTAmGpYd/iBIsD3IxyuSTwf+TP6arjY+ldoKSbnQSY+YeS9pHy0jtVdovUnLCxJ/Xe0h/lFiJ/v6JI0jJGOPyBwbeyJx7qrvSAyB6FbQrwIHMjxnyV30SXU0UFlKFp26DhzkiLGTYj8otPmgH1x1fRabVYM+FxiPMfVwsy1dboS+v3vEkDkusaPg3AjGbLljxLknMNWAkFMpDnKwHeS1DT9o3tE7B/mm/0Lx8+cu/3g6g4HtYnk5JYoeG7wdPB8+OSJhBxm4iD56WaBJLlx8g/o1K2eKGNFQ0Bhw0ElfIUdPHsQEYat+wYkQYaIR0skI/Yd23SPakcx5aZmx2OSSZ2jOQHZPaIv6+iFOOgYWEsirZ5UvteZr0s0U6Rig5RC9lyQNJO2HElPtOkL2CbHTkhOdQ31A7ZwoBgMSCjF+BtHPmCSURAckZYLJLOHCXtJWijKYHqZoEahD8LHQQIwivodOG2f79pFEoMAuiGXWXovRZCY9SbV6BuGE6FbIRiCMG/276hi90XzFGNC+pEVTsugSDKg/uL4enFPCV4elfheNB+sYZPyviqPKoOkX2oa2fJUPEXwstK9+ZJMlNK+H+rB9vl/+oUTKg6kAACAASURBVC6JHQXmtMMYl7tJESPOO4EZseBCFF4UPCOvvLVmSJ3MLN5xx57etmXxm7EXY9Ai18kuUfROhwYsMCqn4LhoX71otz9WH327kKMQ6rA4OeAFUJ4O0Dqf0HOI0YtxLqnbAW1EsqQxNNbCD65AOinYsOkb8zHnWUjvpL+DbNT2L5c8Q3MG0eGYuVfbPfGF/YMLFmRhiJxClvLXlIN0KJF9RoLpuk/9AeUkmzXAXYCiGAw4YaKNYVa6IT71I/TvGp2TPhOSdQ5J1mZfED8uZRBdzt/BXti92Nc/gb5FJXWQxV/I7iMJxRS6BPiRaliRuQzwD74NhNrMDh285l8H9281odd+RetzvU5JuuHflAmKAyNtJLKRJ9EVyJfXnY6aqynGUlKHol+SaqPKrA5yuYT+o5orFtb+mL5/PQ51XGjvX965eqt0gEJzA7V3oY0xiVzYWvjwPJx3AjMiw4ss7CQGCh3cocEbO6EJORswYNgITMEEZord3FX7Y/XRtwc5CqHzzhlsSAxJTJmxZE/dDjSOiZISlf4Id5R92Ty7yvK7Ndt6MeY8i9HJDbsEBD/+uZCjj5UL0jvX2GACE+hbaCEb6hfiU4cYIvVIfHNI7hS/I7Yn5YlRKMAbOGmHJI2lHwUKcQUTFcFFIjIGsXMYmKNBuUOcYn6XJLJSLDRiZGw/i4xjynbbdaV+Swr0jdF6I+Y4EIOimyQpdAlJSKH+WMwk4FdXuoIkdwW6OmpCMzUL9VpPuAbq44fMK0mMA9j2pUhxJ80EepGkCN6vJM32VZL0JDKiy0fN96/u0bTG3mVtcZtL2n1OM3IhLtsYI846gSkxRn0DmWORFNrp1iiVf2ad0HSvHli7//rqK9za+trPIQ4ADRjUTs0/mDApNFYfvdiQoxA4bzQ5niKITKVbSx7Zdno39CvxjjLiFGNs0aH5eOn0t6y1P5KOQcjx5NDJFMFkjC2RspGUg+arq1DCW9Jur28Cko6VmRy4NxbxSbE6jPjUoVeu3Hi85bp1u4jhDF5/HdO3tJkgmx3u2d6kCDJ2Q/WIxmxZKGWbkkRdU7bYOSy2GREfmEJY9tuS4fs6pRtgKWSR1oH4XWmd0nKrVxlzvAkFJubGS2AOvMUxhW3L2SaiWxJ/CG7CSNVwVe6aWwO9lUMXc8flEBfBGmgIHKYv4WSj2LYvhUq5IYkqCFIe7RdSt6isi9WMNa+nPm183Hx/pe/+gz/uQz+2sP9Dm7Bsj1koJkoZr4n0xRWKbZMJzJq0KJgAAxTpGB4qV39wwLyU6h4VzAHoF/CgMgZf4UAAjtXHZWAgvzNI4LzHlB1hKi2bOmjsX6yleyVmbKfY7BOasJYEUFDwItDJvjHYRl2F2LiOhxy9dF4M6LHcfrhKAicwxZsHsXIjz6c6NZriw1mI3F1lQb8viiWkMoF3b378wvkr13f2AXk7IsI+NNsGbcXwtQM+qC/sz6TcxiyX214M9SWYSJjBBkBbfiReyDGOPom5MOYHqe+mR+PfHH3rqbN3bqWco9L+oKc+kfmF6JYkgYnGiVIGHYu+6goDZ+NeTHWAJTWLpsxoTKXmgj4o8F2o7Ij+oeKmLI/2K2Xb67oE/NF2QRuFVh9VPoVuVCcfC/uF5ZfJxa+Eo4KHZIX8V6JxBsd2u75CLnEwvYtEJGAXJjB9W2MaidUrLu5U5g9jnBqoJOoFPDQBHMuUJwnH6iOsA4KJDh3ddgKEDBFq2GLL5wyUWkGTOFkTsh1j6ktnQiH9aVJ5Ukygk306MTU3ja6iNjv3/EJOTfr+Dr6ODeiRhp3+mYH7GJG7ESN0VS/75pOgX0uawEw134KJrmaXEzEHZd/aBOaUH3gI2ZIUdxammkerepB4oW8Dw+uW29n5tHul7k63+DvhTmJcB8uZOLkL2glYXPUDA6eEp9qcQXQA8cdIvaEYca2v2FpSPUyNB6862V6MPcmWg0VjDsvjzRRExHWEr0dC4sE5nmDvzXlgb/Z0+lt/uGJhis/415WLsjjhbOwNYvQHBa+5tf29MXdeNtsE4wiFuPpHtL5/ueb/imtZ9iaSXsT1kyE7uo0x4qxPYIaAD40pGEyIFx1+9/CvZflaqmO9Yr10wdaOWVzQGAXUAGi5g8yTJuLG6qMfL8QBSk4QTclNrH8DBXMGSs1mU7YD6ovYPkh5puwLqpPSwL2rLyC3pHNcyrZdDpqv7mGt/ZPKh4y9r7NPHnQspPIlKTeQBIP6nyiZFtMnyD4nlhcd4z5dgeZAoj6Asg/aWGgMYgZb8WyMPVU0t35Ecjos5SZxjKxaPy6Jn6oTfba86E6w3IvK6BMU7kOSd2vi6lg/g8oaU77XLmDJuWRxEOIDEH+M1IvMW2hxHzNQm89ecwmSs9rDK7lYLONN8WGCdDhENQV1FPKFwOEmkXQZC+Xol38DxF139TC6QeQPXxXWnEnxweKj5PurDSNrH1EmhqO0J2RHIf2ZSYzIBGatEkGj19ScqZKYPthyRuFx1CiACwn1Ah41NKEJhczWsfq4dN7y3UfBRJ+SG8K4r2zOQEm78AkFp6C+QPZBwhRiZsxjodfdEOcTYjMkP8hNbUskDKVlEDa+zpR2qS2jJOnQfGboBAA6FlJeScoxgZkEIzrGfQkraA4IfJakc6DsTGBKoDbKBN/cmPh+zhTxgiSBuWoHPE24Fi9VEhOaY+BYxxZnAvMwQTQOmiKJGXPdARRjDtyz3aV7SN2xugs+H4zVwXkarA+UL1vxXP3ypzILY3enSmKi6+NsgDsqltqQJcOnRj/41pA5tK6B9GcmMSITmPUAw0YqZtc3ZoJpdjbAhYR6AQ8ZmsTB9Vh99GOXeqJD3DInWDS6iQQzUoMfGzSF2gH1BbYPIY6pmSE6GWIzJDvITW1LQvyQ3xE2vt6Qo0fabpcNJh0OV37VyXNHV5voWMTIDT/LBCaMLMUY8wRmEuxQJTH2FGqoVTj8gafw65Qx7WufRXwfksCsYjN3Ysg98ygqW4okJupnUBljyjOBeZieZt5qT6TFjF39bPjjNO02kHmGskDqju87VEMwVsfm6TxtaBcRrF9YzgO9t38lnyZfcUiPsVPikLLEFpbMG20COFa29vOhdQ2kP0xghocnBHyoBjApFDR6fW3VJ2p2vu0uYD4Z7lGaEui9HOhCV8t9LOZdFMfqYxUkI3eNCCY6yC1rgkWjoUgwIzH4fTKkbAfUF7V9GKMvqE7GjAHIbRa6Cs1XB1Nr/yRzB53rQwt4dCwk8iUrwwRmEpToGDOBmQQ7VEmMPYUaahV+IHiXLJ70iJFH+izix9EEZu0LT1/RxONoXH1ooY3EhVJYicr12gUs4ZssDkJ0APHHSL3aeVsdXtnff9wacy96Kk07nHUiqDyJvE6ekwVSt7bPyueCOgrFg4L1m1LO5I9B/VIc2oo44Q7rbhMOHDMnJ9tfYciG+PxQYRZ7ie3ENecX37HF4jVj7C+k3Q3ZUUh/Es0LML7dro/4hIAPDRyo9EGjF1KS+kSm/Ya7L+LUKMeEAQUClUS9gB+beXNMxuojmiySBODoqayYeRHSY83vSDATMviDcxr4YEmonTH1patPqZkhzifEZmgMpuam1E/5lQ+ugZzzK5x02Ozh0Fihr6Nr2KmfGfBPEAPAz6llDTx4FPwa1IdEzEFbMfwKub87qrDfzTXGMfXG2FNtu5IvOWs/MKCVSfoc4vsk8VO73TrBVF5V3TMW8WEfbeJUyi2mXKJ7lKPXSb4PEt1t9hXxx4hupZi3y6TOnU7eMT7GAfHPySL08bAYXY18NsgIiZU19idSfvXjUL8UCczl2vctja7HbA5pE6dqkMCDIRsCjsnhlt2bqs6PvVcY87axxe/bH/aSznG/AfLC+SvXD66vkZOuM4kR+Qp5PaJBowfodLE8lXmXC7jzOTbgFWxwIaFewEOLpMTMx+rj0ojLEyKCiT6m7IgeS8tKjaivL2TwBw1swgTmchzFF5EjQXSIG/o6hmQhijjKmDHYRl1F2PixSznWTV3QJBxDsiBzL1RXSG9T/Q6Nh8B+ppKrrx5Q55PGEtArsUNfG0aC06LovbYAYZ2SW8q6kD7MtWxw0xOID8fuI2KztAkE1Mc2GWj9IxT/zsCu+T6D8yqJb8zZJqJb2nHumi8+KVtae4+1xZ22sCcSn7haNymJBVeFc7JAfHhKzilsFSK71v6kkBOtA+qXcv0dtTmktHmgvUgaf6Fj0CwfkXi96lbKb1i7/3roxDUwx4NcIP81kxiRCcxa44KDG6PI1QS05RddFv0WV8+tMXU1n7XWfE3yQR/QAKiDFHACJGU+Vh+Xia+kCUw02J5hQCBOBMbIDhhrUaI0dX3SeR1cfLYqkiSekOAlZgzGnGdSnqFyCBtfl4R3qM2u30H76KsIJpIQHc7VL5SFkxnZxU/qJ1BZp1rkrxehl069DHxduZcVlAhNFA+lbBO0O5PrjEbPkGe29f7LZfwkjhdiEggKe1sNgT+t4r5Mfgv6ZXKoPeViHtERSVn0NCSSQOtrH13YI34L8YcxcVCIbRXTL4ovOf29zenTLckSmsY8s3vu8tlQ++g8Q1kgMRVat6RvMWUQ2WPsT4yMmmehfkX4eNAXb3RFowtge7Px/eB4VPG+s68XQknLJlDA3gW5pIzXpPob2yYTmDXp4OBKB0RSLllCU+jM0AQZEjBsTCbslEdS5qCRi0pSAEbDRcP2ud0Lew+H9AKqU3Ghd6j9mN/dK6EfSQM0jQNbL+bTn8CUJ6KFc03CMbz43KhFNE8QZxkzBmPOMwlLSRmEja9Pa/+GZPELxb+W5TvSeVLXFb7DDumbdMNLwjSmDLbQLz7YvXDlxpj2UjyL2OeUnFO9bo/MW8nrRhKm4Cu1QTsnHYNU8kv6OFWZsF6EbcdUskvHsZJPGD/19SXMqZdCcPOo/SQyx9yzcP25xguK34x57Plzl38cIwtoFyB/jOhWTByE9j9hQlOsN9C4ol8hR9Z6CWNnlHtXeSRmirU/KeSV1gH1KzLnAa5hDrrg3gzY2VncDm8OCdd+c/H9+NtWuo9FAfYuGF8h/isVZ9AX8A7MHmMQHFypEdGUqxWnuAe+eBwI7gBFhwKGZn+hhWmkAY0MHtV99O0iLKUOEAq0I+5p8vKvDJW/l8QlVD5cLhTeqf67WHzk79qo/2rekDgaxHHGBI0Id0k7oBMWB44hG5BjrMcaA8TJeQ45koEhvu3fETa5ZAZtY3UKKHRnTW2L5B+sMAkWnyj7rvLoCeSdxeImiR3qk82Pv+N5s7N179ZlzJ/dBxE+qP62WPzBwf7v0hb/NfQ2AzZn5adkhniip6OGxhetK0USFrwnLRiDIfXF6kwKPc9Vh2QsU5yUyyU/4sel8VOfrOjmfbMe1F4ii9aYO+FSjwvmH3UL7abMSGIN9ceIbklixNSsV/VVelmUdys+BBS0k6s2kHFFWUCnaCPXK6nHAOESa39Syz5UH9SvyPV31KvkCn3YNt8PzY+I614Aexe0G5K4oql/c4gReQKzHpHg4I5hiOBgiwnM9bCgiRXt5Ms1RkgyLTb4hY5tC5wN4jjRQKk57wBjLXqFfOxEiu8Lqj9SXmONATrPmMCskoz4B0gE887rE1Z3/OIzhR9EAyU0kdCWEVkw9yW+xrTP6wUo9oXg4GYBsghw192IX1Xs0gkkmbN8PhiDIcl6yenlFLo8RR1BvxWxIBqjP4gfT5FAQDeP1gwUp4WQOTaXJDMSD2pfrz9IquG+EIkhEN2SxlY554QiERS0k2MkMCH7PjN7hMTKKexPTv1prY/kb5QlyHmga4GY5Ne2+X7I5whj/bYegXG0yG4g/msOMSITmMIEpk88LEzxGV+8us/S/1mY69zpjZuqv9vis/6rh7FBCTRRmcBcz+lciaG20UCCvVovZK+QBxclLUFi9Aw5TSRJHiABQUzQmCM4RZIb0rEcCliw+S1/fXasMUCDFmTxkSvQQ9h4GVLKjCUYDwhI5zeykIhZfK76ETq1Xdr9dyV3+CA2yCWj9nbPXz6l0Q/Erg5tDI3lXzYWJBdP/Vn+JeUwI8T2xG+SQXd3+m4HA2xwLgXr69OnBqdryzJ/cba/Pr1rFn9yQfMfq/BP+IaCRm8HfUjwXtSwLqSWCakP8eMpfK6XDbM3jd6Ai0tkjsX0zS80rSmuGzpV7nvR/mpt1zihtk0rtyJZV4mL+GNEt0KxqPetC7NzcxXGm+LvirKsv+Jbf8vAvyXxKcf/c7GbJbnsGhL3hFh06Q2S7NDUX81bNwbGLN50sP3XmP9U83dfZS7tx/VQLH7r/xt6g6IpP8JFq+uIPUxVFuqXwN9K5EI2dpv1ofFFrjnS7mMq3w8lMIU5grasSGzrnhXFQ4j/QsfwEOtgHHNIA/kKec+kHBxcxCnGGrxcio/0AQkYNhwDci+KcEJJjOiqDNJH7e4B4rQruQDjBCXTlIt6JOHhxZfoAuI4tYGMlwUZX2k7oMH+2L16elKSoOnS25wLhbHGgAlMmUVacvq6K634aBuWgIAW54A9agX94g/vSAIbdCNImtAdCEjDAxdgg9h+CYMhgVA+EnsHBrzOReruu/M+xiX69rD7XsMBNnjiQHQKv9NOA3c6u0Ze2T135b6wcqUrEbb1873/EvXjSPw0RBj2vY3KkLd1kDmm3VBC+yKZx6BtU8VBSKzVHEtJDKpZAwzZzPAc29A2UXKgTz/BmErcFtIHif+ITECI5d6IO8C3ECRXhyBcUtmfdNa/vyaoX4nW39pNiaoXwFse2+b7oTyOci2fY7wR/1UP4bQxIk9g1vYglMBEFm+qLxgeOGD5nWbIzh+S/EEChg1ns0UJTM0CEzNKSzJAwgAN8JDAWqlfopNPiCHVBEqpg9OmzoLBo991f999ofRu9E4+1NGji5uxxgDlpbUlKQM+hI1vF5V5fVLDFJ+2hf1CURYn5CfnNnuKjnuVEACCfF+/O05yZui+xzZ7dMEs8UvoRoqTCb6DFm0jlCTF7T+WiF5xx3mHk3/ruoHknEYXK310d466/6CJe9EC19WNxGKwrUbmku9rSGdS2jGpH5xCJqSfSCyaMoGAz9+6V2ismHsjGpkD/uSa5CNo4AknOA7SntRC/TGiW4MJTMCnehnj4lrktXq5T0HssEZ+3E9hGytozCx9UwPhktL+IDZSUxbqV6IEppcTXROs+lbHovIDIYjd06zTUvp+yNcIbfTGuvXS6W9Za38k1RPEhyH+a+oYkQnMWgMGg2c0K61ZbHkh0JMLSKCKOHZNYqxauEyfwAQXTnKHigZ4a8MCJDDhBTeYjED1WBrUQI4T2HVrG2dEh6WyV3oLLrhR57j8AvVr9etGwj+A3qB9QNi0pUWDFTQZKKQDFUPHF6o8dWHF/EC/cI7qL3LCEwlo0A0b6QJlNSSI3KEYwNeJcq7lkC846xjg9FcLY3eR04vIfAZ9NJ6oAD4q1Zo6ogQman8Q/mj8JdGZ1OYh2H/FYii1jKH6ED+eOoEA2oSDrgB2GZ1jkg2flSBoDCflp7Ft3o+4zbDHhzbD6pNT9hn4A6UNJUJiCES3huwmeuLLJ4o1X1eubP6Tp96Tx4bImgXYSAL0uzm/kdgK3TxFk95SP4jILJ0/IZs3xu9QvxImMKv1B/468AqJeGM66PsOQZbHXql9P+wDgPWe51AW9mkkRvRopHYUlR1dT+Bx/3pg+Qp5jyEJBs/IKxbLNq65BONZ6eum1eS09gng5E5Q5pajcXom/ANMpo02pk5ggkbUO9SFMT94/tzlH/eRqXcB9x93Z6UfEtLbLAayRCd31YfCnA3ddeQTsO502FnA6In1ayzHmSo4bY8jvpNcn8oIBe++HcW89pWLTk1oA0lpoNel72gQIXWaqrklfAjUT2GtWYqJg7l262jQ4XXMvf7x3SG7sVzE/dy1dbu4t4C9QzdsahnM3s7CPDp0Anop9yuusPgUoHROoLv0S25X3att/xQ6te3rdjHAw4CNrngg94PmTVSUmK5sKlUuf+NbCcZiy8TxU/JEQtypK/F8ahUMz3NMH7RyxDyH+PHUCQSNr/d9RU4LaeaYv4pgxywuDNkIn7wsrf2+1D4gm0m+j0rbVtkgY4o3mnF0FScYe5e1xUmpvH06hcQQiG6FbD4ai0t8arOPS//3tNRPweOJbcyL7W+zD2g86Pvg4o5nd89dPjtkQ8J27tDTYvmheBCIZ2JsYopnoX4lTmDip2UPeoy8hgz2cTLfj86LZWz7hIvlvtenC7G5CKkd1fgvyXpYtZ4IxIg8gVkDCho/nUL6qs1eHUAX/6+9U1k7eXc5tLV3SJ1YY9oPKnt7EsAT3+3I7RjzEx9Q1UFf8fcujLvTX6Tcd+cT6HSCzFGjDu9OrxuoAzCXzHx1FUBWfS7Ku934nQSSyodFBh2gYido1eY15wheKsv9362S5nWAtHPXcvdbvJivtLYwj4SSoquGwXGv5oS1+z/0clav3y52/qebH3c6OW90Rva2vnFPGZwemh9g8rsxDyvdScXd16s5AY3Mb2Rs25xQOyh1muhcR8ojbJB6U5ZFdzHbbWuCjmUdV53d+NUh27covuRuxr8Psn2KUyianftqEWTtK/4C/6aNilg0Q74IOzFTU64XbsWeseb15sdfKj+jYV1Xqjr1g9vrlbb1+0lrzL2RiQrxGKA2aM2/MG86GV9NpDPqzYYYuxG2ZfITWjFyxDyL+PHUCUwvt17/5ddYqNrwHyop7J4tFq+t1grerruk5T3L+OgkxF1xqk5j2yCZFIWRGALRrVAcFOFTr7kDD28ZW/y+HUMfrKX85prFxhPcrMJ1UB2Xg2++1QcAHP+X3Drg9RTrFSRmDtvQhpKC6zeFeid7BOqXIOeBCqbxy8vgSBzHaNqoYq8JfD/yKnaDdbWOb8bjEXHtxhBCdhQ7jNZoZ9wYkQnMGr0oeEbuYEAnP1heJG+zzoSy97YNOky4DxJGSqMhqVpXRuEA9TvhOhE7noIWZy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From f1fccd9d3cb1e34dc138f61bc99109e631ef15e0 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Thu, 28 Mar 2024 22:17:12 -0400
Subject: [PATCH 26/48] Fix up RISC-V datapath to actually work

(This is the fancy way of saying I downloaded an old version (21.1.2) of draw.io off of GitHub and used it to export the RISC-V datapath. If you're a future group and discover this and somehow no one tells you, I'm really sorry)
---
 src/ui/footer/component.rs    | 14 +++++++++-----
 src/ui/visual_datapath/mod.rs |  4 +++-
 static/datapath_riscv.svg     |  3 +--
 3 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/ui/footer/component.rs b/src/ui/footer/component.rs
index 067023236..5ba72247d 100644
--- a/src/ui/footer/component.rs
+++ b/src/ui/footer/component.rs
@@ -1,5 +1,7 @@
 use crate::agent::datapath_communicator::DatapathCommunicator;
 use crate::agent::datapath_reducer::DatapathReducer;
+use crate::emulation_core::architectures::AvailableDatapaths;
+use crate::emulation_core::architectures::AvailableDatapaths::{MIPS, RISCV};
 use crate::ui::console::component::Console;
 use crate::ui::hex_editor::component::HexEditor;
 use crate::ui::visual_datapath::VisualDatapath;
@@ -59,10 +61,12 @@ pub fn footer(props: &Footerprops) -> Html {
             switch_datapath.toggle();
         })
     };
-
-    let svg_path = match *switch_datapath {
-        true => "static/datapath_full.svg",
-        false => "static/datapath_simple.svg",
+    let svg_path = match props.datapath_state.current_architecture {
+        MIPS => match *switch_datapath {
+            true => "static/datapath_full.svg",
+            false => "static/datapath_riscv.svg",
+        },
+        RISCV => "static/datapath_riscv.svg",
     };
 
     let switch_datapath_button_label = match *switch_datapath {
@@ -112,7 +116,7 @@ pub fn footer(props: &Footerprops) -> Html {
                     />
                 </div>
 
-                if **active_tab == FooterTabState::Datapath {
+                if **active_tab == FooterTabState::Datapath && props.datapath_state.current_architecture == MIPS {
                     <div class="min-w-0">
                         <button class="hover:text-primary-100 duration-300 pointer pt-4 min-w-0 text-ellipsis text-nowrap overflow-hidden" onclick={switch_datapath_type}>{switch_datapath_button_label}</button>
                     </div>
diff --git a/src/ui/visual_datapath/mod.rs b/src/ui/visual_datapath/mod.rs
index 59a1e033e..c2a3ab471 100644
--- a/src/ui/visual_datapath/mod.rs
+++ b/src/ui/visual_datapath/mod.rs
@@ -25,6 +25,7 @@
 pub mod consts;
 pub mod utils;
 
+use gloo_console::log;
 use std::{cell::RefCell, rc::Rc};
 
 use gloo_events::EventListener;
@@ -286,6 +287,8 @@ impl VisualDatapath {
                 if let Ok(listeners) =
                     Self::enable_interactivity(element, datapath_state, is_in_current_stage)
                 {
+                    log!("Found an element in the current stage!");
+                    log!(element.get_attribute("id"));
                     for l in listeners {
                         active_listeners.push(l);
                     }
@@ -366,7 +369,6 @@ impl VisualDatapath {
             } else {
                 Self::set_inactive(&path)?;
             }
-            path.style().set_property("stroke-width", "10").unwrap();
 
             if path.tag_name() == "path" {
                 // Set the initial state of this path:
diff --git a/static/datapath_riscv.svg b/static/datapath_riscv.svg
index 0bcbba30f..3cb474d06 100644
--- a/static/datapath_riscv.svg
+++ b/static/datapath_riscv.svg
@@ -1,4 +1,3 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Do not edit this file with editors other than draw.io -->
 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
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color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;"><div style="font-size: 9px;"><font style="font-size: 9px;">Instruction [31-25] (funct7)</font></div></div></div></div></foreignObject><image x="318.5" y="845" width="103" height="13.25" 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KNJS6OyO/RNiN1e5R15ppWHhP5vM/q4eI+yKQR8ZvUE8cYAkhqv8YTxHrxRn1m9n6bb9rjizdorgqxLWSDjpgw9hVEaDC1BpZ45iUSiNJHzHUjys3f5uPe9g1H9I1EqdNKy6EO6RvU/QKx30pYu++5+ggnY+GWA/EWhqrjXqs/Un9By0FByGMmnEqIoit6vpPVJk8kGZfJRyjksAls934jid3BvdKd+5ok94lZxi8uxWzBobrEOQ2KacI409cr8fm+wDFMqeMCOqmWTraSWb6uGLKrvSbAtlBc6LjPuAViCBhspusctGhgbDpZJRaLj020/6h5jERqR1zUjzpkLoHou4+ui1uuPqYSiOIAXakG6OT+1H6WOhGkEoigcIgmyiFbC186gBKB4IlJn8/kHGex/Ba0c6zb9tXjzDVLfwdymM8jyGYDgZVtefsT7Bk+1GZs0Sba+A11EHQMhdgWigsbJxA7PqkmNQ4YFJxOj642DLUzt2BEHTKXQAzZE9Lmm6uPqQRiLpElHT9IuVxtj30fKHhGFOXIarH08RLUF6HoXPdEDPHBobJgLoh123CBCGyTChERZUwDxKg0P8Qer22gkM8HLDbFdgg0V4U8uQhlNOoVxBCnRxzeOIBTIFaDCDgoG/CqpWAs1AfNA8CBKgaLog4pDQArAxYIMuW1EZNurj6mEIjo5CMkYMTyqcOrD/HfLu5qZ+yEE7s+KVvk0ZitUzIeQxOBuO32gP9CvyEtL2m7tC7fcmAu8L2N9DpRrkHzTUiuRAWi9O361OMLealPulVDasSQcpuUqygQK0uLBi362rivE9lVAzPg396aqWuST/e47pPLIdFAHBrUmv3O1ccUAjFn212+4vP71Ilg0aaY90H3AsYUOuiEwPVWZAqf7PODTfRVNC7FtLXPePLx95D7oNdK43bM8Zpjwohy8C2fcwyFThwpEAGBCAdiXw+qr1u86GJWFV9zfSlj6Fa5HBINxDFXwnL1EfYBwaONFCtKga4HXZ46EfgkTFcSy+kvOZJbaCKQGnzd3KTtbJZD4xIFoouy7MXClHEh5xvMLhro78ExJFq86mtDaFwYtUAMGahgUBAbAT19HnWe3vLm7bEtNbvos6IIOqTokVZn0gMfMYfYt33/XH1MIRBBX/W2TzRfbFWUMhEcSvQRN72D/iKOD1LGsZkhicAlnscw2ZRylJTbxPEF+qcEQ7wygklvHSdFR/TYsqhPonzQ+uPBWq0JbHtQ7EHiQtfb0hSIlf0gI6xLJNpHz5Lvv65LPK0zEIODLkhkhQ66tn3WyS1GIIwtdgZmw9ESDugvUHyQMIWYCY66QXwyJFmC3ILGmYSjpMwmji+Us4RDtDIUiEEoQdsGxR4kLlAg9psVNkK5xK3nO6LP7wW50+GL0W9J2qtBh/QO6lAgFnySCMGWq4/1zFj+NQlBMIW4mQbEXHlFGOcQbkPtgUSV47xF0F/g+ODiGrMvqE9SIA5bZwzjC/RPl7vF/b0gptU+GW1CF7roEeLzceHB+Tgo9lAg9lgPTLreRqg2u2+9YE6zPBHbkfrqkx59sbgeDTa+ATIX8y4uufqIJmPJIacgNwpEwUBzJQTQX7zjQy5RjSQCF5shvCC3UfjqJo4vlLNgSMQrQoEYxBK0bVDsQeICVxAjriC2q6pWFPVzWutt89z+3iAPklwsHKSjXUEEH+u7kICDLihxhQ66ldnwpZM/MH7zY1cfF7/3FfDS+tFysVfDcoiqnP7S1Z/YzBCfpEAc/woi+pY9OmaDygtzT2wfb7aZL6nILIjEBQrEhAKxWXW9qviYWVV81Pz/h2SmBEsBj2hzJUNwph40M1oRWRnPZwsddOtsO+hlouIpE0GzAbHvg9QXU5Tjx9zMH3GdYoD4JAXi+AWibeG6/FM06AWFkPb7+GTq+gVd9CoC5uOgPInEBQrETAKxUwDo+YPmYOjj5ndf9/Kqjosk56PZy0CH9F5do0DsNNKbuxf3zgzZHBUMPsE0ls911ZMrUMe+T+z6pIxTHGuEJIIQ/8kVS6QsJeXAuOQd/yRtQcog/hlzAoO0cags0n4fn0QOypZs9YnVb1c94BiiQOwDGuL0YFAIMoLLIZIJRuGXSFAB4st9nczBQReUBJDAJw1MUJ0Bn6BEfVVSHgnUPolg0QaEkeQ+iKiK+dUf5FN7pu+i2IT0RcKmz+45x5nE9yRlwLgUFBsk7ZGWQWwqXSyQ3jtGudRxAeET87OuoWzAMSQa/31tghht2reYfYWKhQUGhSAjxHGY4gn4RRfhXpCSB3CGnC/3dTIHB11QEkBYSgWiCaZ3xHtXzZmYu+dvPOnrdwtW1Rd7iv8p69H64/LP2exPShf/Vf1VfSA5dxMJQiHiBOEuuQ8o1G6acfGwL/PmdSlsncsGOcdZDNYeuSAoNsRqcxWzT96Q5oQxfUquMaETn/YgGa9ttsj4RV/s7LJjGX/M1i5zaOOn5e9VcaeY6y/Kv6rZ7+yfc71/27UdBBxDQdoEiQt8xNw/eoOMECsooCt9UvFBgbhqId8Zdyob5Qx2py+dvGx853mR3wrEKBKEfBJBI+FEPTYDfdQb48s/qP9IeeWyAZjcRiG2wInrKNpcC8QfGYH4kmicFmpv98L1bVnZPKVS+2TO8YuMW5cYBcdQkDZBbECBGCAQrYPMVPFntgrzsfIHy6pm6i4zo7iv/Lsu7jEzirulHzLvawoya6RAPKCIDOBq8qfOXr1w/QoaKiFxVTmLcw+iLYYGuxA/Q1awJCsTSBDy5Y5OcqT3QR6DSW055FPY+C4+371445jER3PZAExuoxBbmyoQkTeZ7fm4X5rNjktW/Nv+ZHyyFKKuJwqS1bFm3al9En2T2UT9l42I/qFkPK0wurT9jvjMY8ekGhxDFIh9BvN91FkmE+yzb4NGQB5thSYRqN1C8YEmV1/uUNuFe6uQwQzZSbh/cyVQ7Gx/ZicC4nYBNoLEiueKAZJ0bB8lvpA6ESxYI/aVCkREsFWH1M9PuB4h9fkGOolBYkkuG4DJTeQ/4rHkWRCMS6No86KryGQO8ZeWkPuN+bfotA3X6lhOgVjnNXHb7eNh6YQrJO67Yg84higQN0Agip0wZCZXObx83wkyI0KSq0QUdNkMDMRBjt95f2CfJRLolgIFm3RUlwECEbO9rVp9562L13+J5E3sHrLHVrnECeLDriC9YAYGa5Njik/MSs3j6EpNudqxP78pnVygcSSXDVBevrEE8WlXWTAujUogIk8sfL6yBU9agFW4HD65WP10+cDy9x4LA9A9BCIUHENBeRKxAR8x93vRoBHQx3/mNl4b2u3qTqFme+bFgbskDo88ZkSSq4/wKMUtJqCCHL9HIIo3RVfXyx85QEGi2ThAIKKre2hCQP1YKrKgIOQRoJcCHZgASNter0JAfoOKRK9vtwN+g/YBYdMeZ2ByG4XYAuPSKNq84F77zsfinABOYJAVypSTlpBTAk6jT3WAuI/mZMmCADiGgvIkFJv5FnOv7HIaAXfC4pYRcOekj6NKp9H6ZekKg+mJs83N3iICUeLko1xBRPaJ2MU988hwptQ/Xj1//Sd9nlGt/Oy/aALYsxLRvlIGTvTICnLdh0Kdc+2ntALXvIJ3TppoEP+CghDot74+jIggfBWl5P5JodWLrhVcj3FtK4cfhSE2QNhQIHqN+qgXoQLX+o/ZO/zSUEyo9+/93DRU9Gi57BAcy7aRiReUzw7HhWoPJQRdMFEt40Kh/1mak6UCmgJxwFKIUAl5PAEOKqdzgkZtEFB7NtlqXfxnO5mUdaria2bg2eMzwAO05atf6ApD2XgzgLaU+ql9lFYl0OIvyi/DmFf8+45Yic0cGvCmMLpCdlC/2jP9+8CIxfcWjw6r4DB/3IA4IQ0Qne0Fgyo8Yz246S2TFN6ez/d/v5iUNL7oY78TDvkXIiJAu1vn2tN6/zXbTtvG2WzrL834eNT41zEz5h/oszsSO5D2l+MDnFy0fScW9yoP+2wdkCdjlE3THmgcDInh6Pjv9RvsycaoVhBtn9BVxAaHmyYm/Golrs2Kb5rzWJ6E4poRnVtbs4eQrRW54oLtL7ISuuRTHlmj3mjmZst6rvUTdTyycVP+I4z14BhyapOhBiITRz5i7icpMoKBLd6LKPcqr5Ki9jZrjtj23nuDAQHug4QU9qKHpMbAMsKgcchWyDE0gc3ruRzaIoHsk3I1d0hQpBSI3knG1SH499jEb1E9kggoEIeNMgZR226h/+QXdsDOC3x8JldcKMduuYihfxGntx61AAKaAnGALxLkQwZqCrHitZfIw9eGLvF9kzLiYB21QATt7mWdxnEQ7lU5D4FoG4W9TOLVjc6L0P11sYPzOgXi2se34MzJPktTIPaPATQmhOSdeCNxtSb/Ve7AVnn6ZUzRJrGJ9z7xQDzwXnD75LDQbwhvG7SQgsQFriD2W0RshIDlfqE/DBfzefxUJfFvPWxOe/8wtBF2MLx14cZXuuoBA7GYOdJm9G1RpG5bdiGg9ufzd80/kwnEdYhENNA12Xns0e0WqAOPV5HJpc+Kh23Q2kSiZxJeQEQSgS8bey9w9WMUj2vBuDSKNvdPBLA9ymh8Wy0vO8mgt73wCyTdNUnz3npEIrbqD46hoDyJxAUKxAgCcV1JRPJChSsYxFqV6pvNgYE4yPGH+mpnroXSu8ALGS505e+bq2vigee5gniQ+PMkhBBxWItZfKN4B/Uh8ZJDIC7Gt5kAYBv4RR7UVwhLMF21iP3RXEyBOGwsyWpVkLkDL44Vx93NCBOHueJCux95RSI+dikQBzwPCfIhAzW1WClXqvR8R3y6uns09paQvjHpukXACxCHqu775Fhq5q7+NX+fQCTeMv0+tdikLU7IgQKxDLJmT6J5w/1MbMHb4HWobwjnQ8yR70n33GToyy1I7AgRQUtxnph7rHFdJWK+pNLnt2BcGvUK4tI3wRdv4DEdIW4t7un1AkmrwZIvOjUv8To9AIFk9hzqQn3fdY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ded8ziQgrHv8zyPwO9hiLRknUZs+dOjz6KyIoEBpAoq8KJE5jaO+KsNV9rnvxA+40ERW1OkKNIFPTWCYjFxRTGbqM/4HwAHROqYrNLYK4CMGvMvdGbEwdB2cfG2ldSLkDEOtnSR3DzYGg83SnT8iyaEEcVRFNezGZZeYxtGJJvGbD8SNqHFK+R1wFHeVH9RfTDwo6SsF4u8M+mmnNVN1wQ5RKZ39UuEkPjtkoSJ40HegK/kCzo7/WpXPu/NIvMdWjgFpuFNY+v/DLok6MXMUsf+bSTp/P0E8rEbyBsWyLT2brhj9MkikdwlgdPQDFERnlB/UySwKzfmrFPxMyzxnxLHke0xzXZnHJx5u65K/et6kfYI/4Y0S1tAtNvEqSMB1vMXRxlLqFvmiH9VsxdlW32J5ydrj+cxIcn9IPieLBhe5b5h12kLyniN2SsxP2qK1WNqVQeUB+jZUlmp9YdzOf7k+Wy+gfjqluLXUi9FptjjLgVCUzFnQqD88zv6nxisbgbSQweduzVF2Yhgyad/BvlnOG2hfmm1KEhgYFOnv5daMHu/6rJymCpk5fulMQL569c35Qf7TcSFLU5QY4iQQCeNBDoGnRAx0DHhKrYrBKY3mCX1n4fCVqgDidMqIh1MjIoG+qfD9hcAuOM1FZBrCIKi9ks24ixDSExz1w85a9yuCFUbr1IbW3USJ/z5bxNLAv7dBb9bS1IEbmGyqYPRDtayyA74Pu0qLJtEJy5dOrlhAlu1z/zhD8xA/rkqEUM/DqwcBSWJxueTnkCSNi0qtgDT576aGi+a5M2KmF6HoJiiATxU5/s8JyNkCXrYQcgfkPGMbX/aK67ENuA+GNEt9C5oF2vIMx9WY3NQfqNyuPKQ7bZ+/DCLJ7TvqkUkM9dCbe4N2btLo4Hl/Ndk7xc9mHUj9OI+1ULB40pojPI3F7WGyXLNvn+1LmsvnHxNmRRmLOpNuvnGiPOPoEJX7QtnGnembokmLt3Bv+T2rGHJEASAwrjEWp+8/eEJzD1Y3v41Uq030hQ1AYEOYqIoNe3q2cEDmv96lxwoTZloIS0jQanh8cYvOAfwy2eU9JqxTq51MdcjrS2VeXJ1Lt/Ug5d5cRslg/H2IaQnHAgoPzyba7xbfYvxUZgs76IhUIIe9fv0QshX+lYi1rfVhWUGvODlK/C5/Mv5gkXXP7RXVPyM+HgqBcx+frQlDzddQ5CHnAxyd1jOW2bVGDEj6d8bbsjjhs+rXqoQ3ViXtrPVbnxbIROvm6fCX+IQ4RltZZZmOIzUtuA6CyiW0iMqPkQnwjIYCH5eCL9Vsglts1j+HBkPRwVD7pY2b8l9deyfE2XjJWPn2JMDj0CxrniMUVlwxOKet+6Tb4f3jBDwXeUT3GPfj7G8THirBOY1ti70p4MaI2wIrk0hoHu0ltpYgBN5MFzJFEC002sl9zrBeLXKTflPOwY0H4jQVFH4Pu2+zfZa2oKHVu1l89w9I96+9X8jr47Vcz2Z/ITmOMtNtoM9U7c1yQOXpw++o+b6OeeaOyzBUei1luFxGyWz8XYhpB86Gvk7rTmxqt3ofprXciz+OzxS9FvM/h6J/KrUSckJpLZ0UqzMMrvX8we8Dq9ymbk70NT6+NstGTuxpQRLBxVjGNk6noWSrZExE9DckuSve3nQ7FRV3vjxxPxtiG7//BvnizMv0pjEMQfI7olTWCOP4YHmiRNQCD9Vsxnkd0Y0x/GJDHF8aCzPcXCXKfNQbjXeE+MuZEv7letAKIxRXVFlejXb9JfAeILtCut8nG+P7tN7emdNG/UByd/fBUXI842genvHxpDOVEj417RcV8KLT4XORu0jweNDprIgwVJkMD0J3dcuzdoX210rxDc1H6FAO03EhS1GUGOQhmA5zcc3SPvDZ67XuGWvlc0pgyUkLalwWnU2MKTJ/SA3kkCOnm1+fXEkET63+MXUvq2N58E2FQPxtiGkMyKhXPQ5jfbhBOkIYFlv0Mytqscc+FzqDtK+7xc1L6j9WEyrEOl4ubXFKcBAn2GdQg+zRwPPck9iCnE6KrD2bnZ33/p5Ub8eI4TmJqElPY+uynWC9rYx4+Nwj+p1Hn5ldrrJA8j/hjRLSmnSezMEkwoHl/xQ/otYd4qE7TNy9fG98b0h1I2ETH+Nfes7KBKq5GYNzwV41M9Asa5wTHVyKFZt2o2hiaZk8pYcYq5sTl2unXlNsSIM05gaqaP4hnghMtUWfSWMg6+xoIm8mBiCRKYcJubD3SemkH7jQRFEQ5QteARnKSIRBh8vPdk0pSBEtK2NDhtktA43yBJtABgjzZlPyU/FYzKpCg/RQDXJyYY2GVNYC4DTfEpZmThPGmgpAzuVDv2Cn0cegQNoDUJkMQiV9VJT+e020Z9ZQ7ZO+qEFlQTJepr7oV5JNXdUinZBu+/NOaxlNcPaGVH/HjqBKb+Awr4InCSRbYbFG1iZw62uEunkFgd0S3JPF7eyfymVtfTPBfWPaTfCpmCtnmKRP2yH0HZotZvClhL5/zM7rnLZ7WPa54D41yY25BM6o+ButPYuxeu3Ij0d9t8PzguCApx2a5DX0MPb0uMuI0JTLcrUn0h6vXV8exq17Ao71Z9GQ6YQNAHGPxX0wq7574c/dvS7r/bPkpeKYgp/q4o7X3IRx38l1SHJnx2xZs8gdl98gTtNxIURTlAcGGvT0IYp2vFG+6OtFdXpyeXX8W9a3mSGdpJ7AvupgyUkLYlwWlzXPVOseZelvu/O7BH/ovxOyru2sREtJP09mphXrZl8ZvVR3jW+mPtI5CNWoJFT7eLvTFYEGUTYxskokF+xFUolQftZ3UKxhR7xprXVwkZH4i6D1fdY21xJ/oGhGa8VYv8Dl313Gufau9ysp8ET4JAwbxG5ibrxcK8cWCjXeyyKL4ExwHLRIXmvln9YrPLx+jlb80V8RioTr8O2bfCnnSyyP0jEDNK7EGKMpKTc+giJoVcXXUgfjwmgentQZ1MKD5ty/LzLuN/CzTODeHRTQ40Hl021b22UdmHcNLrUFzrvq7tGD2Ej3tWuyD2f15uRLckMSKyqb228YX5j7Is/rP9McN6jhZ/r4nHQ74V6Tc+vsOvG+tOah3WGb3/xt5GQOMkBS9ntsZ9fXyp+8ghBrG/bfff67G/w9b/u+vnF90Hm9xHKSsfiv8BXx/fNt8P+4Ge2HYd3xbF32jsB7rZvS0x4vYkMAVf7NWejJAEJ5IAcT17wUmJn7jDDDY6iaQL5nQBkNzu9QXhY/URdhRgAhMJmCoH4l/Ht+VDobtWFB+eEjs4JHiSBI192pCrHY1TrLmbx0Nf3K700tonkASg5gSFNiirg27zbGi3GNXLeuFoRt+F7lkwI4EdtGCSW66DkuhYSRIPircDrrp6/2noa56K00pim+FpqE63CHRK88VfqV1C/cxy1IOsK79y6fTTzlY8nDX5qrgfVWLrKua2vKi9L8x1X6w7sC0S+GC/geUS998XsxfUqbEN2mdCMeTMTsSLT6BreSR+Tqybq3aRTSrpx7nQRJHUpnmZc8ZAqNztsUPWI6ljxNCp5gNZzd7Owjwq/To2Ho8rEtJPnhLPM0RXmuOD+nCxLynLn7t2bpfMYzReRuMviQzNMlPZ2tz9QjmEyqPjVq+9wY+rCvx0Tt+PySuf43C8L+Cw9l1bFCNuRQLTGwR3L9/dEuegew0inBAEnDAc7KwWL24749HQpF8tiJxTv0NYtj6ZIv8aqHoBDzCSit4u1/tq81h9rI0o8LouYDg0wYB0Xni5oSS8Ky8NalIHjX3KkasdVG8Re9RYHIBfMpQ7M1gnl4DRi9CDd6wdGjisD1qjEHoOmq+uMmTBFGq763dUHsk8RBbM/g0G9zXdUxLZ0U1ByWZgI1ACL2EP++lmn0B9FfltdOwQ1isbXRi7K06kVR2Wc0HlR20dHFgfDJiIP+ojETbIXazI1Q6SeRZbJqjryqtJYuXqsX/ixEqO9pE6ax9ZngxtEG/aHflH1HAfLK/byST+SFnuGCjCLkD+OGWMKF1TaBIxaDyusTcpWfTH5PKEksKXyOMDwcbmQdwBrN8QY7EqC8iiqX5gfQRt1KdsW1MXfCrwon+zbQFc5yCPi3L4/uVr9e8J2Yht9VqPL516GdgwFsVXvu5tihFnn8DMHUBUyiBIMolfGxPUlcIASU7lrNqROuJVee0CHg2CNjisj07v/7L/aoB+gzRWH+EJDugDslujDZqwMZIlOsYIlJbcxQsfSdLH14mePECDsJWOazZWkNdQUKfj5cofQMhPVQmdvKoYykZr/6TCofKEdBm5/kBzOgC71kJmM+BEFGBHm3Pur2Up/tBOaL6hPgZNXq7kRjeaQtfKHNQLLgCcT97ZWdwu2Thu6j7ixxrPiQJscRxWGbjild1zV+6TzktfDplLSHIUkUFTNnRSDLX1GhmkzyDxgrTOfOXki+D1PAM+9KkZF2QOhGzaSmZkA0yzJqviN+Ur6og/RnQroV8V2a4uHUWYoLqSkkWX7EiCRqsz4ldZgWs90Pir1ffqmgd32vbFlV+s44LintVr1NI5l9pmRfYrtTiB+mRx4kZcgSTsZuD7pZs22rU8GCeKbBQel08bI84+gal9DREx3qIEpvzUnUhROp3ZwdFd//Uz/+cvTrZ3q1h8sfiDW6j8t/87eoE8uvBCAoYNA6MMUEJJoTr5s//4zs7OU32LqbH6WAVicl0QJccbge9H8pM3eGDt20EMlHTXF5lroaBxyOvlaAcJILVB2Hp8qzuQ7C/kkYLcyUM6WQsA7/jBug+8FipngpdE2Wjtn1QyVJ7QnAmevmoIFqqrrw/SeSK2Ge51afEbB8DipC0/lEwLnJxAxk2TKN4M1gE+1YNhfxB6zbjNTqsr6KbQsl1R3BRK1K36oF0UgDZOZUOldkJaTuLTkQ1vabvacogf17aR5DnFIjjHorLdF2h+CU6DgTJDMW1bdnFCqvEg4o8R3QrZN8TnuTehbkE3enwXV3PX+wsX+39Yddvad2qTvviT+7c/+r82702W6nZKFl1tQv5EsQHp20TWddK3PxA/vtnv4Xi8GsvC3L97Ya++e3fkP/p+jSuoNjbaRt9f3Slf2juraV1986S83n1r4DqXy7mp+reiuNnfQ49utK5GTDrHs8Tl3kQpP2gI+bAD9TwUI84+gakNvMDJHAyesfqw+1Bymw/ECXhZkIChKbvU4W/0V3nKo81srD76diFdEDpu5ORHzOLMy++DSPefG9zkr5Ljzgq95z4i8XH1V/fRKf/f0hb/FbrfETWidVP6L7hKjTXSDnLyQLLREZrLSEJF6nRgnazGWfdFWnSOa21JiCPyOzRfI+yfVCZUntCckc4LbeBY2Qzg9R2JbkELWaEN7eK/squNBeJ6UxBZICL9R+zPkM5AtkmwIQHqXTAmGpYd/iBIsD3IxyuSTwf+TP6arjY+ldoKSbnQSY+YeS9pHy0jtVdovUnLCxJ/Xe0h/lFiJ/v6JI0jJGOPyBwbeyJx7qrvSAyB6FbQrwIHMjxnyV30SXU0UFlKFp26DhzkiLGTYj8otPmgH1x1fRabVYM+FxiPMfVwsy1dboS+v3vEkDkusaPg3AjGbLljxLknMNWAkFMpDnKwHeS1DT9o3tE7B/mm/0Lx8+cu/3g6g4HtYnk5JYoeG7wdPB8+OSJhBxm4iD56WaBJLlx8g/o1K2eKGNFQ0Bhw0ElfIUdPHsQEYat+wYkQYaIR0skI/Yd23SPakcx5aZmx2OSSZ2jOQHZPaIv6+iFOOgYWEsirZ5UvteZr0s0U6Rig5RC9lyQNJO2HElPtOkL2CbHTkhOdQ31A7ZwoBgMSCjF+BtHPmCSURAckZYLJLOHCXtJWijKYHqZoEahD8LHQQIwivodOG2f79pFEoMAuiGXWXovRZCY9SbV6BuGE6FbIRiCMG/276hi90XzFGNC+pEVTsugSDKg/uL4enFPCV4elfheNB+sYZPyviqPKoOkX2oa2fJUPEXwstK9+ZJMlNK+H+rB9vl/+oUTKg6kAACAASURBVC6JHQXmtMMYl7tJESPOO4EZseBCFF4UPCOvvLVmSJ3MLN5xx57etmXxm7EXY9Ai18kuUfROhwYsMCqn4LhoX71otz9WH327kKMQ6rA4OeAFUJ4O0Dqf0HOI0YtxLqnbAW1EsqQxNNbCD65AOinYsOkb8zHnWUjvpL+DbNT2L5c8Q3MG0eGYuVfbPfGF/YMLFmRhiJxClvLXlIN0KJF9RoLpuk/9AeUkmzXAXYCiGAw4YaKNYVa6IT71I/TvGp2TPhOSdQ5J1mZfED8uZRBdzt/BXti92Nc/gb5FJXWQxV/I7iMJxRS6BPiRaliRuQzwD74NhNrMDh285l8H9281odd+RetzvU5JuuHflAmKAyNtJLKRJ9EVyJfXnY6aqynGUlKHol+SaqPKrA5yuYT+o5orFtb+mL5/PQ51XGjvX965eqt0gEJzA7V3oY0xiVzYWvjwPJx3AjMiw4ss7CQGCh3cocEbO6EJORswYNgITMEEZord3FX7Y/XRtwc5CqHzzhlsSAxJTJmxZE/dDjSOiZISlf4Id5R92Ty7yvK7Ndt6MeY8i9HJDbsEBD/+uZCjj5UL0jvX2GACE+hbaCEb6hfiU4cYIvVIfHNI7hS/I7Yn5YlRKMAbOGmHJI2lHwUKcQUTFcFFIjIGsXMYmKNBuUOcYn6XJLJSLDRiZGw/i4xjynbbdaV+Swr0jdF6I+Y4EIOimyQpdAlJSKH+WMwk4FdXuoIkdwW6OmpCMzUL9VpPuAbq44fMK0mMA9j2pUhxJ80EepGkCN6vJM32VZL0JDKiy0fN96/u0bTG3mVtcZtL2n1OM3IhLtsYI846gSkxRn0DmWORFNrp1iiVf2ad0HSvHli7//rqK9za+trPIQ4ADRjUTs0/mDApNFYfvdiQoxA4bzQ5niKITKVbSx7Zdno39CvxjjLiFGNs0aH5eOn0t6y1P5KOQcjx5NDJFMFkjC2RspGUg+arq1DCW9Jur28Cko6VmRy4NxbxSbE6jPjUoVeu3Hi85bp1u4jhDF5/HdO3tJkgmx3u2d6kCDJ2Q/WIxmxZKGWbkkRdU7bYOSy2GREfmEJY9tuS4fs6pRtgKWSR1oH4XWmd0nKrVxlzvAkFJubGS2AOvMUxhW3L2SaiWxJ/CG7CSNVwVe6aWwO9lUMXc8flEBfBGmgIHKYv4WSj2LYvhUq5IYkqCFIe7RdSt6isi9WMNa+nPm183Hx/pe/+gz/uQz+2sP9Dm7Bsj1koJkoZr4n0xRWKbZMJzJq0KJgAAxTpGB4qV39wwLyU6h4VzAHoF/CgMgZf4UAAjtXHZWAgvzNI4LzHlB1hKi2bOmjsX6yleyVmbKfY7BOasJYEUFDwItDJvjHYRl2F2LiOhxy9dF4M6LHcfrhKAicwxZsHsXIjz6c6NZriw1mI3F1lQb8viiWkMoF3b378wvkr13f2AXk7IsI+NNsGbcXwtQM+qC/sz6TcxiyX214M9SWYSJjBBkBbfiReyDGOPom5MOYHqe+mR+PfHH3rqbN3bqWco9L+oKc+kfmF6JYkgYnGiVIGHYu+6goDZ+NeTHWAJTWLpsxoTKXmgj4o8F2o7Ij+oeKmLI/2K2Xb67oE/NF2QRuFVh9VPoVuVCcfC/uF5ZfJxa+Eo4KHZIX8V6JxBsd2u75CLnEwvYtEJGAXJjB9W2MaidUrLu5U5g9jnBqoJOoFPDQBHMuUJwnH6iOsA4KJDh3ddgKEDBFq2GLL5wyUWkGTOFkTsh1j6ktnQiH9aVJ5Ukygk306MTU3ja6iNjv3/EJOTfr+Dr6ODeiRhp3+mYH7GJG7ESN0VS/75pOgX0uawEw134KJrmaXEzEHZd/aBOaUH3gI2ZIUdxammkerepB4oW8Dw+uW29n5tHul7k63+DvhTmJcB8uZOLkL2glYXPUDA6eEp9qcQXQA8cdIvaEYca2v2FpSPUyNB6862V6MPcmWg0VjDsvjzRRExHWEr0dC4sE5nmDvzXlgb/Z0+lt/uGJhis/415WLsjjhbOwNYvQHBa+5tf29MXdeNtsE4wiFuPpHtL5/ueb/imtZ9iaSXsT1kyE7uo0x4qxPYIaAD40pGEyIFx1+9/CvZflaqmO9Yr10wdaOWVzQGAXUAGi5g8yTJuLG6qMfL8QBSk4QTclNrH8DBXMGSs1mU7YD6ovYPkh5puwLqpPSwL2rLyC3pHNcyrZdDpqv7mGt/ZPKh4y9r7NPHnQspPIlKTeQBIP6nyiZFtMnyD4nlhcd4z5dgeZAoj6Asg/aWGgMYgZb8WyMPVU0t35Ecjos5SZxjKxaPy6Jn6oTfba86E6w3IvK6BMU7kOSd2vi6lg/g8oaU77XLmDJuWRxEOIDEH+M1IvMW2hxHzNQm89ecwmSs9rDK7lYLONN8WGCdDhENQV1FPKFwOEmkXQZC+Xol38DxF139TC6QeQPXxXWnEnxweKj5PurDSNrH1EmhqO0J2RHIf2ZSYzIBGatEkGj19ScqZKYPthyRuFx1CiACwn1Ah41NKEJhczWsfq4dN7y3UfBRJ+SG8K4r2zOQEm78AkFp6C+QPZBwhRiZsxjodfdEOcTYjMkP8hNbUskDKVlEDa+zpR2qS2jJOnQfGboBAA6FlJeScoxgZkEIzrGfQkraA4IfJakc6DsTGBKoDbKBN/cmPh+zhTxgiSBuWoHPE24Fi9VEhOaY+BYxxZnAvMwQTQOmiKJGXPdARRjDtyz3aV7SN2xugs+H4zVwXkarA+UL1vxXP3ypzILY3enSmKi6+NsgDsqltqQJcOnRj/41pA5tK6B9GcmMSITmPUAw0YqZtc3ZoJpdjbAhYR6AQ8ZmsTB9Vh99GOXeqJD3DInWDS6iQQzUoMfGzSF2gH1BbYPIY6pmSE6GWIzJDvITW1LQvyQ3xE2vt6Qo0fabpcNJh0OV37VyXNHV5voWMTIDT/LBCaMLMUY8wRmEuxQJTH2FGqoVTj8gafw65Qx7WufRXwfksCsYjN3Ysg98ygqW4okJupnUBljyjOBeZieZt5qT6TFjF39bPjjNO02kHmGskDqju87VEMwVsfm6TxtaBcRrF9YzgO9t38lnyZfcUiPsVPikLLEFpbMG20COFa29vOhdQ2kP0xghocnBHyoBjApFDR6fW3VJ2p2vu0uYD4Z7lGaEui9HOhCV8t9LOZdFMfqYxUkI3eNCCY6yC1rgkWjoUgwIzH4fTKkbAfUF7V9GKMvqE7GjAHIbRa6Cs1XB1Nr/yRzB53rQwt4dCwk8iUrwwRmEpToGDOBmQQ7VEmMPYUaahV+IHiXLJ70iJFH+izix9EEZu0LT1/RxONoXH1ooY3EhVJYicr12gUs4ZssDkJ0APHHSL3aeVsdXtnff9wacy96Kk07nHUiqDyJvE6ekwVSt7bPyueCOgrFg4L1m1LO5I9B/VIc2oo44Q7rbhMOHDMnJ9tfYciG+PxQYRZ7ie3ENecX37HF4jVj7C+k3Q3ZUUh/Es0LML7dro/4hIAPDRyo9EGjF1KS+kSm/Ya7L+LUKMeEAQUClUS9gB+beXNMxuojmiySBODoqayYeRHSY83vSDATMviDcxr4YEmonTH1patPqZkhzifEZmgMpuam1E/5lQ+ugZzzK5x02Ozh0Fihr6Nr2KmfGfBPEAPAz6llDTx4FPwa1IdEzEFbMfwKub87qrDfzTXGMfXG2FNtu5IvOWs/MKCVSfoc4vsk8VO73TrBVF5V3TMW8WEfbeJUyi2mXKJ7lKPXSb4PEt1t9hXxx4hupZi3y6TOnU7eMT7GAfHPySL08bAYXY18NsgIiZU19idSfvXjUL8UCczl2vctja7HbA5pE6dqkMCDIRsCjsnhlt2bqs6PvVcY87axxe/bH/aSznG/AfLC+SvXD66vkZOuM4kR+Qp5PaJBowfodLE8lXmXC7jzOTbgFWxwIaFewEOLpMTMx+rj0ojLEyKCiT6m7IgeS8tKjaivL2TwBw1swgTmchzFF5EjQXSIG/o6hmQhijjKmDHYRl1F2PixSznWTV3QJBxDsiBzL1RXSG9T/Q6Nh8B+ppKrrx5Q55PGEtArsUNfG0aC06LovbYAYZ2SW8q6kD7MtWxw0xOID8fuI2KztAkE1Mc2GWj9IxT/zsCu+T6D8yqJb8zZJqJb2nHumi8+KVtae4+1xZ22sCcSn7haNymJBVeFc7JAfHhKzilsFSK71v6kkBOtA+qXcv0dtTmktHmgvUgaf6Fj0CwfkXi96lbKb1i7/3roxDUwx4NcIP81kxiRCcxa44KDG6PI1QS05RddFv0WV8+tMXU1n7XWfE3yQR/QAKiDFHACJGU+Vh+Xia+kCUw02J5hQCBOBMbIDhhrUaI0dX3SeR1cfLYqkiSekOAlZgzGnGdSnqFyCBtfl4R3qM2u30H76KsIJpIQHc7VL5SFkxnZxU/qJ1BZp1rkrxehl069DHxduZcVlAhNFA+lbBO0O5PrjEbPkGe29f7LZfwkjhdiEggKe1sNgT+t4r5Mfgv6ZXKoPeViHtERSVn0NCSSQOtrH13YI34L8YcxcVCIbRXTL4ovOf29zenTLckSmsY8s3vu8tlQ++g8Q1kgMRVat6RvMWUQ2WPsT4yMmmehfkX4eNAXb3RFowtge7Px/eB4VPG+s68XQknLJlDA3gW5pIzXpPob2yYTmDXp4OBKB0RSLllCU+jM0AQZEjBsTCbslEdS5qCRi0pSAEbDRcP2ud0Lew+H9AKqU3Ghd6j9mN/dK6EfSQM0jQNbL+bTn8CUJ6KFc03CMbz43KhFNE8QZxkzBmPOMwlLSRmEja9Pa/+GZPELxb+W5TvSeVLXFb7DDumbdMNLwjSmDLbQLz7YvXDlxpj2UjyL2OeUnFO9bo/MW8nrRhKm4Cu1QTsnHYNU8kv6OFWZsF6EbcdUskvHsZJPGD/19SXMqZdCcPOo/SQyx9yzcP25xguK34x57Plzl38cIwtoFyB/jOhWTByE9j9hQlOsN9C4ol8hR9Z6CWNnlHtXeSRmirU/KeSV1gH1KzLnAa5hDrrg3gzY2VncDm8OCdd+c/H9+NtWuo9FAfYuGF8h/isVZ9AX8A7MHmMQHFypEdGUqxWnuAe+eBwI7gBFhwKGZn+hhWmkAY0MHtV99O0iLKUOEAq0I+5p8vKvDJW/l8QlVD5cLhTeqf67WHzk79qo/2rekDgaxHHGBI0Id0k7oBMWB44hG5BjrMcaA8TJeQ45koEhvu3fETa5ZAZtY3UKKHRnTW2L5B+sMAkWnyj7rvLoCeSdxeImiR3qk82Pv+N5s7N179ZlzJ/dBxE+qP62WPzBwf7v0hb/NfQ2AzZn5adkhniip6OGxhetK0USFrwnLRiDIfXF6kwKPc9Vh2QsU5yUyyU/4sel8VOfrOjmfbMe1F4ii9aYO+FSjwvmH3UL7abMSGIN9ceIbklixNSsV/VVelmUdys+BBS0k6s2kHFFWUCnaCPXK6nHAOESa39Syz5UH9SvyPV31KvkCn3YNt8PzY+I614Aexe0G5K4oql/c4gReQKzHpHg4I5hiOBgiwnM9bCgiRXt5Ms1RkgyLTb4hY5tC5wN4jjRQKk57wBjLXqFfOxEiu8Lqj9SXmONATrPmMCskoz4B0gE887rE1Z3/OIzhR9EAyU0kdCWEVkw9yW+xrTP6wUo9oXg4GYBsghw192IX1Xs0gkkmbN8PhiDIcl6yenlFLo8RR1BvxWxIBqjP4gfT5FAQDeP1gwUp4WQOTaXJDMSD2pfrz9IquG+EIkhEN2SxlY554QiERS0k2MkMCH7PjN7hMTKKexPTv1prY/kb5QlyHmga4GY5Ne2+X7I5whj/bYegXG0yG4g/msOMSITmMIEpk88LEzxGV+8us/S/1mY69zpjZuqv9vis/6rh7FBCTRRmcBcz+lciaG20UCCvVovZK+QBxclLUFi9Aw5TSRJHiABQUzQmCM4RZIb0rEcCliw+S1/fXasMUCDFmTxkSvQQ9h4GVLKjCUYDwhI5zeykIhZfK76ETq1Xdr9dyV3+CA2yCWj9nbPXz6l0Q/Erg5tDI3lXzYWJBdP/Vn+JeUwI8T2xG+SQXd3+m4HA2xwLgXr69OnBqdryzJ/cba/Pr1rFn9yQfMfq/BP+IaCRm8HfUjwXtSwLqSWCakP8eMpfK6XDbM3jd6Ai0tkjsX0zS80rSmuGzpV7nvR/mpt1zihtk0rtyJZV4mL+GNEt0KxqPetC7NzcxXGm+LvirKsv+Jbf8vAvyXxKcf/c7GbJbnsGhL3hFh06Q2S7NDUX81bNwbGLN50sP3XmP9U83dfZS7tx/VQLH7r/xt6g6IpP8JFq+uIPUxVFuqXwN9K5EI2dpv1ofFFrjnS7mMq3w8lMIU5grasSGzrnhXFQ4j/QsfwEOtgHHNIA/kKec+kHBxcxCnGGrxcio/0AQkYNhwDci+KcEJJjOiqDNJH7e4B4rQruQDjBCXTlIt6JOHhxZfoAuI4tYGMlwUZX2k7oMH+2L16elKSoOnS25wLhbHGgAlMmUVacvq6K634aBuWgIAW54A9agX94g/vSAIbdCNImtAdCEjDAxdgg9h+CYMhgVA+EnsHBrzOReruu/M+xiX69rD7XsMBNnjiQHQKv9NOA3c6u0Ze2T135b6wcqUrEbb1873/EvXjSPw0RBj2vY3KkLd1kDmm3VBC+yKZx6BtU8VBSKzVHEtJDKpZAwzZzPAc29A2UXKgTz/BmErcFtIHif+ITECI5d6IO8C3ECRXhyBcUtmfdNa/vyaoX4nW39pNiaoXwFse2+b7oTyOci2fY7wR/1UP4bQxIk9g1vYglMBEFm+qLxgeOGD5nWbIzh+S/EEChg1ns0UJTM0CEzNKSzJAwgAN8JDAWqlfopNPiCHVBEqpg9OmzoLBo991f999ofRu9E4+1NGji5uxxgDlpbUlKQM+hI1vF5V5fVLDFJ+2hf1CURYn5CfnNnuKjnuVEACCfF+/O05yZui+xzZ7dMEs8UvoRoqTCb6DFm0jlCTF7T+WiF5xx3mHk3/ruoHknEYXK310d466/6CJe9EC19WNxGKwrUbmku9rSGdS2jGpH5xCJqSfSCyaMoGAz9+6V2ismHsjGpkD/uSa5CNo4AknOA7SntRC/TGiW4MJTMCnehnj4lrktXq5T0HssEZ+3E9hGytozCx9UwPhktL+IDZSUxbqV6IEppcTXROs+lbHovIDIYjd06zTUvp+yNcIbfTGuvXS6W9Za38k1RPEhyH+a+oYkQnMWgMGg2c0K61ZbHkh0JMLSKCKOHZNYqxauEyfwAQXTnKHigZ4a8MCJDDhBTeYjED1WBrUQI4T2HVrG2dEh6WyV3oLLrhR57j8AvVr9etGwj+A3qB9QNi0pUWDFTQZKKQDFUPHF6o8dWHF/EC/cI7qL3LCEwlo0A0b6QJlNSSI3KEYwNeJcq7lkC846xjg9FcLY3eR04vIfAZ9NJ6oAD4q1Zo6ogQman8Q/mj8JdGZ1OYh2H/FYii1jKH6ED+eOoEA2oSDrgB2GZ1jkg2flSBoDCflp7Ft3o+4zbDHhzbD6pNT9hn4A6UNJUJiCES3huwmeuLLJ4o1X1eubP6Tp96Tx4bImgXYSAL0uzm/kdgK3TxFk95SP4jILJ0/IZs3xu9QvxImMKv1B/468AqJeGM66PsOQZbHXql9P+wDgPWe51AW9mkkRvRopHYUlR1dT+Bx/3pg+Qp5jyEJBs/IKxbLNq65BONZ6eum1eS09gng5E5Q5pajcXom/ANMpo02pk5ggkbUO9SFMT94/tzlH/eRqXcB9x93Z6UfEtLbLAayRCd31YfCnA3ddeQTsO502FnA6In1ayzHmSo4bY8jvpNcn8oIBe++HcW89pWLTk1oA0lpoNel72gQIXWaqrklfAjUT2GtWYqJg7l262jQ4XXMvf7x3SG7sVzE/dy1dbu4t4C9QzdsahnM3s7CPDp0Anop9yuusPgUoHROoLv0S25X3att/xQ6te3rdjHAw4CNrngg94PmTVSUmK5sKlUuf+NbCcZiy8TxU/JEQtypK/F8ahUMz3NMH7RyxDyH+PHUCQSNr/d9RU4LaeaYv4pgxywuDNkIn7wsrf2+1D4gm0m+j0rbVtkgY4o3mnF0FScYe5e1xUmpvH06hcQQiG6FbD4ai0t8arOPS//3tNRPweOJbcyL7W+zD2g86Pvg4o5nd89dPjtkQ8J27tDTYvmheBCIZ2JsYopnoX4lTmDip2UPeoy8hgz2cTLfj86LZWz7hIvlvtenC7G5CKkd1fgvyXpYtZ4IxIg8gVkDCho/nUL6qs1eHUAX/6+9U1k7eXc5tLV3SJ1YY9oPKnt7EsAT3+3I7RjzEx9Q1UFf8fcujLvTX6Tcd+cT6HSCzFGjDu9OrxuoAzCXzHx1FUBWfS7Ku934nQSSyodFBh2gYido1eY15wheKsv9362S5nWAtHPXcvdbvJivtLYwj4SSoquGwXGv5oS1+z/0clav3y52/qebH3c6OW90Rva2vnFPGZwemh9g8rsxDyvdScXd16s5AY3Mb2Rs25xQOyh1muhcR8ojbJB6U5ZFdzHbbWuCjmUdV53d+NUh27covuRuxr8Psn2KUyianftqEWTtK/4C/6aNilg0Q74IOzFTU64XbsWeseb15sdfKj+jYV1Xqjr1g9vrlbb1+0lrzL2RiQrxGKA2aM2/MG86GV9NpDPqzYYYuxG2ZfITWjFyxDyL+PHUCUwvt17/5ddYqNrwHyop7J4tFq+t1grerruk5T3L+OgkxF1xqk5j2yCZFIWRGALRrVAcFOFTr7kDD28ZW/y+HUMfrKX85prFxhPcrMJ1UB2Xg2++1QcAHP+X3Drg9RTrFSRmDtvQhpKC6zeFeid7BOqXIOeBCqbxy8vgSBzHaNqoYq8JfD/yKnaDdbWOb8bjEXHtxhBCdhQ7jNZoZ9wYkQnMGr0oeEbuYEAnP1heJG+zzoSy97YNOky4DxJGSqMhqVpXRuEA9TvhOhE7noIWZy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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 198px; margin-left: 1000px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Branch</div></div></div></foreignObject><text x="1000" y="201" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Branch</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-76" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;pc_plus_4&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="pc_plus_4"><path d="M 540 265 L 750 265" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-77" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 943px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><div><font color="#97D077" style="font-size: 20px;"><b><font color="#60854C">Execute</font></b></font></div></div></div></div></foreignObject><text x="943" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Execute</text></switch></g></g><g id="cell-alQhddrq2ZLo0OdN9rPj-8"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 486px; margin-left: 506px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 8px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">RegWriteEn</div></div></div></foreignObject><text x="506" y="488" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" text-anchor="middle">RegWriteEn</text></switch></g></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-9"><path d="M 143 595 L 143 473" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-7" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="143" cy="472" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-820M2oltKgqR7LxoU5un-1"><path d="M 1340.57 523.33 L 1340.57 578.11 L 1373.43 573.54 L 1373.43 527.89 Z" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" text-anchor="end" font-size="11px"><text x="1370.2" y="554.72">Mux</text></g><path d="M 1373.43 550.72 L 1378 550.72" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="1342.8" y="536.46">0</text></g><path d="M 1336 532.46 L 1340.57 532.46" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="1342.8" y="548.63">1</text></g><path d="M 1336 544.63 L 1340.57 544.63" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="1342.8" y="560.8">2</text></g><path d="M 1336 556.8 L 1340.57 556.8" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="1342.8" y="572.98">3</text></g><path d="M 1336 568.98 L 1340.57 568.98" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><path d="M 1357 575.83 L 1357 582.67" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-820M2oltKgqR7LxoU5un-5" content="&lt;object label=&quot;&quot; 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From 66e5a8cc509bb08407a7a79629a510c56739add9 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Thu, 28 Mar 2024 22:36:38 -0400
Subject: [PATCH 27/48] Fatten up the MIPS datapaths

---
 media/datapath-full.drawio   | 228 +++++++++++++++++------------------
 media/datapath-simple.drawio | 109 +++++++++--------
 src/ui/footer/component.rs   |   2 +-
 static/datapath_full.svg     |   3 +-
 static/datapath_simple.svg   |   3 +-
 5 files changed, 173 insertions(+), 172 deletions(-)

diff --git a/media/datapath-full.drawio b/media/datapath-full.drawio
index 9b9e89f2e..2f6572d75 100644
--- a/media/datapath-full.drawio
+++ b/media/datapath-full.drawio
@@ -1,9 +1,24 @@
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+<mxfile host="Electron" modified="2024-03-29T02:34:22.987Z" agent="Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/21.1.2 Chrome/106.0.5249.199 Electron/21.4.3 Safari/537.36" etag="qKf5UTrC8ZgmZlBglxSW" compressed="false" version="21.1.2" type="device">
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+    <mxGraphModel dx="1727" dy="1038" grid="0" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="2000" pageHeight="2000" math="0" shadow="0">
       <root>
         <mxCell id="0" />
         <mxCell id="1" parent="0" />
+        <object label="" stage="instruction_decode" id="3k0CTQaYQrwH0m9Gb4zG-12">
+          <mxCell style="shape=waypoint;sketch=0;fillStyle=solid;size=6;pointerEvents=1;points=[];fillColor=none;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;" parent="1" vertex="1">
+            <mxGeometry x="561.9999999999999" y="730" width="40" height="40" as="geometry" />
+          </mxCell>
+        </object>
+        <object label="" stage="instruction_decode" variable="imm" id="_5b_4j9nvjmzGaxmlqEA-36">
+          <mxCell style="shape=waypoint;sketch=0;fillStyle=solid;size=6;pointerEvents=1;points=[];fillColor=none;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;" parent="1" vertex="1">
+            <mxGeometry x="500" y="594" width="40" height="40" as="geometry" />
+          </mxCell>
+        </object>
+        <object label="" stage="instruction_fetch" variable="pc" id="_5b_4j9nvjmzGaxmlqEA-51">
+          <mxCell style="shape=waypoint;sketch=0;fillStyle=solid;size=6;pointerEvents=1;points=[];fillColor=none;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;" parent="1" vertex="1">
+            <mxGeometry x="333" y="575" width="40" height="40" as="geometry" />
+          </mxCell>
+        </object>
         <mxCell id="-I45d_4FKIcXNRPlzvKB-53" style="edgeStyle=orthogonalEdgeStyle;rounded=0;orthogonalLoop=1;jettySize=auto;html=1;exitX=0.85;exitY=0.86;exitDx=0;exitDy=0;exitPerimeter=0;entryX=0.5;entryY=0;entryDx=0;entryDy=0;strokeColor=#A34A47;fontSize=8;startSize=3;fillColor=#f8cecc;noJump=1;" parent="1" source="_5b_4j9nvjmzGaxmlqEA-79" target="-I45d_4FKIcXNRPlzvKB-51" edge="1">
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@@ -20,7 +35,7 @@
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         </mxCell>
         <object label="" stage="writeback" variable="register_write_data" id="mJyIEkHkixJ9JkuoTiU8-94">
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+          <mxCell style="edgeStyle=orthogonalEdgeStyle;rounded=0;sketch=0;jumpStyle=arc;orthogonalLoop=1;jettySize=auto;html=1;exitX=1;exitY=0.5;exitDx=0;exitDy=-5;exitPerimeter=0;entryX=0;entryY=0.86;entryDx=0;entryDy=0;entryPerimeter=0;fontSize=11;endArrow=classic;endFill=1;strokeWidth=3;" parent="1" source="mJyIEkHkixJ9JkuoTiU8-91" target="-Lmf1zb877u7wcXiO0Bk-16" edge="1">
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@@ -110,7 +125,7 @@
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+          <mxCell style="edgeStyle=elbowEdgeStyle;elbow=horizontal;endArrow=none;html=1;rounded=0;exitX=0.511;exitY=0.604;exitDx=0;exitDy=0;exitPerimeter=0;entryDx=0;entryDy=3;entryPerimeter=0;strokeWidth=3;" parent="1" source="_5b_4j9nvjmzGaxmlqEA-25" target="_5b_4j9nvjmzGaxmlqEA-36" edge="1">
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@@ -174,7 +189,7 @@
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@@ -182,7 +197,7 @@
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@@ -190,7 +205,7 @@
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@@ -207,7 +222,7 @@
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@@ -217,16 +232,11 @@
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@@ -235,7 +245,7 @@
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@@ -243,7 +253,7 @@
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@@ -252,7 +262,7 @@
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@@ -263,7 +273,7 @@
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@@ -283,7 +293,7 @@
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@@ -291,7 +301,7 @@
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@@ -299,7 +309,7 @@
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@@ -319,7 +329,7 @@
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@@ -327,7 +337,7 @@
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@@ -338,7 +348,7 @@
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@@ -372,7 +377,7 @@
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@@ -383,7 +388,7 @@
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@@ -439,7 +444,7 @@
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@@ -499,7 +504,7 @@
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@@ -605,7 +610,7 @@
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@@ -616,7 +621,7 @@
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@@ -640,7 +645,7 @@
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@@ -654,7 +659,7 @@
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@@ -672,7 +677,7 @@
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@@ -700,7 +705,7 @@
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@@ -708,7 +713,7 @@
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@@ -793,7 +798,7 @@
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@@ -808,7 +813,7 @@
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@@ -816,7 +821,7 @@
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@@ -826,7 +831,7 @@
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@@ -834,7 +839,7 @@
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@@ -849,7 +854,7 @@
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@@ -865,7 +870,7 @@
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@@ -973,12 +978,12 @@
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@@ -995,7 +1000,7 @@
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         </mxCell>
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@@ -1005,7 +1010,7 @@
           <mxGeometry x="910" y="1340" width="60" height="50" as="geometry" />
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         <object label="" stage="instruction_decode" variable="instruction" id="mJyIEkHkixJ9JkuoTiU8-53">
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               <mxPoint x="500" y="1170" as="targetPoint" />
@@ -1018,7 +1023,7 @@
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@@ -1031,7 +1036,7 @@
           </mxGeometry>
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         <object label="" stage="execute" variable="fpu_alu_result" id="mJyIEkHkixJ9JkuoTiU8-65">
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@@ -1059,7 +1064,7 @@
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         <object label="" stage="instruction_decode" variable="fpu_read_data_2" id="mJyIEkHkixJ9JkuoTiU8-78">
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@@ -1075,7 +1080,7 @@
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         <object label="" stage="instruction_decode" variable="fpu_read_data_2" id="mJyIEkHkixJ9JkuoTiU8-72">
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@@ -1095,7 +1100,7 @@
           <mxGeometry x="5" y="65" width="50" height="30" as="geometry" />
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@@ -1110,7 +1115,7 @@
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@@ -1118,7 +1123,7 @@
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@@ -1134,7 +1139,7 @@
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@@ -1156,7 +1161,7 @@
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@@ -1185,7 +1190,7 @@
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@@ -1193,7 +1198,7 @@
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@@ -1209,7 +1214,7 @@
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@@ -1218,7 +1223,7 @@
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@@ -1246,7 +1251,7 @@
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@@ -1262,7 +1267,7 @@
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@@ -1274,7 +1279,7 @@
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@@ -1309,7 +1314,7 @@
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@@ -1334,7 +1339,7 @@
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@@ -1369,7 +1374,7 @@
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@@ -1397,7 +1402,7 @@
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@@ -1412,7 +1417,7 @@
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@@ -1420,7 +1425,7 @@
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@@ -1447,7 +1452,7 @@
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@@ -1455,7 +1460,7 @@
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@@ -1472,7 +1477,7 @@
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@@ -1516,7 +1521,7 @@
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@@ -1546,7 +1551,7 @@
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@@ -1679,7 +1684,7 @@
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@@ -1795,7 +1800,7 @@
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@@ -1809,7 +1814,7 @@
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@@ -1817,7 +1822,7 @@
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@@ -1879,7 +1884,7 @@
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@@ -1915,7 +1920,7 @@
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@@ -1927,22 +1932,17 @@
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@@ -1960,7 +1960,7 @@
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@@ -1971,7 +1971,7 @@
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@@ -1990,7 +1990,7 @@
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@@ -2006,7 +2006,7 @@
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@@ -2024,7 +2024,7 @@
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diff --git a/media/datapath-simple.drawio b/media/datapath-simple.drawio
index ca5307789..dc0364d1f 100644
--- a/media/datapath-simple.drawio
+++ b/media/datapath-simple.drawio
@@ -1,9 +1,19 @@
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+<mxfile host="Electron" modified="2024-03-29T02:21:52.203Z" agent="Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/21.1.2 Chrome/106.0.5249.199 Electron/21.4.3 Safari/537.36" etag="Z89i9xkq2Ns1UFz6zufZ" compressed="false" version="21.1.2" type="device">
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       <root>
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@@ -47,7 +57,7 @@
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@@ -161,7 +174,7 @@
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@@ -225,7 +238,7 @@
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@@ -522,7 +530,7 @@
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@@ -539,7 +547,7 @@
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@@ -577,7 +585,7 @@
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@@ -632,7 +640,7 @@
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@@ -645,7 +653,7 @@
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@@ -659,7 +667,7 @@
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@@ -673,7 +681,7 @@
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@@ -689,7 +697,7 @@
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@@ -701,7 +709,7 @@
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@@ -715,7 +723,7 @@
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         <object label="" stage="instruction_decode" variable="lower_26" id="_5b_4j9nvjmzGaxmlqEA-126">
-          <mxCell style="endArrow=classic;html=1;rounded=0;strokeColor=#000000;fillColor=#97D077;entryX=0;entryY=0.5;entryDx=0;entryDy=0;exitX=0.589;exitY=0.358;exitDx=0;exitDy=0;exitPerimeter=0;edgeStyle=orthogonalEdgeStyle;jumpStyle=arc;" parent="1" source="_5b_4j9nvjmzGaxmlqEA-123" target="_5b_4j9nvjmzGaxmlqEA-125" edge="1">
+          <mxCell style="endArrow=classic;html=1;rounded=0;strokeColor=#000000;fillColor=#97D077;entryX=0;entryY=0.5;entryDx=0;entryDy=0;exitX=0.589;exitY=0.358;exitDx=0;exitDy=0;exitPerimeter=0;edgeStyle=orthogonalEdgeStyle;jumpStyle=arc;strokeWidth=3;" parent="1" source="_5b_4j9nvjmzGaxmlqEA-123" target="_5b_4j9nvjmzGaxmlqEA-125" edge="1">
             <mxGeometry width="50" height="50" relative="1" as="geometry">
               <mxPoint x="425" y="230" as="sourcePoint" />
               <mxPoint x="475" y="180" as="targetPoint" />
@@ -884,7 +887,7 @@
           </mxGeometry>
         </mxCell>
         <object label="" stage="instruction_decode" variable="sign_extend" id="_5b_4j9nvjmzGaxmlqEA-9">
-          <mxCell style="edgeStyle=elbowEdgeStyle;elbow=horizontal;endArrow=classic;html=1;rounded=0;exitDx=0;exitDy=0;entryX=0;entryY=0.5;entryDx=0;entryDy=0;startArrow=none;jumpStyle=arc;" parent="1" source="_5b_4j9nvjmzGaxmlqEA-17" target="_5b_4j9nvjmzGaxmlqEA-11" edge="1">
+          <mxCell style="edgeStyle=elbowEdgeStyle;elbow=horizontal;endArrow=classic;html=1;rounded=0;exitDx=0;exitDy=0;entryX=0;entryY=0.5;entryDx=0;entryDy=0;startArrow=none;jumpStyle=arc;strokeWidth=3;" parent="1" source="_5b_4j9nvjmzGaxmlqEA-17" target="_5b_4j9nvjmzGaxmlqEA-11" edge="1">
             <mxGeometry width="50" height="50" relative="1" as="geometry">
               <mxPoint x="705" y="750" as="sourcePoint" />
               <mxPoint x="735" y="460" as="targetPoint" />
diff --git a/src/ui/footer/component.rs b/src/ui/footer/component.rs
index 5ba72247d..68c9baa02 100644
--- a/src/ui/footer/component.rs
+++ b/src/ui/footer/component.rs
@@ -64,7 +64,7 @@ pub fn footer(props: &Footerprops) -> Html {
     let svg_path = match props.datapath_state.current_architecture {
         MIPS => match *switch_datapath {
             true => "static/datapath_full.svg",
-            false => "static/datapath_riscv.svg",
+            false => "static/datapath_simple.svg",
         },
         RISCV => "static/datapath_riscv.svg",
     };
diff --git a/static/datapath_full.svg b/static/datapath_full.svg
index 280bad613..b6efe2728 100644
--- a/static/datapath_full.svg
+++ b/static/datapath_full.svg
@@ -1,4 +1,3 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Do not edit this file with editors other than diagrams.net -->
 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
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04k1ELX3cHbsDcQGzp6648+RPF5IBnF8sOmZypu4f/8/VgOiCxhnbdQIEsPaMRDAI8N4nDHonHcyN4JoT+z/E18JDpJvFI8SiGiSEBWe510xi+8bWXd1kjZjreIb3iHZbQQ8e0R/EZn62yJJqvIJ58d1rfE6Fog8pRLnh1d/vFveC1gJvmyxTctaoBvyYXNcePkdWJMBb+i7LQVEEYalh5fPeK03ZwOV4umxKJrPombmKvl/RSHWlUSozIprOEaSle8hjBnVgxdPY8PL8XLUDgpk4ZtzQLkN6ZR8rwgkfJ5RBmI/Rc7/gdjR1IaJZLbgxo8CtgA+mRz+dEq1ZUY6wxCF+2Gq9nl0lDs2WLz0yyIBjhZEBzZRcZJvzFhtkKZm7va0DC7sxNEa/U7+qJ/FDuCqZzYTq0fFmj3ygH7R5ueCTz9jDE0P+/cIjbP6C1r4HN7mRmtNpATDkGb0d/GIdtH9REaTuzZBAx5lDTZ8tk03dPWXB/bAaL36vnUePwgyJEVVVaABA9/e03TjWEaIGIthVLSxQV9dlgKPBkLSE6VhMB7gIN5AXDqsMYzrmRsDBXJKu2qvXJQsOYECLkTpU3lgAfF/g6R5zsIGQmP9u1sY9ThOvagqSjjHuLb0Ff+hjCzVvNgEQCUUrtzwCdTpPjwDHGjmg+QCgpvD4FIoSXxTAmlxCDKwCdBw7wxj2/xQ8RGTJJ4g1wgKf0NbD5Agw5fkVuNcMiGU3ofqcSqQH8eZUSPEtspAYqfR4lHhZLfBdg72LUQybqgZKS+8zv/QVNKBclGjDQ6nvY8Sg6Opwo0J49T1LliR8cTuy12By5jx+6e13pbaG7l6Yc+UlqN1y8g2Z8/QjlwyIG5YYA4A0QHFvtt7NKQFxst2VXbRrv9z6u+MHy7J+2BUzybaEzwUeuRWUtQ92mh5nI7xWIVelcrO3FKjEK2lxrVWVsApCgiCBXHH/VUIMONPPcYg/pdJK9F2znVSKnzakY+86BlDWPlF0XoYyJl2esC3iaS+uhsK+1opUdDKwzvDD4d4o9mq8nysL4X+xA8a54AwHSzW2b7uPlTz/p3n9x53mne/o7mJ9zddH/8HNbXf6yyBy5wGvOpCfZAFr55IIBll8QYrLGnnrrJ0H65j41mwst4sGQVCdYutN3CHq4jc0A+vWd2b5lP75mKXI6Lyu645WXF0nvm9rlUz88Vc+8ZUR9iB0G+Az7xYqqEm88CzYVTT9X5fLtF5joirNYw7Gw42j6Sb54Ms/V78iPSLz2OPA9v9FXWze6UDR5HWLyLwrKzIXzWIp5MiGmcnHQO8lDp6LQfTcc1rp+pjM/tjiMe8TlGWcnHG4CYN5DqPSL1r7sk7AQoewl+0h5RQBMM4zPBEfaVeMxe5bsBBVkLMlTWgPlM81iVkN0r3rP5rNGsSCKOpmksBS13xaIh52Vw9EgFubiH326tYnfM7D1RAYncvFpfSkjO9VC0dNVP4MRTee1eESXMRP8NJ9dVwVosRR+efAU5y6HEQ0Wt6/l4+4/g3UlAzIMSBO/zMdoWu93IdVsQY9yy25GY7y95nw8EfN8RJR8L2ERQJ6FA6svDVHt/kUteENjVZrbPLkXT7/gzfzaSeRGx2quwW7HKZDHYuX1ioTVZLiejf7v65hB10vjiLq0NFq9a6eGkN2g3e/rSWJz8bO3SmG68fvhQ+rjjadBcrUOQAmvMhT+W25xOpFBIuBc195WPuEvWnq7YC6hV5qqtWH2HqBSQfN0G/63B8eRmNbI3AcN7GbbK+RLrHdOsKXEzAMCsEkGYy85AiaeeGflfApfJiKKzwsG09N6fTMK+Y4gLzmB5GVA8uYjANIMOzYYiDK7bAbg0nVxPwEf5OWkxc6yQNk55ASd/DU0jK2JKzEriFFiJJazsXpQU70+GX4BU73AB4PQb2AVBlZhRa+0KsZMuNGNUNfQOqbypcZiPUMPFYRaBM3Me0V8+lrU5Jdx5fXzOtEa2gp8NhkFGEJz7jaLkA8Nu5HnxeFM01I8Rm3/C2BsFA1Ri45B96g2ex8ETsqHL+Bm3Be0IybuixIS750nV6KWnvIgVBW1N54KCyN5E5ZQ2sD+QSr1r/DgIbNa8NACh+Xw1pz8qoxAkT6H9UT/4/M/7o1jyOvxYA9yJk2KiqVEw71ISAnqXWHY5Hu/yyCriC8F1a/zCj4Pgb5DhgcFIxTosOHmiSEkOdGlFnEmDblgfkkr27NOzESflV7pK0/iBpILzTHIjYmEdNk06hqYDeICg5MHmpJzcaqnYZdlzevujt9MEW8Q7RldfDZdBwIlnvbmqis6IllO5OdYQyKHcPMYB2sB70+K3VJi5V+q6olmA2dp4nY5KMgOlvvZsbuid3UhhtknaPpPXYy8+I3e6lJBbXdxJgTwbAH0DCcDcKphQFQx0NmMhQclo0HXSb+hZ2zBq2ZnLx8ez6QcFSR2TbFD9U731L5pH6tvHwJaI5EDPIEsKAppg/+1Hz+A6GtlrHnj0qW6AUmFKP1NNV55AxXdowk8/xO8Ueeyrm9OOj0vxKSojLkCSD/8tMUZF4knRcLZ6cbCPvplstlsyLqKNZqDzS6YmVWS1xjBdjCqS3xwC5jGMuM8a10ADxgAWkrntJ4s113zpztj9Q0m7hB7FyNP7xxvcAGXW4IFAmyoRvLs9Pce+jo11Ex8MoZbuetXF5fvkoZDLfpZhMf9a2zOJRIAKboQPTgCREJBFlZt74VfSxgQwM0m/G7811h+D7RB1m+J7qdCzd4X8AYYRXqJ2vWnQIaQSVDKqDE7+i8dYyzKWYkHeFenEBar3+fhuXMDTbdSjWnZKAQyWLwSMhHDn9BEsR7epdzpzY7FgchJSH1i46PI3NASuqoh7ePopCnihRUqcDFVxhvzArvYMvneIj56QEeNI9BAlqSL1Q3vU2WEXIJ/yN+LLOC9IqDGc7AbZbXRDIXuq4+ncW7QbMem5+iBOl5BRJXs3KXJZG7auFzxK25gQfGSMJgeHD0Nt80hztNqA5nLSPPzMlBYSfWg54kbvgEh6IbtAqRvII23X1JZs/yIlWPwBKA5ErJ9GDN1XQCCfKjLCeFwwKJIwSAJfYqVQSMW6dSPRIgaquz9v0w2tPOoHqAZeEQrDZlFMJwN3lWIqjgLO+A36dLoCUQNeF8RUHHUg6iO9k/T6JKJbwidUzalsD3c4+hLRBDalVQPiX9VA5LwhAUK/faoBEJkHYCa9uxDeAtoWyT/RJ6ZrXx/fSYgw3MCtb/vss5EZ5La5mpqowCS9Z06MHb1NSRMdYi9FoYbJAMVZUppRYurzDq9jaVMdvNoTht00V6GcwfxHGUu1cSuuxxNxjuxYMrkrm6jBdeqAYBp3JFp8XXIh1T4jtz4lU90gxnoscpHRCwlrAeXAc8i4zDItNt+3QVh1wY5VdeHOhqoLd3ZpODGfyrhnnmN/4T1rsvC//GQ6n7SNxcKETiiA/7PfszWP9I4nHRz7T+/SwmEKwjI+ybT2Rw8eMumYHrwlikN8UocN1X84G3R0HxbfDxMoe99HRyPi5jchffQ6S4YeOasKfcr+7QMrNcL464/dAKcM0ArlqQAttsdCdi1Vjd5gYQomuWPgdFU4EIzTabp3NNzWe7seFF2Iw3cHFY9jbozkHpziVp2+Kxk59GIqh15U5WEpzhWvCxX3K4HrZXvac0jwnntxop8cU9wPEp/ExZh6K6w/6JxRfUhOiT2hhGBrkWVyGGwCK3DbtsOaGe5lOWjK6VRf36kjUVeFbgqgQkAebcnwdCm/FSNJI8gVI03Df3jF7MjjbCtGRgeH/rWTJftbrqOvBc68XpQJOfZ6FfSl/rdWp9E26QAmu1ZkSHZAw/1SxWK75vsv9hPWS3M67PYmztmWC/osVxyG6+cuFzi3s8FSjeAddEaviAIQS/Ed4+5Tt1mluc14vj7Mc/EkRTl5LgcBLp9UPp08pECxJpt0ue7vescXsT0ousLTKM4IUhGnef3ObhGJKi+qkZ9rhgOspJvLBDPkHitKFNlJJ9etbvM/vFDwzKskkrjlsL+/x/aGWCrgrHCh2N5k14ocZe1ie9knsHJIAWNbhECkWeNkk1i2V3vypCjbKelIC1tEL+nPGf+lhYOnhUPilNtAiTRliUVy7+l3Z4kDrEo6s8QibVvsN2eJI6/YubPEIrkT84uzxJGX6+xZYpGMbH9pljj6Wp07S0ypz/rFWeLg65WyLLEdYvw3ssSRlyvJLDGd+4mMVEuT+Uhf/oHg9yrFplMci8e701Wzi5EpUFdcO/nm5yFRcZvlBf+FqPEOPZWXrg52LvS0dcIzccGPJIWtT4ZNrSmbHI5R7VZRM5AvANgFx8L/uov/IxQ+gdrmhansVqZHLEDqsrkLMJ86ZyghTpXNAEEHZCDnHc7WKkd9grInBPyWRjlXFGC3A/jANyBRQpfU98O5MvJRhYN5YCTncey+hocz0ssk0LsrCwPOJzR+HetrU3FeEGauPQEP9PAUZAo75HZOzpJBiPed6Wn0csKxQYWW/YfXUu+qNuu0wDZfnX5+DQzhxu7/Tq2PE5/lA4KnXPyZPg/TJ/160weAp3T8GtvHavrsMDiltg9IYTngfq7xGzFZv9TG+IIWxvrx9fJSZeoYw3loC4R7OA9lq6L6EM6PlmeJ58mF8pBPTvQ2ULTpByPH8DAtY3E8ZPnPdwnhu4gqmWb/bb7Lj4rbT4hDVOfoYllWIyE+ZJ56ke7AHhDt6KGdG8JNio0X0WW8CNUUJeaBZGSAsckgIdRWA183JJpQRnVD4jNTeyP6Z6ZCmCkaJ8MvM1N+417SZaYiaLzAqPEpm+VCGg+U+hibzQyJ5zFDYabdBqDi9SMRpBoyjM7NAB3ZUP5RCOA0pIg6iuaPKaQiJBSB7y4NTEqGT84RDy+4jtklLpC9R3kp2PBC/ILINLh08Sfr6ErT1Tnn8ZIy5am3EZIFUefU4J658wZcWMvoedozQxYWmqkhh5lS8oB+dI4nhV4ApACx6MsDEnLWGaWF1PB8Pg3TtgHdX/YU+fNp+/E5HtmylaT0/ThmN4LCO4Kp04Gi+rwdFQ80Jx4oMIobI54ignOiAGD1YzAZo9Ldmi+WBsNjC2BgIAk+lSAaqgDbvpzbEULOnloAVejp1xCcyyGuEGVvZwsIeAE1dkU8zhOgcK1Z9exP8/YPwtYjvHDZd1FlDRsrwGcbxjkA64LDlgzbGttbBHFg7yGdEBJ8k3e3YgFSvgkWjTK7nr6urDzdyXhpQIrRxkeTs8DDCzjmKRKRwB8ZE4Qy3hpO9WDnjOM1kxJpJvP5n2QhJZ4WEokICyU4FSrg83ywO8QYoKBUg5cZoWgO/JL4mVAYagLF74xQUEpStZh6AZtaw2OQM96JHvgKmwcqXiBFJJCWpqvcXB+bqvOD8BTxxFPteO3WcaeoMykVJ5pi+10xoqmS2pBjj6bIiaaCFCnfs5+F/f033/wP/DXoqrDuCMeMrvgoaiD5YKWI1zMEv0IVfDbb7GIilwtigmOFJAwx4bhsjJ4nVaN3bkAO0Dt7hBw+gIwk6MTOiN20XDH37nmtt4XmVp5+6COl1Xj9ApI98/VstWgw+u69O1S5gVswzA6dp6E+cEjJ05y3Ap+x5J7igVVezBfypubNJ9b1+yFPuDgNh4PpwnpmPmSENPLBDHLj2BPkPZGgy2GwP6zSie9Msdsddru5uLttRnNhKQxNDIi0PW+i5H1ccyE5PHydw5dzP+76rbX9cQW6Hd+/v+T2+Q/HXRbFhYfwG545zrRCROBi85meMgvahQoOZkH7xPPQkgSrDtyPanavDkwUqoXvZqVDNnTvACdXNsxcy26D1Y9q1I1URuo99/SvyNi9yPh4j9iLjBkL00gCtwT0PAmlVBNSSs49pnND7zQ7ptw2AYMmSt4d9QnVq3HI74ZzxXluaSqszap21PWD4d4paJBF0Hya83+KoCXL/0EXNJByQWOzHJTdRsKUuLDsU2w3u60NnCoBgoIZYYnivtMmFBxdeu7xreQ+3YV1ILLiNg+5Qg6CyU9G5qPVl9YcZI8hMZ7TjG2vbrE0xu3B8H/zt+d+a1Lula7r3f5cvV8PvxZfan2pCFdL5alaKBcLLcUQrhp3MxOSZuBp8jUaZxfd2hfMqfczMOl187Pca6dYkW8vc5VZ8UHJmZDRGN5e/4O5SU0e39bWlfeX7uft7fqlvq69tjtIL3y934zb6vWstloLi/asu60IN+3tTQmprYlYzz7dVjpVo9aotPNFcFk0v07ppfoqfkrz2aZWEM17PHzmem2tOynO3+TL0nqZG6JaVnysbgRBbTzedDet4stn/z27FRfm58ib0XGuUDZvozeMliCWlmj5YLx3vhot+DL4KAvCc6Vdu3kf3pVy0nsZVHPv3WnhStvM4fV1S5iNy6vOQ/tm8jhrXb9J+Sej/7zWsrl+L98f35t3Laoj8+/c1+P9tlAvqdvZ5+jaEi1YgpVq/0M0sb73LjwP3r8Go2mtIz8PkLFoj6WcRdtn/vd//qkOlrkLGZcgfR/heyUmMsAtfj+kB+hjG/bhu0jPqPjG9k4owWMJJnjxxrRAMwUShg6y0NwxGEqwE93f0LBn6CWQ4s2YTxIbEcWfJTh0T0uAVT5uRDsMCGUYES2Gi4022E5HnY6MurOyo1VjsRrGQR78o1fPuXiIXDxaR2dcfMKjkzF3pFNuujadwc55Z6Ulkbx5SdLRwED320OU57iW2Eqa44+Hl3/sfIiZy1hmZx2Ip2qR3PCVRMwRFm1lOE9TsP3FKaas9e26HjRit/nTcU718PBlW662LPjQqjDzwVzRSMNnPIgSWzSCM5KkeStB9qahCEg0QLZwCxkUPCXgC4Wn5dMCxloiSaFKEJkAhDop9ciHxS/VeR4SA1nDQCY0hwExbTVhuCKn5VFGshLUcCK42Ic2TJ52elq/ZbfBDaGqsRFyVg9GLVaxby1h9YNJUb8bG6O9WrpmV9vHjEtzfuKUe3N/pyKZH2cfCvCBUNwjJB3Q8A6ZxLpzlFhjeSgQskcmnI/PC0uoe/nazJX5lNpZG9vnS9MFNCFV32/Mmuts2bCcbUSww5RQ9hz9cYi17op/jp+Okxq+EY3wyhQXqxy49wlPtsuaiOlAoBpRHmBs2usAKMw3oE5rg6BTiy15OP2jhAmgcaV25BKYdMlTRfwDaYl77TZX5NYiI3cM/QaRkjB8jIEP0p+taYAG4p6uRewJHAFvLEWAV0TEKMPkdFxCqBMv/zoVCt41YASmBW9vDjKeELedKpka4lQtxrjeDJv8iZJiYU1RWog0UHK+6uGoi6saHt/I9FnSbVKIO60DHfFUCDOq8P0HOvVDlFAmJEEm6aciifZWPsAa1D1WCb5CIHl+TuIClETPFXKvTzlJXpWmq+zdy8M0PamtkJ2yiGdflqrKzpzUQZKiGn8si5r4eISoJYSKd9X4+XcqQ7jCLsC/NhZLj2grBUWIQJVS59wS3g9juj8oBpPvhHxYZimfTUZRUJhnaa+30nnX7f6WVg1/3A/sjKsI47qTKdPdU88PHwKmIVeY5pbsUkJmu4JgLOlYh9yB8Oyx9YVchfsOhItviZciyCLMhNysJTivZFnKCIH96ehbt/QcIq3SBHNPU1GsTjxGSSYHP8ZWcOqZf3X0Ypu/70oOXXI/f0Xif0Xiv6BI3BtL0lEkTv+MIqGzf0XibtUvUVf57EXi9C9AViv9yiJxTquXqiLxuNqF9/xDKU7BcO0PDpHP4ZtkOXeOJXhiBC8Ql3wTI8QVqoRJf0oTI/+Nea5xJEbwXJgEfuBs+hDg6TPj9VyJEfgfSoxwH9DJmBiRRIVbYkRSY0qFnFU7VO2HuhayV1GyyHVbyN7x50xUxexmpGW4DRAI/fJhHiU3YIJfge20p9YzUb2HtP55Ju7JU81FSH65Z6KmvgeYY+hmz7B3AG548KTRPnmibOy+B8FWI2FTmFg9DwrxjSpmTtuk2SbTB65xIt7WGUVGRF62CiYthsrFJIdnoJCcV8En/FAVKv1M7VpSJYiI8CPYOmdIfQS420P0dMdcvq2RZX3WIL2fNqZU41quh+xkMd/OVI1609ir99bWWrb09oeba7HzKrCzvIXmR3gXlMgOeXXsM3cxsTTEBOzOupBdUs00VGeCUlCpLe7Xxq02XlQ+B7dPs+Lo5YKVP0BLin8EEuN8cPxzgdJ4ojMmVWFQECD4sF2cX0Pc/Qi3rIgsQkVFqipDSdYEr/2XkDkSqvwHaA8LsjtDVQ/bGJ/qh5cepbOrUCU7sgpHseXAegPI6pDogTrFE4JkpK5RIvUQfPqMrhFZIVZebYjHuOjrnZ3EWk+xoy/6x0dK+EXETnr98NV2rxyyOKNNz3z6/YwxNNd9brlRGb1lCXl7mRmtNpC2GMPBtGYbK/PnKz+fO0ACBWNcUSlEqSplVeJjO9RibJrl4HBkRIXzJK3Y5hTS8JZTzGZPmjqHqxFNuv7aWWNsZwWChJXQHwtm+OdjaR7fk4nIF8XN0lQdNxdvYZ7SNHansLt7PlzorDOIThaD1xMnPWybdunkidtDoU6fuC34MWfAvdkvx8aaeRFA6qPSMEFhnGRKDFYlggmwtxbTMxE+lDt9/B7p9wO5IDSeqocqW+Xjeckog3U0AUcSMJVY4RKFAy48PDErPiuvWlqqD1S8IEdAfqUEeA9+8Cug9jP6RQ/L+Vd9EKIuEltzFB95S3zFBwGRFfhUfbHz/BKRyL5rkIyNNKUgKDtc9Ofz/eYOlm2imIMbJvItmmTCTzrNL2BlmToibUp4flVRoxUT2NKP90Yw75LiMQwCRO1l4EKFtNRUdozFcjDWGVm0AUx7kMOvNvJ0B4DiCXk5Qu5Vy9QQTEJAFtXA6s+k4u3S5KNzeyMsX0bvpfdmq4pA7gJopIYnNISZrmIISBlJFRSkmTBr/o2NmpchzJiHYEhmJYSPrpchtvnNqc4IQYX+Rml3sjirNc8tc0siQtHTMKkH/WlQ9qk99Shu9ZCRlgF7lDhgBSZlWsZ8SgihWKRaxjuqZJ8eLPICEXlfYDORulyQSH0eJFPvBHM+EC7Qrt9b+F+383+27qWQKt/uHuVSkAREVePioB13W+wapEMBfJooxLoLFj+I82TyVPhBbhD87Z4kB8EAUlyUJDE4OEh6m37yAhlnc/LyFSiXI+xywFY7fc6Aoz2ZzidtY7GYzDNsega9w/m/5I8rbssAE8gf2xTLiMjnn1USvYc1PGAyz3aDSfms+KwkSQwbvhH9qiLIKCd5HoUJ+AIjOtlyq3ojus8FSUR/3CpIRb695al2cJDg+OPXfsvb1RFZy6JjGCfhkkglZrPERXwK8W0ppGhn1hkfvfCurP5zSNy39iFuEWIsvjovdnr3S58fO0MN7+HYyxceLFXmvSkxIaykiDVjDwnlVpLXBhbH5rxwlUi2Hv4VpyZTnArOPWwFsLDUpgDOeNa3c2o+Dg9xGjPE2esePxE+zjweAeLwemDWEbrBKV2IDx1tTgkfH2J+GBW+b3htjlab5nJi/cPiWEi/zbFgKDF2hmpAg6qsAMn++weUI0rM4Z2S6r4+QKHwTWkh8mkTmt2cximKUXBGHySTRlqhGGk1uJHmnEdtzfVxu9/sDvUeC9jIPglVmtK4FtMFLGzzBTLXXt1DE9wpaoRzEXjpP62YwOWBs7aiJVNNRyRw7W3/wEafuJMqxGPzyTeSvGeZARn3ubEreFceND7UyeeXka2teiMkaJvr1qRGm2lIVh7YdQd7LbZu2bWkam5eAUtdfbgw/xUs3T5LWUJI3hRgyyqXOgUEoHNT9AJw0QRFwu6K3SG2qgXv5rQDnpugP1gwlm+ihCaeJTdXOrAHqXhxsPBsiI7gMtqWwN9moHgKNAMHWzK+YyAeyhvckRe/AjqvSKTm6/ik0+/TcvBdvy34cZXs3WAflwIFjzE4AJxpATqDnWNrubXNwXj3VTtMzqt3pBw/jLnFr6ro+ONHY3MuQqhINecuSwK5O8LniYPtL+KVFLVdqZ3bVZksdmJsHmpNlsvJaI8EIRAF99CWljh6ocpw0hu0mz19aSwyB/2ZN+OCFwnv3RXtTZgTeBEp8BKCrIU7vDChSkLTSvjjzk9wephLmGwFPLfTIxHmVEq83eNUxH2E92++SGhgw/MKosQ2SyuhygXuOJf24q8w7kzQPb8ES8DY4z05oXkjpgjgIq+gENNTSRJawkdAbGNMOKAz4hlguiumUwN7xtiY68OmnbdjSNL4sDmlwMvgFE3wzdjHSVpn6KiFOJKKA1u9TlWe2o6f8k1B+3v8tGDo+2dLBUwnQz98KGvFyQ3FEznpGF19tZs+6l79sXNi9ve7sKp4OLkhwJmIhpStR5lCpSbGxVZ4TD/+mtXXxx0Oy89jsRFRVgjI1QYCLVkXWzmYwqDspFt1XFLgXEHr9Yq+NFd2vHsFCmTSFHqbM3yhKObNdS1Sss2K90oLoYc5EK4VcavQ9aJ8ap+60+/ypx2jT3c+GTVH+mDcPPYFsjhISkKT3WJIwyiO6iUUNfsLY8/KKMyhCX9HJZzfj7OpqZoPNRpBv6bIic9lC9SDongHCL8wkwNVXlYV4844ToZKRyLHE0J3kDk/mZXuIyXQGyXZmdDYec2wgNCiK4GBo0ImtKIW0rDnUZR0OQGmt+dkxpBFLZwXoGHb6qqK3ShRWoCg5dCsHVacJx+nIEUSuI7F03lgypEwOg8cpp14OwznYiELzu6F+wmSt2dBXCDLPPeHWIO2H1G2DV3DbFoxN6eMClKx6k+FEmPb+elT2Md7VhImm8YIMah5Q8gOkcawNVk7zLn1gnmgP5kPvsxF0oduUMGr4NsF5KBXfYwryNGKw5lw6uJakjtNqXR73W7cVyvDr8/b3IVE2ZemwhRg5ZFPqH4b8wSUsD1bSJYyKjxpS3V6KlDOIPmUPYHF3QiMvViaxKaYc2dXCng+BtX29a7nYzGj7OTfTiJkNDZGe7WkAkQwZ0r9dftN/IuCk0262JrruzlkS21KN4fs75Fu18POiZCuBwcXAwAMWZDINs9CgvG4GB6wgedorcZU5vIiNfU1I670htJpT6nogQQp6Si1B7/7pzlU7vgQLicLcWosOzRy7xPHrlAUnwuAgKJdgOTE2brCDcRQvWvbf2H6l990IXy37bjLmo78L3szb8CxGOoP5u2nVue5ZKXWxmIZJmQMj8bsG2RqPGksCnsbziwrYzTLzFvKxDSuI+0s5/iO+MyYgeCdKrt7XuttobmVpx/6SGk1Xr+AdJHS2ZvFLMrtas94IyxRwHJ8Jw5YizB+Y4kyuTcuMiPq6pJN1sTqJkESe5wAJCqOaFZTw2XNAmX/nYLVVdtGu+0pCCEpaumVjBRKby89jH3oiCJlJIHIXB3lFTlIZjW2MmXKuygZbG+Pkf3AH+XYBF8lBL9q9PZxM00BEh9g4KmtPHgBoGgXTkadX4DNd8FC9DA8AGxLaFdwRsAqLl6ae8mjeyV1yFw8qNQW92vjVhsvKp+D26dZcfRi8znE7kGRjV3JqixlFkkqXJHYmBZjraVFCJv/JNqh/7l8EZgSZyT4zlpQ/T/xd8To/g4/vnx7BXydEZiUN6JqGWykhwhQJixnvgozWEQlagljGOl3lKarH+B6QJ6+hyzawTdfTqIjr5jtVKZrkhJeokDfWefLRhTZnzmpOfnORqm2E3P4/bgHQGP32FU8hgHW4w5nRlA1B04iEBgnmVCRudaBOnXJFozYp4hoJo6Bw1RI62+n0GtixpqIh8k+LzY5hLB386kJwMZWYuenYUPBY9F//X4CB0dSlmQHPzteCQPj8irj20tgA+oYa8l8i8/jTYmFjk+pKS6VshngCbRpqRUDmpdgh52cjWTZwRmA5cEkgLu3yY3RJnxY+jIxMHNC+cJ84HtyTkubBKuJTWjpC+PcTJz0phkPDefk80rHWYR8fV4JZ/dMioeTEUo7TiilIoTIvhEbR1muN2+y05uVkQQ8h2FF202lPx7K8INoDmhCAIpXeeE+KTNXsqfDiyDYdVUpTpzm7fhCGfsyPqNMRfzLx9rmQBUcINFSpugYzTnUDM1WE/vAxd5XzZonoOlmJ7z2YfOnnvUvScYsW9hzgHxrDjQ6lAuW9m+1v+wc6L9DsZze/ujt9N4zsqVnVz1Qi4d5EDLCcWc4agoES6xglQnntgZYkya9fpedUDC9TRrhZkPzdbxtBPpxTRoYy8dx5ymMqw2Ub1cbS0UocgbGlCXBBmLIPnWXsoKfr3A0FkkrsMjeOxFLZLzfWkGK3fBw8NxgSC6uZJw8e2fAt73B1uq0KCveJKSErQnZKSt/DeUXDbv4WCTdExkOCxfHWRXzZTpDYA9V5uPj7LYBYoiAgYbdNWURMAaZ1FSD31whf7IJDo6Pmysjq5ri1QESR8hLcV1+RMiLt1iGRUOfkFdQMubLMGqmkO1LoAOvKeseD3Y+71CXrkDkzAoz5NQtVsrcIQ51/oYj8HA4mC4sTVr3B0vjaarv5HM916dOnQkSTKpekL0w32Iw7uUOjH+7PVRXhWHfjlEVrINHOAjJKUOeSiqAbXrP072/MB9O09gsTcRiQUvIjJb8HcyQZPLhsRBQqnI8dSAlWKhibMnHFEdg+h48jygLtI2Z2AdAF9ul+nVzKSrbK6m++SiWV88tO8Fyhhq1fZgDZYcc+kihe1F7cA5f6uOg0Nect0mbbRVJOhhiWRPf8v82KT+qx0WVztfjAgav6sDQH43exW1+O5oXPp9vL2iegcvaLkwD1B4M/7epvXVaUrlXqgjgsz8pTo3Pd2mum1JSehy8zy4fX97v7+pWanvVrykV/Wum1lfq02v7FpnaAa2kd79X6H3MK7eT16x8uXqpGFfXm+lrSR4Z13r/GRZfa4/1u/t6djoHH/n2be1OazceKvdXnU5e/qqN7zrV8kjpAeX+XgWF9bB/o1cH0sfypdfuF8W33GXjbYBmvfa2cHOvrh9ncuXzNa9mS4PX+6wxqnc+StlGY72BN7BTrj/kO/Oq+ZlqrQXU3h409IasT7lZlR8KIujnn4V87n0miPnazcviVqtVb8y4NVf/EK/769Lj8321U31VjNZjzvQbcrNcRWnVW6/b2aNeeb3qtadPWXFx1StIQjt3rT3fXV5e9/XZ6K3wLA1u7ka1m34rq4JZ4bGdrVWq8vxu9fz4mStnh63t3b2RHQ+UXlZQn9aPhU+4WorVZdsYPV8uu2+dNnpedtbl3pNQe9HqpZeuWO991u+mZetjXG3F2dPXcpg15u2B+eXerisPnXqu1rE+ZF1ZaGKlNKt2pfHq2Tz6oixnddOQlizqt9zYaswvVSuGXOgrT2JDUUbZjXWPwqdY6NVXTw+9enH+/NwaSfO7x2lD7rek7KMlK2Lh//x9RA5apGFTG2VVYdIiu6r7PG7clzGfHNw4o9McjEZGZ6AvsXorqpJ6t2+fpa/DzdPbxWOh0vtEPofJzlKfFyTtrBf4nZslDut7VH02TzVBinQ+OozwiykCpT5pezfw28y8mdpwYWuDdblTH9jzf0Oju4yW/aMImqsW8ho8qzizArxqvPEyGui8Q+LZPk+h8A5U/6pIT7jMJI9iO0WMzYf003V9+NjvdOYz+HY3ER4699q88s7iUoYwOHiiwZ3swcEJxTo2QKJ5/ipsiYjSq9SRDbUjea1tkCyDyiejIGlOmA9JByxh+UpA9DHz6wKiig9pKoJW5ZgrgpflmBBtr973i6KmFARrMxkv37HfsIW/cPgE1JshQZWlvF8tUGmHYG7lP4e3neOvmCcSn8WvdsjEliWmQhiyWUp2QMxgG2pMOOrUJhtcHVrMARqh6kz+k+NDj5RWjgE3yF29WONpqvS615R1Bp8u4vSjBbpwsPaC9dygUD1Qwe1+1Ds+ks4k18eXHU/wPynteOkMZVguLWcdm7TTmpJ/mbQXbfbDP0HmKMgACLKPJGsUFu3YBJnsPP51glw+EHP+yTFPORZFmCY51n6/HNe/J4T8iTJPUZaRHySDQ6YxqixzZrbsYkVkD6+l3lVt1mmBbb46/fwaGMLNBV86S44Z830V07+4KsioD4OSIKcWkNnVg2fOkOM1V0AWHClsSsk48LzAmfOm9PFrGSChPTmD9Td+M7gjbsAlP9FBSX4ZV/d1/8u4MgRa0Ku9GUgSWTeW+sZ9ZqgUUwGVgchQOPI8AUp1rReIxk5ogo/1lVBYiid8bKWEYAbbIYqtPoz6CAN2B3TP0x1AypK72nDaHxRsg4URR0bdH8TyRzz2B8kNYBoPo0JduOQqAUWoyCqCAlI1JMtAOfXBnJADgmOO28QGd4rLwNyFrESXjpoH2nnpmLmr4OzdInTMUiDrZWWc6i7oBdCnTMK8IzE/PVJXOptiBCjA++Pt9HPbFOS1Uf69wklUW9IWG/ov9g9h6Q3pcXkSZvpiV9rJfCmkmqIHnZEpj1gE6eLJ8cKa9M71PEzsFP59T+zkNcEFathTh/ZTP+30oDT9oOD19HxGHJ/0+1BG8lFXNu3DWlz5L1VJgshKkgsqsEDHI/rjOUsr6HxA5nSbS0h5Xu+M4usA3DvCp8eFHR+uSdinSdf4cEZ9At6ZsjOmiwPMnURsusAk1/SnREmVeCvA2cfKiZhLCH3GtlKuUCAmx3zLp6kPmtKCJedEcCHsMiPJp0R8SaE8tIoPYYIk2tOxIvNiO9b3+Kxjr5nmhlXe9Ai/JavvL3LBXUOA63ZipdTJSgg759AZ3UMXly/onD9XwkrcbXQZCOgXzvpHqfGMUKWYJiJhFXZgO4B4Ps68VQbyKvz2s3l395WHoQz6uQ14nE+NtWHU1aC5ksS4DIAEVO30vzAhi8f8tEAcXKE58aiPnEamQD+RUcKT4VIghk7KipRBZNoluFZgW28iYNOIwG6poIrYG0XyMdkUjEoKw4X+dJdVYutS8E82zffyEscgd83LCT5Q0NiKtv/teWfQLnaG6PBS9SDPQObklQARn8RzROdTt4RWV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font-size="9px" text-anchor="end">Read Data 2</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-20"><rect x="1860" y="735" width="270" height="255" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" stroke-width="1.5" pointer-events="none"/><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 178px; height: 1px; padding-top: 575px; margin-left: 1241px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">Data 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Registers</div></div></div></foreignObject><text x="715" y="1488" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle" font-weight="bold">Floating Point Registers</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-35"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 1432px; margin-left: 642px;"><div style="box-sizing: border-box; font-size: 0px; text-align: left;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Register 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transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 68px; height: 1px; padding-top: 1439px; margin-left: 725px;"><div style="box-sizing: border-box; font-size: 0px; text-align: right;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Data 1</div></div></div></foreignObject><text x="793" y="1442" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="end">Read Data 1</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-40"><g transform="translate(-0.5 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visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 1409px; margin-left: 642px;"><div style="box-sizing: border-box; font-size: 0px; text-align: left;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Format</div></div></div></foreignObject><text x="642" y="1412" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Format</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-9" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;fpu_fs&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="fpu_fs"><path d="M 790.5 2157 L 882.75 2157 L 882.75 2147.7 L 935.45 2147.7" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><path d="M 943.32 2147.7 L 932.82 2152.95 L 935.45 2147.7 L 932.82 2142.45 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-20"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1438px; margin-left: 427px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div 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stage=&quot;instruction_decode&quot; variable=&quot;instruction&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="instruction"><path d="M 735 2157 L 735 2202 L 735 2157 L 735 2202" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-19" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;fpu_fmt&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="fpu_fmt"><path d="M 735 2110.5 L 855 2110.5 L 935.45 2110.63" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><path d="M 943.32 2110.65 L 932.81 2115.88 L 935.45 2110.63 L 932.83 2105.38 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-22"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1408px; margin-left: 422px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [25-21] (fmt)</div></div></div></foreignObject><text x="422" y="1411" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction [25-21] (fmt)</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-15" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="735" cy="2110.5" rx="4.5" ry="4.5" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-16" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;instruction&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="instruction"><path d="M 735 1861.5 L 735 2110.5" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-23" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="735" cy="2280" rx="4.5" ry="4.5" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-24" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;instruction&quot;/&gt;" data-label="" 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rgb(255, 255, 255); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">DataSrc</div></div></div></foreignObject><text x="781" y="1284" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">DataSrc</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-87"><path d="M 1582.5 1875 L 1642.5 1875 L 1620 1875 L 1640.45 1875" fill="none" stroke="#9673a6" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><path d="M 1648.32 1875 L 1637.82 1880.25 L 1640.45 1875 L 1637.82 1869.75 Z" fill="#9673a6" stroke="#9673a6" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-146"><path d="M 1140 1860 L 1395 1860 L 1395 2000.45" fill="none" stroke="#9673a6" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><path d="M 1395 2008.32 L 1389.75 1997.82 L 1395 2000.45 L 1400.25 1997.82 Z" fill="#9673a6" stroke="#9673a6" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-147"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1241px; margin-left: 776px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">CC</div></div></div></foreignObject><text x="776" y="1244" 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style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">Data</div></div></div></foreignObject><text x="1145" y="1253" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle" font-weight="bold">Data</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-91"><path d="M 1350 1290 L 1440 1308 L 1440 1437 L 1350 1455 Z" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" transform="translate(1395,0)scale(-1,1)translate(-1395,0)" pointer-events="none"/><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" pointer-events="none" text-anchor="middle" font-size="8.25px" transform="translate(1395,0)scale(-1,1)translate(-1395,0)"><text x="1355.5" y="1337.13">0</text></g><g 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rx="4.5" ry="4.5" fill="#9673a6" stroke="none" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-101" content="&lt;object label=&quot;Sign-Extend&quot; variable=&quot;fpu_sign_extend_data&quot;/&gt;" data-label="Sign-Extend" data-variable="fpu_sign_extend_data"><ellipse cx="1879.5" cy="1908" rx="19.5" ry="16.5" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" stroke-width="1.5" pointer-events="none"/><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 24px; height: 1px; padding-top: 1272px; margin-left: 1241px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 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pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-125" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;fpu_destination&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="fpu_destination"><path d="M 903 2284.16 L 935.45 2284.35" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><path d="M 943.32 2284.47 L 932.74 2289.56 L 935.45 2284.35 L 932.91 2279.06 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-25" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><path d="M 735 2280 L 780 2280 L 780 2304 L 838.5 2304 L 831.97 2303.54" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><path d="M 839.83 2304.09 L 828.98 2308.59 L 831.97 2303.54 L 829.72 2298.12 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-26"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1514px; margin-left: 430px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [10-6] (fd)</div></div></div></foreignObject><text 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content="&lt;object label=&quot;&quot; stage=&quot;writeback&quot; variable=&quot;fpu_register_write_mux_to_mux&quot;/&gt;" data-label="" data-stage="writeback" data-variable="fpu_register_write_mux_to_mux"><path d="M 1170 2542.5 L 1140 2542.5 L 1140 2589.75 L 1119.55 2589.75" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><path d="M 1111.68 2589.75 L 1122.18 2584.5 L 1119.55 2589.75 L 1122.18 2595 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-143"><path d="M 1185 2475 L 1260 2487 L 1260 2568 L 1185 2580 Z" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" transform="rotate(180,1222.5,2535)" pointer-events="none"/><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" pointer-events="none" text-anchor="middle" font-size="8.25px" transform="rotate(180,1222.5,2535)"><text x="1190.5" y="2507.13">0</text></g><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" pointer-events="none" text-anchor="middle" font-size="8.25px" transform="rotate(180,1222.5,2535)"><text x="1190.5" y="2555.13">1</text></g><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" pointer-events="none" text-anchor="middle" font-size="8.25px" transform="rotate(180,1222.5,2535)"><text x="1229.5" y="2591.13">S0</text></g><path d="M 1170 2503.5 L 1185 2503.5 M 1170 2551.5 L 1185 2551.5 M 1260 2527.5 L 1275 2527.5 M 1222.5 2574 L 1222.5 2595" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" transform="rotate(180,1222.5,2535)" pointer-events="none"/><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1690px; margin-left: 815px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;">Mux</div></div></div></foreignObject><text x="815" y="1693" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Mux</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-150" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;fpu_branch_flag&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="fpu_branch_flag"><path d="M 735 2280 L 735 2766 L 2302.5 2766 L 2302.5 2094.55" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><path d="M 2302.5 2086.68 L 2307.75 2097.18 L 2302.5 2094.55 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864.95 920.73" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><path d="M 872.82 920.71 L 862.34 925.99 L 864.95 920.73 L 862.31 915.49 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-146"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 608px; margin-left: 545px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 6px; font-family: Helvetica; color: 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stage=&quot;instruction_decode&quot; variable=&quot;rt&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="rt"><path d="M 765 858 L 787.5 858 L 810 858" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-144"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 563px; margin-left: 551px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 8px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 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pointer-events="none"/><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 16px; height: 1px; padding-top: 615px; margin-left: 867px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 8px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: normal; overflow-wrap: normal;">&lt;&lt;</div></div></div></foreignObject><text x="875" y="617" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" text-anchor="middle">&lt;&lt;</text></switch></g></g><g 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891.88 Z" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" text-anchor="end" font-size="16.5px"><text x="1423.07" y="930.74">Mux</text></g><path d="M 1427.48 924.49 L 1434 924.49" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="16.5px"><text x="1383.93" y="911.17">0</text></g><path d="M 1374 904.92 L 1380.52 904.92" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="16.5px"><text x="1383.93" y="930.74">1</text></g><path d="M 1374 924.49 L 1380.52 924.49" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" 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944.07 L 1361.82 938.82 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-1iY8ieaQeg-KCymrDvTK-5"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 1px; height: 1px; padding-top: 813px; margin-left: 651px;"><div style="box-sizing: border-box; font-size: 0px; text-align: left;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Zero-extended 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justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 367px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><font style="font-size: 20px;" color="#97D077"><b><font color="#60854C">Instruction Fetch</font><br /></b></font></div></div></div></foreignObject><text x="367" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Instruction Fetch&#xa;</text></switch></g></g><g id="cell-alQhddrq2ZLo0OdN9rPj-6"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 755px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><div><font style="font-size: 20px;" color="#97D077"><b><font color="#60854C">Instruction Decode / Register Read</font></b></font></div></div></div></div></foreignObject><text x="755" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Instruction Decode / Register Read</text></switch></g></g><g id="cell-alQhddrq2ZLo0OdN9rPj-7"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" 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width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 1612px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><div><font style="font-size: 20px;" color="#97D077"><b><font color="#60854C">Writeback</font></b></font></div></div></div></div></foreignObject><text x="1612" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Writeback</text></switch></g></g><g id="cell-OYFgHVqdb1yCRpvzie0J-5" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;fpu_ft&quot;/&gt;" data-label="" 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1627.5 455.25" fill="none" stroke="#ea6b66" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-LNPOl51hBx1QrpeweeW8-17"><ellipse cx="1609.5" cy="455.25" rx="4.5" ry="4.5" fill="#ea6b66" stroke="none" pointer-events="none"/></g><g id="cell-Xk8ovzeAVugm609xIboV-51"><path d="M 2278.9 715.85 L 2278.9 882 L 2378.6 868.15 L 2378.6 729.69 Z" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" text-anchor="end" font-size="16.5px"><text x="2369.79" y="805.17">Mux</text></g><path d="M 2378.6 798.92 L 2392.44 798.92" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="16.5px"><text x="2286.71" y="763.63">2</text></g><path d="M 2265.06 757.38 L 2278.9 757.38" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" 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933.74 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-cFokdKJ0tUmjFj_bR61B-23"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 12px; height: 1px; padding-top: 626px; margin-left: 550px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 8px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">31</div></div></div></foreignObject><text x="556" y="628" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" 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border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [10-6] (shamt)</div></div></div></foreignObject><text x="706" y="854" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction [10-6] (shamt)</text></switch></g></g><g id="cell-q4aLnZXwkiyl6f_3jFDg-5" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;read_data_1&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="read_data_1"><path d="M 1222.5 821.25 L 1275 821.25 L 1342.5 822" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-q4aLnZXwkiyl6f_3jFDg-4"><path d="M 2043.84 205.73 L 2043.84 296.69 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1065px; margin-left: 245px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 28px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; font-weight: bold; white-space: nowrap;"><font style="font-size: 28px;">Floating Point Unit (Coprocessor 1)<br style="font-size: 28px;" /></font></div></div></div></foreignObject><text x="245" y="1073" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="28px" text-anchor="middle" font-weight="bold">Floating Point Unit (Coprocessor 1)&#xa;</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-16"><rect x="645" y="500" width="170" height="190" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 168px; height: 1px; padding-top: 595px; margin-left: 646px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">Registers</div></div></div></foreignObject><text x="730" y="599" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">Registers</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-17"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 542px; margin-left: 657px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Register 1</div></div></div></foreignObject><text x="657" y="545" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Read Register 1</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-18"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 573px; margin-left: 657px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Register 2</div></div></div></foreignObject><text x="657" y="576" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Read Register 2</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-19"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 633px; margin-left: 657px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Write Register</div></div></div></foreignObject><text x="657" y="636" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Write Register</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-20"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 665px; margin-left: 657px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Write Data</div></div></div></foreignObject><text x="657" y="668" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Write Data</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-21"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 68px; height: 1px; padding-top: 549px; margin-left: 740px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Data 1</div></div></div></foreignObject><text x="808" y="552" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="end">Read Data 1</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-22"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 68px; height: 1px; padding-top: 642px; margin-left: 740px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Data 2</div></div></div></foreignObject><text x="808" y="645" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="end">Read Data 2</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-20"><rect x="1240" y="490" width="180" height="170" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 178px; height: 1px; padding-top: 575px; margin-left: 1241px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">Data Memory</div></div></div></foreignObject><text x="1330" y="579" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">Data Memory</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-28"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 58px; height: 1px; padding-top: 618px; margin-left: 1252px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;"><div>Write Data<br /></div></div></div></div></foreignObject><text x="1252" y="620" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Write Data&#xa;</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-29"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 58px; height: 1px; padding-top: 530px; margin-left: 1252px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Address</div></div></div></foreignObject><text x="1252" y="533" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Address</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-30"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 58px; height: 1px; padding-top: 532px; margin-left: 1354px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Data</div></div></div></foreignObject><text x="1412" y="535" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="end">Read Data</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-34"><rect x="630" y="1390" width="170" height="190" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 168px; height: 1px; padding-top: 1485px; margin-left: 631px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">Floating Point Registers</div></div></div></foreignObject><text x="715" y="1488" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle" font-weight="bold">Floating Point Registers</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-35"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 1432px; margin-left: 642px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Register 1</div></div></div></foreignObject><text x="642" y="1435" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Read Register 1</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-36"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 1463px; margin-left: 642px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Register 2</div></div></div></foreignObject><text x="642" y="1466" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Read Register 2</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-37"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 1523px; margin-left: 642px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 68px; height: 1px; padding-top: 1439px; margin-left: 725px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Data 1</div></div></div></foreignObject><text x="793" y="1442" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="end">Read Data 1</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-40"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 68px; height: 1px; padding-top: 1532px; margin-left: 725px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Data 2</div></div></div></foreignObject><text x="793" y="1535" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="end">Read Data 2</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-13"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 1409px; margin-left: 642px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Format</div></div></div></foreignObject><text x="642" y="1412" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Format</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-9" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;fpu_fs&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="fpu_fs"><path d="M 527 1438 L 588.5 1438 L 588.5 1431.83 L 619.9 1431.81" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 626.65 1431.8 L 617.65 1436.31 L 619.9 1431.81 L 617.64 1427.31 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-20"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1439px; margin-left: 428px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [15-11] (fs)</div></div></div></foreignObject><text x="428" y="1442" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction [15-11] (fs)</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-5" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="490" cy="1438" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-6" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1408px; margin-left: 421px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [25-21] (fmt)</div></div></div></foreignObject><text x="421" y="1411" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction [25-21] (fmt)</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-15" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="490" cy="1407" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-16" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1281px; margin-left: 781px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">DataSrc</div></div></div></foreignObject><text x="781" y="1284" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">DataSrc</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-87"><path d="M 1055 1250 L 1095 1250 L 1080 1250 L 1093.63 1250" fill="none" stroke="#9673a6" stroke-miterlimit="10" pointer-events="none"/><path d="M 1098.88 1250 L 1091.88 1253.5 L 1093.63 1250 L 1091.88 1246.5 Z" fill="#9673a6" stroke="#9673a6" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-146"><path d="M 760 1240 L 930 1240 L 930 1333.63" fill="none" stroke="#9673a6" stroke-miterlimit="10" pointer-events="none"/><path d="M 930 1338.88 L 926.5 1331.88 L 930 1333.63 L 933.5 1331.88 Z" fill="#9673a6" stroke="#9673a6" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-147"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 1240px; margin-left: 641px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">FPU Control Unit</div></div></div></foreignObject><text x="700" y="1244" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">FPU Control Unit</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-32" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;instruction&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="instruction"><path d="M 490 1241 L 575 1241 L 630.98 1240.7" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 637.73 1240.66 L 628.75 1245.21 L 630.98 1240.7 L 628.7 1236.21 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-28" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 1518px; margin-left: 931px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">FP ALU</div></div></div></foreignObject><text x="960" y="1521" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle" font-weight="bold">FP ALU</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-43"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; 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variable=&quot;fpu_sign_extend_data&quot;/&gt;" data-label="Sign-Extend" data-variable="fpu_sign_extend_data"><ellipse cx="1253" cy="1272" rx="13" ry="11" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 24px; height: 1px; padding-top: 1272px; margin-left: 1241px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 6px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Sign-Extend</div></div></div></foreignObject><text x="1253" y="1274" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="6px" text-anchor="middle">Sign-Ext...</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-115" content="&lt;object label=&quot;&quot; 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font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [10-6] (fd)</div></div></div></foreignObject><text x="430" y="1517" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction [10-6] (fd)</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-132" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;fpu_fs&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="fpu_fs"><path d="M 527 1438 L 527 1523 L 550.9 1522.92" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 557.65 1522.82 L 548.71 1527.45 L 550.9 1522.92 L 548.58 1518.45 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-129" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1690px; margin-left: 815px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;">Mux</div></div></div></foreignObject><text x="815" y="1693" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Mux</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-150" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;fpu_branch_flag&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="fpu_branch_flag"><path d="M 490 1520 L 490 1844 L 1535 1844 L 1535 1400.1" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 1535 1393.35 L 1539.5 1402.35 L 1535 1400.1 L 1530.5 1402.35 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-Xk8ovzeAVugm609xIboV-67"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1835px; margin-left: 594px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [16] (branch if true/false flag)</div></div></div></foreignObject><text x="594" y="1838" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction [16] (branch if true/false flag)</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-168" content="&lt;object label=&quot;&quot; stage=&quot;memory&quot; variable=&quot;fpu_branch_decision&quot;/&gt;" data-label="" data-stage="memory" data-variable="fpu_branch_decision"><path d="M 1560 1354.5 L 1570 1354.5 L 1570 1255 L 1579.9 1255" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 1586.65 1255 L 1577.65 1259.5 L 1579.9 1255 L 1577.65 1250.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-151"><path d="M 1520 1329 L 1550 1335.1 L 1550 1373.9 L 1520 1380 Z" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" pointer-events="none" text-anchor="middle" font-size="5.5px"><text x="1523.5" y="1345.5">0</text></g><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" pointer-events="none" text-anchor="middle" font-size="5.5px"><text x="1523.5" y="1368">1</text></g><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" pointer-events="none" text-anchor="middle" font-size="5.5px"><text x="1539.5" y="1387.25">S0</text></g><path d="M 1510 1343.25 L 1520 1343.25 M 1510 1365.75 L 1520 1365.75 M 1550 1354.5 L 1560 1354.5 M 1535 1376.95 L 1535 1390" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 475px; margin-left: 638px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">RegWidth</div></div></div></foreignObject><text x="638" y="478" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">RegWidth</text></switch></g></g><g id="cell-LTwac0_y5pkam7bXYz14-31"><path d="M 775 1340 L 803.63 1340" fill="none" stroke="#9673a6" stroke-miterlimit="10" pointer-events="none"/><path d="M 808.88 1340 L 801.88 1343.5 L 803.63 1340 L 801.88 1336.5 Z" fill="#9673a6" stroke="#9673a6" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-LTwac0_y5pkam7bXYz14-26"><ellipse cx="673" cy="1326" rx="3" ry="3" fill="#9673a6" stroke="none" pointer-events="none"/></g><g id="cell-LTwac0_y5pkam7bXYz14-27"><path d="M 679.6 1316.8 L 673 1316.83 L 673 1326" fill="none" stroke="#9673a6" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-LTwac0_y5pkam7bXYz14-28"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="556" cy="542" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell--I45d_4FKIcXNRPlzvKB-46" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;rs&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="rs"><path d="M 510 542 L 533 542 L 556 542" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell--I45d_4FKIcXNRPlzvKB-47"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 533px; margin-left: 570px;"><div data-drawio-colors="color: rgb(0, 0, 0); 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 16px; height: 1px; padding-top: 615px; margin-left: 867px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 8px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: normal; overflow-wrap: normal;">&lt;&lt;</div></div></div></foreignObject><text x="875" y="617" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" text-anchor="middle">&lt;&lt;</text></switch></g></g><g id="cell--I45d_4FKIcXNRPlzvKB-52" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;sign_extend&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="sign_extend"><path d="M 846 616.5 L 866 617" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-EcFWI_t37yH4WxkEMuTb-6"><path d="M 855 480 L 1057.5 480 L 1057.5 470 L 1285 470 L 1285 483.63" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="none"/><path d="M 1285 488.88 L 1281.5 481.88 L 1285 483.63 L 1288.5 481.88 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-EcFWI_t37yH4WxkEMuTb-3"><ellipse cx="855" cy="480" rx="3" ry="3" fill="#ea6b66" stroke="none" pointer-events="none"/></g><g id="cell-1iY8ieaQeg-KCymrDvTK-1"><path d="M 920.35 590.24 L 920.35 642.41 L 951.65 638.07 L 951.65 594.59 Z" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" text-anchor="end" font-size="11px"><text x="948.54" y="620.33">Mux</text></g><path d="M 951.65 616.33 L 956 616.33" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="922.46" y="607.28">0</text></g><path d="M 916 603.28 L 920.35 603.28" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="922.46" y="620.33">1</text></g><path d="M 916 616.33 L 920.35 616.33" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="922.46" y="633.37">2</text></g><path d="M 916 629.37 L 920.35 629.37" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><path d="M 936 640.24 L 936 646.76" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-1iY8ieaQeg-KCymrDvTK-4" content="&lt;object label=&quot;&quot; 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width: 1px; height: 1px; padding-top: 813px; margin-left: 651px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Zero-extended immediate</div></div></div></foreignObject><text x="651" y="816" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px">Zero-extended immediate</text></switch></g></g><g id="cell-1iY8ieaQeg-KCymrDvTK-2" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="645" cy="750" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-alQhddrq2ZLo0OdN9rPj-1"><path d="M 484 9 L 483 1995" fill="none" stroke="#82b366" stroke-width="4" stroke-miterlimit="10" stroke-dasharray="4 4" pointer-events="none"/></g><g id="cell-alQhddrq2ZLo0OdN9rPj-5"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 367px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><font color="#97D077" style="font-size: 20px;"><b><font color="#60854C">Instruction Fetch</font><br /></b></font></div></div></div></foreignObject><text x="367" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Instruction Fetch&#xa;</text></switch></g></g><g id="cell-alQhddrq2ZLo0OdN9rPj-6"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 755px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><div><font color="#97D077" style="font-size: 20px;"><b><font color="#60854C">Instruction Decode / Register Read</font></b></font></div></div></div></div></foreignObject><text x="755" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Instruction Decode / Register Read</text></switch></g></g><g id="cell-alQhddrq2ZLo0OdN9rPj-7"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 1143px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><div><font color="#97D077" style="font-size: 20px;"><b><font color="#60854C">Execute</font></b></font></div></div></div></div></foreignObject><text x="1143" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Execute</text></switch></g></g><g id="cell-alQhddrq2ZLo0OdN9rPj-8"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; 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justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 1612px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><div><font color="#97D077" style="font-size: 20px;"><b><font color="#60854C">Writeback</font></b></font></div></div></div></div></foreignObject><text x="1612" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Writeback</text></switch></g></g><g id="cell-OYFgHVqdb1yCRpvzie0J-5" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;fpu_ft&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="fpu_ft"><path d="M 540 1468 L 540 1509 L 550.9 1509" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 557.65 1509 L 548.65 1513.5 L 550.9 1509 L 548.65 1504.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-OYFgHVqdb1yCRpvzie0J-2" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="540" cy="1468" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-OYFgHVqdb1yCRpvzie0J-3" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;fpu_ft&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="fpu_ft"><path d="M 490 1468 L 530 1468 L 500 1468 L 540 1468" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-OYFgHVqdb1yCRpvzie0J-4"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 1469px; margin-left: 429px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [20-16] (ft)</div></div></div></foreignObject><text x="429" y="1472" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction [20-16] (ft)</text></switch></g></g><g id="cell-1PVsNweK9nsPviKSqEmU-7"><path d="M 775 1340 L 775 1328 L 846 1328 L 846 1213 L 1310 1213 L 1310 1219.63" fill="none" stroke="#9673a6" stroke-miterlimit="10" pointer-events="none"/><path d="M 1310 1224.88 L 1306.5 1217.88 L 1310 1219.63 L 1313.5 1217.88 Z" fill="#9673a6" stroke="#9673a6" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-1PVsNweK9nsPviKSqEmU-1"><ellipse cx="775" cy="1340" rx="3" ry="3" fill="#9673a6" stroke="none" pointer-events="none"/></g><g id="cell-1PVsNweK9nsPviKSqEmU-2"><path d="M 673 1326 L 707 1326 C 707 1322.1 713 1322.1 713 1326 L 713 1326 L 724 1326 L 724 1340 L 775 1340" fill="none" stroke="#9673a6" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-1PVsNweK9nsPviKSqEmU-3"><path d="M 1291 1226 L 1329 1232.1 L 1329 1270.9 L 1291 1277 Z" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" transform="translate(0,1256.5)scale(1,-1)translate(0,-1256.5)" pointer-events="none"/><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" pointer-events="none" text-anchor="middle" font-size="6px" transform="translate(0,1256.5)scale(1,-1)translate(0,-1256.5)"><text x="1294.5" y="1242.75">0</text></g><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" pointer-events="none" text-anchor="middle" font-size="6px" transform="translate(0,1256.5)scale(1,-1)translate(0,-1256.5)"><text x="1294.5" y="1265.25">1</text></g><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" pointer-events="none" text-anchor="middle" font-size="6px" transform="translate(0,1256.5)scale(1,-1)translate(0,-1256.5)"><text x="1314.5" y="1284.5">S0</text></g><path d="M 1281 1240.25 L 1291 1240.25 M 1281 1262.75 L 1291 1262.75 M 1329 1251.5 L 1339 1251.5 M 1310 1273.95 L 1310 1287" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" transform="translate(0,1256.5)scale(1,-1)translate(0,-1256.5)" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 19px; height: 1px; padding-top: 302px; margin-left: 380px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 6px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;"><font style="font-size: 10px;">4</font></div></div></div></foreignObject><text x="390" y="303" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="6px" text-anchor="middle">4</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-8"><path d="M 1000 525 L 1000 570.6 L 1013.33 582 L 1000 593.4 L 1000 639 L 1060 616.2 L 1060 547.8 Z" fill="#ffffff" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 582px; margin-left: 1001px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;"><div>ALU</div></div></div></div></foreignObject><text x="1030" y="586" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">ALU</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-25"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; 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" style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [10-6] (fd)</div></div></div></foreignObject><text x="430" y="1517" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction [10-6] (fd)</text></switch></g></g><g id="cell-cFokdKJ0tUmjFj_bR61B-22"><path d="M 587.57 580.33 L 587.57 635.11 L 620.43 630.54 L 620.43 584.89 Z" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" text-anchor="end" font-size="11px"><text x="617.2" y="611.72">Mux</text></g><path d="M 620.43 607.72 L 625 607.72" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="589.8" y="593.46">0</text></g><path d="M 583 589.46 L 587.57 589.46" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="589.8" y="605.63">1</text></g><path d="M 583 601.63 L 587.57 601.63" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="589.8" y="617.8">2</text></g><path d="M 583 613.8 L 587.57 613.8" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="589.8" y="629.98">3</text></g><path d="M 583 625.98 L 587.57 625.98" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><path d="M 604 632.83 L 604 639.67" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-cFokdKJ0tUmjFj_bR61B-24" content="&lt;object label=&quot;&quot; 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font-size: 8px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">31</div></div></div></foreignObject><text x="556" y="628" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" text-anchor="middle">31</text></switch></g></g><g id="cell-eaMoe0dZ3GEupYeplDxx-1"><path d="M 805 98 Q 865 98 865 138 Q 865 178 805 178 Q 835 138 805 98 Z" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-eaMoe0dZ3GEupYeplDxx-2" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;lower_26_shifted_left_by_2&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="lower_26_shifted_left_by_2"><path d="M 675 162 L 675 165 L 709 165 L 709 118 L 805.4 118" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 812.15 118 L 803.15 122.5 L 805.4 118 L 803.15 113.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-yYPQ0_M2gV9F3_eBWWuV-5" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;imm&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="imm"><path d="M 572 750 L 510 750 L 510 614" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-yYPQ0_M2gV9F3_eBWWuV-6" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;imm&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="imm"><path d="M 572 750 L 600 750" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-3k0CTQaYQrwH0m9Gb4zG-13" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;shamt&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="shamt"><path d="M 572 750 L 572 850 L 959 850 L 959 796.17 L 963.14 796.19" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 969.89 796.22 L 960.86 800.68 L 963.14 796.19 L 960.91 791.68 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-3k0CTQaYQrwH0m9Gb4zG-14"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 851px; margin-left: 706px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [10-6] (shamt)</div></div></div></foreignObject><text x="706" y="854" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction [10-6] (shamt)</text></switch></g></g><g id="cell-q4aLnZXwkiyl6f_3jFDg-5" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;read_data_1&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="read_data_1"><path d="M 815 547.5 L 850 547.5 L 895 548" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-q4aLnZXwkiyl6f_3jFDg-4"><path d="M 1362.56 137.15 L 1362.56 197.79 L 1398.95 192.74 L 1398.95 142.21 Z" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" text-anchor="end" font-size="11px"><text x="1395.41" y="171.47">Mux</text></g><path d="M 1398.95 167.47 L 1404 167.47" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="1365.1" y="156.31">2</text></g><path d="M 1357.51 152.31 L 1362.56 152.31" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="1365.1" y="171.47">1</text></g><path d="M 1357.51 167.47 L 1362.56 167.47" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g fill="#000000" font-family="Arial,Helvetica" pointer-events="none" font-size="11px"><text x="1365.1" y="186.63">0</text></g><path d="M 1357.51 182.63 L 1362.56 182.63" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><path d="M 1380.76 195.27 L 1380.76 202.85" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-q4aLnZXwkiyl6f_3jFDg-7" content="&lt;object label=&quot;&quot; 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stage=&quot;instruction_decode&quot; variable=&quot;lower_26&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="lower_26"><path d="M 490 595 L 490 270 C 496.5 270 496.5 260 490 260 L 490 260 L 490 165 L 599.9 165" fill="none" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 606.65 165 L 597.65 169.5 L 599.9 165 L 597.65 160.5 Z" fill="#000000" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-135"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 166px; margin-left: 558px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); 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index 8ef5a51a1..65dfdbae4 100644
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requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 68px; height: 1px; padding-top: 445px; margin-left: 736px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Shift Left 2</div></div></div></foreignObject><text x="770" y="449" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Shift Left 2</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-17" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="1081.5" cy="936.75" rx="4.5" ry="4.5" fill="rgb(0, 0, 0)" stroke="none" pointer-events="all"/><rect x="1051.5" y="906.75" width="60" height="60" fill="none" stroke="none" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-18" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;sign_extend&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="sign_extend"><path d="M 982.5 1125 L 1081.5 1125 L 1081.5 936.75" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-22" content="&lt;object label=&quot;&quot; stage=&quot;memory&quot; variable=&quot;memory_data&quot;/&gt;" data-label="" data-stage="memory" data-variable="memory_data"><path d="M 1942.5 798.75 L 2091.95 798.42" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 2099.82 798.38 L 2089.35 803.68 L 2091.95 798.42 L 2089.3 793.18 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="1.5" 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label=&quot;&quot; stage=&quot;execute&quot; variable=&quot;alu_result&quot;/&gt;" data-label="" data-stage="execute" data-variable="alu_result"><path d="M 1402.5 870.75 L 1484.7 870.75 L 1484.7 798 L 1567.5 798" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-45"><ellipse cx="1357.5" cy="1170" rx="90" ry="60" fill="rgb(255, 255, 255)" stroke="#ea6b66" stroke-width="1.5" pointer-events="all"/><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 780px; margin-left: 846px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" 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pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-102"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 825px; margin-left: 592px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [5-0] (funct)</div></div></div></foreignObject><text x="592" y="829" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" 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Z" fill="none" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="all"/><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 265px; margin-left: 296px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Add</div></div></div></foreignObject><text x="325" y="269" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Add</text></switch></g></g><g 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stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1855.32 237.38 L 1844.83 242.63 L 1847.45 237.38 L 1844.82 232.13 Z" fill="#000000" stroke="#000000" stroke-width="1.5" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-141"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 139px; margin-left: 1038px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: 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pointer-events="stroke"/><path d="M 1896.01 197.82 L 1890.79 187.31 L 1896.03 189.95 L 1901.29 187.34 Z" fill="#ea6b66" stroke="#ea6b66" stroke-width="1.5" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-132"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 290px; margin-left: 580px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); 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label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;pc_plus_4_upper&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="pc_plus_4_upper"><path d="M 922.5 397.5 L 922.5 237.06 L 1026.2 237.01" fill="none" stroke="#000000" stroke-width="1.5" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1034.07 237 L 1023.58 242.26 L 1026.2 237.01 L 1023.57 231.76 Z" fill="#000000" stroke="#000000" stroke-width="1.5" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-139"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 204px; margin-left: 620px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">PC + 4 [63-28]</div></div></div></foreignObject><text x="620" y="208" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">PC + 4 [63-28]</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-16"><rect x="780" y="750" width="255" height="285" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" stroke-width="1.5" pointer-events="none"/><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 168px; height: 1px; padding-top: 595px; margin-left: 521px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">Registers</div></div></div></foreignObject><text x="605" y="599" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">Registers</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-17"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 542px; margin-left: 532px;"><div style="box-sizing: border-box; font-size: 0px; text-align: left;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Register 1</div></div></div></foreignObject><text x="532" y="545" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Read Register 1</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-18"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 573px; margin-left: 532px;"><div style="box-sizing: border-box; font-size: 0px; text-align: left;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Register 2</div></div></div></foreignObject><text x="532" y="576" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Read Register 2</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-19"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 633px; margin-left: 532px;"><div style="box-sizing: border-box; font-size: 0px; text-align: left;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Write Register</div></div></div></foreignObject><text x="532" y="636" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Write Register</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-20"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 665px; margin-left: 532px;"><div style="box-sizing: border-box; font-size: 0px; text-align: left;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: 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color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">Data Memory</div></div></div></foreignObject><text x="1205" y="579" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">Data Memory</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-28"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 58px; height: 1px; padding-top: 618px; margin-left: 1127px;"><div style="box-sizing: border-box; font-size: 0px; text-align: left;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;"><div>Write Data<br /></div></div></div></div></foreignObject><text x="1127" y="620" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Write Data&#xa;</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-29"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 58px; height: 1px; padding-top: 530px; margin-left: 1127px;"><div style="box-sizing: border-box; font-size: 0px; text-align: left;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: 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807.49 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="1.5" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell--I45d_4FKIcXNRPlzvKB-47"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 532px; margin-left: 449px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 8px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [25-21] (rs or base)</div></div></div></foreignObject><text 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style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 562px; margin-left: 425px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "><div style="display: inline-block; font-size: 8px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [20-16] (rt)</div></div></div></foreignObject><text x="425" y="565" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" text-anchor="middle">Instruction [20-16] (rt)</text></switch></g></g><g id="cell--I45d_4FKIcXNRPlzvKB-50" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;rt&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="rt"><path d="M 622.5 858 L 622.5 895.26 L 676.7 895.15" fill="none" stroke="rgb(0, 0, 0)" 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pointer-events="none"/></g><g id="cell-alQhddrq2ZLo0OdN9rPj-2"><path d="M 1342.5 4.5 L 1342.5 754.5 L 1294.5 754.5 L 1294.5 1075.5 L 1260.06 1075.5 L 1260 1383" fill="none" stroke="#82b366" stroke-width="6" stroke-miterlimit="10" stroke-dasharray="6 6" pointer-events="none"/></g><g id="cell-alQhddrq2ZLo0OdN9rPj-5"><g transform="translate(-0.5 -0.5)scale(1.5)"><switch><foreignObject style="overflow: visible; text-align: left;" pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 242px;"><div style="box-sizing: border-box; font-size: 0px; text-align: center;" data-drawio-colors="color: rgb(0, 0, 0); "><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 826px; margin-left: 517px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [5-0] (funct)</div></div></div></foreignObject><text x="517" y="829" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction [5-0] (funct)</text></switch></g></g><g id="cell-NFu5_vnd6gg_ZSHdmE7s-3" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;imm&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="imm"><path d="M 402.5 750 L 469.9 750" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 476.65 750 L 467.65 754.5 L 469.9 750 L 467.65 745.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-47" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 265px; margin-left: 221px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Add</div></div></div></foreignObject><text x="250" y="269" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Add</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-52" content="&lt;object label=&quot;&quot; stage=&quot;instruction_fetch&quot; variable=&quot;pc&quot;/&gt;" data-label="" data-stage="instruction_fetch" data-variable="pc"><path d="M 130 595 L 143 595" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-61" content="&lt;object label=&quot;&quot; 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" style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Jump Address</div></div></div></foreignObject><text x="963" y="142" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Jump Address</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-130" content="&lt;object label=&quot;&quot; stage=&quot;memory&quot; variable=&quot;mem_mux1_to_mem_mux2&quot;/&gt;" data-label="" data-stage="memory" data-variable="mem_mux1_to_mem_mux2"><path d="M 1119 183 L 1152.9 182.81" fill="none" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1159.65 182.77 L 1150.67 187.32 L 1152.9 182.81 L 1150.62 178.32 Z" fill="#000000" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-131"><path d="M 502.32 311.6 L 502.3 260 L 1219 260 L 1219 120 L 1189 120 L 1189 126.63" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1189 131.88 L 1185.5 124.88 L 1189 126.63 L 1192.5 124.88 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-132"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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stage=&quot;instruction_decode&quot; variable=&quot;pc_plus_4&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="pc_plus_4"><path d="M 280 265 L 540 265" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-138" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;pc_plus_4_upper&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="pc_plus_4_upper"><path d="M 540 265 L 540 158 L 605.4 158" fill="none" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 612.15 158 L 603.15 162.5 L 605.4 158 L 603.15 153.5 Z" fill="#000000" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-139"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 205px; margin-left: 545px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">PC + 4 [63-28]</div></div></div></foreignObject><text x="545" y="208" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">PC + 4 [63-28]</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-16"><rect x="445" y="500" width="170" height="190" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 168px; height: 1px; padding-top: 595px; margin-left: 446px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">Registers</div></div></div></foreignObject><text x="530" y="599" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">Registers</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-17"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 542px; margin-left: 457px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Register 1</div></div></div></foreignObject><text x="457" y="545" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Read Register 1</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-18"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 573px; margin-left: 457px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Register 2</div></div></div></foreignObject><text x="457" y="576" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Read Register 2</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-19"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 633px; margin-left: 457px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Write Register</div></div></div></foreignObject><text x="457" y="636" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Write Register</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-20"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 68px; height: 1px; padding-top: 665px; margin-left: 457px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Write Data</div></div></div></foreignObject><text x="457" y="668" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Write Data</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-21"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 68px; height: 1px; padding-top: 549px; margin-left: 540px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Data 1</div></div></div></foreignObject><text x="608" y="552" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="end">Read Data 1</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-22"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 68px; height: 1px; padding-top: 642px; margin-left: 540px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Data 2</div></div></div></foreignObject><text x="608" y="645" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="end">Read Data 2</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-20"><rect x="1040" y="490" width="180" height="170" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 178px; height: 1px; padding-top: 575px; margin-left: 1041px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">Data Memory</div></div></div></foreignObject><text x="1130" y="579" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">Data Memory</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-28"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 58px; height: 1px; padding-top: 618px; margin-left: 1052px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;"><div>Write Data<br /></div></div></div></div></foreignObject><text x="1052" y="620" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Write Data&#xa;</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-29"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 58px; height: 1px; padding-top: 530px; margin-left: 1052px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Address</div></div></div></foreignObject><text x="1052" y="533" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Address</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-30"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-end; width: 58px; height: 1px; padding-top: 532px; margin-left: 1154px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Data</div></div></div></foreignObject><text x="1212" y="535" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="end">Read Data</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-119" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;read_data_2&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="read_data_2"><path d="M 630 603 L 630 694 L 641 694 C 641 687.5 651 687.5 651 694 L 651 694 L 909 694 L 909 617.5 L 1029.9 617.5" fill="none" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 1036.65 617.5 L 1027.65 622 L 1029.9 617.5 L 1027.65 613 Z" fill="#000000" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-172" content="&lt;object label=&quot;&quot; stage=&quot;writeback&quot; variable=&quot;data_result&quot;/&gt;" data-label="" data-stage="writeback" data-variable="data_result"><path d="M 1379 545.5 L 1389 545.5 L 1389 877 L 423 877 L 423 831 C 429.5 831 429.5 821 423 821 L 423 821 L 423 755 C 429.5 755 429.5 745 423 745 L 423 745 L 423 663.4 L 434.9 663.4" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 441.65 663.4 L 432.65 667.9 L 434.9 663.4 L 432.65 658.9 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell--I45d_4FKIcXNRPlzvKB-46" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;rs&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="rs"><path d="M 310 542 L 378 542 L 434.9 541.83" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 441.65 541.81 L 432.66 546.34 L 434.9 541.83 L 432.63 537.34 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell--I45d_4FKIcXNRPlzvKB-47"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 533px; margin-left: 375px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 8px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [25-21] (rs or base)</div></div></div></foreignObject><text x="375" y="535" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" text-anchor="middle">Instruction [25-21] (rs or base)</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-35" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;rd&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="rd"><path d="M 310 618.5 L 320 618.5 L 372.4 618.29" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 379.15 618.26 L 370.16 622.8 L 372.4 618.29 L 370.13 613.8 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-146"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 610px; margin-left: 344px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 6px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;"><font style="font-size: 6px;">Instruction [15-11] (rd)</font></div></div></div></foreignObject><text x="344" y="612" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="6px" text-anchor="middle">Instruction [15-11] (rd)</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-27" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;rt&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="rt"><path d="M 340 572 L 380 572 L 434.9 572.17" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 441.65 572.19 L 432.63 576.66 L 434.9 572.17 L 432.66 567.66 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-31" content="&lt;object label=&quot;&quot; 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From ab06eff134e778cfde71fdd74e40fb4471556393 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Thu, 28 Mar 2024 22:54:29 -0400
Subject: [PATCH 28/48] Fix up some visual issues with the RISC-V datapath

---
 media/datapath-riscv.drawio   | 89 +++++++++++++++++------------------
 src/ui/footer/component.rs    |  1 -
 src/ui/visual_datapath/mod.rs |  2 -
 static/datapath_riscv.svg     |  2 +-
 4 files changed, 45 insertions(+), 49 deletions(-)

diff --git a/media/datapath-riscv.drawio b/media/datapath-riscv.drawio
index edf78be1f..3406a6495 100644
--- a/media/datapath-riscv.drawio
+++ b/media/datapath-riscv.drawio
@@ -1,9 +1,14 @@
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+<mxfile host="Electron" modified="2024-03-29T02:51:11.624Z" agent="Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/21.1.2 Chrome/106.0.5249.199 Electron/21.4.3 Safari/537.36" etag="yherGLgyHY42ZOc-xMCX" compressed="false" version="21.1.2" type="device">
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+    <mxGraphModel dx="1219" dy="733" grid="0" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1600" pageHeight="950" math="0" shadow="0">
       <root>
         <mxCell id="0" />
         <mxCell id="1" parent="0" />
+        <object label="" stage="instruction_decode" id="_5b_4j9nvjmzGaxmlqEA-36">
+          <mxCell style="shape=waypoint;sketch=0;fillStyle=solid;size=6;pointerEvents=1;points=[];fillColor=none;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;" parent="1" vertex="1">
+            <mxGeometry x="365" y="612.5" width="40" height="40" as="geometry" />
+          </mxCell>
+        </object>
         <object label="" stage="instruction_decode" id="_5b_4j9nvjmzGaxmlqEA-123">
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@@ -15,7 +20,7 @@
           </mxCell>
         </object>
         <object label="" stage="instruction_decode" variable="read_data_1" id="iX89XPK5i3SNc3MIlNae-8">
-          <mxCell style="edgeStyle=orthogonalEdgeStyle;elbow=horizontal;endArrow=none;html=1;rounded=0;exitX=1;exitY=0.25;exitDx=0;exitDy=0;exitPerimeter=0;jumpStyle=arc;endFill=0;entryDx=0;entryDy=0;entryPerimeter=0;strokeWidth=3;" edge="1" parent="1" source="-Lmf1zb877u7wcXiO0Bk-16" target="iX89XPK5i3SNc3MIlNae-9">
+          <mxCell style="edgeStyle=orthogonalEdgeStyle;elbow=horizontal;endArrow=none;html=1;rounded=0;exitX=1;exitY=0.25;exitDx=0;exitDy=0;exitPerimeter=0;jumpStyle=arc;endFill=0;entryDx=0;entryDy=0;entryPerimeter=0;strokeWidth=3;" parent="1" source="-Lmf1zb877u7wcXiO0Bk-16" target="iX89XPK5i3SNc3MIlNae-9" edge="1">
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@@ -106,7 +111,9 @@
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               <mxPoint x="385" y="595" as="sourcePoint" />
               <mxPoint x="455" y="619.75" as="targetPoint" />
-              <Array as="points" />
+              <Array as="points">
+                <mxPoint x="385" y="615" />
+              </Array>
             </mxGeometry>
           </mxCell>
         </object>
@@ -297,7 +304,7 @@
             </mxGeometry>
           </mxCell>
         </object>
-        <object label="" stage="execute" variable="pc_plus_4" id="_5b_4j9nvjmzGaxmlqEA-77">
+        <object label="" stage="instruction_decode" variable="pc_plus_4" id="_5b_4j9nvjmzGaxmlqEA-77">
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@@ -429,7 +436,7 @@
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-            <Array as="points" />
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+        <object label="" stage="instruction_decode" variable="rs1" id="FCG2xz2OeAt8uY0nZYsg-3">
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+              <mxPoint x="520" y="542" as="targetPoint" />
+              <Array as="points" />
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@@ -861,12 +858,14 @@
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-            <mxPoint x="218" y="473" as="targetPoint" />
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-        </mxCell>
+        <object label="" stage="instruction_fetch" variable="pc" id="FCG2xz2OeAt8uY0nZYsg-9">
+          <mxCell style="endArrow=none;html=1;rounded=0;exitX=0.55;exitY=0.426;exitDx=0;exitDy=0;exitPerimeter=0;edgeStyle=orthogonalEdgeStyle;endFill=0;strokeWidth=3;" parent="1" edge="1">
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         <object label="" stage="instruction_decode" id="FCG2xz2OeAt8uY0nZYsg-7">
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@@ -938,17 +937,17 @@
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-        <mxCell id="iX89XPK5i3SNc3MIlNae-1" value="Add" style="shape=stencil(rZThboMgFIWfhr8Nwmzsz8Wt78Hs7SRDMEDb9e0HXrqstpi1SozJOUc+buAK4bVrRQ+EUS06IPyNMCbUIbyD1aIuKEV9Qr1JUrgeGo/eUVgpPhRg4rw1X3CSO58QUrdgpY8pfyf0NXwTH143RusAkUa7q+RPHmBC6jCXfiMsLX9OasVQ92GFDjzYVDW6hG2fBleLgVflCF3EcRdPl8BXcSyFL0bw8pFt4XVwcqfM672x8GnNQe/ulrOXSmEzTdTci9hmN8El7swRsmc8tRsXgJI6C3h5gjBClLOLWM8m/P7ijyA214xqPuJ/59Eo46b6IfiZlgi3Xa6Zhmk33Ti4eEMOxg8=);whiteSpace=wrap;html=1;" vertex="1" parent="1">
+        <mxCell id="iX89XPK5i3SNc3MIlNae-1" value="Add" style="shape=stencil(rZThboMgFIWfhr8Nwmzsz8Wt78Hs7SRDMEDb9e0HXrqstpi1SozJOUc+buAK4bVrRQ+EUS06IPyNMCbUIbyD1aIuKEV9Qr1JUrgeGo/eUVgpPhRg4rw1X3CSO58QUrdgpY8pfyf0NXwTH143RusAkUa7q+RPHmBC6jCXfiMsLX9OasVQ92GFDjzYVDW6hG2fBleLgVflCF3EcRdPl8BXcSyFL0bw8pFt4XVwcqfM672x8GnNQe/ulrOXSmEzTdTci9hmN8El7swRsmc8tRsXgJI6C3h5gjBClLOLWM8m/P7ijyA214xqPuJ/59Eo46b6IfiZlgi3Xa6Zhmk33Ti4eEMOxg8=);whiteSpace=wrap;html=1;" parent="1" vertex="1">
           <mxGeometry x="585" y="91" width="60" height="106" as="geometry" />
         </mxCell>
-        <mxCell id="iX89XPK5i3SNc3MIlNae-2" value="Mux" style="shadow=0;dashed=0;align=center;html=1;strokeWidth=1;shape=mxgraph.electrical.abstract.mux2;spacingBottom=8;movable=1;resizable=1;rotatable=1;deletable=1;editable=1;locked=0;connectable=1;" vertex="1" parent="1">
+        <mxCell id="iX89XPK5i3SNc3MIlNae-2" value="Mux" style="shadow=0;dashed=0;align=center;html=1;strokeWidth=1;shape=mxgraph.electrical.abstract.mux2;spacingBottom=8;movable=1;resizable=1;rotatable=1;deletable=1;editable=1;locked=0;connectable=1;" parent="1" vertex="1">
           <mxGeometry x="797" y="109" width="50" height="70" as="geometry" />
         </mxCell>
-        <mxCell id="iX89XPK5i3SNc3MIlNae-3" value="Shift Left 2" style="ellipse;whiteSpace=wrap;html=1;strokeColor=#000000;" vertex="1" parent="1">
+        <mxCell id="iX89XPK5i3SNc3MIlNae-3" value="Shift Left 2" style="ellipse;whiteSpace=wrap;html=1;strokeColor=#000000;" parent="1" vertex="1">
           <mxGeometry x="688.5" y="169" width="65" height="50" as="geometry" />
         </mxCell>
         <object label="" stage="instruction_decode" variable="imm" id="iX89XPK5i3SNc3MIlNae-5">
-          <mxCell style="endArrow=none;html=1;rounded=0;exitX=0.567;exitY=0.558;exitDx=0;exitDy=0;exitPerimeter=0;entryDx=0;entryDy=0;jumpStyle=arc;endFill=0;strokeWidth=3;" edge="1" parent="1" source="_5b_4j9nvjmzGaxmlqEA-17" target="iX89XPK5i3SNc3MIlNae-4">
+          <mxCell style="endArrow=none;html=1;rounded=0;exitX=0.567;exitY=0.558;exitDx=0;exitDy=0;exitPerimeter=0;entryDx=0;entryDy=0;jumpStyle=arc;endFill=0;strokeWidth=3;" parent="1" source="_5b_4j9nvjmzGaxmlqEA-17" target="iX89XPK5i3SNc3MIlNae-4" edge="1">
             <mxGeometry width="50" height="50" relative="1" as="geometry">
               <mxPoint x="721" y="625" as="sourcePoint" />
               <mxPoint x="900" y="198" as="targetPoint" />
@@ -957,12 +956,12 @@
           </mxCell>
         </object>
         <object label="" stage="instruction_decode" id="iX89XPK5i3SNc3MIlNae-4">
-          <mxCell style="shape=waypoint;sketch=0;fillStyle=solid;size=6;pointerEvents=1;points=[];fillColor=none;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;" vertex="1" parent="1">
+          <mxCell style="shape=waypoint;sketch=0;fillStyle=solid;size=6;pointerEvents=1;points=[];fillColor=none;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;" parent="1" vertex="1">
             <mxGeometry x="701" y="421" width="40" height="40" as="geometry" />
           </mxCell>
         </object>
         <object label="" stage="instruction_decode" variable="imm" id="iX89XPK5i3SNc3MIlNae-6">
-          <mxCell style="endArrow=classic;html=1;rounded=0;exitX=0.651;exitY=0.448;exitDx=0;exitDy=0;exitPerimeter=0;entryX=0.5;entryY=1;entryDx=0;entryDy=0;strokeWidth=3;" edge="1" parent="1" source="iX89XPK5i3SNc3MIlNae-4" target="iX89XPK5i3SNc3MIlNae-3">
+          <mxCell style="endArrow=classic;html=1;rounded=0;exitX=0.651;exitY=0.448;exitDx=0;exitDy=0;exitPerimeter=0;entryX=0.5;entryY=1;entryDx=0;entryDy=0;strokeWidth=3;" parent="1" source="iX89XPK5i3SNc3MIlNae-4" target="iX89XPK5i3SNc3MIlNae-3" edge="1">
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               <mxPoint x="762" y="323" as="sourcePoint" />
               <mxPoint x="812" y="273" as="targetPoint" />
@@ -970,7 +969,7 @@
           </mxCell>
         </object>
         <object label="" stage="instruction_decode" variable="imm_shifted_left_by_2" id="iX89XPK5i3SNc3MIlNae-7">
-          <mxCell style="endArrow=classic;html=1;rounded=0;exitX=0.5;exitY=0;exitDx=0;exitDy=0;entryX=0;entryY=0.5785714285714286;entryDx=0;entryDy=3;entryPerimeter=0;strokeWidth=3;" edge="1" parent="1" source="iX89XPK5i3SNc3MIlNae-3" target="iX89XPK5i3SNc3MIlNae-2">
+          <mxCell style="endArrow=classic;html=1;rounded=0;exitX=0.5;exitY=0;exitDx=0;exitDy=0;entryX=0;entryY=0.5785714285714286;entryDx=0;entryDy=3;entryPerimeter=0;strokeWidth=3;" parent="1" source="iX89XPK5i3SNc3MIlNae-3" target="iX89XPK5i3SNc3MIlNae-2" edge="1">
             <mxGeometry width="50" height="50" relative="1" as="geometry">
               <mxPoint x="640" y="201" as="sourcePoint" />
               <mxPoint x="690" y="151" as="targetPoint" />
@@ -981,12 +980,12 @@
           </mxCell>
         </object>
         <object label="" stage="instruction_decode" id="iX89XPK5i3SNc3MIlNae-9">
-          <mxCell style="shape=waypoint;sketch=0;fillStyle=solid;size=6;pointerEvents=1;points=[];fillColor=none;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;" vertex="1" parent="1">
+          <mxCell style="shape=waypoint;sketch=0;fillStyle=solid;size=6;pointerEvents=1;points=[];fillColor=none;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;" parent="1" vertex="1">
             <mxGeometry x="724" y="528" width="40" height="40" as="geometry" />
           </mxCell>
         </object>
         <object label="" stage="instruction_decode" variable="read_data_1" id="iX89XPK5i3SNc3MIlNae-11">
-          <mxCell style="endArrow=classic;html=1;rounded=0;entryX=0;entryY=0.2;entryDx=0;entryDy=0;jumpStyle=arc;strokeWidth=3;" edge="1" parent="1" source="iX89XPK5i3SNc3MIlNae-9" target="iX89XPK5i3SNc3MIlNae-1">
+          <mxCell style="endArrow=classic;html=1;rounded=0;entryX=0;entryY=0.2;entryDx=0;entryDy=0;jumpStyle=arc;strokeWidth=3;" parent="1" source="iX89XPK5i3SNc3MIlNae-9" target="iX89XPK5i3SNc3MIlNae-1" edge="1">
             <mxGeometry width="50" height="50" relative="1" as="geometry">
               <mxPoint x="768" y="327" as="sourcePoint" />
               <mxPoint x="818" y="277" as="targetPoint" />
@@ -1022,12 +1021,12 @@
           </mxGeometry>
         </mxCell>
         <object label="" stage="instruction_decode" id="iX89XPK5i3SNc3MIlNae-12">
-          <mxCell style="shape=waypoint;sketch=0;fillStyle=solid;size=6;pointerEvents=1;points=[];fillColor=none;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;" vertex="1" parent="1">
+          <mxCell style="shape=waypoint;sketch=0;fillStyle=solid;size=6;pointerEvents=1;points=[];fillColor=none;resizable=0;rotatable=0;perimeter=centerPerimeter;snapToPoint=1;" parent="1" vertex="1">
             <mxGeometry x="701" y="219" width="40" height="40" as="geometry" />
           </mxCell>
         </object>
         <object label="" stage="instruction_decode" variable="imm" id="iX89XPK5i3SNc3MIlNae-13">
-          <mxCell style="endArrow=classic;html=1;rounded=0;exitX=0.444;exitY=0.447;exitDx=0;exitDy=0;exitPerimeter=0;entryX=0;entryY=0.8;entryDx=0;entryDy=0;strokeWidth=3;" edge="1" parent="1" source="iX89XPK5i3SNc3MIlNae-12" target="iX89XPK5i3SNc3MIlNae-1">
+          <mxCell style="endArrow=classic;html=1;rounded=0;exitX=0.444;exitY=0.447;exitDx=0;exitDy=0;exitPerimeter=0;entryX=0;entryY=0.8;entryDx=0;entryDy=0;strokeWidth=3;" parent="1" source="iX89XPK5i3SNc3MIlNae-12" target="iX89XPK5i3SNc3MIlNae-1" edge="1">
             <mxGeometry width="50" height="50" relative="1" as="geometry">
               <mxPoint x="615" y="242" as="sourcePoint" />
               <mxPoint x="665" y="192" as="targetPoint" />
@@ -1039,7 +1038,7 @@
           </mxCell>
         </object>
         <object label="" stage="instruction_decode" variable="i_type_address" id="iX89XPK5i3SNc3MIlNae-14">
-          <mxCell style="endArrow=classic;html=1;rounded=0;exitX=1;exitY=0.5;exitDx=0;exitDy=0;entryX=0;entryY=0.19285714285714287;entryDx=0;entryDy=3;entryPerimeter=0;strokeWidth=3;" edge="1" parent="1" source="iX89XPK5i3SNc3MIlNae-1" target="iX89XPK5i3SNc3MIlNae-2">
+          <mxCell style="endArrow=classic;html=1;rounded=0;exitX=1;exitY=0.5;exitDx=0;exitDy=0;entryX=0;entryY=0.19285714285714287;entryDx=0;entryDy=3;entryPerimeter=0;strokeWidth=3;" parent="1" source="iX89XPK5i3SNc3MIlNae-1" target="iX89XPK5i3SNc3MIlNae-2" edge="1">
             <mxGeometry width="50" height="50" relative="1" as="geometry">
               <mxPoint x="686" y="152" as="sourcePoint" />
               <mxPoint x="736" y="102" as="targetPoint" />
@@ -1050,7 +1049,7 @@
             </mxGeometry>
           </mxCell>
         </object>
-        <mxCell id="iX89XPK5i3SNc3MIlNae-15" value="" style="endArrow=classic;html=1;rounded=0;exitX=0.85;exitY=0.14;exitDx=0;exitDy=0;exitPerimeter=0;entryX=0.3;entryY=1;entryDx=10;entryDy=0;entryPerimeter=0;fillColor=#f8cecc;strokeColor=#FF6666;" edge="1" parent="1" source="_5b_4j9nvjmzGaxmlqEA-79" target="iX89XPK5i3SNc3MIlNae-2">
+        <mxCell id="iX89XPK5i3SNc3MIlNae-15" value="" style="endArrow=classic;html=1;rounded=0;exitX=0.85;exitY=0.14;exitDx=0;exitDy=0;exitPerimeter=0;entryX=0.3;entryY=1;entryDx=10;entryDy=0;entryPerimeter=0;fillColor=#f8cecc;strokeColor=#FF6666;" parent="1" source="_5b_4j9nvjmzGaxmlqEA-79" target="iX89XPK5i3SNc3MIlNae-2" edge="1">
           <mxGeometry width="50" height="50" relative="1" as="geometry">
             <mxPoint x="676" y="270" as="sourcePoint" />
             <mxPoint x="726" y="220" as="targetPoint" />
@@ -1059,7 +1058,7 @@
             </Array>
           </mxGeometry>
         </mxCell>
-        <mxCell id="iX89XPK5i3SNc3MIlNae-16" value="&lt;div&gt;JumpSrc&lt;/div&gt;" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="iX89XPK5i3SNc3MIlNae-15">
+        <mxCell id="iX89XPK5i3SNc3MIlNae-16" value="&lt;div&gt;JumpSrc&lt;/div&gt;" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" parent="iX89XPK5i3SNc3MIlNae-15" vertex="1" connectable="0">
           <mxGeometry x="-0.8338" y="-1" relative="1" as="geometry">
             <mxPoint as="offset" />
           </mxGeometry>
diff --git a/src/ui/footer/component.rs b/src/ui/footer/component.rs
index 68c9baa02..d3980865d 100644
--- a/src/ui/footer/component.rs
+++ b/src/ui/footer/component.rs
@@ -1,6 +1,5 @@
 use crate::agent::datapath_communicator::DatapathCommunicator;
 use crate::agent::datapath_reducer::DatapathReducer;
-use crate::emulation_core::architectures::AvailableDatapaths;
 use crate::emulation_core::architectures::AvailableDatapaths::{MIPS, RISCV};
 use crate::ui::console::component::Console;
 use crate::ui::hex_editor::component::HexEditor;
diff --git a/src/ui/visual_datapath/mod.rs b/src/ui/visual_datapath/mod.rs
index c2a3ab471..17e3e97b6 100644
--- a/src/ui/visual_datapath/mod.rs
+++ b/src/ui/visual_datapath/mod.rs
@@ -287,8 +287,6 @@ impl VisualDatapath {
                 if let Ok(listeners) =
                     Self::enable_interactivity(element, datapath_state, is_in_current_stage)
                 {
-                    log!("Found an element in the current stage!");
-                    log!(element.get_attribute("id"));
                     for l in listeners {
                         active_listeners.push(l);
                     }
diff --git a/static/datapath_riscv.svg b/static/datapath_riscv.svg
index 3cb474d06..02f1d3f2d 100644
--- a/static/datapath_riscv.svg
+++ b/static/datapath_riscv.svg
@@ -1,3 +1,3 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
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stage=&quot;instruction_decode&quot; variable=&quot;read_data_1&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="read_data_1"><path d="M 615 547.5 L 669 548" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-lXCeeo62gMUK_VRSTubw-29" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;funct7&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="funct7"><path d="M 310 862 L 725 861 L 725 808 L 777.9 808" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 784.65 808 L 775.65 812.5 L 777.9 808 L 775.65 803.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-lXCeeo62gMUK_VRSTubw-30"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 850px; margin-left: 370px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;"><div style="font-size: 9px;"><font style="font-size: 9px;">Instruction [31-25] (funct7)</font></div></div></div></div></foreignObject><text x="370" y="853" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [31-25] (funct7)</text></switch></g></g><g id="cell-lXCeeo62gMUK_VRSTubw-22" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;funct3&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="funct3"><path d="M 310 817 L 695 816 L 695 752 L 777.9 752" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 784.65 752 L 775.65 756.5 L 777.9 752 L 775.65 747.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-lXCeeo62gMUK_VRSTubw-23"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 806px; margin-left: 369px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;"><font style="font-size: 9px;">Instruction [14-12] (funct3)<br style="font-size: 9px;" /></font></div></div></div></foreignObject><text x="369" y="809" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [14-12] (funct3)&#xa;</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-103"><path d="M 537.6 380.88 L 640 380.9 L 640 847 L 830 847 L 830 826.37" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 830 821.12 L 833.5 828.12 L 830 826.37 L 826.5 828.12 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-104"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 380px; margin-left: 565px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">ALUOp</div></div></div></foreignObject><text x="565" y="384" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">ALUOp</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-107"><path d="M 529.08 437.84 L 624 437.8 L 624 671 L 740 671 L 740 654.37" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 740 649.12 L 743.5 656.12 L 740 654.37 L 736.5 656.12 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-108"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 438px; margin-left: 576px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">OP2Select</div></div></div></foreignObject><text x="576" y="442" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">OP2Select</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-25" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="310" cy="595" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="all"/><rect x="290" y="575" width="40" height="40" fill="none" stroke="none" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-28" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="310" cy="572" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="all"/><rect x="290" y="552" width="40" height="40" fill="none" stroke="none" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-37" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;instruction&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="instruction"><path d="M 310 595 L 310 613.75 L 310 632.5" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-1"><rect x="70" y="560" width="60" height="70" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 595px; margin-left: 71px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">PC</div></div></div></foreignObject><text x="100" y="599" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">PC</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-3" content="&lt;object label=&quot;Instruction Memory&quot; stage=&quot;instruction_fetch&quot; variable=&quot;instruction&quot;/&gt;" data-label="Instruction Memory" data-stage="instruction_fetch" data-variable="instruction"><rect x="160" y="540" width="120" height="110" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 595px; margin-left: 161px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Instruction Memory</div></div></div></foreignObject><text x="220" y="599" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Instruction Memory</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-4" content="&lt;object label=&quot;&quot; stage=&quot;instruction_fetch&quot; variable=&quot;pc&quot;/&gt;" data-label="" data-stage="instruction_fetch" data-variable="pc"><path d="M 143 595 L 149.9 595" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 156.65 595 L 147.65 599.5 L 149.9 595 L 147.65 590.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-12" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;instruction&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="instruction"><path d="M 290 595 L 310 595" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-29" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;instruction&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="instruction"><path d="M 310 595 L 310 590 L 310 572" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-38"><ellipse cx="530" cy="750" rx="50" ry="50" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 750px; margin-left: 481px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">IMM Decode</div></div></div></foreignObject><text x="530" y="754" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">IMM Decode</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-6" content="&lt;object label=&quot;&quot; stage=&quot;execute&quot; variable=&quot;alu_input2&quot;/&gt;" data-label="" data-stage="execute" data-variable="alu_input2"><path d="M 765 613.5 L 783 613.5 L 789.9 613.38" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 796.65 613.26 L 787.73 617.92 L 789.9 613.38 L 787.57 608.92 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-7" content="&lt;object label=&quot;&quot; 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stage=&quot;memory&quot; variable=&quot;memory_data&quot;/&gt;" data-label="" data-stage="memory" data-variable="memory_data"><path d="M 1220 532.5 L 1325.9 532.46" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1332.65 532.46 L 1323.65 536.97 L 1325.9 532.46 L 1323.64 527.97 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-23" content="&lt;object label=&quot;&quot; stage=&quot;execute&quot; variable=&quot;alu_result&quot;/&gt;" data-label="" data-stage="execute" data-variable="alu_result"><path d="M 970 532 L 1005 532 L 1029.9 532.36" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1036.65 532.45 L 1027.58 536.82 L 1029.9 532.36 L 1027.71 527.82 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-40" content="&lt;object label=&quot;&quot; stage=&quot;execute&quot;/&gt;" data-label="" data-stage="execute"><ellipse cx="970" cy="532" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="all"/><rect x="950" y="512" width="40" height="40" fill="none" stroke="none" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-41" content="&lt;object label=&quot;&quot; stage=&quot;execute&quot; variable=&quot;alu_result&quot;/&gt;" data-label="" data-stage="execute" data-variable="alu_result"><path d="M 860 580.5 L 915 580.5 L 915 532 L 970 532" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-45"><ellipse cx="830" cy="780" rx="60" ry="40" fill="rgb(255, 255, 255)" stroke="#ea6b66" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 780px; margin-left: 771px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ALU Control</div></div></div></foreignObject><text x="830" y="784" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">ALU Control</text></switch></g></g><g id="cell-NFu5_vnd6gg_ZSHdmE7s-3" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;imm_input&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="imm_input"><path d="M 310 750 L 469.9 750" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 476.65 750 L 467.65 754.5 L 469.9 750 L 467.65 745.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-48" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;instruction&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="instruction"><path d="M 310 632.5 L 310 680 L 310 750" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-145"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 738px; margin-left: 367px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [31-12] (imm)</div></div></div></foreignObject><text x="367" y="741" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [31-12] (imm)</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-49" content="&lt;object label=&quot;&quot; variable=&quot;alu_control&quot;/&gt;" data-label="" data-variable="alu_control"><path d="M 830 740 L 830 629.26" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 830 624.01 L 833.5 631.01 L 830 629.26 L 826.5 631.01 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-50"><path d="M 220 205 L 220 253 L 233.33 265 L 220 277 L 220 325 L 280 301 L 280 229 Z" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 265px; margin-left: 221px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Add</div></div></div></foreignObject><text x="250" y="269" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Add</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-52" content="&lt;object label=&quot;&quot; stage=&quot;instruction_fetch&quot; variable=&quot;pc&quot;/&gt;" data-label="" data-stage="instruction_fetch" data-variable="pc"><path d="M 130 595 L 143 595" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-61" content="&lt;object label=&quot;&quot; stage=&quot;instruction_fetch&quot; variable=&quot;pc&quot;/&gt;" data-label="" data-stage="instruction_fetch" data-variable="pc"><path d="M 143 472 L 142 472 L 142 229 L 209.9 229" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 216.65 229 L 207.65 233.5 L 209.9 229 L 207.65 224.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-73"><path d="M 1079 153 L 1109 160 L 1109 206 L 1079 213 Z" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="all"/><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" text-anchor="middle" font-size="6px"><text x="1082.5" y="172">0</text></g><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" text-anchor="middle" font-size="6px"><text x="1082.5" y="199">1</text></g><g fill="rgb(0, 0, 0)" font-family="Arial,Helvetica" text-anchor="middle" font-size="6px"><text x="1098.5" y="220.5">S0</text></g><path d="M 1069 169.5 L 1079 169.5 M 1069 196.5 L 1079 196.5 M 1109 183 L 1119 183 M 1094 209.5 L 1094 223" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 178px; height: 1px; padding-top: 575px; margin-left: 1041px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;">Data Memory</div></div></div></foreignObject><text x="1130" y="579" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">Data Memory</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-28"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 58px; height: 1px; padding-top: 618px; margin-left: 1052px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: left;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;"><div>Write Data<br /></div></div></div></div></foreignObject><text x="1052" y="620" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px">Write Data&#xa;</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-29"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 58px; 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" style="box-sizing: border-box; font-size: 0px; text-align: right;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;">Read Data</div></div></div></foreignObject><text x="1212" y="535" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="end">Read Data</text></switch></g></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-119" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;read_data_2&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="read_data_2"><path d="M 630 603 L 630 694 L 641 694 C 641 687.5 651 687.5 651 694 L 651 694 L 909 694 L 909 617.5 L 1029.9 617.5" fill="none" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 1036.65 617.5 L 1027.65 622 L 1029.9 617.5 L 1027.65 613 Z" fill="#000000" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-mJyIEkHkixJ9JkuoTiU8-172" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 167px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><font color="#97D077" style="font-size: 20px;"><b><font color="#60854C">Instruction Fetch</font><br /></b></font></div></div></div></foreignObject><text x="167" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Instruction Fetch&#xa;</text></switch></g></g><g id="cell-alQhddrq2ZLo0OdN9rPj-6"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 555px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><div><font color="#97D077" style="font-size: 20px;"><b><font color="#60854C">Instruction Decode / Register Read</font></b></font></div></div></div></div></foreignObject><text x="555" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Instruction Decode / Register Read</text></switch></g></g><g id="cell-alQhddrq2ZLo0OdN9rPj-7"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 943px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><div><font color="#97D077" style="font-size: 20px;"><b><font color="#60854C">Execute</font></b></font></div></div></div></div></foreignObject><text x="943" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Execute</text></switch></g></g><g id="cell-alQhddrq2ZLo0OdN9rPj-8"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; 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justify-content: unsafe center; width: 1px; height: 1px; padding-top: 21px; margin-left: 1412px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: nowrap;"><div><font color="#97D077" style="font-size: 20px;"><b><font color="#60854C">Writeback</font></b></font></div></div></div></div></foreignObject><text x="1412" y="25" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Writeback</text></switch></g></g><g id="cell-LNPOl51hBx1QrpeweeW8-16"><path d="M 860 561.97 L 873 561.97 L 873 299.25 L 983.63 299.25" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="none"/><path d="M 988.88 299.25 L 981.88 302.75 L 983.63 299.25 L 981.88 295.75 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-42" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 533px; margin-left: 367px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 8px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; background-color: rgb(255, 255, 255); white-space: nowrap;"><div>Instruction [19-15] (rs1)</div></div></div></div></foreignObject><text x="367" y="535" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" text-anchor="middle">Instruction [19-15] (rs1)</text></switch></g></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-5" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="415" cy="542" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-6" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 850px; margin-left: 370px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;"><div style="font-size: 9px;"><font style="font-size: 9px;">Instruction [31-25] (funct7)</font></div></div></div></div></foreignObject><text x="370" y="853" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [31-25] (funct7)</text></switch></g></g><g id="cell-lXCeeo62gMUK_VRSTubw-22" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;funct3&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="funct3"><path d="M 310 817 L 695 816 L 695 752 L 777.9 752" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 784.65 752 L 775.65 756.5 L 777.9 752 L 775.65 747.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-lXCeeo62gMUK_VRSTubw-23"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 806px; margin-left: 369px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;"><font style="font-size: 9px;">Instruction [14-12] (funct3)<br style="font-size: 9px;" /></font></div></div></div></foreignObject><text x="369" y="809" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [14-12] (funct3)&#xa;</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-103"><path d="M 537.6 380.88 L 640 380.88 L 640 847 L 830 847 L 830 826.37" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 830 821.12 L 833.5 828.12 L 830 826.37 L 826.5 828.12 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-104"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 595px; margin-left: 71px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">PC</div></div></div></foreignObject><text x="100" y="599" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">PC</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-3" content="&lt;object label=&quot;Instruction Memory&quot; stage=&quot;instruction_fetch&quot; variable=&quot;instruction&quot;/&gt;" data-label="Instruction Memory" data-stage="instruction_fetch" data-variable="instruction"><rect x="160" y="540" width="120" height="110" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 595px; margin-left: 161px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Instruction Memory</div></div></div></foreignObject><text x="220" y="599" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Instruction Memory</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-4" content="&lt;object label=&quot;&quot; stage=&quot;instruction_fetch&quot; variable=&quot;pc&quot;/&gt;" data-label="" data-stage="instruction_fetch" data-variable="pc"><path d="M 143 595 L 149.9 595" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 156.65 595 L 147.65 599.5 L 149.9 595 L 147.65 590.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-12" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 750px; margin-left: 481px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">IMM Decode</div></div></div></foreignObject><text x="530" y="754" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">IMM Decode</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-6" content="&lt;object label=&quot;&quot; stage=&quot;execute&quot; variable=&quot;alu_input2&quot;/&gt;" data-label="" data-stage="execute" data-variable="alu_input2"><path d="M 765 613.5 L 782.47 613.5 L 789.9 613.37" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 796.65 613.26 L 787.72 617.91 L 789.9 613.37 L 787.57 608.91 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-7" content="&lt;object label=&quot;&quot; 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align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 780px; margin-left: 771px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ALU Control</div></div></div></foreignObject><text x="830" y="784" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">ALU Control</text></switch></g></g><g id="cell-NFu5_vnd6gg_ZSHdmE7s-3" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;imm_input&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="imm_input"><path d="M 310 750 L 469.9 750" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 476.65 750 L 467.65 754.5 L 469.9 750 L 467.65 745.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-48" content="&lt;object label=&quot;&quot; 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pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [31-12] (imm)</div></div></div></foreignObject><text x="367" y="740" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [31-12] (imm)</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-49" content="&lt;object label=&quot;&quot; variable=&quot;alu_control&quot;/&gt;" data-label="" data-variable="alu_control"><path d="M 830 740 L 830 629.26" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 830 624.01 L 833.5 631.01 L 830 629.26 L 826.5 631.01 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-50"><path d="M 220 205 L 220 253 L 233.33 265 L 220 277 L 220 325 L 280 301 L 280 229 Z" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 265px; margin-left: 221px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Add</div></div></div></foreignObject><text x="250" y="269" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Add</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-52" content="&lt;object label=&quot;&quot; stage=&quot;instruction_fetch&quot; variable=&quot;pc&quot;/&gt;" data-label="" data-stage="instruction_fetch" data-variable="pc"><path d="M 130 595 L 143 595" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-61" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 198px; margin-left: 999px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Branch</div></div></div></foreignObject><text x="999" y="201" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Branch</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-76" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;pc_plus_4&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="pc_plus_4"><path d="M 540 265 L 750 265" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-77" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 381px; margin-left: 359px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction</div></div></div></foreignObject><text x="359" y="384" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-81" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="310" cy="542" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="all"/><rect x="290" y="522" width="40" height="40" fill="none" stroke="none" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-82" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 397px; margin-left: 579px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">ReadWrite</div></div></div></foreignObject><text x="579" y="400" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">ReadWrite</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-116" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="630" cy="603" rx="3" ry="3" fill="#000000" stroke="none" pointer-events="all"/><rect x="610" y="583" width="40" height="40" fill="none" stroke="none" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-117" content="&lt;object label=&quot;&quot; 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" style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Jump Address</div></div></div></foreignObject><text x="971" y="142" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Jump Address</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-130" content="&lt;object label=&quot;&quot; stage=&quot;memory&quot; variable=&quot;mem_mux1_to_mem_mux2&quot;/&gt;" data-label="" data-stage="memory" data-variable="mem_mux1_to_mem_mux2"><path d="M 1119 183 L 1152.9 182.81" fill="none" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1159.65 182.77 L 1150.67 187.32 L 1152.9 182.81 L 1150.62 178.32 Z" fill="#000000" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-131"><path d="M 502.32 311.6 L 502.35 260.06 L 1218.94 260.06 L 1218.94 120.06 L 1188.94 120.06 L 1188.97 126.63" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1188.99 131.88 L 1185.46 124.9 L 1188.97 126.63 L 1192.46 124.87 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-132"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 19px; height: 1px; padding-top: 302px; margin-left: 180px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 6px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;"><font style="font-size: 10px;">4</font></div></div></div></foreignObject><text x="190" y="303" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="6px" text-anchor="middle">4</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-8"><path d="M 800 526 L 800 569.6 L 813.33 580.5 L 800 591.4 L 800 635 L 860 613.2 L 860 547.8 Z" fill="#ffffff" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 581px; margin-left: 801px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;"><div>ALU</div></div></div></div></foreignObject><text x="830" y="584" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">ALU</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-25"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; 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background-color: rgb(255, 255, 255); white-space: nowrap;"><div>Instruction [19-15] (rs1)</div></div></div></div></foreignObject><text x="367" y="535" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" text-anchor="middle">Instruction [19-15] (rs1)</text></switch></g></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-5" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="415" cy="542" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-6" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;rs1&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="rs1"><path d="M 415 542 L 415 478 L 653 478 L 653 535 L 707.9 535.28" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 714.65 535.31 L 705.62 539.76 L 707.9 535.28 L 705.67 530.76 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-8" content="&lt;object label=&quot;&quot; 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From e049880712174ada70aa1b365be2caa13da02b8a Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 23:10:46 -0400
Subject: [PATCH 29/48] Fixed issues. Every instruction aside from FLW is
 working correctly.

---
 src/emulation_core/riscv/coprocessor.rs | 66 +++++++++++--------------
 1 file changed, 29 insertions(+), 37 deletions(-)

diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 6d73cf351..d1bd8ecde 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -2,8 +2,7 @@
 
 use std::ops::Neg;
 
-use super::constants::{OPCODE_MADD, OPCODE_MSUB, OPCODE_NMADD, OPCODE_NMSUB};
-// use super::constants::*;
+use super::constants::*;
 use super::instruction::Instruction;
 use super::registers::FpRegisters;
 use super::{constants::RISC_NAN, control_signals::floating_point::*};
@@ -206,11 +205,16 @@ impl RiscFpCoprocessor {
                 self.signals = FpuControlSignals {
                     data_write: DataWrite::NoWrite,
                     fpu_mem_to_reg: FpuMemToReg::UseDataWrite,
-                    fpu_reg_dst: FpuRegDst::Reg3,
                     fpu_reg_write: FpuRegWrite::YesWrite,
+                    fpu_reg_dst: FpuRegDst::Reg3,
                     ..Default::default()
                 };
 
+                if r.op != OPCODE_OP_FP {
+                    self.signals.fpu_reg_write = FpuRegWrite::NoWrite;
+                    return;
+                }
+
                 match r.funct7 >> 2 {
                     0 => self.signals.fpu_alu_op = FpuAluOp::Addition,
                     1 => self.signals.fpu_alu_op = FpuAluOp::Subtraction,
@@ -272,13 +276,17 @@ impl RiscFpCoprocessor {
                     _ => self.error("Unsupported Rounding Mode!"),
                 }
             }
-            Instruction::IType(_i) => {
+            Instruction::IType(i) => {
                 self.signals = FpuControlSignals {
                     data_write: DataWrite::NoWrite,
                     fpu_mem_to_reg: FpuMemToReg::UseMemory,
                     fpu_reg_dst: FpuRegDst::Reg3,
                     fpu_reg_write: FpuRegWrite::YesWrite,
                     ..Default::default()
+                };
+
+                if i.op != OPCODE_LOAD_FP {
+                    self.signals.fpu_reg_write = FpuRegWrite::NoWrite;
                 }
             }
             Instruction::SType(_s) => {
@@ -286,7 +294,7 @@ impl RiscFpCoprocessor {
                     data_write: DataWrite::NoWrite,
                     fpu_reg_write: FpuRegWrite::NoWrite,
                     ..Default::default()
-                }
+                };
             }
             Instruction::R4Type(r4) => {
                 self.signals = FpuControlSignals {
@@ -437,13 +445,7 @@ impl RiscFpCoprocessor {
             RoundingMode::RDN => f32::to_bits(result_f32.floor()) as u64,
             RoundingMode::RUP => f32::to_bits(result_f32.ceil()) as u64,
             RoundingMode::RMM => f32::to_bits(result_f32.round()) as u64,
-            _ => {
-                self.error(&format!(
-                    "Unsupported operation in FPU `{:?}`",
-                    self.signals.fpu_alu_op
-                ));
-                0
-            }
+            _ => f32::to_bits(result_f32) as u64,
         };
     }
 
@@ -458,14 +460,7 @@ impl RiscFpCoprocessor {
             FpuAluOp::MultiplicationOrEqual => (input1_f32 == input2_f32) as u64,
             FpuAluOp::Slt => (input1_f32 < input2_f32) as u64,
             FpuAluOp::Sle => (input1_f32 <= input2_f32) as u64,
-            FpuAluOp::Addition | FpuAluOp::Subtraction | FpuAluOp::Division => 0, // No operation
-            _ => {
-                self.error(&format!(
-                    "Unsupported operation in comparator `{:?}`",
-                    self.signals.fpu_alu_op
-                ));
-                0
-            }
+            _ => 0,
         }
     }
 
@@ -488,13 +483,17 @@ impl RiscFpCoprocessor {
     /// Set the data line that goes from `Read Data 1` to the multiplexer in the main processor
     /// controlled by [`MemWriteSrc`](super::control_signals::MemWriteSrc).
     fn write_fp_register_to_memory(&mut self) {
-        self.state.fp_register_to_memory = self.state.read_data_1;
+        self.state.fp_register_to_memory = f32::from_bits(self.state.read_data_2 as u32) as u64;
     }
 
     // ======================= Memory (MEM) =======================
     /// Set the data line between the multiplexer after the `Data` register and the
     /// multiplexer in the main processor controlled by the [`DataWrite`] control signal.
     fn set_data_writeback(&mut self) {
+        if let DataWrite::NoWrite = self.signals.data_write {
+            return;
+        }
+
         self.state.data_writeback = match self.signals.data_src {
             DataSrc::MainProcessorUnit => match self.state.rs2 {
                 0 => f32::to_bits(self.data as i32 as f32) as u64,
@@ -528,27 +527,20 @@ impl RiscFpCoprocessor {
                     RoundingMode::RTZ => data_unrounded.trunc(),
                     RoundingMode::RDN => data_unrounded.floor(),
                     RoundingMode::RUP => data_unrounded.ceil(),
-                    RoundingMode::RMM => data_unrounded.round(),
-                    _ => {
-                        self.error(&format!(
-                            "Unsupported Rounding Mode `{:?}`",
-                            self.signals.round_mode
-                        ));
-                        0.0
-                    }
+                    _ => data_unrounded.round(),
                 };
 
                 match self.state.rs2 {
                     0 => {
-                        if (data_rounded <= (-(2_i32.pow(31))) as f32)
+                        if (data_rounded <= (-(2_i64.pow(31))) as f32)
                             | (data_rounded == f32::NEG_INFINITY)
                         {
-                            -(2_i32.pow(31)) as u64
-                        } else if (data_rounded >= (2_i32.pow(31) - 1) as f32)
+                            -(2_i64.pow(31)) as u64
+                        } else if (data_rounded >= (2_i64.pow(31) - 1) as f32)
                             | (data_rounded == f32::INFINITY)
                             | (data_rounded.is_nan())
                         {
-                            (2_i32.pow(31) - 1) as u64
+                            (2_i64.pow(31) - 1) as u64
                         } else {
                             data_rounded as i32 as u64
                         }
@@ -556,11 +548,11 @@ impl RiscFpCoprocessor {
                     1 => {
                         if (data_rounded <= 0.0) | (data_rounded == f32::NEG_INFINITY) {
                             0
-                        } else if (data_rounded >= (2_u32.pow(32) - 1) as f32)
+                        } else if (data_rounded >= (2_u64.pow(32) - 1) as f32)
                             | (data_rounded == f32::INFINITY)
                             | (data_rounded.is_nan())
                         {
-                            (2_u32.pow(32) - 1) as u64
+                            2_u64.pow(32) - 1
                         } else {
                             data_rounded as u32 as u64
                         }
@@ -582,11 +574,11 @@ impl RiscFpCoprocessor {
                     3 => {
                         if (data_rounded <= 0.0) | (data_rounded == f32::NEG_INFINITY) {
                             0
-                        } else if (data_rounded >= (2_u64.pow(64) - 1) as f32)
+                        } else if (data_rounded >= (0x1111111111111111_i64) as f32)
                             | (data_rounded == f32::INFINITY)
                             | (data_rounded.is_nan())
                         {
-                            2_u64.pow(64) - 1
+                            0x1111111111111111
                         } else {
                             data_rounded as u64
                         }

From f81a8404c4d01cfa48951361ad621481424a7a03 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Thu, 28 Mar 2024 23:14:17 -0400
Subject: [PATCH 30/48] One instruction was wrong. Fixed now.

---
 src/emulation_core/riscv/coprocessor.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index d1bd8ecde..cc12133d9 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -483,7 +483,7 @@ impl RiscFpCoprocessor {
     /// Set the data line that goes from `Read Data 1` to the multiplexer in the main processor
     /// controlled by [`MemWriteSrc`](super::control_signals::MemWriteSrc).
     fn write_fp_register_to_memory(&mut self) {
-        self.state.fp_register_to_memory = f32::from_bits(self.state.read_data_2 as u32) as u64;
+        self.state.fp_register_to_memory = self.state.read_data_2;
     }
 
     // ======================= Memory (MEM) =======================

From dcf96c5dc3fb2b9817091d33293d492be94a7d7e Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Thu, 28 Mar 2024 23:58:43 -0400
Subject: [PATCH 31/48] Fix RISC-V visual datapath displaying information from
 the MIPS core

---
 media/datapath-riscv.drawio          |  22 +-
 src/emulation_core/riscv/datapath.rs |   1 +
 src/ui/visual_datapath/utils.rs      | 521 +++++++++++----------------
 static/datapath_riscv.svg            |   2 +-
 4 files changed, 213 insertions(+), 333 deletions(-)

diff --git a/media/datapath-riscv.drawio b/media/datapath-riscv.drawio
index 3406a6495..c38e2ee7e 100644
--- a/media/datapath-riscv.drawio
+++ b/media/datapath-riscv.drawio
@@ -1,6 +1,6 @@
-<mxfile host="Electron" modified="2024-03-29T02:51:11.624Z" agent="Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/21.1.2 Chrome/106.0.5249.199 Electron/21.4.3 Safari/537.36" etag="yherGLgyHY42ZOc-xMCX" compressed="false" version="21.1.2" type="device">
+<mxfile host="Electron" modified="2024-03-29T03:56:32.284Z" agent="Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/21.1.2 Chrome/106.0.5249.199 Electron/21.4.3 Safari/537.36" etag="rmfZJRMoEfBek-6dzESh" compressed="false" version="21.1.2" type="device">
   <diagram id="582QG3pIvltcbfHTLR_8" name="Page-1">
-    <mxGraphModel dx="1219" dy="733" grid="0" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1600" pageHeight="950" math="0" shadow="0">
+    <mxGraphModel dx="592" dy="356" grid="0" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1600" pageHeight="950" math="0" shadow="0">
       <root>
         <mxCell id="0" />
         <mxCell id="1" parent="0" />
@@ -120,7 +120,7 @@
         <mxCell id="_5b_4j9nvjmzGaxmlqEA-1" value="PC" style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
           <mxGeometry x="145" y="560" width="60" height="70" as="geometry" />
         </mxCell>
-        <object label="Instruction Memory" stage="instruction_fetch" variable="instruction" id="_5b_4j9nvjmzGaxmlqEA-3">
+        <object label="Instruction Memory" id="_5b_4j9nvjmzGaxmlqEA-3">
           <mxCell style="rounded=0;whiteSpace=wrap;html=1;" parent="1" vertex="1">
             <mxGeometry x="235" y="540" width="120" height="110" as="geometry" />
           </mxCell>
@@ -576,20 +576,8 @@
             <mxPoint x="-13" y="-12" as="offset" />
           </mxGeometry>
         </mxCell>
-        <object label="" stage="instruction_decode" variable="rs2" id="_5b_4j9nvjmzGaxmlqEA-27">
-          <mxCell style="edgeStyle=elbowEdgeStyle;elbow=horizontal;endArrow=classic;html=1;rounded=0;exitDx=0;exitDy=0;exitPerimeter=0;entryX=0;entryY=0.38;entryDx=0;entryDy=0;entryPerimeter=0;startArrow=none;strokeWidth=3;" parent="1" target="-Lmf1zb877u7wcXiO0Bk-16" edge="1">
-            <mxGeometry width="50" height="50" relative="1" as="geometry">
-              <mxPoint x="415" y="572" as="sourcePoint" />
-              <mxPoint x="520.1700000000003" y="575.24" as="targetPoint" />
-              <Array as="points">
-                <mxPoint x="455" y="570" />
-                <mxPoint x="435" y="577" />
-              </Array>
-            </mxGeometry>
-          </mxCell>
-        </object>
         <object label="" stage="instruction_decode" variable="rt" id="_5b_4j9nvjmzGaxmlqEA-31">
-          <mxCell style="edgeStyle=elbowEdgeStyle;elbow=horizontal;endArrow=none;html=1;rounded=0;exitX=0.675;exitY=0.525;exitDx=0;exitDy=0;exitPerimeter=0;entryDx=0;entryDy=0;entryPerimeter=0;strokeWidth=3;" parent="1" source="_5b_4j9nvjmzGaxmlqEA-28" edge="1">
+          <mxCell style="edgeStyle=elbowEdgeStyle;elbow=horizontal;endArrow=classicThin;html=1;rounded=0;exitX=0.675;exitY=0.525;exitDx=0;exitDy=0;exitPerimeter=0;entryDx=0;entryDy=0;entryPerimeter=0;strokeWidth=3;entryX=0;entryY=0.38;endFill=0;" parent="1" source="_5b_4j9nvjmzGaxmlqEA-28" edge="1" target="-Lmf1zb877u7wcXiO0Bk-16">
             <mxGeometry width="50" height="50" relative="1" as="geometry">
               <mxPoint x="385" y="575" as="sourcePoint" />
               <mxPoint x="415" y="572" as="targetPoint" />
@@ -599,7 +587,7 @@
         </object>
         <mxCell id="_5b_4j9nvjmzGaxmlqEA-144" value="Instruction [24-20] (rs2)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];fontSize=8;" parent="_5b_4j9nvjmzGaxmlqEA-31" vertex="1" connectable="0">
           <mxGeometry x="0.3846" y="-1" relative="1" as="geometry">
-            <mxPoint x="43" y="-11" as="offset" />
+            <mxPoint x="-38" y="-11" as="offset" />
           </mxGeometry>
         </mxCell>
         <object label="" stage="instruction_decode" variable="imm" id="-I45d_4FKIcXNRPlzvKB-52">
diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index dd65a7af9..7aa10b6c1 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -56,6 +56,7 @@ use super::{super::mips::memory::Memory, registers::RiscGpRegisters};
 use crate::emulation_core::architectures::DatapathRef;
 use crate::emulation_core::datapath::{DatapathUpdateSignal, Syscall};
 use crate::emulation_core::riscv::registers::GpRegisterType::{X10, X11};
+use gloo_console::log;
 use serde::{Deserialize, Serialize};
 
 /// An implementation of a datapath for the MIPS64 ISA.
diff --git a/src/ui/visual_datapath/utils.rs b/src/ui/visual_datapath/utils.rs
index 522d833b5..6ed40001a 100644
--- a/src/ui/visual_datapath/utils.rs
+++ b/src/ui/visual_datapath/utils.rs
@@ -350,7 +350,7 @@ pub fn visual_line_to_data(
                 },
                 "jump_address" => LineInformation {
                     title: String::from("Jump Address"),
-                    description: String::from("The concatenation of the upper 36 bits of PC + 4 with the lower 26 bits of the instruction, shifted left by 2. This is used as the new PC value for J-type instructions."),
+                    description: String::from("The calculated next program counter for jump instructions. For I type instructions, this is the immediate value added to the data in rs1. For U type instructions, this is the immediate value shifted left by 2."),
                     value: datapath_state.mips.state.jump_address,
                     bits: 64,
                 },
@@ -495,321 +495,212 @@ pub fn visual_line_to_data(
             }
         },
         AvailableDatapaths::RISCV => {
-            // just a stand in
-            LineInformation {
-                title: String::from("ALU Input 2"),
-                description: String::from("The second input to the ALU. This is determined by the ALUSrc control signal to select between register data, a sign-extended and left-shifted immediate value, or a zero-extended immediate value."),
-                value: datapath_state.mips.state.alu_input2,
-                bits: 64
+            match variable {
+                "alu_input1" => LineInformation {
+                    title: String::from("ALU Input 1"),
+                    description: String::from("The first input to the ALU. This is determined by the OP1Select control signal to select between the current program counter, a sign-extended and left-shifted immediate value, or the data from rs1."),
+                    value: datapath_state.riscv.state.alu_input1,
+                    bits: 64,
+                },
+                "alu_input2" => LineInformation {
+                    title: String::from("ALU Input 2"),
+                    description: String::from("The second input to the ALU. This is determined by the ALUSrc control signal to select between register data and a sign-extended and left-shifted immediate value."),
+                    value: datapath_state.riscv.state.alu_input2,
+                    bits: 64,
+                },
+                "alu_result" => LineInformation {
+                    title: String::from("ALU Result"),
+                    description: String::from("The result of the calculation performed by the ALU. This is used either as an address to access memory or as a value that is saved into a register."),
+                    value: datapath_state.riscv.state.alu_result,
+                    bits: 64,
+                },
+                "data_result" => LineInformation {
+                    title: String::from("Writeback Data"),
+                    description: String::from("After finishing processing the instruction, this will either be the ALU result, data from memory, or PC + 4, based on the MemToReg control signal. This data is saved into registers."),
+                    value: datapath_state.riscv.state.data_result,
+                    bits: 64,
+                },
+                "funct3" => LineInformation {
+                    title: String::from("Instruction [14-12] (funct)"),
+                    description: String::from("The funct3 field. Controls the type of operation to execute for all RISC-V instructions except for U and J type instructions."),
+                    value: datapath_state.riscv.state.funct3 as u64,
+                    bits: 3,
+                },
+                "funct7" => LineInformation {
+                    title: String::from("Instruction [31-25] (funct7)"),
+                    description: String::from("The funct7 field. Controls the type of operation to execute for R type instructions."),
+                    value: datapath_state.riscv.state.funct7 as u64,
+                    bits: 7,
+                },
+                "imm" => LineInformation {
+                    title: String::from("Immediate"),
+                    description: String::from("The immediate field. This field is a different size depending on the instruction type, but it can be at most 20 bits."),
+                    value: datapath_state.riscv.state.imm as u64,
+                    bits: 20,
+                },
+                "imm_input" => LineInformation {
+                    title: String::from("Instruction [31-12] (immediate)"),
+                    description: String::from("The part of the instruction used to extract the imm field from an instruction. In RISC-V, depending on the instruction type, the imm field can be split up within an instruction (S, B, and J type) or even out of order (B and J type)."),
+                    value: 0u64, // FIXME: Use the real line
+                    bits: 20,
+                },
+                "instruction" => LineInformation {
+                    title: String::from("Instruction"),
+                    description: String::from("The currently-loaded instruction. This is broken down into different fields, where each field serves a different purpose in identifying what the instruction does."),
+                    value: datapath_state.riscv.state.instruction as u64,
+                    bits: 32,
+                },
+                "i_type_address" => LineInformation {
+                    title: String::from("I type jump address"),
+                    description: String::from("The jump address used for I type instructions. Calculated from the data in rs1 and imm."),
+                    value: 0u64, // FIXME: Use the real line
+                    bits: 16,
+                },
+                "jump_address" => LineInformation {
+                    title: String::from("Jump Address"),
+                    description: String::from("The calculated next program counter for jump instructions. For I type instructions, this is the immediate value added to the data in rs1. For U type instructions, this is the immediate value shifted left by 2."),
+                    value: datapath_state.riscv.state.jump_address,
+                    bits: 64,
+                },
+                "lower_26" => LineInformation {
+                    title: String::from("Instruction [25-0]"),
+                    description: String::from("The lower 26 bits of instruction. This is used as part of the new PC value for J-type instructions."),
+                    value: datapath_state.riscv.state.lower_26 as u64,
+                    bits: 26,
+                },
+                "lower_26_shifted_left_by_2" => LineInformation {
+                    title: String::from("Instruction [25-0] << 2"),
+                    description: String::from("The lower 26 bits of instruction, shifted left by 2. This is used as part of the new PC value for J-type instructions."),
+                    value: datapath_state.riscv.state.lower_26_shifted_left_by_2 as u64,
+                    bits: 28,
+                },
+                "mem_mux1_to_mem_mux2" => LineInformation {
+                    title: String::from("Relative PC Address"),
+                    description: String::from("Based on the control signals for branching and jumping, this address may be the next PC value. This is used for general non-branching instructions or branch-type instructions."),
+                    value: datapath_state.riscv.state.mem_mux1_to_mem_mux2,
+                    bits: 64,
+                },
+                "memory_data" => LineInformation {
+                    title: String::from("Memory Data"),
+                    description: String::from("The data retrieved from memory, given that the MemRead control signal is set. This may be 32 bits or 64 bits, depending on the RegWidth control signal."),
+                    value: datapath_state.riscv.state.memory_data,
+                    bits: 64,
+                },
+                "new_pc" => LineInformation {
+                    title: String::from("New Program Counter"),
+                    description: String::from("The address of the next instruction to execute. In other words, the next value of the program counter (PC) register."),
+                    value: datapath_state.riscv.state.new_pc,
+                    bits: 64,
+                },
+                "pc" => LineInformation {
+                    title: String::from("Program Counter"),
+                    description: String::from("The address of the currently-executing instruction."),
+                    value: datapath_state.riscv.registers.pc,
+                    bits: 64,
+                },
+                "pc_plus_4" => LineInformation {
+                    title: String::from("PC + 4"),
+                    description: String::from("The address of the currently-executing instruction, plus 4. By default, this will become the next value of the PC register. However, a different address may be used in the case of a branch or jump instruction."),
+                    value: datapath_state.riscv.state.pc_plus_4,
+                    bits: 64,
+                },
+                "pc_plus_4_upper" => LineInformation {
+                    title: String::from("PC + 4 [63-28]"),
+                    description: String::from("The upper 36 bits of PC + 4. This is to be concatenated with the lower 26 bits of the instruction to calculate a jump address."),
+                    value: datapath_state.riscv.state.pc_plus_4 & 0xffff_ffff_f000_0000 >> 28,
+                    bits: 36,
+                },
+                "ra_id" => LineInformation {
+                    title: String::from("Return Address Register Index"),
+                    description: String::from("The value 31. This represents the thirty-second register, the return address register ($ra)."),
+                    value: 31,
+                    bits: 5,
+                },
+                "rd" => LineInformation {
+                    title: String::from("Instruction [11-7] (rd)"),
+                    description: String::from("The rd field. This will be the register written to for an instruction."),
+                    value: datapath_state.riscv.state.rd as u64,
+                    bits: 5,
+                },
+                "read_data_1" => LineInformation {
+                    title: String::from("Read Data 1"),
+                    description: String::from("Data retrieved from the register specified by the rs1 instruction field. Based on the instruction, this may be used as the first input to the ALU, or in the calculation of the next value of the PC register."),
+                    value: datapath_state.riscv.state.read_data_1,
+                    bits: 64,
+                },
+                "read_data_2" => LineInformation {
+                    title: String::from("Read Data 2"),
+                    description: String::from("Data retrieved from the register specified by the rs2 instruction field. Based on the instruction, this may be used as the second input to the ALU or data written to memory."),
+                    value: datapath_state.riscv.state.read_data_2,
+                    bits: 64,
+                },
+                "register_write_data" => LineInformation {
+                    title: String::from("Register Write Data"),
+                    description: String::from("Data that will be written to a general-purpose register, given that RegWrite is set."),
+                    value: datapath_state.riscv.state.register_write_data,
+                    bits: 64,
+                },
+                "relative_pc_branch" => LineInformation {
+                    title: String::from("Branch Address"),
+                    description: String::from("The absolute address used in branch instructions. This is the sign-extended immediate value, shifted left by 2."),
+                    value: datapath_state.riscv.state.relative_pc_branch,
+                    bits: 64,
+                },
+                "rs1" => LineInformation {
+                    title: String::from("Instruction [19-15] (rs1)"),
+                    description: String::from("The rs1 field. Contains the first register to be read for an instruction."),
+                    value: datapath_state.riscv.state.rs1 as u64,
+                    bits: 5,
+                },
+                "rs2" => LineInformation {
+                    title: String::from("Instruction [24-20] (rs2)"),
+                    description: String::from("The rs2 field. Contains the second register to be read for an instruction."),
+                    value: datapath_state.riscv.state.rs2 as u64,
+                    bits: 5,
+                },
+                "shamt" => LineInformation {
+                    title: String::from("Instruction [10-6] (shamt)"),
+                    description: String::from("The shamt (\"shift amount\") field. Specifies the number of bits to shift for those instructions that perform bit-shifting."),
+                    value: datapath_state.riscv.state.shamt as u64,
+                    bits: 5,
+                },
+                "sign_extend" => LineInformation {
+                    title: String::from("Sign-Extended Immediate"),
+                    description: String::from("The immediate field, sign-extended to a 64-bit value."),
+                    value: datapath_state.riscv.state.sign_extend,
+                    bits: 64,
+                },
+                "sign_extend_shift_left_by_2" => LineInformation {
+                    title: String::from("Sign-Extended Immediate << 2"),
+                    description: String::from("The immediate field, sign-extended to a 64-bit value, then shifted left by 2."),
+                    value: datapath_state.riscv.state.sign_extend_shift_left_by_2,
+                    bits: 64,
+                },
+                "write_data" => LineInformation {
+                    title: String::from("Memory Write Data"),
+                    description: String::from("Given that the MemWrite control signal is set, this data will be written to memory."),
+                    value: datapath_state.riscv.state.write_data,
+                    bits: 64,
+                },
+                "write_register" => LineInformation {
+                    title: String::from("Write Register"),
+                    description: String::from("The register that will be written to, assuming RegWrite is set. Depending on the RegDst control signal, this will consist of the rs, rt, or rd register, or 31 (indicating the $ra register)."),
+                    value: datapath_state.riscv.state.write_register_destination as u64,
+                    bits: 5,
+                },
+                "zero_extended_immediate" => LineInformation {
+                    title: String::from("Zero-Extended Immediate"),
+                    description: String::from("The immediate field, zero-extended to a 64-bit value."),
+                    value: datapath_state.riscv.state.imm as u64,
+                    bits: 64,
+                },
+                _ => LineInformation {
+                    title: String::from("[Title]"),
+                    description: String::from("[Description]"),
+                    value: 0,
+                    bits: 0,
+                },
             }
-    //     match variable {
-    //         "alu_input2" => LineInformation {
-    //             title: String::from("ALU Input 2"),
-    //             description: String::from("The second input to the ALU. This is determined by the ALUSrc control signal to select between register data, a sign-extended and left-shifted immediate value, or a zero-extended immediate value."),
-    //             value: datapath_state.riscv.state.alu_input2,
-    //             bits: 64,
-    //         },
-    //         "alu_result" => LineInformation {
-    //             title: String::from("ALU Result"),
-    //             description: String::from("The result of the calculation performed by the ALU. This is used either as an address to access memory or as a value that is saved into a register."),
-    //             value: datapath_state.riscv.state.alu_result,
-    //             bits: 64,
-    //         },
-    //         "data_result" => LineInformation {
-    //             title: String::from("Writeback Data"),
-    //             description: String::from("After finishing processing the instruction, this will either be the ALU result, data from memory, or PC + 4, based on the MemToReg control signal. This data is saved into registers."),
-    //             value: datapath_state.riscv.state.data_result,
-    //             bits: 64,
-    //         },
-    //         "fpu_alu_result" => LineInformation {
-    //             title: String::from("Floating-Point ALU Result"),
-    //             description: String::from("The result of the calculation performed by the floating-point ALU. This is used as an option to be written to a floating-point register, based on the DataWrite and FpuMemToReg control signals."),
-    //             value: datapath_state.riscv.coprocessor_state.alu_result,
-    //             bits: 64,
-    //         },
-    //         "fpu_branch_decision" => LineInformation {
-    //             title: String::from("FPU Branch Decision"),
-    //             description: String::from("Based on the true/false branch flag, determines whether to branch. (The FpuBranch control signal must also be set.)"),
-    //             value: datapath_state.riscv.coprocessor_state.condition_code_mux as u64,
-    //             bits: 1,
-    //         },
-    //         "fpu_branch_flag" => LineInformation {
-    //             title: String::from("Instruction [16] (True/False Branch Flag)"),
-    //             description: String::from("The true/false branch flag of branching coprocessor instructions. This flag specifies whether a floating-point branch instruction is BC1T or BC1F."),
-    //             value: datapath_state.riscv.coprocessor_state.branch_flag as u64,
-    //             bits: 1,
-    //         },
-    //         "fpu_comparator_result" => LineInformation {
-    //             title: String::from("Floating-Point Comparator Result"),
-    //             description: String::from("The result of the comparison of two floating-point values. This is routed to the \"Condition Code\" (cc) register, and will be written there if the CcWrite control signal is set."),
-    //             value: datapath_state.riscv.coprocessor_state.comparator_result,
-    //             bits: 64,
-    //         },
-    //         "fpu_condition_code" => LineInformation {
-    //             title: String::from("Condition Code Value"),
-    //             description: String::from("Data retrieved from the \"Condition Code\" (cc) register. This specifies whether a previous conditional instruction was true or false."),
-    //             value: datapath_state.riscv.coprocessor_state.condition_code_bit as u64,
-    //             bits: 1,
-    //         },
-    //         "fpu_condition_code_inverted" => LineInformation {
-    //             title: String::from("Condition Code Value (Inverted)"),
-    //             description: String::from("Inverted form of the condition code register value."),
-    //             value: datapath_state.riscv.coprocessor_state.condition_code_bit_inverted as u64,
-    //             bits: 1,
-    //         },
-    //         "fpu_data" => LineInformation {
-    //             title: String::from("Floating-Point Data Register Value"),
-    //             description: String::from("Data retrieved from the \"Data\" register. This register acts as a means to communicate data between the main processor and floating-point coprocessor in MTC1 and MFC1 instructions."),
-    //             value: datapath_state.riscv.coprocessor_state.fmt as u64,
-    //             bits: 64,
-    //         },
-    //         "fpu_data_writeback" => LineInformation {
-    //             title: String::from("Floating-Point Data Writeback"),
-    //             description: String::from("The value from the floating-point unit's \"Data\" register. Depending on the FpuRegWidth control signal, this will be 64-bit data or sign-extended 32-bit data."),
-    //             value: datapath_state.riscv.coprocessor_state.data_writeback,
-    //             bits: 64,
-    //         },
-    //         "fpu_destination" => LineInformation {
-    //             title: String::from("Floating-Point Write Register"),
-    //             description: String::from("The register that will be written to, assuming FpuRegWrite is set. Depending on the FpuRegDst control signal, this will consist of the fs, ft, or fd register."),
-    //             value: datapath_state.riscv.coprocessor_state.destination as u64,
-    //             bits: 5,
-    //         },
-    //         "fpu_fd" => LineInformation {
-    //             title: String::from("Instruction [10-6] (fd)"),
-    //             description: String::from("The fd field. Depending on the FpuRegDst control signal, this will be the register written to in a floating-point operation. This register is used as the destination for most floating-point arithmetic instructions."),
-    //             value: datapath_state.riscv.coprocessor_state.fd as u64,
-    //             bits: 5,
-    //         },
-    //         "fpu_fmt" => LineInformation {
-    //             title: String::from("Instruction [25-21] (fmt)"),
-    //             description: String::from("The fmt field. This is used to distinguish between single-precision and double-precision floating-point instructions."),
-    //             value: datapath_state.riscv.coprocessor_state.fmt as u64,
-    //             bits: 5,
-    //         },
-    //         "fpu_fp_register_data_from_main_processor" => LineInformation {
-    //             title: String::from("Writeback Data (To Floating-Point Coprocessor)"),
-    //             description: String::from("This data is written to a floating-point register, given FpuMemToReg is set. This line allows data to load from memory to a floating-point register, specifically in the case of the LWC1 instruction."),
-    //             value: datapath_state.riscv.coprocessor_state.fp_register_data_from_main_processor,
-    //             bits: 64,
-    //         },
-    //         "fpu_fp_register_to_memory" => LineInformation {
-    //             title: String::from("Memory Write Data (from FPU)"),
-    //             description: String::from("If the MemWriteSrc control signal is set, this data will be written to memory. This is used for the SWC1 instruction."),
-    //             value: datapath_state.riscv.coprocessor_state.fp_register_to_memory,
-    //             bits: 64,
-    //         },
-    //         "fpu_fs" => LineInformation {
-    //             title: String::from("Instruction [15-11] (fs)"),
-    //             description: String::from("The fs field. Contains the first register to be read for a floating-point instruction."),
-    //             value: datapath_state.riscv.coprocessor_state.fs as u64,
-    //             bits: 5,
-    //         },
-    //         "fpu_ft" => LineInformation {
-    //             title: String::from("Instruction [20-16] (ft)"),
-    //             description: String::from("The ft field. Contains the second register to be read for a floating-point instruction."),
-    //             value: datapath_state.riscv.coprocessor_state.ft as u64,
-    //             bits: 5,
-    //         },
-    //         "fpu_new_data" => LineInformation {
-    //             title: String::from("New Floating-Point Data Register Value"),
-    //             description: String::from("Data sent to the \"Data\" register. Depending on the DataSrc control signal, this will either be data from the main processor or the floating-point coprocessor. This register acts as a means to communicate data between the main processor and floating-point coprocessor in MTC1 and MFC1 instructions."),
-    //             value: datapath_state.riscv.coprocessor_state.fmt as u64,
-    //             bits: 64,
-    //         },
-    //         "fpu_read_data_1" => LineInformation {
-    //             title: String::from("FPU Read Data 1"),
-    //             description: String::from("Data retrieved from the register specified by the fs instruction field. This is used as the first inputs to the floating-point ALU and comparator. This can additionally be written to the \"Data\" register, based on the DataSrc and DataWrite control signals."),
-    //             value: datapath_state.riscv.coprocessor_state.read_data_1,
-    //             bits: 64,
-    //         },
-    //         "fpu_read_data_2" => LineInformation {
-    //             title: String::from("FPU Read Data 2"),
-    //             description: String::from("Data retrieved from the register specified by the ft instruction field. This is used as the second inputs to the floating-point ALU and comparator. This can additionally be used as data to be written to memory, based on the MemWriteSrc control signal."),
-    //             value: datapath_state.riscv.coprocessor_state.read_data_2,
-    //             bits: 64,
-    //         },
-    //         "fpu_register_write_data" => LineInformation {
-    //             title: String::from("FPU Register Write Data"),
-    //             description: String::from("Data that will be written to a floating-point register, given that FpuRegWrite is set."),
-    //             value: datapath_state.riscv.coprocessor_state.register_write_data,
-    //             bits: 64,
-    //         },
-    //         "fpu_register_write_mux_to_mux" => LineInformation {
-    //             title: String::from("FPU Register Write Data (When FpuMemToReg is Unset)"),
-    //             description: String::from("Based on the DataWrite control signal, this will either be the result of the floating-point ALU or the contents of the \"Data\" register. (The \"Data\" register is used for transferring data between the processor and floating-point coprocessor.)"),
-    //             value: datapath_state.riscv.coprocessor_state.register_write_mux_to_mux,
-    //             bits: 64,
-    //         },
-    //         "fpu_sign_extend_data" => LineInformation {
-    //             title: String::from("Floating-Point Data Register Value (Sign-Extended)"),
-    //             description: String::from("In the case where FpuRegWidth indicates a 32-bit width, this is the bottom 32 bits of the value from the \"Data\" register, then sign-extended to 64 bits."),
-    //             value: datapath_state.riscv.coprocessor_state.sign_extend_data,
-    //             bits: 64,
-    //         },
-    //         "funct" => LineInformation {
-    //             title: String::from("Instruction [5-0] (funct)"),
-    //             description: String::from("The funct field. Contains the type of operation to execute for R-type instructions."),
-    //             value: datapath_state.riscv.state.funct as u64,
-    //             bits: 6,
-    //         },
-    //         "imm" => LineInformation {
-    //             title: String::from("Instruction [15-0] (immediate)"),
-    //             description: String::from("The immediate field. Contains the 16-bit constant value used for I-type instructions."),
-    //             value: datapath_state.riscv.state.imm as u64,
-    //             bits: 16,
-    //         },
-    //         "instruction" => LineInformation {
-    //             title: String::from("Instruction"),
-    //             description: String::from("The currently-loaded instruction. This is broken down into different fields, where each field serves a different purpose in identifying what the instruction does."),
-    //             value: datapath_state.riscv.state.instruction as u64,
-    //             bits: 32,
-    //         },
-    //         "jump_address" => LineInformation {
-    //             title: String::from("Jump Address"),
-    //             description: String::from("The concatenation of the upper 36 bits of PC + 4 with the lower 26 bits of the instruction, shifted left by 2. This is used as the new PC value for J-type instructions."),
-    //             value: datapath_state.riscv.state.jump_address,
-    //             bits: 64,
-    //         },
-    //         "lower_26" => LineInformation {
-    //             title: String::from("Instruction [25-0]"),
-    //             description: String::from("The lower 26 bits of instruction. This is used as part of the new PC value for J-type instructions."),
-    //             value: datapath_state.riscv.state.lower_26 as u64,
-    //             bits: 26,
-    //         },
-    //         "lower_26_shifted_left_by_2" => LineInformation {
-    //             title: String::from("Instruction [25-0] << 2"),
-    //             description: String::from("The lower 26 bits of instruction, shifted left by 2. This is used as part of the new PC value for J-type instructions."),
-    //             value: datapath_state.riscv.state.lower_26_shifted_left_by_2 as u64,
-    //             bits: 28,
-    //         },
-    //         "mem_mux1_to_mem_mux2" => LineInformation {
-    //             title: String::from("Relative PC Address"),
-    //             description: String::from("Based on the control signals for branching and jumping, this address may be the next PC value. This is used for general non-branching instructions or branch-type instructions."),
-    //             value: datapath_state.riscv.state.mem_mux1_to_mem_mux2,
-    //             bits: 64,
-    //         },
-    //         "memory_data" => LineInformation {
-    //             title: String::from("Memory Data"),
-    //             description: String::from("The data retrieved from memory, given that the MemRead control signal is set. This may be 32 bits or 64 bits, depending on the RegWidth control signal."),
-    //             value: datapath_state.riscv.state.memory_data,
-    //             bits: 64,
-    //         },
-    //         "new_pc" => LineInformation {
-    //             title: String::from("New Program Counter"),
-    //             description: String::from("The address of the next instruction to execute. In other words, the next value of the program counter (PC) register."),
-    //             value: datapath_state.riscv.state.new_pc,
-    //             bits: 64,
-    //         },
-    //         "pc" => LineInformation {
-    //             title: String::from("Program Counter"),
-    //             description: String::from("The address of the currently-executing instruction."),
-    //             value: datapath_state.riscv.registers.pc,
-    //             bits: 64,
-    //         },
-    //         "pc_plus_4" => LineInformation {
-    //             title: String::from("PC + 4"),
-    //             description: String::from("The address of the currently-executing instruction, plus 4. By default, this will become the next value of the PC register. However, a different address may be used in the case of a branch or jump instruction."),
-    //             value: datapath_state.riscv.state.pc_plus_4,
-    //             bits: 64,
-    //         },
-    //         "pc_plus_4_upper" => LineInformation {
-    //             title: String::from("PC + 4 [63-28]"),
-    //             description: String::from("The upper 36 bits of PC + 4. This is to be concatenated with the lower 26 bits of the instruction to calculate a jump address."),
-    //             value: datapath_state.riscv.state.pc_plus_4 & 0xffff_ffff_f000_0000 >> 28,
-    //             bits: 36,
-    //         },
-    //         "ra_id" => LineInformation {
-    //             title: String::from("Return Address Register Index"),
-    //             description: String::from("The value 31. This represents the thirty-second register, the return address register ($ra)."),
-    //             value: 31,
-    //             bits: 5,
-    //         },
-    //         "rd" => LineInformation {
-    //             title: String::from("Instruction [15-11] (rd)"),
-    //             description: String::from("The rd field. Depending on the RegDst control signal, this will be the register written to for an instruction. This register is used as the destination for most R-type instructions."),
-    //             value: datapath_state.riscv.state.rd as u64,
-    //             bits: 5,
-    //         },
-    //         "read_data_1" => LineInformation {
-    //             title: String::from("Read Data 1"),
-    //             description: String::from("Data retrieved from the register specified by the rs instruction field. Based on the instruction, this may be used as the first input to the ALU, or the next value of the PC register."),
-    //             value: datapath_state.riscv.state.read_data_1,
-    //             bits: 64,
-    //         },
-    //         "read_data_2" => LineInformation {
-    //             title: String::from("Read Data 2"),
-    //             description: String::from("Data retrieved from the register specified by the rt instruction field. Based on the instruction, this may be used as the second input to the ALU, data written to memory, or data transferred to the floating-point coprocessor."),
-    //             value: datapath_state.riscv.state.read_data_2,
-    //             bits: 64,
-    //         },
-    //         "register_write_data" => LineInformation {
-    //             title: String::from("Register Write Data"),
-    //             description: String::from("Data that will be written to a general-purpose register, given that RegWrite is set."),
-    //             value: datapath_state.riscv.state.register_write_data,
-    //             bits: 64,
-    //         },
-    //         "relative_pc_branch" => LineInformation {
-    //             title: String::from("Relative PC Branch Address"),
-    //             description: String::from("The relative address used in branch instructions. This is the sum of PC + 4 and the sign-extended immediate value, shifted left by 2."),
-    //             value: datapath_state.riscv.state.relative_pc_branch,
-    //             bits: 64,
-    //         },
-    //         "rs" => LineInformation {
-    //             title: String::from("Instruction [25-21] (rs)"),
-    //             description: String::from("The rs field. Contains the first register to be read for an instruction."),
-    //             value: datapath_state.riscv.state.rs as u64,
-    //             bits: 5,
-    //         },
-    //         "rt" => LineInformation {
-    //             title: String::from("Instruction [20-16] (rt)"),
-    //             description: String::from("The rt field. Contains the second register to be read for an instruction."),
-    //             value: datapath_state.riscv.state.rt as u64,
-    //             bits: 5,
-    //         },
-    //         "shamt" => LineInformation {
-    //             title: String::from("Instruction [10-6] (shamt)"),
-    //             description: String::from("The shamt (\"shift amount\") field. Specifies the number of bits to shift for those instructions that perform bit-shifting."),
-    //             value: datapath_state.riscv.state.shamt as u64,
-    //             bits: 5,
-    //         },
-    //         "sign_extend" => LineInformation {
-    //             title: String::from("Sign-Extended Immediate"),
-    //             description: String::from("The immediate field, sign-extended to a 64-bit value."),
-    //             value: datapath_state.riscv.state.sign_extend,
-    //             bits: 64,
-    //         },
-    //         "sign_extend_shift_left_by_2" => LineInformation {
-    //             title: String::from("Sign-Extended Immediate << 2"),
-    //             description: String::from("The immediate field, sign-extended to a 64-bit value, then shifted left by 2."),
-    //             value: datapath_state.riscv.state.sign_extend_shift_left_by_2,
-    //             bits: 64,
-    //         },
-    //         "write_data" => LineInformation {
-    //             title: String::from("Memory Write Data"),
-    //             description: String::from("Given that the MemWrite control signal is set, this data will be written to memory."),
-    //             value: datapath_state.riscv.state.write_data,
-    //             bits: 64,
-    //         },
-    //         "write_register" => LineInformation {
-    //             title: String::from("Write Register"),
-    //             description: String::from("The register that will be written to, assuming RegWrite is set. Depending on the RegDst control signal, this will consist of the rs, rt, or rd register, or 31 (indicating the $ra register)."),
-    //             value: datapath_state.riscv.state.write_register_destination as u64,
-    //             bits: 5,
-    //         },
-    //         "zero_extended_immediate" => LineInformation {
-    //             title: String::from("Zero-Extended Immediate"),
-    //             description: String::from("The immediate field, zero-extended to a 64-bit value."),
-    //             value: datapath_state.riscv.state.imm as u64,
-    //             bits: 64,
-    //         },
-    //         _ => LineInformation {
-    //             title: String::from("[Title]"),
-    //             description: String::from("[Description]"),
-    //             value: 0,
-    //             bits: 0,
-    //         },
-    //     }
         }
     }
 }
diff --git a/static/datapath_riscv.svg b/static/datapath_riscv.svg
index 02f1d3f2d..a79227d1b 100644
--- a/static/datapath_riscv.svg
+++ b/static/datapath_riscv.svg
@@ -1,3 +1,3 @@
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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 850px; margin-left: 370px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;"><div style="font-size: 9px;"><font style="font-size: 9px;">Instruction [31-25] (funct7)</font></div></div></div></div></foreignObject><text x="370" y="853" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [31-25] (funct7)</text></switch></g></g><g id="cell-lXCeeo62gMUK_VRSTubw-22" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;funct3&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="funct3"><path d="M 310 817 L 695 816 L 695 752 L 777.9 752" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 784.65 752 L 775.65 756.5 L 777.9 752 L 775.65 747.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-lXCeeo62gMUK_VRSTubw-23"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 806px; margin-left: 369px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;"><font style="font-size: 9px;">Instruction [14-12] (funct3)<br style="font-size: 9px;" /></font></div></div></div></foreignObject><text x="369" y="809" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [14-12] (funct3)&#xa;</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-103"><path d="M 537.6 380.88 L 640 380.88 L 640 847 L 830 847 L 830 826.37" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 830 821.12 L 833.5 828.12 L 830 826.37 L 826.5 828.12 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-104"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 595px; margin-left: 71px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">PC</div></div></div></foreignObject><text x="100" y="599" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">PC</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-3" content="&lt;object label=&quot;Instruction Memory&quot; stage=&quot;instruction_fetch&quot; variable=&quot;instruction&quot;/&gt;" data-label="Instruction Memory" data-stage="instruction_fetch" data-variable="instruction"><rect x="160" y="540" width="120" height="110" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 595px; margin-left: 161px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Instruction Memory</div></div></div></foreignObject><text x="220" y="599" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Instruction Memory</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-4" content="&lt;object label=&quot;&quot; stage=&quot;instruction_fetch&quot; variable=&quot;pc&quot;/&gt;" data-label="" data-stage="instruction_fetch" data-variable="pc"><path d="M 143 595 L 149.9 595" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 156.65 595 L 147.65 599.5 L 149.9 595 L 147.65 590.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-12" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 750px; margin-left: 481px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">IMM Decode</div></div></div></foreignObject><text x="530" y="754" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">IMM Decode</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-6" content="&lt;object label=&quot;&quot; stage=&quot;execute&quot; variable=&quot;alu_input2&quot;/&gt;" data-label="" data-stage="execute" data-variable="alu_input2"><path d="M 765 613.5 L 782.47 613.5 L 789.9 613.37" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 796.65 613.26 L 787.72 617.91 L 789.9 613.37 L 787.57 608.91 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-7" content="&lt;object label=&quot;&quot; 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align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 780px; margin-left: 771px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ALU Control</div></div></div></foreignObject><text x="830" y="784" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">ALU Control</text></switch></g></g><g id="cell-NFu5_vnd6gg_ZSHdmE7s-3" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;imm_input&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="imm_input"><path d="M 310 750 L 469.9 750" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 476.65 750 L 467.65 754.5 L 469.9 750 L 467.65 745.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-48" content="&lt;object label=&quot;&quot; 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pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [31-12] (imm)</div></div></div></foreignObject><text x="367" y="740" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [31-12] (imm)</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-49" content="&lt;object label=&quot;&quot; variable=&quot;alu_control&quot;/&gt;" data-label="" data-variable="alu_control"><path d="M 830 740 L 830 629.26" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 830 624.01 L 833.5 631.01 L 830 629.26 L 826.5 631.01 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-50"><path d="M 220 205 L 220 253 L 233.33 265 L 220 277 L 220 325 L 280 301 L 280 229 Z" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 198px; margin-left: 999px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Branch</div></div></div></foreignObject><text x="999" y="201" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Branch</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-76" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;pc_plus_4&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="pc_plus_4"><path d="M 540 265 L 750 265" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-77" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 381px; margin-left: 359px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction</div></div></div></foreignObject><text x="359" y="384" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-81" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="310" cy="542" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="all"/><rect x="290" y="522" width="40" height="40" fill="none" stroke="none" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-82" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 397px; margin-left: 579px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">ReadWrite</div></div></div></foreignObject><text x="579" y="400" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">ReadWrite</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-116" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="630" cy="603" rx="3" ry="3" fill="#000000" stroke="none" pointer-events="all"/><rect x="610" y="583" width="40" height="40" fill="none" stroke="none" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-117" content="&lt;object label=&quot;&quot; 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" style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Jump Address</div></div></div></foreignObject><text x="971" y="142" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Jump Address</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-130" content="&lt;object label=&quot;&quot; stage=&quot;memory&quot; variable=&quot;mem_mux1_to_mem_mux2&quot;/&gt;" data-label="" data-stage="memory" data-variable="mem_mux1_to_mem_mux2"><path d="M 1119 183 L 1152.9 182.81" fill="none" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1159.65 182.77 L 1150.67 187.32 L 1152.9 182.81 L 1150.62 178.32 Z" fill="#000000" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-131"><path d="M 502.32 311.6 L 502.35 260.06 L 1218.94 260.06 L 1218.94 120.06 L 1188.94 120.06 L 1188.97 126.63" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1188.99 131.88 L 1185.46 124.9 L 1188.97 126.63 L 1192.46 124.87 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-132"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 19px; height: 1px; padding-top: 302px; margin-left: 180px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 6px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;"><font style="font-size: 10px;">4</font></div></div></div></foreignObject><text x="190" y="303" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="6px" text-anchor="middle">4</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-8"><path d="M 800 526 L 800 569.6 L 813.33 580.5 L 800 591.4 L 800 635 L 860 613.2 L 860 547.8 Z" fill="#ffffff" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 581px; margin-left: 801px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; font-weight: bold; white-space: normal; overflow-wrap: normal;"><div>ALU</div></div></div></div></foreignObject><text x="830" y="584" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle" font-weight="bold">ALU</text></switch></g></g><g id="cell--Lmf1zb877u7wcXiO0Bk-25"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; 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background-color: rgb(255, 255, 255); white-space: nowrap;"><div>Instruction [19-15] (rs1)</div></div></div></div></foreignObject><text x="367" y="535" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" text-anchor="middle">Instruction [19-15] (rs1)</text></switch></g></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-5" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="415" cy="542" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-6" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;rs1&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="rs1"><path d="M 415 542 L 415 478 L 653 478 L 653 535 L 707.9 535.28" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 714.65 535.31 L 705.62 539.76 L 707.9 535.28 L 705.67 530.76 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-8" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 850px; margin-left: 370px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;"><div style="font-size: 9px;"><font style="font-size: 9px;">Instruction [31-25] (funct7)</font></div></div></div></div></foreignObject><text x="370" y="853" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [31-25] (funct7)</text></switch></g></g><g id="cell-lXCeeo62gMUK_VRSTubw-22" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;funct3&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="funct3"><path d="M 310 817 L 695 816 L 695 752 L 777.9 752" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 784.65 752 L 775.65 756.5 L 777.9 752 L 775.65 747.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-lXCeeo62gMUK_VRSTubw-23"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 806px; margin-left: 369px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 9px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;"><font style="font-size: 9px;">Instruction [14-12] (funct3)<br style="font-size: 9px;" /></font></div></div></div></foreignObject><text x="369" y="809" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [14-12] (funct3)&#xa;</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-103"><path d="M 537.6 380.88 L 640.03 380.91 L 640.03 847.03 L 830.03 847.03 L 830.01 826.37" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 830 821.12 L 833.51 828.11 L 830.01 826.37 L 826.51 828.12 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-104"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 380px; margin-left: 565px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">ALUOp</div></div></div></foreignObject><text x="565" y="383" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">ALUOp</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-107"><path d="M 529.08 437.84 L 624.03 437.77 L 624.03 671.03 L 740.03 671.03 L 740.01 654.37" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 740 649.12 L 743.51 656.11 L 740.01 654.37 L 736.51 656.12 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-108"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 595px; margin-left: 71px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">PC</div></div></div></foreignObject><text x="100" y="599" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">PC</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-3" content="&lt;object label=&quot;Instruction Memory&quot;/&gt;" data-label="Instruction Memory"><rect x="160" y="540" width="120" height="110" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 750px; margin-left: 481px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">IMM Decode</div></div></div></foreignObject><text x="530" y="754" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">IMM Decode</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-6" content="&lt;object label=&quot;&quot; stage=&quot;execute&quot; variable=&quot;alu_input2&quot;/&gt;" data-label="" data-stage="execute" data-variable="alu_input2"><path d="M 765 613.5 L 782.71 613.5 L 789.9 613.38" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 796.65 613.26 L 787.73 617.91 L 789.9 613.38 L 787.57 608.92 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-7" content="&lt;object label=&quot;&quot; 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align-items: unsafe center; justify-content: unsafe center; width: 118px; height: 1px; padding-top: 780px; margin-left: 771px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ALU Control</div></div></div></foreignObject><text x="830" y="784" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">ALU Control</text></switch></g></g><g id="cell-NFu5_vnd6gg_ZSHdmE7s-3" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;imm_input&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="imm_input"><path d="M 310 750 L 469.9 750" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 476.65 750 L 467.65 754.5 L 469.9 750 L 467.65 745.5 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-48" content="&lt;object label=&quot;&quot; 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pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction [31-12] (imm)</div></div></div></foreignObject><text x="366" y="740" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="9px" text-anchor="middle">Instruction [31-12] (imm)</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-49" content="&lt;object label=&quot;&quot; variable=&quot;alu_control&quot;/&gt;" data-label="" data-variable="alu_control"><path d="M 830 740 L 830 629.26" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 830 624.01 L 833.5 631.01 L 830 629.26 L 826.5 631.01 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-50"><path d="M 220 205 L 220 253 L 233.33 265 L 220 277 L 220 325 L 280 301 L 280 229 Z" fill="none" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="all"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 58px; height: 1px; padding-top: 265px; margin-left: 221px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Add</div></div></div></foreignObject><text x="250" y="269" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="12px" text-anchor="middle">Add</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-52" content="&lt;object label=&quot;&quot; stage=&quot;instruction_fetch&quot; variable=&quot;pc&quot;/&gt;" data-label="" data-stage="instruction_fetch" data-variable="pc"><path d="M 130 595 L 143 595" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-61" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 198px; margin-left: 999px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Branch</div></div></div></foreignObject><text x="999" y="201" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Branch</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-76" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;pc_plus_4&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="pc_plus_4"><path d="M 540 265 L 750 265" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-77" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 380px; margin-left: 360px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Instruction</div></div></div></foreignObject><text x="360" y="384" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Instruction</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-81" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="310" cy="542" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="all"/><rect x="290" y="522" width="40" height="40" fill="none" stroke="none" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-82" content="&lt;object label=&quot;&quot; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 397px; margin-left: 579px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">ReadWrite</div></div></div></foreignObject><text x="579" y="400" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">ReadWrite</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-116" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="630" cy="603" rx="3" ry="3" fill="#000000" stroke="none" pointer-events="all"/><rect x="610" y="583" width="40" height="40" fill="none" stroke="none" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-117" content="&lt;object label=&quot;&quot; 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" style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Jump Address</div></div></div></foreignObject><text x="971" y="142" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Jump Address</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-130" content="&lt;object label=&quot;&quot; stage=&quot;memory&quot; variable=&quot;mem_mux1_to_mem_mux2&quot;/&gt;" data-label="" data-stage="memory" data-variable="mem_mux1_to_mem_mux2"><path d="M 1119 183 L 1152.9 182.81" fill="none" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1159.65 182.77 L 1150.67 187.32 L 1152.9 182.81 L 1150.62 178.32 Z" fill="#000000" stroke="#000000" stroke-width="3" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-131"><path d="M 502.32 311.6 L 502.31 260 L 1219 260 L 1219 120 L 1189 120 L 1189 126.63" fill="none" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="stroke"/><path d="M 1189 131.88 L 1185.5 124.88 L 1189 126.63 L 1192.5 124.88 Z" fill="#ea6b66" stroke="#ea6b66" stroke-miterlimit="10" pointer-events="all"/></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-132"><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 290px; margin-left: 505px;"><div data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Jump</div></div></div></foreignObject><text x="505" y="293" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="11px" text-anchor="middle">Jump</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-137" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;pc_plus_4&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="pc_plus_4"><path d="M 280 265 L 540 265" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="stroke"/></g><g id="cell--Lmf1zb877u7wcXiO0Bk-16"><rect x="445" y="500" width="170" height="190" fill="rgb(255, 255, 255)" stroke="rgb(0, 0, 0)" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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text-align: left;"><div xmlns="http://www.w3.org/1999/xhtml" style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 19px; height: 1px; padding-top: 302px; margin-left: 180px;"><div data-drawio-colors="color: rgb(0, 0, 0); " style="box-sizing: border-box; font-size: 0px; text-align: center;"><div style="display: inline-block; font-size: 6px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: none; white-space: normal; overflow-wrap: normal;"><font style="font-size: 10px;">4</font></div></div></div></foreignObject><text x="190" y="303" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="6px" text-anchor="middle">4</text></switch></g></g><g id="cell-_5b_4j9nvjmzGaxmlqEA-8"><path d="M 800 526 L 800 569.6 L 813.33 580.5 L 800 591.4 L 800 635 L 860 613.2 L 860 547.8 Z" fill="#ffffff" stroke="rgb(0, 0, 0)" stroke-miterlimit="10" pointer-events="none"/><g transform="translate(-0.5 -0.5)"><switch><foreignObject pointer-events="none" width="100%" height="100%" requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" style="overflow: visible; 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background-color: rgb(255, 255, 255); white-space: nowrap;"><div>Instruction [19-15] (rs1)</div></div></div></div></foreignObject><text x="366" y="535" fill="rgb(0, 0, 0)" font-family="Helvetica" font-size="8px" text-anchor="middle">Instruction [19-15] (rs1)</text></switch></g></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-5" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot;/&gt;" data-label="" data-stage="instruction_decode"><ellipse cx="415" cy="542" rx="3" ry="3" fill="rgb(0, 0, 0)" stroke="none" pointer-events="none"/></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-6" content="&lt;object label=&quot;&quot; stage=&quot;instruction_decode&quot; variable=&quot;rs1&quot;/&gt;" data-label="" data-stage="instruction_decode" data-variable="rs1"><path d="M 415 542 L 415 478 L 653 478 L 653 535 L 707.9 535.28" fill="none" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/><path d="M 714.65 535.31 L 705.62 539.76 L 707.9 535.28 L 705.67 530.76 Z" fill="rgb(0, 0, 0)" stroke="rgb(0, 0, 0)" stroke-width="3" stroke-miterlimit="10" pointer-events="none"/></g><g id="cell-FCG2xz2OeAt8uY0nZYsg-8" content="&lt;object label=&quot;&quot; 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From 7428f07f9c47169486030ec88552994992b3ddb7 Mon Sep 17 00:00:00 2001
From: Geetis <capiix1@gmail.com>
Date: Fri, 29 Mar 2024 00:21:42 -0400
Subject: [PATCH 32/48] Fixed sign extension

---
 src/emulation_core/riscv/datapath.rs    | 58 +++++++++++++++++++------
 src/emulation_core/riscv/instruction.rs |  8 ++--
 2 files changed, 49 insertions(+), 17 deletions(-)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 158f57113..11be502bc 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -61,6 +61,8 @@ use crate::emulation_core::stack::Stack;
 use crate::emulation_core::stack::StackFrame;
 use serde::{Deserialize, Serialize};
 
+use gloo_console::log;
+
 /// An implementation of a datapath for the MIPS64 ISA.
 #[derive(Clone, PartialEq)]
 pub struct RiscDatapath {
@@ -95,9 +97,9 @@ pub struct RiscDatapathState {
     pub shamt: u32,
     pub funct3: u32,
     pub funct7: u32,
-    pub imm: u32,
-    pub imm1: u32,
-    pub imm2: u32,
+    pub imm: i32,
+    pub imm1: i32,
+    pub imm2: i32,
 
     /// *Data line.* The first input of the ALU.
     pub alu_input1: u64,
@@ -212,7 +214,7 @@ impl Default for RiscDatapath {
 
         // Set the stack pointer ($sp) to initially start at the end
         // of memory.
-        datapath.registers.gpr[29] = super::super::mips::memory::CAPACITY_BYTES as u64;
+        datapath.registers.gpr[2] = super::super::mips::memory::CAPACITY_BYTES as u64;
 
         datapath
     }
@@ -530,21 +532,21 @@ impl RiscDatapath {
                 self.state.rs1 = i.rs1 as u32;
                 self.state.funct3 = i.funct3 as u32;
                 self.state.rd = i.rd as u32;
-                self.state.imm = i.imm as u32;
+                self.state.imm = i.imm as i32;
                 self.state.shamt = (i.imm & 0x003f) as u32;
             }
             Instruction::SType(s) => {
                 self.state.rs2 = s.rs2 as u32;
                 self.state.rs1 = s.rs1 as u32;
                 self.state.funct3 = s.funct3 as u32;
-                self.state.imm1 = s.imm1 as u32;
-                self.state.imm2 = s.imm2 as u32;
+                self.state.imm1 = s.imm1 as i32;
+                self.state.imm2 = s.imm2 as i32;
             }
             Instruction::BType(b) => {
                 self.state.rs1 = b.rs1 as u32;
                 self.state.rs2 = b.rs2 as u32;
                 self.state.funct3 = b.funct3 as u32;
-                self.state.imm = b.imm as u32;
+                self.state.imm = b.imm as i32;
             }
             Instruction::UType(u) => {
                 self.state.imm = u.imm;
@@ -562,12 +564,21 @@ impl RiscDatapath {
 
     fn set_immediate(&mut self) {
         let mut signed_imm = 0x0000;
-        if self.state.instruction >> 31 == 1 {
-            signed_imm = 0xffffffff;
-        }
+        // if self.state.instruction >> 31 == 1 {
+        //     signed_imm = 0xffffffff;
+        // }
+
+        log!("self.state.imm: ", format!("{:012b}", self.state.imm));
 
         signed_imm = match self.signals.imm_select {
-            ImmSelect::ISigned => (signed_imm << 12) | self.state.imm,
+            ImmSelect::ISigned => {
+                let mask = 0b100000000000;
+                if self.state.imm & mask != 0 {
+                    !(!self.state.imm & 0xFFF)
+                } else {
+                    self.state.imm
+                }
+            }
             ImmSelect::IShamt => (signed_imm << 12) | self.state.imm,
             ImmSelect::IUnsigned => self.state.imm,
             ImmSelect::SType => ((signed_imm << 7) | self.state.imm1) << 5 | self.state.imm2,
@@ -576,6 +587,9 @@ impl RiscDatapath {
             ImmSelect::JType => self.state.imm,
         };
 
+        log!("signed_imm: ", format!("{:?}", signed_imm));
+        log!("self.state.imm: ", format!("{:?}", self.state.imm));
+
         self.state.imm = signed_imm;
     }
 
@@ -854,6 +868,8 @@ impl RiscDatapath {
             OP1Select::IMM => self.state.rs1 as u64,
         };
 
+        log!("self.state.imm (alu): ", format!("{:?}", self.state.imm));
+
         self.state.alu_input2 = match self.signals.op2_select {
             OP2Select::DATA2 => self.state.read_data_2,
             OP2Select::IMM => self.state.imm as i64 as u64,
@@ -869,6 +885,15 @@ impl RiscDatapath {
             self.state.alu_input2 = self.state.alu_input2 as u32 as i64 as u64;
         }
 
+        log!(
+            "self.state.alu_input1: ",
+            format!("{:?}", self.state.alu_input1)
+        );
+        log!(
+            "self.state.alu_input2: ",
+            format!("{:?}", self.state.alu_input2)
+        );
+
         // Set the result.
         self.state.alu_result = match self.signals.alu_op {
             AluOp::Addition => self.state.alu_input1.wrapping_add(self.state.alu_input2),
@@ -984,7 +1009,14 @@ impl RiscDatapath {
     }
 
     fn calc_relative_pc_branch(&mut self) {
-        self.state.relative_pc_branch = self.state.imm as u64 * 4;
+        log!("calc_relative_pc_branch");
+        log!(
+            "self.state.imm as u64",
+            format!("{:?}", self.state.imm as u64)
+        );
+        if self.state.imm > 0 {
+            self.state.relative_pc_branch = self.state.imm as u64 * 4;
+        }
     }
 
     /// Determine the value of the [`CpuBranch`] signal.
diff --git a/src/emulation_core/riscv/instruction.rs b/src/emulation_core/riscv/instruction.rs
index 795949d69..18966cdac 100644
--- a/src/emulation_core/riscv/instruction.rs
+++ b/src/emulation_core/riscv/instruction.rs
@@ -60,14 +60,14 @@ pub struct BType {
 
 #[derive(Clone, Copy, Debug, Default, PartialEq)]
 pub struct UType {
-    pub imm: u32,
+    pub imm: i32,
     pub rd: u8,
     pub op: u8,
 }
 
 #[derive(Clone, Copy, Debug, Default, PartialEq)]
 pub struct JType {
-    pub imm: u32,
+    pub imm: i32,
     pub rd: u8,
     pub op: u8,
 }
@@ -149,14 +149,14 @@ impl TryFrom<u32> for Instruction {
 
             // U-type instruction:
             OPCODE_LUI | OPCODE_AUIPC => Ok(Instruction::UType(UType {
-                imm: value >> 12,
+                imm: (value >> 12) as i32,
                 rd: ((value >> 7) & 0x1f) as u8,
                 op: (value & 0x7f) as u8,
             })),
 
             // J-type instruction:
             OPCODE_JAL => Ok(Instruction::JType(JType {
-                imm: value >> 12,
+                imm: (value >> 12) as i32,
                 rd: ((value >> 7) & 0x1f) as u8,
                 op: (value & 0x7f) as u8,
             })),

From 8d25bf6237101a8b21f4887e1acad4b02424a3f4 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Fri, 29 Mar 2024 00:36:43 -0400
Subject: [PATCH 33/48] Address clippy warnings

---
 src/emulation_core/riscv/datapath.rs | 1 -
 src/ui/visual_datapath/mod.rs        | 1 -
 src/ui/visual_datapath/utils.rs      | 2 +-
 3 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 2e8a8523b..1421d1eeb 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -59,7 +59,6 @@ use crate::emulation_core::datapath::{DatapathUpdateSignal, Syscall};
 use crate::emulation_core::riscv::registers::RiscGpRegisterType::{X10, X11};
 use crate::emulation_core::stack::Stack;
 use crate::emulation_core::stack::StackFrame;
-use gloo_console::log;
 use serde::{Deserialize, Serialize};
 
 /// An implementation of a datapath for the MIPS64 ISA.
diff --git a/src/ui/visual_datapath/mod.rs b/src/ui/visual_datapath/mod.rs
index b565fac28..f4abed410 100644
--- a/src/ui/visual_datapath/mod.rs
+++ b/src/ui/visual_datapath/mod.rs
@@ -25,7 +25,6 @@
 pub mod consts;
 pub mod utils;
 
-use gloo_console::log;
 use std::{cell::RefCell, rc::Rc};
 
 use gloo_events::EventListener;
diff --git a/src/ui/visual_datapath/utils.rs b/src/ui/visual_datapath/utils.rs
index 6ed40001a..180a0cd1e 100644
--- a/src/ui/visual_datapath/utils.rs
+++ b/src/ui/visual_datapath/utils.rs
@@ -541,7 +541,7 @@ pub fn visual_line_to_data(
                 "imm_input" => LineInformation {
                     title: String::from("Instruction [31-12] (immediate)"),
                     description: String::from("The part of the instruction used to extract the imm field from an instruction. In RISC-V, depending on the instruction type, the imm field can be split up within an instruction (S, B, and J type) or even out of order (B and J type)."),
-                    value: 0u64, // FIXME: Use the real line
+                    value: datapath_state.riscv.state.imm_input,
                     bits: 20,
                 },
                 "instruction" => LineInformation {

From bb6b00406ad491d3a68ce158c68078d261e33dc4 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Fri, 29 Mar 2024 00:48:00 -0400
Subject: [PATCH 34/48] Fixed my idiotic programming. Everything works now

---
 src/emulation_core/riscv/coprocessor.rs |  2 +-
 src/emulation_core/riscv/instruction.rs | 17 ++++++++---------
 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index cc12133d9..9aba1f522 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -480,7 +480,7 @@ impl RiscFpCoprocessor {
         };
     }
 
-    /// Set the data line that goes from `Read Data 1` to the multiplexer in the main processor
+    /// Set the data line that goes from `Read Data 2` to the multiplexer in the main processor
     /// controlled by [`MemWriteSrc`](super::control_signals::MemWriteSrc).
     fn write_fp_register_to_memory(&mut self) {
         self.state.fp_register_to_memory = self.state.read_data_2;
diff --git a/src/emulation_core/riscv/instruction.rs b/src/emulation_core/riscv/instruction.rs
index 7cad14a46..e1c9bc92f 100644
--- a/src/emulation_core/riscv/instruction.rs
+++ b/src/emulation_core/riscv/instruction.rs
@@ -121,15 +121,14 @@ impl TryFrom<u32> for Instruction {
             })),
 
             // I-type instructions:
-            OPCODE_IMM | OPCODE_IMM_32 | OPCODE_JALR | OPCODE_LOAD | OPCODE_SYSTEM => {
-                Ok(Instruction::IType(IType {
-                    imm: (value >> 20) as u16,
-                    rs1: ((value >> 15) & 0x1f) as u8,
-                    funct3: ((value >> 12) & 0x07) as u8,
-                    rd: ((value >> 7) & 0x1f) as u8,
-                    op: (value & 0x7f) as u8,
-                }))
-            }
+            OPCODE_IMM | OPCODE_IMM_32 | OPCODE_JALR | OPCODE_LOAD | OPCODE_SYSTEM
+            | OPCODE_LOAD_FP => Ok(Instruction::IType(IType {
+                imm: (value >> 20) as u16,
+                rs1: ((value >> 15) & 0x1f) as u8,
+                funct3: ((value >> 12) & 0x07) as u8,
+                rd: ((value >> 7) & 0x1f) as u8,
+                op: (value & 0x7f) as u8,
+            })),
 
             // S-type instruction:
             OPCODE_STORE | OPCODE_STORE_FP => Ok(Instruction::SType(SType {

From e35fa7bd26550227dede8077d955717dd17b79f6 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Fri, 29 Mar 2024 01:00:01 -0400
Subject: [PATCH 35/48] Fixed final instructions.

---
 src/emulation_core/riscv/coprocessor.rs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index 9aba1f522..c20b4ffb4 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -263,6 +263,11 @@ impl RiscFpCoprocessor {
                             _ => self.error("Unsupported Instruction!"),
                         }
                     }
+                    30 => {
+                        self.signals.data_write = DataWrite::YesWrite;
+                        self.signals.fpu_reg_write = FpuRegWrite::YesWrite;
+                        self.signals.data_src = DataSrc::MainProcessorBits;
+                    }
                     _ => self.error("Unsupported Instruction!"),
                 }
 

From 754bf2dc7f3443933041f490671d655ba9268641 Mon Sep 17 00:00:00 2001
From: Geetis <capiix1@gmail.com>
Date: Fri, 29 Mar 2024 01:22:19 -0400
Subject: [PATCH 36/48] Call and tail pseudo-instructions

---
 src/emulation_core/riscv/datapath.rs     |   1 +
 src/parser/pseudo_instruction_parsing.rs | 174 ++++++++++++++++++++++-
 2 files changed, 174 insertions(+), 1 deletion(-)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 11be502bc..9d432c4ac 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -519,6 +519,7 @@ impl RiscDatapath {
 
         // Set the data lines based on the contents of the instruction.
         // Some lines will hold uninitialized values as a result.
+        log!("Current Instruction: ", format!("{:?}", self.instruction));
         match self.instruction {
             Instruction::RType(r) => {
                 self.state.rs1 = r.rs1 as u32;
diff --git a/src/parser/pseudo_instruction_parsing.rs b/src/parser/pseudo_instruction_parsing.rs
index e01c15b70..0a8bc4019 100644
--- a/src/parser/pseudo_instruction_parsing.rs
+++ b/src/parser/pseudo_instruction_parsing.rs
@@ -1249,7 +1249,7 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
     data: &Vec<Data>,
     monaco_line_info: &mut [MonacoLineInfo],
 ) {
-    //figure out list of labels to be used for lw and sw labels
+    //figure out list of labels
     let mut list_of_labels: Vec<String> = Vec::new();
     for instruction in instructions.clone() {
         for label in instruction.labels {
@@ -1386,6 +1386,178 @@ pub fn expand_pseudo_instructions_and_assign_instruction_numbers_riscv(
                 monaco_line_info[instruction.line_number]
                     .update_pseudo_string(vec![instruction, &mut addi_instruction]);
             }
+            "call" => {
+                let info = PseudoDescription {
+                    name: "call".to_string(),
+                    syntax: "call offset".to_string(),
+                    translation_lines: vec![
+                        "auipc x6, offset[31:12]".to_string(),
+                        "jalr x1, x6, offset[11:0]".to_string(),
+                    ],
+                };
+                monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string();
+
+                // Change to function implementation
+                if !check_operands(instruction, 1) {
+                    continue;
+                }
+
+                // Parse the immediate value from the second operand
+                let imm_value: i32 = match instruction.operands[0].token_name.parse() {
+                    Ok(val) => val,
+                    Err(_) => {
+                        instruction.errors.push(Error {
+                            error_name: IncorrectImmediateValue,
+                            token_causing_error: instruction.operands[1].token_name.clone(),
+                            start_end_columns: instruction.operands[1].start_end_columns,
+                            message: "Invalid immediate value".to_string(),
+                        });
+                        continue;
+                    }
+                };
+
+                // Extract the upper and lower parts of the immediate value
+                let upper_imm = imm_value >> 12;
+                let lower_imm = imm_value & 0xFFF;
+
+                // auipc instruction
+                instruction.operator.token_name = "auipc".to_string();
+                instruction.operator.start_end_columns = (0, 0);
+                instruction.operator.token_type = Default::default();
+                instruction.operands[0].token_name = "x6".to_string();
+                instruction.operands.insert(
+                    1,
+                    Token {
+                        token_name: upper_imm.to_string(),
+                        start_end_columns: (0, 0),
+                        token_type: Default::default(),
+                    },
+                );
+                instruction.binary = 0;
+                instruction.errors = vec![];
+                instruction.labels = Vec::new();
+
+                // jalr instruction
+                let mut jalr_instruction = Instruction {
+                    operator: Token {
+                        token_name: "jalr".to_string(),
+                        start_end_columns: (0, 0),
+                        token_type: Default::default(),
+                    },
+                    operands: vec![
+                        Token {
+                            token_name: "x1".to_string(),
+                            start_end_columns: (0, 0),
+                            token_type: Default::default(),
+                        },
+                        Token {
+                            token_name: "x6".to_string(),
+                            start_end_columns: (0, 0),
+                            token_type: Default::default(),
+                        },
+                        Token {
+                            token_name: lower_imm.to_string(),
+                            start_end_columns: (0, 0),
+                            token_type: Default::default(),
+                        },
+                    ],
+                    binary: 0,
+                    instruction_number: instruction.instruction_number + 1,
+                    line_number: instruction.line_number,
+                    errors: vec![],
+                    labels: Vec::new(),
+                };
+                vec_of_added_instructions.push(jalr_instruction.clone());
+
+                monaco_line_info[instruction.line_number]
+                    .update_pseudo_string(vec![instruction, &mut jalr_instruction]);
+            }
+            "tail" => {
+                let info = PseudoDescription {
+                    name: "tail".to_string(),
+                    syntax: "tail offset".to_string(),
+                    translation_lines: vec![
+                        "auipc x6, offset[31:12]".to_string(),
+                        "jalr x0, x6, offset[11:0]".to_string(),
+                    ],
+                };
+                monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string();
+
+                // Change to function implementation
+                if !check_operands(instruction, 1) {
+                    continue;
+                }
+
+                // Parse the immediate value from the second operand
+                let imm_value: i32 = match instruction.operands[0].token_name.parse() {
+                    Ok(val) => val,
+                    Err(_) => {
+                        instruction.errors.push(Error {
+                            error_name: IncorrectImmediateValue,
+                            token_causing_error: instruction.operands[1].token_name.clone(),
+                            start_end_columns: instruction.operands[1].start_end_columns,
+                            message: "Invalid immediate value".to_string(),
+                        });
+                        continue;
+                    }
+                };
+
+                // Extract the upper and lower parts of the immediate value
+                let upper_imm = imm_value >> 12;
+                let lower_imm = imm_value & 0xFFF;
+
+                // auipc instruction
+                instruction.operator.token_name = "auipc".to_string();
+                instruction.operator.start_end_columns = (0, 0);
+                instruction.operator.token_type = Default::default();
+                instruction.operands[0].token_name = "x6".to_string();
+                instruction.operands.insert(
+                    1,
+                    Token {
+                        token_name: upper_imm.to_string(),
+                        start_end_columns: (0, 0),
+                        token_type: Default::default(),
+                    },
+                );
+                instruction.binary = 0;
+                instruction.errors = vec![];
+                instruction.labels = Vec::new();
+
+                // jalr instruction
+                let mut jalr_instruction = Instruction {
+                    operator: Token {
+                        token_name: "jalr".to_string(),
+                        start_end_columns: (0, 0),
+                        token_type: Default::default(),
+                    },
+                    operands: vec![
+                        Token {
+                            token_name: "x0".to_string(),
+                            start_end_columns: (0, 0),
+                            token_type: Default::default(),
+                        },
+                        Token {
+                            token_name: "x6".to_string(),
+                            start_end_columns: (0, 0),
+                            token_type: Default::default(),
+                        },
+                        Token {
+                            token_name: lower_imm.to_string(),
+                            start_end_columns: (0, 0),
+                            token_type: Default::default(),
+                        },
+                    ],
+                    binary: 0,
+                    instruction_number: instruction.instruction_number + 1,
+                    line_number: instruction.line_number,
+                    errors: vec![],
+                    labels: Vec::new(),
+                };
+                vec_of_added_instructions.push(jalr_instruction.clone());
+
+                monaco_line_info[instruction.line_number]
+                    .update_pseudo_string(vec![instruction, &mut jalr_instruction]);
+            }
             "mv" => {
                 // Set Pseudo Description
                 let info = PseudoDescription {

From ecf76fdd73bfc0ded7b0ef3aeca0ecbdf4a79215 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Fri, 29 Mar 2024 01:28:05 -0400
Subject: [PATCH 37/48] Connect the FP registers to the visual display

---
 src/agent.rs                            |  5 +++++
 src/agent/datapath_reducer.rs           | 18 +++++++++++++++++-
 src/agent/messages.rs                   |  3 ++-
 src/bin/main.rs                         |  3 +--
 src/emulation_core/riscv/coprocessor.rs |  4 ++--
 src/emulation_core/riscv/registers.rs   | 23 +++++++++++------------
 src/ui/regview/component.rs             |  4 ++--
 7 files changed, 40 insertions(+), 20 deletions(-)

diff --git a/src/agent.rs b/src/agent.rs
index 1b50b1d01..16d19bb9c 100644
--- a/src/agent.rs
+++ b/src/agent.rs
@@ -159,6 +159,11 @@ pub async fn emulation_core_agent(scope: ReactorScope<Command, DatapathUpdate>)
                         state.updates.changed_stack,
                         RiscStateUpdate::UpdateStack(datapath.stack.clone())
                     );
+                    send_update_riscv!(
+                        state.scope,
+                        state.updates.changed_coprocessor_registers,
+                        RiscStateUpdate::UpdateCoprocessorRegisters(datapath.coprocessor.registers)
+                    );
                 }
             }
             state.updates = Default::default();
diff --git a/src/agent/datapath_reducer.rs b/src/agent/datapath_reducer.rs
index 2e32746e9..6c6160515 100644
--- a/src/agent/datapath_reducer.rs
+++ b/src/agent/datapath_reducer.rs
@@ -8,7 +8,9 @@ use crate::emulation_core::mips::gp_registers::{GpRegisterType, GpRegisters};
 use crate::emulation_core::mips::memory::Memory;
 use crate::emulation_core::register::{RegisterType, Registers};
 use crate::emulation_core::riscv::datapath::{RiscDatapathState, RiscStage};
-use crate::emulation_core::riscv::registers::{RiscGpRegisterType, RiscGpRegisters};
+use crate::emulation_core::riscv::registers::{
+    RiscFpRegisters, RiscGpRegisterType, RiscGpRegisters,
+};
 use crate::emulation_core::stack::Stack;
 use gloo_console::log;
 use std::rc::Rc;
@@ -40,6 +42,7 @@ pub struct MipsCoreState {
 pub struct RiscCoreState {
     pub state: RiscDatapathState,
     pub registers: RiscGpRegisters,
+    pub coprocessor_registers: RiscFpRegisters,
     pub memory: Memory,
     pub current_stage: RiscStage,
     pub stack: Stack,
@@ -151,6 +154,12 @@ impl Reducible for DatapathReducer {
                         stack,
                         ..self.riscv.clone()
                     },
+                    RiscStateUpdate::UpdateCoprocessorRegisters(coprocessor_registers) => {
+                        RiscCoreState {
+                            coprocessor_registers,
+                            ..self.riscv.clone()
+                        }
+                    }
                 },
                 ..(*self).clone()
             },
@@ -180,6 +189,13 @@ impl DatapathReducer {
         }
     }
 
+    pub fn get_dyn_fp_registers(&self) -> Vec<(Rc<dyn RegisterType>, u64)> {
+        match self.current_architecture {
+            MIPS => self.mips.coprocessor_registers.get_dyn_register_list(),
+            RISCV => self.riscv.coprocessor_registers.get_dyn_register_list(),
+        }
+    }
+
     pub fn get_memory(&self) -> &Memory {
         match self.current_architecture {
             MIPS => &self.mips.memory,
diff --git a/src/agent/messages.rs b/src/agent/messages.rs
index 2943f4caa..51a8dbbfd 100644
--- a/src/agent/messages.rs
+++ b/src/agent/messages.rs
@@ -4,7 +4,7 @@ use crate::emulation_core::mips::fp_registers::FpRegisters;
 use crate::emulation_core::mips::gp_registers::GpRegisters;
 use crate::emulation_core::mips::memory::Memory;
 use crate::emulation_core::riscv::datapath::{RiscDatapathState, RiscStage};
-use crate::emulation_core::riscv::registers::RiscGpRegisters;
+use crate::emulation_core::riscv::registers::{RiscFpRegisters, RiscGpRegisters};
 use crate::emulation_core::stack::Stack;
 use crate::emulation_core::{architectures::AvailableDatapaths, mips::datapath::Stage};
 use serde::{Deserialize, Serialize};
@@ -44,6 +44,7 @@ pub enum MipsStateUpdate {
 pub enum RiscStateUpdate {
     UpdateState(RiscDatapathState),
     UpdateRegisters(RiscGpRegisters),
+    UpdateCoprocessorRegisters(RiscFpRegisters),
     UpdateMemory(Memory),
     UpdateStage(RiscStage),
     UpdateStack(Stack),
diff --git a/src/bin/main.rs b/src/bin/main.rs
index e6f7d9c82..3f9a84992 100644
--- a/src/bin/main.rs
+++ b/src/bin/main.rs
@@ -32,7 +32,6 @@ use web_sys::HtmlInputElement;
 use yew::prelude::*;
 use yew::{html, Html, Properties};
 
-use swim::emulation_core::register::Registers;
 use swim::emulation_core::riscv::datapath::RiscStage;
 use yew_agent::Spawnable;
 
@@ -657,7 +656,7 @@ fn app(props: &AppProps) -> Html {
                 </div>
 
                 // Right column
-                <Regview gp={datapath_state.get_dyn_gp_registers()} fp={datapath_state.mips.coprocessor_registers.get_dyn_register_list()} pc_limit={*pc_limit} communicator={props.communicator}/>
+                <Regview gp={datapath_state.get_dyn_gp_registers()} fp={datapath_state.get_dyn_fp_registers()} pc_limit={*pc_limit} communicator={props.communicator}/>
             </div>
         </>
     }
diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index c20b4ffb4..c23ef4041 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -4,7 +4,7 @@ use std::ops::Neg;
 
 use super::constants::*;
 use super::instruction::Instruction;
-use super::registers::FpRegisters;
+use super::registers::RiscFpRegisters;
 use super::{constants::RISC_NAN, control_signals::floating_point::*};
 use serde::{Deserialize, Serialize};
 
@@ -18,7 +18,7 @@ pub struct RiscFpCoprocessor {
     pub signals: FpuControlSignals,
     pub state: RiscFpuState,
     pub is_halted: bool,
-    pub registers: FpRegisters,
+    pub registers: RiscFpRegisters,
     pub condition_code: u64,
     pub data: u64,
 }
diff --git a/src/emulation_core/riscv/registers.rs b/src/emulation_core/riscv/registers.rs
index c5d763b8e..aeb28bcc7 100644
--- a/src/emulation_core/riscv/registers.rs
+++ b/src/emulation_core/riscv/registers.rs
@@ -260,12 +260,12 @@ impl IntoIterator for RiscGpRegisters {
 
 /// Collection of general-purpose registers used by the datapath.
 #[derive(Clone, Copy, Debug, Default, PartialEq, Serialize, Deserialize)]
-pub struct FpRegisters {
+pub struct RiscFpRegisters {
     pub fpr: [u64; 32],
 }
 
 /// Specifies all of the valid registers accessible in an instance
-/// of [`FpRegisters`].
+/// of [`RiscFpRegisters`].
 #[derive(Clone, Copy, Debug, Display, EnumIter, EnumString, Eq, PartialEq)]
 #[strum(ascii_case_insensitive)]
 #[strum(serialize_all = "lowercase")]
@@ -302,7 +302,6 @@ pub enum FpRegisterType {
     F29 = 29,
     F30 = 30,
     F31 = 31,
-    FCSR = 32,
 }
 
 impl RegisterType for FpRegisterType {
@@ -314,7 +313,7 @@ impl RegisterType for FpRegisterType {
     }
 }
 
-impl Registers for FpRegisters {
+impl Registers for RiscFpRegisters {
     fn get_dyn_register_list(&self) -> Vec<(Rc<dyn RegisterType>, u64)> {
         self.into_iter()
             .map(|(register, val)| {
@@ -325,7 +324,7 @@ impl Registers for FpRegisters {
     }
 }
 
-impl ToString for FpRegisters {
+impl ToString for RiscFpRegisters {
     fn to_string(&self) -> String {
         let mut output = String::new();
 
@@ -342,7 +341,7 @@ impl ToString for FpRegisters {
     }
 }
 
-impl Index<&str> for FpRegisters {
+impl Index<&str> for RiscFpRegisters {
     type Output = u64;
 
     // Convert string to the corresponding RegistersEnum value and use this to index.
@@ -355,7 +354,7 @@ impl Index<&str> for FpRegisters {
     }
 }
 
-impl IndexMut<&str> for FpRegisters {
+impl IndexMut<&str> for RiscFpRegisters {
     // Convert string to the corresponding RegistersEnum value and use this to index.
     // If this is an invalid string, no enum will be returned, causing a panic as desired.
     fn index_mut(&mut self, index: &str) -> &mut Self::Output {
@@ -366,7 +365,7 @@ impl IndexMut<&str> for FpRegisters {
     }
 }
 
-impl Index<FpRegisterType> for FpRegisters {
+impl Index<FpRegisterType> for RiscFpRegisters {
     type Output = u64;
 
     fn index(&self, index: FpRegisterType) -> &Self::Output {
@@ -374,7 +373,7 @@ impl Index<FpRegisterType> for FpRegisters {
     }
 }
 
-impl IndexMut<FpRegisterType> for FpRegisters {
+impl IndexMut<FpRegisterType> for RiscFpRegisters {
     fn index_mut(&mut self, index: FpRegisterType) -> &mut Self::Output {
         &mut self.fpr[index as usize]
     }
@@ -388,7 +387,7 @@ impl IndexMut<FpRegisterType> for FpRegisters {
 /// normally just "add 1" to get to the next register, we use an internal iterator
 /// that can track the progression of one [`FpRegisterType`] to the next.
 pub struct FpRegistersIter {
-    registers: FpRegisters,
+    registers: RiscFpRegisters,
     register_iter: FpRegisterTypeIter,
 }
 
@@ -408,11 +407,11 @@ impl Iterator for FpRegistersIter {
 /// [`IntoIterator`] is a standard library trait that can convert any type into
 /// an [`Iterator`]. In this case, this is an instance of [`FpRegistersIter`] with all the
 /// data in the registers and a new [`FpRegisterTypeIter`].
-impl IntoIterator for FpRegisters {
+impl IntoIterator for RiscFpRegisters {
     type Item = (FpRegisterType, u64);
     type IntoIter = FpRegistersIter;
 
-    /// Consumes the [`FpRegisters`] struct to create a new [`FpRegistersIter`] that can
+    /// Consumes the [`RiscFpRegisters`] struct to create a new [`FpRegistersIter`] that can
     /// be iterated over.
     fn into_iter(self) -> Self::IntoIter {
         FpRegistersIter {
diff --git a/src/ui/regview/component.rs b/src/ui/regview/component.rs
index eb4abcf14..f7953e28c 100644
--- a/src/ui/regview/component.rs
+++ b/src/ui/regview/component.rs
@@ -177,8 +177,8 @@ pub fn generate_fpr_rows(props: &Regviewprops, unit_type: UnitState) -> Html {
                         }}
                         value={
                             match unit_type {
-                                UnitState::Float => format!("{:e}", data).to_string(),
-                                UnitState::Double => format!("{:e}", data).to_string(),
+                                UnitState::Float => format!("{}", f32::from_bits(data as u32)).to_string(),
+                                UnitState::Double => format!("{}", f64::from_bits(data)).to_string(),
                                 UnitState::Hex => format!("{:#04x?}", data).to_string(),
                                 UnitState::Bin => format!("{:#b}", data).to_string(),
                                 _ => format!("{:?}", data).to_string(),

From 953a311e69261a408d41e8f542d161ba10890304 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Fri, 29 Mar 2024 01:50:09 -0400
Subject: [PATCH 38/48] Avoid highlighting the first line at the end of
 execution

---
 src/bin/main.rs                 | 11 ++++++++---
 src/ui/swim_editor/component.rs |  5 ++++-
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/bin/main.rs b/src/bin/main.rs
index c54f2598e..94a8bc115 100644
--- a/src/bin/main.rs
+++ b/src/bin/main.rs
@@ -235,7 +235,10 @@ fn app(props: &AppProps) -> Html {
 
                 let list_of_line_numbers = program_info.address_to_line_number;
                 let index = datapath_state.get_pc() as usize / 4;
-                editor_curr_line.set(*list_of_line_numbers.get(index).unwrap_or(&0) as f64 + 1.0); // add one to account for the editor's line numbers
+                editor_curr_line.set(match list_of_line_numbers.get(index) {
+                    Some(val) => (val + 1) as f64,
+                    None => 0f64,
+                });
                 memory_curr_instr.set(datapath_state.get_pc());
 
                 // Execute instruction
@@ -294,8 +297,10 @@ fn app(props: &AppProps) -> Html {
 
                     let list_of_line_numbers = program_info.address_to_line_number;
                     let index = datapath_state.get_pc() as usize / 4;
-                    editor_curr_line
-                        .set(*list_of_line_numbers.get(index).unwrap_or(&0) as f64 + 1.0);
+                    editor_curr_line.set(match list_of_line_numbers.get(index) {
+                        Some(val) => (val + 1) as f64,
+                        None => 0f64,
+                    });
                     memory_curr_instr.set(datapath_state.get_pc());
                     communicator.execute_stage();
                 } else {
diff --git a/src/ui/swim_editor/component.rs b/src/ui/swim_editor/component.rs
index b6d41bd6a..0300cedeb 100644
--- a/src/ui/swim_editor/component.rs
+++ b/src/ui/swim_editor/component.rs
@@ -118,7 +118,10 @@ pub fn SwimEditor(props: &SwimEditorProps) -> Html {
             let program_info = props.program_info.clone();
             let list_of_line_numbers = program_info.address_to_line_number;
             let index = props.pc as usize / 4;
-            curr_line.set(*list_of_line_numbers.get(index).unwrap_or(&0) as f64 + 1.0);
+            curr_line.set(match list_of_line_numbers.get(index) {
+                Some(val) => (val + 1) as f64,
+                None => 0f64,
+            });
             // add one to account for the editor's line numbers
         }
 

From af5afa84992e17bc4da965911d00dca055d4fb09 Mon Sep 17 00:00:00 2001
From: Geetis <capiix1@gmail.com>
Date: Fri, 29 Mar 2024 01:57:49 -0400
Subject: [PATCH 39/48] Sign-extend S-type and adjust riscv_fib

---
 src/emulation_core/riscv/datapath.rs   | 10 +++++++++-
 static/assembly_examples/riscv_fib.asm |  3 ---
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 9d432c4ac..cac824a8d 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -582,7 +582,15 @@ impl RiscDatapath {
             }
             ImmSelect::IShamt => (signed_imm << 12) | self.state.imm,
             ImmSelect::IUnsigned => self.state.imm,
-            ImmSelect::SType => ((signed_imm << 7) | self.state.imm1) << 5 | self.state.imm2,
+            ImmSelect::SType => {
+                let uimm = ((signed_imm << 7) | self.state.imm1) << 5 | self.state.imm2;
+                let mask = 0b100000000000;
+                if uimm & mask != 0 {
+                    !(!uimm & 0xFFF)
+                } else {
+                    self.state.imm
+                }
+            }
             ImmSelect::BType => self.state.imm,
             ImmSelect::UType => ((signed_imm << 20) | self.state.imm) << 12,
             ImmSelect::JType => self.state.imm,
diff --git a/static/assembly_examples/riscv_fib.asm b/static/assembly_examples/riscv_fib.asm
index 424c2c231..51fd1f6d4 100644
--- a/static/assembly_examples/riscv_fib.asm
+++ b/static/assembly_examples/riscv_fib.asm
@@ -15,13 +15,11 @@ L2:
  lw a5,-20(s0)
  addi a5,a5,-1
  mv a0,a5
- auipc ra,0
  jalr ra # 26 <.L2+0x8>
  mv s1,a0
  lw a5,-20(s0)
  addi a5,a5,-2
  mv a0,a5
- auipc ra,0
  jalr ra # 38 <.L2+0x1a>
  mv a5,a0
  add a5,a5,s1
@@ -42,7 +40,6 @@ main:
  li a5,5
  sw a5,-20(s0)
  lw a0,-20(s0)
- auipc ra,0
  jalr ra # 62 <main+0x12>
  sw a0,-24(s0)
  lw a5,-24(s0)

From 0d1076dcd25b8657bcbbc697397c890961848958 Mon Sep 17 00:00:00 2001
From: rharding8 <ry287616@ucf.edu>
Date: Fri, 29 Mar 2024 02:08:15 -0400
Subject: [PATCH 40/48] Fixed my stupid coprocessor.

---
 src/emulation_core/riscv/coprocessor.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/emulation_core/riscv/coprocessor.rs b/src/emulation_core/riscv/coprocessor.rs
index c23ef4041..a542144e8 100644
--- a/src/emulation_core/riscv/coprocessor.rs
+++ b/src/emulation_core/riscv/coprocessor.rs
@@ -321,7 +321,7 @@ impl RiscFpCoprocessor {
                     }
                 };
             }
-            _ => self.error("Unsupported Instruction!"),
+            _ => (),
         }
     }
 

From 9a442de7299b78a0cfda397fb2c684f7c81f9075 Mon Sep 17 00:00:00 2001
From: Geetis <capiix1@gmail.com>
Date: Fri, 29 Mar 2024 02:52:11 -0400
Subject: [PATCH 41/48] Fixed S-type instruction immediate

---
 src/emulation_core/riscv/datapath.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 7aceedf24..516a8a4e6 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -623,7 +623,7 @@ impl RiscDatapath {
                 if uimm & mask != 0 {
                     !(!uimm & 0xFFF)
                 } else {
-                    self.state.imm
+                    uimm
                 }
             }
             ImmSelect::BType => self.state.imm,

From 4da8faa9b781439d82c5dcf0e8ca36c74b490d2a Mon Sep 17 00:00:00 2001
From: Geetis <capiix1@gmail.com>
Date: Fri, 29 Mar 2024 03:11:31 -0400
Subject: [PATCH 42/48] Updated RISC-V fib. THANKS BROOKS!!!!! <3

---
 static/assembly_examples/riscv_fib.asm | 72 +++++++++-----------------
 1 file changed, 25 insertions(+), 47 deletions(-)

diff --git a/static/assembly_examples/riscv_fib.asm b/static/assembly_examples/riscv_fib.asm
index 51fd1f6d4..e5d745b27 100644
--- a/static/assembly_examples/riscv_fib.asm
+++ b/static/assembly_examples/riscv_fib.asm
@@ -1,50 +1,28 @@
-fib:
- addi sp,sp,-32
- sw ra,28(sp)
- sw s0,24(sp)
- sw s1,20(sp)
- addi s0,sp,32
- sw a0,-20(s0)
- lw a4,-20(s0)
- li a5,1
- blt a5,a4,L2
- lw a5,-20(s0)
- j L3
+fib(int):
+        # t0 and t1 are the last two values of the fib sequence
+        ori t0, zero, 0 # a_n-2
+        ori t1, zero, 1 # a_n-1
+        ori t2, zero, 1 # a_n
+        ori t3, zero, 1 # index
 
-L2:
- lw a5,-20(s0)
- addi a5,a5,-1
- mv a0,a5
- jalr ra # 26 <.L2+0x8>
- mv s1,a0
- lw a5,-20(s0)
- addi a5,a5,-2
- mv a0,a5
- jalr ra # 38 <.L2+0x1a>
- mv a5,a0
- add a5,a5,s1
-
-L3:
- mv a0,a5
- lw ra,28(sp)
- lw s0,24(sp)
- lw s1,20(sp)
- addi sp,sp,32
- ret
+COND:
+        bne a0, t3, LOOP # If we've reached our index, return
+        or a1, zero, t2
+        #Pseudo-Instruction: ret
+        jalr x0, x1, 0 #Pseudo-Instruction Translation
 
+LOOP:
+        # Legendary fibonacci calculation
+        add t2, t0, t1
+        or t0, zero, t1
+        or t1, zero, t2
+        addi t3, t3, 1
+        jal x0, COND
+        
 main:
- addi sp,sp,-32
- sw ra,28(sp)
- sw s0,24(sp)
- addi s0,sp,32
- li a5,5
- sw a5,-20(s0)
- lw a0,-20(s0)
- jalr ra # 62 <main+0x12>
- sw a0,-24(s0)
- lw a5,-24(s0)
- mv a0,a5
- lw ra,28(sp)
- lw s0,24(sp)
- addi sp,sp,32
- ret
\ No newline at end of file
+        ori a0, zero, 15
+        jal ra, fib(int)
+        ori a0, zero, 1
+        ecall
+        ori a0, zero, 0
+        ecall
\ No newline at end of file

From 9e531a8b08ef7145cc72cda2680aaa39b5ea467b Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Fri, 29 Mar 2024 04:06:09 -0400
Subject: [PATCH 43/48] Add new data lines for visual datapath

---
 src/emulation_core/riscv/datapath.rs |  9 ++++-----
 src/ui/visual_datapath/utils.rs      | 18 ++++++++++++------
 2 files changed, 16 insertions(+), 11 deletions(-)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 3a126930f..906b09a6e 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -178,6 +178,7 @@ pub struct RiscDatapathState {
     pub write_data: u64,
 
     pub imm_input: u64,
+    pub i_type_jump: u64,
 }
 
 /// The possible stages the datapath could be in during execution.
@@ -393,7 +394,7 @@ impl RiscDatapath {
         self.set_control_signals();
         self.set_immediate();
         self.read_registers();
-
+        self.construct_jump_address();
         self.coprocessor.stage_instruction_decode();
         self.coprocessor
             .set_data_from_main_processor(self.state.read_data_1);
@@ -1065,10 +1066,6 @@ impl RiscDatapath {
             self.state.alu_result = self.state.alu_result as u32 as i64 as u64;
         }
 
-        if self.signals.branch_jump == BranchJump::J {
-            self.construct_jump_address();
-        }
-
         // Set the zero bit/signal.
         self.datapath_signals.alu_z = match self.state.alu_result {
             0 => AluZ::YesZero,
@@ -1104,6 +1101,8 @@ impl RiscDatapath {
     }
 
     fn construct_jump_address(&mut self) {
+        self.state.i_type_jump =
+            (self.state.imm as u64 + self.state.read_data_1) & 0xfffffffffffffff0;
         self.state.jump_address = match self.instruction {
             Instruction::IType(_i) => self.state.imm as u64 + self.state.read_data_1,
             Instruction::JType(_j) => self.state.imm as u64 * 4,
diff --git a/src/ui/visual_datapath/utils.rs b/src/ui/visual_datapath/utils.rs
index 180a0cd1e..639d431eb 100644
--- a/src/ui/visual_datapath/utils.rs
+++ b/src/ui/visual_datapath/utils.rs
@@ -544,18 +544,24 @@ pub fn visual_line_to_data(
                     value: datapath_state.riscv.state.imm_input,
                     bits: 20,
                 },
+                "imm_shifted_left_by_2" => LineInformation {
+                    title: String::from("Immediate (shifted left by 2)"),
+                    description: String::from("The immediate field shifed left by two bits. This value is later used as a jump address."),
+                    value: (datapath_state.riscv.state.imm << 2) as u64,
+                    bits: 22,
+                },
+                "i_type_address" => LineInformation {
+                    title: String::from("I Type Jump Address"),
+                    description: String::from("The jump address used for I type jump instructions. This is calculated by adding the immediate value and the contents of rs1."),
+                    value: datapath_state.riscv.state.i_type_jump,
+                    bits: 22,
+                },
                 "instruction" => LineInformation {
                     title: String::from("Instruction"),
                     description: String::from("The currently-loaded instruction. This is broken down into different fields, where each field serves a different purpose in identifying what the instruction does."),
                     value: datapath_state.riscv.state.instruction as u64,
                     bits: 32,
                 },
-                "i_type_address" => LineInformation {
-                    title: String::from("I type jump address"),
-                    description: String::from("The jump address used for I type instructions. Calculated from the data in rs1 and imm."),
-                    value: 0u64, // FIXME: Use the real line
-                    bits: 16,
-                },
                 "jump_address" => LineInformation {
                     title: String::from("Jump Address"),
                     description: String::from("The calculated next program counter for jump instructions. For I type instructions, this is the immediate value added to the data in rs1. For U type instructions, this is the immediate value shifted left by 2."),

From 8204869e764bab6208749af4e8bd6f2b8667b60a Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Fri, 29 Mar 2024 05:04:19 -0400
Subject: [PATCH 44/48] Fix negative imm values

---
 src/emulation_core/riscv/datapath.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index b20b354e8..41a3f0acb 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -1102,10 +1102,10 @@ impl RiscDatapath {
 
     fn construct_jump_address(&mut self) {
         self.state.i_type_jump =
-            (self.state.imm as u64 + self.state.read_data_1) & 0xfffffffffffffff0;
+            ((self.state.imm as u64).wrapping_add(self.state.read_data_1)) & 0xfffffffffffffff0;
         self.state.jump_address = match self.instruction {
-            Instruction::IType(_i) => self.state.imm as u64 + self.state.read_data_1,
-            Instruction::JType(_j) => self.state.imm as u64 * 4,
+            Instruction::IType(_i) => (self.state.imm as u64).wrapping_add(self.state.read_data_1),
+            Instruction::JType(_j) => (self.state.imm as u64).wrapping_shl(2),
             _ => self.state.jump_address,
         }
     }

From 259873f203cb6c658a2b9282fbe34c315d586fbc Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Fri, 29 Mar 2024 05:09:01 -0400
Subject: [PATCH 45/48] Fix breakpoints regression

---
 src/agent.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/agent.rs b/src/agent.rs
index 16d19bb9c..833913b52 100644
--- a/src/agent.rs
+++ b/src/agent.rs
@@ -309,7 +309,7 @@ impl EmulatorCoreAgentState {
             DatapathRef::MIPS(datapath) => datapath.registers.pc,
             DatapathRef::RISCV(datapath) => datapath.registers.pc,
         };
-        if self.breakpoints.contains(&current_pc) && self.updates.hit_breakpoint {
+        if self.breakpoints.contains(&current_pc) || self.updates.hit_breakpoint {
             self.executing = false;
             // Unset the hit_breakpoint flag after processing
             self.updates.hit_breakpoint = false;

From 2a6a3d7494803edd8cfd0f64e1529041b8db65c4 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Fri, 29 Mar 2024 05:27:49 -0400
Subject: [PATCH 46/48] Evil hack to fix the stack view in RISC-V

---
 src/emulation_core/riscv/datapath.rs | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/emulation_core/riscv/datapath.rs b/src/emulation_core/riscv/datapath.rs
index 41a3f0acb..19159bc9a 100644
--- a/src/emulation_core/riscv/datapath.rs
+++ b/src/emulation_core/riscv/datapath.rs
@@ -473,7 +473,9 @@ impl RiscDatapath {
             changed_stack = true;
         }
 
-        let hit_jump = matches!(self.signals.branch_jump, BranchJump::J);
+        let hit_jump = matches!(self.signals.branch_jump, BranchJump::J)
+            // Evil hack to stop JALR from appearing in the stack frame viewer
+            && ((self.state.instruction & 0b1111111) as u8 != OPCODE_JALR);
         if hit_jump {
             // Add current line to stack if we call a function
             let frame = StackFrame::new(

From f5863aca17456663debfb7f25494df389eba84f6 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Fri, 29 Mar 2024 05:30:47 -0400
Subject: [PATCH 47/48] OOPs silly me I used the wrong register for sp and that
 broke the stack frame

---
 src/agent/datapath_reducer.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/agent/datapath_reducer.rs b/src/agent/datapath_reducer.rs
index b651e1023..cb09a691a 100644
--- a/src/agent/datapath_reducer.rs
+++ b/src/agent/datapath_reducer.rs
@@ -178,7 +178,7 @@ impl DatapathReducer {
     pub fn get_sp(&self) -> u64 {
         match self.current_architecture {
             MIPS => self.mips.registers[GpRegisterType::Sp],
-            RISCV => self.riscv.registers[RiscGpRegisterType::X1],
+            RISCV => self.riscv.registers[RiscGpRegisterType::X2],
         }
     }
 

From 3514992a20d52b3b4bd140666b1cf1e2d6cee530 Mon Sep 17 00:00:00 2001
From: Brooks McKinley <31021010+brooksmckinley@users.noreply.github.com>
Date: Fri, 29 Mar 2024 05:33:53 -0400
Subject: [PATCH 48/48] Recursive version of riscv_fib to show off the stack
 viewer

---
 .../assembly_examples/riscv_fib_recursive.asm | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 static/assembly_examples/riscv_fib_recursive.asm

diff --git a/static/assembly_examples/riscv_fib_recursive.asm b/static/assembly_examples/riscv_fib_recursive.asm
new file mode 100644
index 000000000..5d67e4bfd
--- /dev/null
+++ b/static/assembly_examples/riscv_fib_recursive.asm
@@ -0,0 +1,55 @@
+fib(int):
+        # Stack variables: | return addr | argument | n - 1 | n - 2 |
+
+        # Save return address and argument
+        sw ra, 0(sp)
+        sw a0, 4(sp)
+
+        ori t0, zero, 0
+        ori t1, zero, 1
+        beq a0, t0, RET_0
+        beq a0, t1, RET_1
+
+        # Recursive call for fib(n-1)
+        addi a0, a0, -1 # Setting arg
+        addi sp, sp, -16 # Making space on the stack
+        jal ra, fib(int)
+        sw a1, 8(sp) # Storing the return value
+        lw a0, 4(sp) # Restoring our original argument
+
+        # Recursive call for fib(n-2)
+        addi a0, a0, -2
+        addi sp, sp, -16
+        jal ra, fib(int)
+        sw a1, 12(sp)
+
+        # Adding together n-1 and n-2 and returning
+        lw t0, 8(sp)
+        lw t1, 12(sp)
+
+        add a1, t0, t1
+        lw ra, 0(sp)
+        addi sp, sp, 16
+        #Pseudo-Instruction: ret
+        jalr x0, x1, 0 #Pseudo-Instruction Translation
+
+
+RET_0:
+        ori a1, zero, 0
+        addi sp, sp, 16
+        #Pseudo-Instruction: ret
+        jalr x0, x1, 0 #Pseudo-Instruction Translation
+RET_1:
+        ori a1, zero, 1
+        addi sp, sp, 16
+        #Pseudo-Instruction: ret
+        jalr x0, x1, 0 #Pseudo-Instruction Translation
+
+main:
+        ori a0, zero, 5
+        addi sp, sp, -16
+        jal ra, fib(int)
+        ori a0, zero, 1
+        ecall
+        ori a0, zero, 0
+        ecall