More processors

[xotmatrix]

This is a really interesting project. I'd love see some more processor variants. In particular, the 65C02 processors used in Apple II computers are not represented here. They used NCR and GTE vendor chips which do not include the Rockwell extensions. This looks like the feature set of Synertek but NCR/GTE undefined NOPs have different byte/cycle counts and SBC behaves differently with invalid BCD. Those processors would be very helpful for people working on Apple II emulators. Even MAME could use some assistance here.

It's also worth noting that there are two or three WDC variants, maybe more. WDC and 65C02 documentation in general is lacking and what exists is riddled with errors. The WDC currently in the collection appears to be a later W65C02S but I do not have one to verify this. Earlier versions do not include the Rockwell RMB/SMB/BBR/BBS instructions. It's unclear if there is WDC version without WAI/STP.

Some more information about your profiling method would welcome too. Maybe it can be reproduced and more profiles can be sourced. I have on hand a GTE, NCR, and what appears to be an early WDC (markings removed).

[TomHarte]

Sorry, status update on this:

I've added the 65816, and intend to add the 68000 shortly, with the Z80 possibly to follow.

I'm attempting to follow up on the BCD discrepancies with the 65C02 and will update tests if and when I can resolve that issue.

[xotmatrix]

Hi Tom. I'm hoping you see this. If you think there might be some errant BCD data in the sets I've see some very suspicious results recorded.

During an immediate mode ADC/SBC instruction there is a cycle that discards an unused read from memory. According to the recorded data, the following zero page locations are always read. It doesn't make sense.

Decimal Mode ADC/SBC Junk Read
------------------------------
VENDOR              ADC #$dd    SBC #$dd
Rockwell R65C02     zp.$59      zp.$B1
WDC W65C02S         zp.$7F      zp.$B8
Synertek SY65C02    zp.$56      zp.$5C

I was unable to reproduce like behavior with any of the chips I have on hand but my test rig is manually operated and somewhat primitive. In my tests with the NCR/GTE and suspected 1st generation WDC variants of the 65C02, the junk data simply comes from the address pointed to by the program counter (ie. the next fetched opcode).

----+---------------------------+-----------------------+-----------------------
    |   ADC/SBC abs             |   ADC/SBC zp          |   ADC/SBC imm
----+---------------------------+-----------------------+-----------------------
T0  |   Fetch OP    PC          |   Fetch OP    PC      |   Fetch OP    PC      
T1  |   Fetch ADL   PC+1        |   Fetch ADL   PC+1    |   Fetch DATA  PC+1
T2  |   Fetch ADH   PC+2        |   Read DATA   00,ADL  |   Read JUNK   PC+2
T3  |   Read DATA   ADH,ADL     |   Read JUNK   PC+2    |
T4  |   Read JUNK   PC+3        |                       |

I've not had much luck getting my faster, automated test rig to work reliably.