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#! /usr/local/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "/usr/local/lib/ivl/system.vpi";
:vpi_module "/usr/local/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/local/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/local/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/local/lib/ivl/va_math.vpi";
:vpi_module "/usr/local/lib/ivl/v2009.vpi";
S_0x557f825fe240 .scope package, "$unit" "$unit" 2 1;
.timescale 0 0;
S_0x557f82693ea0 .scope module, "AXIS_Sink" "AXIS_Sink" 3 3;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "m_valid";
.port_info 2 /OUTPUT 1 "m_ready";
.port_info 3 /INPUT 8 "m_data";
.port_info 4 /OUTPUT 80 "out_data";
P_0x557f82691f40 .param/l "BUS_W" 0 3 4, +C4<00000000000000000000000000001000>;
P_0x557f82691f80 .param/l "N_BEATS" 0 3 5, +C4<00000000000000000000000000001010>;
P_0x557f82691fc0 .param/l "PROB_READY" 0 3 4, +C4<00000000000000000000000000010100>;
P_0x557f82692000 .param/l "WORDS_PER_BEAT" 0 3 6, +C4<00000000000000000000000000000001>;
P_0x557f82692040 .param/l "WORD_W" 0 3 4, +C4<00000000000000000000000000001000>;
o0x7f4816b51018 .functor BUFZ 1, C4<z>; HiZ drive
v0x557f82683b40_0 .net "clk", 0 0, o0x7f4816b51018; 0 drivers
v0x557f8269dd90_0 .var/2u "done", 0 0;
v0x557f8269cc30_0 .var/2s "i_beats", 31 0;
o0x7f4816b510a8 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
v0x557f82697330_0 .net "m_data", 7 0, o0x7f4816b510a8; 0 drivers
v0x557f82697db0_0 .var "m_ready", 0 0;
o0x7f4816b51108 .functor BUFZ 1, C4<z>; HiZ drive
v0x557f82697660_0 .net "m_valid", 0 0, o0x7f4816b51108; 0 drivers
v0x557f82694610_0 .var "out_data", 79 0;
S_0x557f82694030 .scope task, "axis_pull_packet" "axis_pull_packet" 3 17, 3 17 0, S_0x557f82693ea0;
.timescale -9 -12;
E_0x557f82652f20 .event posedge, v0x557f82683b40_0;
TD_AXIS_Sink.axis_pull_packet ;
T_0.0 ;
%load/vec4 v0x557f8269dd90_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_0.1, 8;
%wait E_0x557f82652f20;
%load/vec4 v0x557f82697db0_0;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_0.4, 9;
%load/vec4 v0x557f82697660_0;
%and;
T_0.4;
%flag_set/vec4 8;
%jmp/0xz T_0.2, 8;
%load/vec4 v0x557f82697330_0;
%load/vec4 v0x557f8269cc30_0;
%pad/s 35;
%muli 8, 0, 35;
%ix/vec4/s 4;
%store/vec4 v0x557f82694610_0, 4, 8;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x557f8269cc30_0;
%pushi/vec4 1, 0, 32;
%add;
%cast2;
%store/vec4 v0x557f8269cc30_0, 0, 32;
%load/vec4 v0x557f8269cc30_0;
%pushi/vec4 10, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%store/vec4 v0x557f8269dd90_0, 0, 1;
T_0.2 ;
%delay 10, 0;
%vpi_func 3 27 "$urandom_range" 32, 32'sb00000000000000000000000000000000, 32'sb00000000000000000000000001100011 {0 0 0};
%cmpi/u 20, 0, 32;
%flag_get/vec4 5;
%store/vec4 v0x557f82697db0_0, 0, 1;
%jmp T_0.0;
T_0.1 ;
%pushi/vec4 0, 0, 34;
%split/vec4 1;
%store/vec4 v0x557f8269dd90_0, 0, 1;
%split/vec4 32;
%store/vec4 v0x557f8269cc30_0, 0, 32;
%store/vec4 v0x557f82697db0_0, 0, 1;
%end;
S_0x557f82601260 .scope module, "AXIS_Source" "AXIS_Source" 3 34;
.timescale -9 -12;
.port_info 0 /INPUT 80 "in_data";
.port_info 1 /INPUT 1 "clk";
.port_info 2 /INPUT 1 "s_ready";
.port_info 3 /OUTPUT 1 "s_valid";
.port_info 4 /OUTPUT 8 "s_data";
P_0x557f82693320 .param/l "BUS_W" 0 3 35, +C4<00000000000000000000000000001000>;
P_0x557f82693360 .param/l "N_BEATS" 0 3 36, +C4<00000000000000000000000000001010>;
P_0x557f826933a0 .param/l "PROB_VALID" 0 3 35, +C4<00000000000000000000000000010100>;
P_0x557f826933e0 .param/l "WORDS_PER_BEAT" 1 3 37, +C4<00000000000000000000000000000001>;
P_0x557f82693420 .param/l "WORD_W" 0 3 35, +C4<00000000000000000000000000001000>;
o0x7f4816b51258 .functor BUFZ 1, C4<z>; HiZ drive
v0x557f826b2850_0 .net "clk", 0 0, o0x7f4816b51258; 0 drivers
v0x557f826b2930_0 .var/2u "done", 0 0;
v0x557f826b29f0_0 .var/2s "i_beats", 31 0;
o0x7f4816b512e8 .functor BUFZ 80, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
v0x557f826b2ab0_0 .net "in_data", 79 0, o0x7f4816b512e8; 0 drivers
v0x557f826b2b70_0 .var/2u "prev_handshake", 0 0;
v0x557f826b2c80_0 .var "s_data", 7 0;
v0x557f826b2d40_0 .var "s_data_val", 7 0;
o0x7f4816b513a8 .functor BUFZ 1, C4<z>; HiZ drive
v0x557f826b2e00_0 .net "s_ready", 0 0, o0x7f4816b513a8; 0 drivers
v0x557f826b2ec0_0 .var "s_valid", 0 0;
S_0x557f82694350 .scope task, "axis_push_packet" "axis_push_packet" 3 50, 3 50 0, S_0x557f82601260;
.timescale -9 -12;
E_0x557f82654150 .event posedge, v0x557f826b2850_0;
TD_AXIS_Source.axis_push_packet ;
T_1.5 ;
%load/vec4 v0x557f826b2930_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_1.6, 8;
%load/vec4 v0x557f826b2b70_0;
%flag_set/vec4 8;
%jmp/0xz T_1.7, 8;
%load/vec4 v0x557f826b2ab0_0;
%load/vec4 v0x557f826b29f0_0;
%pad/s 35;
%muli 8, 0, 35;
%part/s 8;
%store/vec4 v0x557f826b2d40_0, 0, 8;
; show_stmt_assign_vector: Get l-value for compressed += operand
%load/vec4 v0x557f826b29f0_0;
%pushi/vec4 1, 0, 32;
%add;
%cast2;
%store/vec4 v0x557f826b29f0_0, 0, 32;
T_1.7 ;
%vpi_func 3 57 "$urandom_range" 32, 32'sb00000000000000000000000000000000, 32'sb00000000000000000000000001100011 {0 0 0};
%cmpi/u 20, 0, 32;
%flag_get/vec4 5;
%store/vec4 v0x557f826b2ec0_0, 0, 1;
%load/vec4 v0x557f826b2ec0_0;
%flag_set/vec4 8;
%jmp/0 T_1.9, 8;
%load/vec4 v0x557f826b2d40_0;
%jmp/1 T_1.10, 8;
T_1.9 ; End of true expr.
%pushi/vec4 255, 255, 8;
%jmp/0 T_1.10, 8;
; End of false expr.
%blend;
T_1.10;
%store/vec4 v0x557f826b2c80_0, 0, 8;
%wait E_0x557f82654150;
%load/vec4 v0x557f826b2ec0_0;
%flag_set/vec4 8;
%flag_get/vec4 8;
%jmp/0 T_1.11, 8;
%load/vec4 v0x557f826b2e00_0;
%and;
T_1.11;
%cast2;
%store/vec4 v0x557f826b2b70_0, 0, 1;
%load/vec4 v0x557f826b2ec0_0;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_1.13, 9;
%load/vec4 v0x557f826b2e00_0;
%and;
T_1.13;
%flag_set/vec4 8;
%flag_get/vec4 8;
%jmp/0 T_1.12, 8;
%load/vec4 v0x557f826b29f0_0;
%pushi/vec4 10, 0, 32;
%cmp/e;
%flag_get/vec4 4;
%and;
T_1.12;
%cast2;
%store/vec4 v0x557f826b2930_0, 0, 1;
%delay 10, 0;
%jmp T_1.5;
T_1.6 ;
%pushi/vec4 0, 0, 42;
%split/vec4 1;
%store/vec4 v0x557f826b2930_0, 0, 1;
%split/vec4 32;
%store/vec4 v0x557f826b29f0_0, 0, 32;
%split/vec4 8;
%store/vec4 v0x557f826b2c80_0, 0, 8;
%store/vec4 v0x557f826b2ec0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557f826b2b70_0, 0, 1;
%end;
S_0x557f826941c0 .scope module, "mvm_uart_system_tb" "mvm_uart_system_tb" 4 1;
.timescale -9 -12;
P_0x557f82656ba0 .param/l "BITS_PER_WORD" 1 4 7, +C4<00000000000000000000000000001000>;
P_0x557f82656be0 .param/l "C" 1 4 4, +C4<00000000000000000000000000000010>;
P_0x557f82656c20 .param/l "CLK_PERIOD" 1 4 14, +C4<00000000000000000000000000001010>;
P_0x557f82656c60 .param/l "CLOCKS_PER_PULSE" 1 4 6, +C4<00000000000000000101000101100001>;
P_0x557f82656ca0 .param/l "NUM_EXP" 1 4 15, +C4<00000000000000000000000000001010>;
P_0x557f82656ce0 .param/l "N_WORDS_KX" 1 4 11, +C4<0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010>;
P_0x557f82656d20 .param/l "N_WORDS_Y" 1 4 12, +C4<0000000000000000000000000000000000000000000000000000000000000010>;
P_0x557f82656d60 .param/l "PACKET_SIZE_TX" 1 4 13, +C4<000000000000000000000000000001101>;
P_0x557f82656da0 .param/l "R" 1 4 4, +C4<00000000000000000000000000000010>;
P_0x557f82656de0 .param/l "W_BUS_KX" 1 4 9, +C4<0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000>;
P_0x557f82656e20 .param/l "W_BUS_Y" 1 4 10, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
P_0x557f82656e60 .param/l "W_K" 1 4 4, +C4<00000000000000000000000000000010>;
P_0x557f82656ea0 .param/l "W_X" 1 4 4, +C4<00000000000000000000000000000100>;
P_0x557f82656ee0 .param/l "W_Y" 1 4 8, +C4<0000000000000000000000000000000111>;
P_0x557f82656f20 .param/l "W_Y_OUT" 1 4 5, +C4<00000000000000000000000000001000>;
v0x557f826c1eb0_0 .net *"_ivl_3", 0 0, v0x557f826c25e0_0; 1 drivers
v0x557f826c1fb0_0 .var "clk", 0 0;
v0x557f826c2070_0 .var "exp_data", 15 0;
v0x557f826c2110_0 .var "k_out", 7 0;
v0x557f826c21b0_0 .var "k_row_out", 3 0;
v0x557f826c2270_0 .var "m_data", 15 0;
v0x557f826c2330_0 .var "m_packet", 7 0;
v0x557f826c2410_0 .var/queue "queue_kx", 16;
v0x557f826c24b0_0 .var "rstn", 0 0;
v0x557f826c25e0_0 .var "rx", 0 0;
v0x557f826c26a0_0 .var/2s "rx_bits", 31 0;
v0x557f826c2780_0 .var "s_data", 15 0;
v0x557f826c2870_0 .var "s_packet", 9 0;
v0x557f826c2950_0 .net "tx", 0 0, L_0x557f826c3100; 1 drivers
v0x557f826c2a10_0 .var/2s "tx_bits", 31 0;
v0x557f826c2af0_0 .net "ui_in", 7 0, L_0x557f826c2ff0; 1 drivers
o0x7f4816b52ab8 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
v0x557f826c2be0_0 .net "uio_in", 7 0, o0x7f4816b52ab8; 0 drivers
L_0x7f4816b08258 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
v0x557f826c2cb0_0 .net "uio_oe", 7 0, L_0x7f4816b08258; 1 drivers
L_0x7f4816b08210 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
v0x557f826c2d80_0 .net "uio_out", 7 0, L_0x7f4816b08210; 1 drivers
v0x557f826c2e50_0 .net "uo_out", 7 0, L_0x557f826d5030; 1 drivers
v0x557f826c2f20_0 .var "x_out", 7 0;
E_0x557f825f0c10 .event anyedge, v0x557f826c25e0_0;
L_0x557f826c2ff0 .part/pv v0x557f826c25e0_0, 0, 1, 8;
L_0x557f826c3100 .part L_0x557f826d5030, 0, 1;
S_0x557f826b3060 .scope begin, "$ivl_for_loop0" "$ivl_for_loop0" 4 57, 4 57 0, S_0x557f826941c0;
.timescale -9 -12;
v0x557f826b3550_0 .var/2s "iw", 31 0;
S_0x557f826b3210 .scope begin, "$ivl_for_loop1" "$ivl_for_loop1" 4 63, 4 63 0, S_0x557f826b3060;
.timescale -9 -12;
v0x557f826b3450_0 .var/2s "ib", 31 0;
E_0x557f825f0e50 .event posedge, v0x557f826b9e60_0;
S_0x557f826b3650 .scope begin, "$ivl_for_loop2" "$ivl_for_loop2" 4 86, 4 86 0, S_0x557f826941c0;
.timescale -9 -12;
v0x557f826b3e90_0 .var/2s "iw", 31 0;
E_0x557f826b3850 .event anyedge, v0x557f826c2950_0;
S_0x557f826b38b0 .scope begin, "$ivl_for_loop3" "$ivl_for_loop3" 4 91, 4 91 0, S_0x557f826b3650;
.timescale -9 -12;
v0x557f826b3ab0_0 .var/2s "ib", 31 0;
S_0x557f826b3bb0 .scope begin, "$ivl_for_loop4" "$ivl_for_loop4" 4 97, 4 97 0, S_0x557f826b3650;
.timescale -9 -12;
v0x557f826b3db0_0 .var/2s "ib", 31 0;
S_0x557f826b3f90 .scope begin, "$ivl_for_loop5" "$ivl_for_loop5" 4 127, 4 127 0, S_0x557f826941c0;
.timescale -9 -12;
v0x557f826b4170_0 .var/2s "n", 31 0;
S_0x557f826b4250 .scope begin, "$ivl_for_loop6" "$ivl_for_loop6" 4 135, 4 135 0, S_0x557f826941c0;
.timescale -9 -12;
v0x557f826b4430_0 .var/2s "n", 31 0;
S_0x557f826b4530 .scope begin, "$ivl_foreach0" "$ivl_foreach0" 4 107, 4 107 0, S_0x557f826941c0;
.timescale -9 -12;
v0x557f826b4a60_0 .var/2s "r", 31 0;
S_0x557f826b4760 .scope begin, "$ivl_foreach1" "$ivl_foreach1" 4 109, 4 109 0, S_0x557f826b4530;
.timescale -9 -12;
v0x557f826b4960_0 .var/2s "c", 31 0;
S_0x557f826b4b60 .scope module, "dut" "tt_um_uart_mvm" 4 31, 5 8 0, S_0x557f826941c0;
.timescale 0 0;
.port_info 0 /INPUT 8 "ui_in";
.port_info 1 /OUTPUT 8 "uo_out";
.port_info 2 /INPUT 8 "uio_in";
.port_info 3 /OUTPUT 8 "uio_out";
.port_info 4 /OUTPUT 8 "uio_oe";
.port_info 5 /INPUT 1 "ena";
.port_info 6 /INPUT 1 "clk";
.port_info 7 /INPUT 1 "rst_n";
P_0x557f826b4d40 .param/l "BITS_PER_WORD" 1 5 21, +C4<00000000000000000000000000001000>;
P_0x557f826b4d80 .param/l "C" 1 5 25, +C4<00000000000000000000000000000010>;
P_0x557f826b4dc0 .param/l "CLOCKS_PER_PULSE" 1 5 20, +C4<00000000000000000101000101100001>;
P_0x557f826b4e00 .param/l "PACKET_SIZE_TX" 1 5 22, +C4<000000000000000000000000000001101>;
P_0x557f826b4e40 .param/l "R" 1 5 24, +C4<00000000000000000000000000000010>;
P_0x557f826b4e80 .param/l "W_K" 1 5 27, +C4<00000000000000000000000000000010>;
P_0x557f826b4ec0 .param/l "W_X" 1 5 26, +C4<00000000000000000000000000000100>;
P_0x557f826b4f00 .param/l "W_Y_OUT" 1 5 23, +C4<00000000000000000000000000001000>;
v0x557f826c1230_0 .net *"_ivl_14", 6 0, L_0x557f826d5250; 1 drivers
L_0x7f4816b082a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x557f826c1330_0 .net/2u *"_ivl_15", 0 0, L_0x7f4816b082a0; 1 drivers
v0x557f826c1410_0 .net *"_ivl_17", 18 0, L_0x557f826d5380; 1 drivers
L_0x7f4816b081c8 .functor BUFT 1, C4<0000000>, C4<0>, C4<0>, C4<0>;
v0x557f826c14d0_0 .net/2s *"_ivl_7", 6 0, L_0x7f4816b081c8; 1 drivers
v0x557f826c15b0_0 .net "_unused", 0 0, L_0x557f826d54e0; 1 drivers
v0x557f826c16c0_0 .net "clk", 0 0, v0x557f826c1fb0_0; 1 drivers
L_0x7f4816b082e8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
v0x557f826c1760_0 .net "ena", 0 0, L_0x7f4816b082e8; 1 drivers
v0x557f826c1820_0 .net "rst_n", 0 0, v0x557f826c24b0_0; 1 drivers
v0x557f826c18c0_0 .net "ui_in", 7 0, L_0x557f826c2ff0; alias, 1 drivers
v0x557f826c1a30_0 .net "uio_in", 7 0, o0x7f4816b52ab8; alias, 0 drivers
v0x557f826c1b10_0 .net "uio_oe", 7 0, L_0x7f4816b08258; alias, 1 drivers
v0x557f826c1bf0_0 .net "uio_out", 7 0, L_0x7f4816b08210; alias, 1 drivers
v0x557f826c1cd0_0 .net "uo_out", 7 0, L_0x557f826d5030; alias, 1 drivers
L_0x557f826d4f40 .part L_0x557f826c2ff0, 0, 1;
L_0x557f826d5030 .concat8 [ 1 7 0 0], L_0x557f826c4b10, L_0x7f4816b081c8;
L_0x557f826d5250 .part L_0x557f826c2ff0, 1, 7;
LS_0x557f826d5380_0_0 .concat [ 1 1 1 1], L_0x7f4816b082a0, v0x557f826c24b0_0, v0x557f826c1fb0_0, L_0x7f4816b082e8;
LS_0x557f826d5380_0_4 .concat [ 7 8 0 0], L_0x557f826d5250, o0x7f4816b52ab8;
L_0x557f826d5380 .concat [ 4 15 0 0], LS_0x557f826d5380_0_0, LS_0x557f826d5380_0_4;
L_0x557f826d54e0 .reduce/and L_0x557f826d5380;
S_0x557f826b5410 .scope module, "MVM_UART_SYSTEM" "mvm_uart_system" 5 38, 6 2 0, S_0x557f826b4b60;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rstn";
.port_info 2 /INPUT 1 "rx";
.port_info 3 /OUTPUT 1 "tx";
P_0x557f826b5610 .param/l "BITS_PER_WORD" 0 6 4, +C4<00000000000000000000000000001000>;
P_0x557f826b5650 .param/l "C" 0 6 7, +C4<00000000000000000000000000000010>;
P_0x557f826b5690 .param/l "CLOCKS_PER_PULSE" 0 6 3, +C4<00000000000000000101000101100001>;
P_0x557f826b56d0 .param/l "PACKET_SIZE_TX" 0 6 5, +C4<000000000000000000000000000001101>;
P_0x557f826b5710 .param/l "R" 0 6 7, +C4<00000000000000000000000000000010>;
P_0x557f826b5750 .param/l "W_BUS_KX" 1 6 13, +C4<0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000>;
P_0x557f826b5790 .param/l "W_BUS_Y" 1 6 14, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
P_0x557f826b57d0 .param/l "W_K" 0 6 7, +C4<00000000000000000000000000000010>;
P_0x557f826b5810 .param/l "W_X" 0 6 7, +C4<00000000000000000000000000000100>;
P_0x557f826b5850 .param/l "W_Y" 1 6 15, +C4<0000000000000000000000000000000111>;
P_0x557f826b5890 .param/l "W_Y_OUT" 0 6 6, +C4<00000000000000000000000000001000>;
L_0x557f826c3880 .functor BUFZ 1, L_0x557f826c4340, C4<0>, C4<0>, C4<0>;
v0x557f826c0630_0 .net "_unused", 0 0, L_0x557f826c3880; 1 drivers
v0x557f826c0710_0 .net "clk", 0 0, v0x557f826c1fb0_0; alias, 1 drivers
v0x557f826c07d0_0 .net "m_data_y", 13 0, v0x557f826baf20_0; 1 drivers
v0x557f826c08c0_0 .net "m_ready", 0 0, L_0x557f826d4d80; 1 drivers
v0x557f826c0960_0 .net "m_valid", 0 0, v0x557f826bb090_0; 1 drivers
v0x557f826c0a50_0 .net "o_flat", 15 0, L_0x557f826c3610; 1 drivers
v0x557f826c0af0 .array "o_up", 0 1;
v0x557f826c0af0_0 .net v0x557f826c0af0 0, 7 0, L_0x557f826c32c0; 1 drivers
v0x557f826c0af0_1 .net v0x557f826c0af0 1, 7 0, L_0x557f826c3540; 1 drivers
v0x557f826c0bf0_0 .net "rstn", 0 0, v0x557f826c24b0_0; alias, 1 drivers
v0x557f826c0d20_0 .net "rx", 0 0, L_0x557f826d4f40; 1 drivers
v0x557f826c0e50_0 .net "s_data_kx", 15 0, v0x557f826bd290_0; 1 drivers
v0x557f826c0ef0_0 .net "s_ready", 0 0, L_0x557f826c4340; 1 drivers
v0x557f826c0f90_0 .net "s_valid", 0 0, v0x557f826bd3a0_0; 1 drivers
v0x557f826c1030_0 .net "tx", 0 0, L_0x557f826c4b10; 1 drivers
v0x557f826c10d0 .array "y_up", 0 1;
v0x557f826c10d0_0 .net v0x557f826c10d0 0, 6 0, L_0x557f826c3220; 1 drivers
v0x557f826c10d0_1 .net v0x557f826c10d0 1, 6 0, L_0x557f826c34a0; 1 drivers
L_0x557f826c3220 .part v0x557f826baf20_0, 0, 7;
L_0x557f826c34a0 .part v0x557f826baf20_0, 7, 7;
L_0x557f826c3610 .concat8 [ 8 8 0 0], L_0x557f826c33e0, L_0x557f826c3750;
S_0x557f826b5bb0 .scope module, "AXIS_MVM" "axis_matvec_mul" 6 37, 7 1 0, S_0x557f826b5410;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rstn";
.port_info 2 /OUTPUT 1 "s_axis_kx_tready";
.port_info 3 /INPUT 1 "s_axis_kx_tvalid";
.port_info 4 /INPUT 16 "s_axis_kx_tdata";
.port_info 5 /INPUT 1 "m_axis_y_tready";
.port_info 6 /OUTPUT 1 "m_axis_y_tvalid";
.port_info 7 /OUTPUT 14 "m_axis_y_tdata";
P_0x557f826b6080 .param/l "C" 0 7 2, +C4<00000000000000000000000000000010>;
P_0x557f826b60c0 .param/l "LATENCY" 0 7 3, +C4<000000000000000000000000000000010>;
P_0x557f826b6100 .param/l "R" 0 7 2, +C4<00000000000000000000000000000010>;
P_0x557f826b6140 .param/l "W_K" 0 7 2, +C4<00000000000000000000000000000010>;
P_0x557f826b6180 .param/l "W_X" 0 7 2, +C4<00000000000000000000000000000100>;
P_0x557f826b61c0 .param/l "W_Y" 0 7 4, +C4<0000000000000000000000000000000111>;
L_0x557f826c3b90 .functor BUFZ 16, v0x557f826bd290_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>;
L_0x557f826c4340 .functor BUFZ 1, v0x557f826bb320_0, C4<0>, C4<0>, C4<0>;
v0x557f826bb730_0 .net *"_ivl_4", 15 0, L_0x557f826c3b90; 1 drivers
v0x557f826bb830_0 .net "clk", 0 0, v0x557f826c1fb0_0; alias, 1 drivers
v0x557f826bb8f0_0 .net "i_data", 13 0, L_0x557f826c4230; 1 drivers
v0x557f826bb9e0_0 .net "i_ready", 0 0, v0x557f826bb320_0; 1 drivers
v0x557f826bbad0_0 .var "i_valid", 0 0;
v0x557f826bbbc0_0 .net "k", 7 0, L_0x557f826c3960; 1 drivers
v0x557f826bbc60_0 .net "m_axis_y_tdata", 13 0, v0x557f826baf20_0; alias, 1 drivers
v0x557f826bbd00_0 .net "m_axis_y_tready", 0 0, L_0x557f826d4d80; alias, 1 drivers
v0x557f826bbdd0_0 .net "m_axis_y_tvalid", 0 0, v0x557f826bb090_0; alias, 1 drivers
v0x557f826bbea0_0 .net "rstn", 0 0, v0x557f826c24b0_0; alias, 1 drivers
v0x557f826bbf70_0 .net "s_axis_kx_tdata", 15 0, v0x557f826bd290_0; alias, 1 drivers
v0x557f826bc010_0 .net "s_axis_kx_tready", 0 0, L_0x557f826c4340; alias, 1 drivers
v0x557f826bc0b0_0 .net "s_axis_kx_tvalid", 0 0, v0x557f826bd3a0_0; alias, 1 drivers
v0x557f826bc150_0 .var "shift", 0 0;
v0x557f826bc210_0 .net "x", 7 0, L_0x557f826c3a50; 1 drivers
L_0x557f826c3960 .part L_0x557f826c3b90, 8, 8;
L_0x557f826c3a50 .part L_0x557f826c3b90, 0, 8;
S_0x557f826b6630 .scope module, "MATVEC" "matvec_mul" 7 23, 8 1 0, S_0x557f826b5bb0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "cen";
.port_info 2 /INPUT 8 "kf";
.port_info 3 /INPUT 8 "xf";
.port_info 4 /OUTPUT 14 "yf";
P_0x557f826b6830 .param/l "C" 0 8 2, +C4<00000000000000000000000000000010>;
P_0x557f826b6870 .param/l "C_PAD" 1 8 14, +C4<00000000000000000000000000000010>;
P_0x557f826b68b0 .param/l "DEPTH" 1 8 3, +C4<00000000000000000000000000000001>;
P_0x557f826b68f0 .param/l "R" 0 8 2, +C4<00000000000000000000000000000010>;
P_0x557f826b6930 .param/l "W_K" 0 8 2, +C4<00000000000000000000000000000010>;
P_0x557f826b6970 .param/l "W_M" 1 8 4, +C4<000000000000000000000000000000110>;
P_0x557f826b69b0 .param/l "W_X" 0 8 2, +C4<00000000000000000000000000000100>;
P_0x557f826b69f0 .param/l "W_Y" 1 8 5, +C4<0000000000000000000000000000000111>;
v0x557f826b9d80_0 .net "cen", 0 0, v0x557f826bb320_0; alias, 1 drivers
v0x557f826b9e60_0 .net "clk", 0 0, v0x557f826c1fb0_0; alias, 1 drivers
v0x557f826b9f20 .array "k_pad", 3 0;
v0x557f826b9f20_0 .net/s v0x557f826b9f20 0, 1 0, L_0x557f826c3ce0; 1 drivers
v0x557f826b9f20_1 .net/s v0x557f826b9f20 1, 1 0, L_0x557f826c4010; 1 drivers
v0x557f826b9f20_2 .net/s v0x557f826b9f20 2, 1 0, L_0x557f826c3d80; 1 drivers
v0x557f826b9f20_3 .net/s v0x557f826b9f20 3, 1 0, L_0x557f826c40b0; 1 drivers
v0x557f826ba0a0_0 .net "kf", 7 0, L_0x557f826c3960; alias, 1 drivers
v0x557f826ba180 .array "tree", 7 0, 6 0;
v0x557f826ba3e0 .array "x_pad", 0 1;
v0x557f826ba3e0_0 .net/s v0x557f826ba3e0 0, 3 0, L_0x557f826c3c40; 1 drivers
v0x557f826ba3e0_1 .net/s v0x557f826ba3e0 1, 3 0, L_0x557f826c3eb0; 1 drivers
v0x557f826ba500_0 .net "xf", 7 0, L_0x557f826c3a50; alias, 1 drivers
v0x557f826ba5e0_0 .net "yf", 13 0, L_0x557f826c4230; alias, 1 drivers
L_0x557f826c3c40 .part L_0x557f826c3a50, 0, 4;
L_0x557f826c3ce0 .part L_0x557f826c3960, 0, 2;
L_0x557f826c3d80 .part L_0x557f826c3960, 4, 2;
L_0x557f826c3eb0 .part L_0x557f826c3a50, 4, 4;
L_0x557f826c4010 .part L_0x557f826c3960, 2, 2;
L_0x557f826c40b0 .part L_0x557f826c3960, 6, 2;
v0x557f826ba180_2 .array/port v0x557f826ba180, 2;
v0x557f826ba180_6 .array/port v0x557f826ba180, 6;
L_0x557f826c4230 .concat8 [ 7 7 0 0], v0x557f826ba180_2, v0x557f826ba180_6;
S_0x557f826b6e70 .scope generate, "genblk1[0]" "genblk1[0]" 8 23, 8 23 0, S_0x557f826b6630;
.timescale 0 0;
P_0x557f826b7090 .param/l "c" 1 8 23, +C4<00>;
S_0x557f826b7170 .scope generate, "genblk1[0]" "genblk1[0]" 8 25, 8 25 0, S_0x557f826b6e70;
.timescale 0 0;
P_0x557f826b7370 .param/l "r" 1 8 25, +C4<00>;
S_0x557f826b7450 .scope generate, "genblk1[1]" "genblk1[1]" 8 25, 8 25 0, S_0x557f826b6e70;
.timescale 0 0;
P_0x557f826b7650 .param/l "r" 1 8 25, +C4<01>;
S_0x557f826b7710 .scope generate, "genblk1[1]" "genblk1[1]" 8 23, 8 23 0, S_0x557f826b6630;
.timescale 0 0;
P_0x557f826b7910 .param/l "c" 1 8 23, +C4<01>;
S_0x557f826b79d0 .scope generate, "genblk1[0]" "genblk1[0]" 8 25, 8 25 0, S_0x557f826b7710;
.timescale 0 0;
P_0x557f826b7bd0 .param/l "r" 1 8 25, +C4<00>;
S_0x557f826b7cb0 .scope generate, "genblk1[1]" "genblk1[1]" 8 25, 8 25 0, S_0x557f826b7710;
.timescale 0 0;
P_0x557f826b7eb0 .param/l "r" 1 8 25, +C4<01>;
S_0x557f826b7f70 .scope generate, "genblk2[0]" "genblk2[0]" 8 29, 8 29 0, S_0x557f826b6630;
.timescale 0 0;
P_0x557f826b8180 .param/l "r" 1 8 29, +C4<00>;
v0x557f826b8d90_0 .net *"_ivl_2", 6 0, v0x557f826ba180_2; 1 drivers
S_0x557f826b8240 .scope generate, "genblk1[0]" "genblk1[0]" 8 30, 8 30 0, S_0x557f826b7f70;
.timescale 0 0;
P_0x557f826b8440 .param/l "c" 1 8 30, +C4<00>;
S_0x557f826b8520 .scope generate, "genblk1[1]" "genblk1[1]" 8 30, 8 30 0, S_0x557f826b7f70;
.timescale 0 0;
P_0x557f826b8720 .param/l "c" 1 8 30, +C4<01>;
S_0x557f826b87e0 .scope generate, "genblk2[0]" "genblk2[0]" 8 34, 8 34 0, S_0x557f826b7f70;
.timescale 0 0;
P_0x557f826b89f0 .param/l "d" 1 8 34, +C4<00>;
S_0x557f826b8ab0 .scope generate, "genblk1[0]" "genblk1[0]" 8 35, 8 35 0, S_0x557f826b87e0;
.timescale 0 0;
P_0x557f826b8cb0 .param/l "a" 1 8 35, +C4<00>;
S_0x557f826b8e70 .scope generate, "genblk2[1]" "genblk2[1]" 8 29, 8 29 0, S_0x557f826b6630;
.timescale 0 0;
P_0x557f826b9070 .param/l "r" 1 8 29, +C4<01>;
v0x557f826b9ca0_0 .net *"_ivl_2", 6 0, v0x557f826ba180_6; 1 drivers
S_0x557f826b9150 .scope generate, "genblk1[0]" "genblk1[0]" 8 30, 8 30 0, S_0x557f826b8e70;
.timescale 0 0;
P_0x557f826b9350 .param/l "c" 1 8 30, +C4<00>;
S_0x557f826b9430 .scope generate, "genblk1[1]" "genblk1[1]" 8 30, 8 30 0, S_0x557f826b8e70;
.timescale 0 0;
P_0x557f826b9630 .param/l "c" 1 8 30, +C4<01>;
S_0x557f826b96f0 .scope generate, "genblk2[0]" "genblk2[0]" 8 34, 8 34 0, S_0x557f826b8e70;
.timescale 0 0;
P_0x557f826b9900 .param/l "d" 1 8 34, +C4<00>;
S_0x557f826b99c0 .scope generate, "genblk1[0]" "genblk1[0]" 8 35, 8 35 0, S_0x557f826b96f0;
.timescale 0 0;
P_0x557f826b9bc0 .param/l "a" 1 8 35, +C4<00>;
S_0x557f826ba760 .scope module, "SKID" "skid_buffer" 7 38, 9 1 0, S_0x557f826b5bb0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rstn";
.port_info 2 /INPUT 1 "s_valid";
.port_info 3 /INPUT 1 "m_ready";
.port_info 4 /INPUT 14 "s_data";
.port_info 5 /OUTPUT 14 "m_data";
.port_info 6 /OUTPUT 1 "m_valid";
.port_info 7 /OUTPUT 1 "s_ready";
P_0x557f826018a0 .param/l "EMPTY" 1 9 7, +C4<00000000000000000000000000000000>;
P_0x557f826018e0 .param/l "FULL" 1 9 7, +C4<00000000000000000000000000000010>;
P_0x557f82601920 .param/l "PARTIAL" 1 9 7, +C4<00000000000000000000000000000001>;
P_0x557f82601960 .param/l "WIDTH" 0 9 1, +C4<000000000000000000000000000000000000000000000000000000000000001110>;
v0x557f826bad30_0 .var "buffer", 13 0;
v0x557f826bae30_0 .net "clk", 0 0, v0x557f826c1fb0_0; alias, 1 drivers
v0x557f826baf20_0 .var "m_data", 13 0;
v0x557f826baff0_0 .net "m_ready", 0 0, L_0x557f826d4d80; alias, 1 drivers
v0x557f826bb090_0 .var "m_valid", 0 0;
v0x557f826bb1a0_0 .net "rstn", 0 0, v0x557f826c24b0_0; alias, 1 drivers
v0x557f826bb260_0 .net "s_data", 13 0, L_0x557f826c4230; alias, 1 drivers
v0x557f826bb320_0 .var "s_ready", 0 0;
v0x557f826bb3f0_0 .net "s_valid", 0 0, v0x557f826bbad0_0; 1 drivers
v0x557f826bb490_0 .var "state", 1 0;
v0x557f826bb550_0 .var "state_next", 1 0;
E_0x557f826bac70/0 .event negedge, v0x557f826bb1a0_0;
E_0x557f826bac70/1 .event posedge, v0x557f826b9e60_0;
E_0x557f826bac70 .event/or E_0x557f826bac70/0, E_0x557f826bac70/1;
E_0x557f826bacd0 .event anyedge, v0x557f826bb490_0, v0x557f826bb3f0_0, v0x557f826baff0_0;
S_0x557f826bc3e0 .scope module, "UART_RX" "uart_rx" 6 24, 10 1 0, S_0x557f826b5410;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rstn";
.port_info 2 /INPUT 1 "rx";
.port_info 3 /OUTPUT 1 "m_valid";
.port_info 4 /OUTPUT 16 "m_data";
P_0x557f826bc590 .param/l "BITS_PER_WORD" 0 10 3, +C4<00000000000000000000000000001000>;
P_0x557f826bc5d0 .param/l "CLOCKS_PER_PULSE" 0 10 2, +C4<00000000000000000101000101100001>;
P_0x557f826bc610 .param/l "DATA" 1 10 25, +C4<00000000000000000000000000000010>;
P_0x557f826bc650 .param/l "END" 1 10 25, +C4<00000000000000000000000000000011>;
P_0x557f826bc690 .param/l "IDLE" 1 10 25, +C4<00000000000000000000000000000000>;
P_0x557f826bc6d0 .param/l "NUM_WORDS" 1 10 10, +C4<0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010>;
P_0x557f826bc710 .param/l "START" 1 10 25, +C4<00000000000000000000000000000001>;
P_0x557f826bc750 .param/l "W_CBITS" 1 10 15, +C4<00000000000000000000000000000011>;
P_0x557f826bc790 .param/l "W_CCLOCKS" 1 10 14, +C4<00000000000000000000000000001111>;
P_0x557f826bc7d0 .param/l "W_CWORDS" 1 10 16, +C4<00000000000000000000000000000001>;
P_0x557f826bc810 .param/l "W_OUT" 0 10 4, +C4<0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000>;
v0x557f826bcf40_0 .var "c_bits", 2 0;
v0x557f826bd020_0 .var "c_clocks", 14 0;
v0x557f826bd100_0 .var "c_words", 0 0;
v0x557f826bd1f0_0 .net "clk", 0 0, v0x557f826c1fb0_0; alias, 1 drivers
v0x557f826bd290_0 .var "m_data", 15 0;
v0x557f826bd3a0_0 .var "m_valid", 0 0;
v0x557f826bd470_0 .net "rstn", 0 0, v0x557f826c24b0_0; alias, 1 drivers
v0x557f826bd560_0 .net "rx", 0 0, L_0x557f826d4f40; alias, 1 drivers
v0x557f826bd600_0 .var "state", 1 0;
S_0x557f826bcb30 .scope module, "UART_TX" "uart_tx" 6 68, 11 1 0, S_0x557f826b5410;
.timescale 0 0;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "rstn";
.port_info 2 /INPUT 1 "s_valid";
.port_info 3 /INPUT 16 "s_data_f";
.port_info 4 /OUTPUT 1 "tx";
.port_info 5 /OUTPUT 1 "s_ready";
P_0x557f826bd760 .param/l "BITS_PER_WORD" 0 11 3, +C4<00000000000000000000000000001000>;
P_0x557f826bd7a0 .param/l "CLOCKS_PER_PULSE" 0 11 2, +C4<00000000000000000101000101100001>;
P_0x557f826bd7e0 .param/l "END_BITS" 1 11 22, +C4<00000000000000000000000000000000100>;
P_0x557f826bd820 .param/l "IDLE" 1 11 42, +C4<00000000000000000000000000000000>;
P_0x557f826bd860 .param/l "NUM_WORDS" 1 11 7, +C4<0000000000000000000000000000000000000000000000000000000000000010>;
P_0x557f826bd8a0 .param/l "PACKET_SIZE" 0 11 4, +C4<000000000000000000000000000001101>;
P_0x557f826bd8e0 .param/l "SEND" 1 11 42, +C4<00000000000000000000000000000001>;
P_0x557f826bd920 .param/l "W_CCLOCKS" 1 11 35, +C4<00000000000000000000000000001111>;
P_0x557f826bd960 .param/l "W_CPULSES" 1 11 34, +C4<00000000000000000000000000000101>;
P_0x557f826bd9a0 .param/l "W_OUT" 0 11 5, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
L_0x7f4816b08138 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x557f826bf0c0_0 .net *"_ivl_12", 30 0, L_0x7f4816b08138; 1 drivers
L_0x7f4816b08180 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0x557f826bf1c0_0 .net/2u *"_ivl_13", 31 0, L_0x7f4816b08180; 1 drivers
v0x557f826bf2a0_0 .net *"_ivl_9", 31 0, L_0x557f826c4c30; 1 drivers
v0x557f826bf390_0 .var "c_clocks", 14 0;
v0x557f826bf470_0 .var "c_pulses", 4 0;
v0x557f826bf5a0_0 .net "clk", 0 0, v0x557f826c1fb0_0; alias, 1 drivers
v0x557f826bf640_0 .var "m_packets", 25 0;
v0x557f826bf720_0 .net "rstn", 0 0, v0x557f826c24b0_0; alias, 1 drivers
v0x557f826bf7c0 .array "s_data", 0 1;
v0x557f826bf7c0_0 .net v0x557f826bf7c0 0, 7 0, L_0x557f826c43b0; 1 drivers
v0x557f826bf7c0_1 .net v0x557f826bf7c0 1, 7 0, L_0x557f826c4480; 1 drivers
v0x557f826bf8e0_0 .net "s_data_f", 15 0, L_0x557f826c3610; alias, 1 drivers
v0x557f826bf9c0_0 .net "s_packets", 25 0, L_0x557f826c47e0; 1 drivers
v0x557f826bfaa0_0 .net "s_ready", 0 0, L_0x557f826d4d80; alias, 1 drivers
v0x557f826bfb40_0 .net "s_valid", 0 0, v0x557f826bb090_0; alias, 1 drivers
v0x557f826bfbe0_0 .var "state", 0 0;
v0x557f826bfca0_0 .net "tx", 0 0, L_0x557f826c4b10; alias, 1 drivers
L_0x557f826c43b0 .part L_0x557f826c3610, 0, 8;
L_0x557f826c4480 .part L_0x557f826c3610, 8, 8;
L_0x557f826c47e0 .concat8 [ 13 13 0 0], L_0x557f826c4640, L_0x557f826c4900;
L_0x557f826c4b10 .part v0x557f826bf640_0, 0, 1;
L_0x557f826c4c30 .concat [ 1 31 0 0], v0x557f826bfbe0_0, L_0x7f4816b08138;
L_0x557f826d4d80 .cmp/eq 32, L_0x557f826c4c30, L_0x7f4816b08180;
S_0x557f826be010 .scope generate, "genblk1[0]" "genblk1[0]" 11 18, 11 18 0, S_0x557f826bcb30;
.timescale 0 0;
P_0x557f826be210 .param/l "n" 1 11 18, +C4<00>;
S_0x557f826be2f0 .scope generate, "genblk1[1]" "genblk1[1]" 11 18, 11 18 0, S_0x557f826bcb30;
.timescale 0 0;
P_0x557f826be4f0 .param/l "n" 1 11 18, +C4<01>;
S_0x557f826be5b0 .scope generate, "genblk2[0]" "genblk2[0]" 11 27, 11 27 0, S_0x557f826bcb30;
.timescale 0 0;
P_0x557f826be7c0 .param/l "n" 1 11 27, +C4<00>;
L_0x7f4816b08018 .functor BUFT 1, C4<1111>, C4<0>, C4<0>, C4<0>;
v0x557f826be880_0 .net/2s *"_ivl_0", 3 0, L_0x7f4816b08018; 1 drivers
L_0x7f4816b08060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x557f826be960_0 .net/2u *"_ivl_3", 0 0, L_0x7f4816b08060; 1 drivers
v0x557f826bea40_0 .net *"_ivl_5", 12 0, L_0x557f826c4640; 1 drivers
L_0x557f826c4640 .concat [ 1 8 4 0], L_0x7f4816b08060, L_0x557f826c43b0, L_0x7f4816b08018;
S_0x557f826beb30 .scope generate, "genblk2[1]" "genblk2[1]" 11 27, 11 27 0, S_0x557f826bcb30;
.timescale 0 0;
P_0x557f826bed30 .param/l "n" 1 11 27, +C4<01>;
L_0x7f4816b080a8 .functor BUFT 1, C4<1111>, C4<0>, C4<0>, C4<0>;
v0x557f826bee10_0 .net/2s *"_ivl_0", 3 0, L_0x7f4816b080a8; 1 drivers
L_0x7f4816b080f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
v0x557f826beef0_0 .net/2u *"_ivl_3", 0 0, L_0x7f4816b080f0; 1 drivers
v0x557f826befd0_0 .net *"_ivl_5", 12 0, L_0x557f826c4900; 1 drivers
L_0x557f826c4900 .concat [ 1 8 4 0], L_0x7f4816b080f0, L_0x557f826c4480, L_0x7f4816b080a8;
S_0x557f826bfe60 .scope generate, "genblk1[0]" "genblk1[0]" 6 55, 6 55 0, S_0x557f826b5410;
.timescale 0 0;
P_0x557f826c0060 .param/l "r" 1 6 55, +C4<00>;
L_0x557f826c33e0 .functor BUFZ 8, L_0x557f826c32c0, C4<00000000>, C4<00000000>, C4<00000000>;
v0x557f826c0140_0 .net *"_ivl_8", 7 0, L_0x557f826c33e0; 1 drivers
L_0x557f826c32c0 .extend/s 8, L_0x557f826c3220;
S_0x557f826c0220 .scope generate, "genblk1[1]" "genblk1[1]" 6 55, 6 55 0, S_0x557f826b5410;
.timescale 0 0;
P_0x557f826c0470 .param/l "r" 1 6 55, +C4<01>;
L_0x557f826c3750 .functor BUFZ 8, L_0x557f826c3540, C4<00000000>, C4<00000000>, C4<00000000>;
v0x557f826c0550_0 .net *"_ivl_8", 7 0, L_0x557f826c3750; 1 drivers
L_0x557f826c3540 .extend/s 8, L_0x557f826c34a0;
.scope S_0x557f82693ea0;
T_2 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557f82697db0_0, 0, 1;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x557f8269cc30_0, 0, 32;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557f8269dd90_0, 0, 1;
%end;
.thread T_2, $init;
.scope S_0x557f82601260;
T_3 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557f826b2ec0_0, 0, 1;
%pushi/vec4 0, 0, 8;
%store/vec4 v0x557f826b2c80_0, 0, 8;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x557f826b29f0_0, 0, 32;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557f826b2b70_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557f826b2930_0, 0, 1;
%end;
.thread T_3, $init;
.scope S_0x557f826bc3e0;
T_4 ;
%wait E_0x557f826bac70;
%load/vec4 v0x557f826bd470_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_4.0, 8;
%pushi/vec4 0, 0, 36;
%split/vec4 16;
%assign/vec4 v0x557f826bd290_0, 0;
%split/vec4 1;
%assign/vec4 v0x557f826bd3a0_0, 0;
%split/vec4 15;
%assign/vec4 v0x557f826bd020_0, 0;
%split/vec4 3;
%assign/vec4 v0x557f826bcf40_0, 0;
%assign/vec4 v0x557f826bd100_0, 0;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x557f826bd600_0, 0;
%jmp T_4.1;
T_4.0 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x557f826bd3a0_0, 0;
%load/vec4 v0x557f826bd600_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_4.2, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_4.3, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_4.4, 6;
%dup/vec4;
%pushi/vec4 3, 0, 2;
%cmp/u;
%jmp/1 T_4.5, 6;
%jmp T_4.6;
T_4.2 ;
%load/vec4 v0x557f826bd560_0;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_4.7, 4;
%pushi/vec4 1, 0, 2;
%assign/vec4 v0x557f826bd600_0, 0;
T_4.7 ;
%jmp T_4.6;
T_4.3 ;
%load/vec4 v0x557f826bd020_0;
%cmpi/e 10415, 0, 15;
%jmp/0xz T_4.9, 4;
%pushi/vec4 2, 0, 2;
%assign/vec4 v0x557f826bd600_0, 0;
%pushi/vec4 0, 0, 15;
%assign/vec4 v0x557f826bd020_0, 0;
%jmp T_4.10;
T_4.9 ;
%load/vec4 v0x557f826bd020_0;
%addi 1, 0, 15;
%assign/vec4 v0x557f826bd020_0, 0;
T_4.10 ;
%jmp T_4.6;
T_4.4 ;
%load/vec4 v0x557f826bd020_0;
%cmpi/e 20832, 0, 15;
%jmp/0xz T_4.11, 4;
%pushi/vec4 0, 0, 15;
%assign/vec4 v0x557f826bd020_0, 0;
%load/vec4 v0x557f826bd560_0;
%load/vec4 v0x557f826bd290_0;
%parti/s 15, 1, 2;
%concat/vec4; draw_concat_vec4
%assign/vec4 v0x557f826bd290_0, 0;
%load/vec4 v0x557f826bcf40_0;
%cmpi/e 7, 0, 3;
%jmp/0xz T_4.13, 4;
%pushi/vec4 3, 0, 2;
%assign/vec4 v0x557f826bd600_0, 0;
%pushi/vec4 0, 0, 3;
%assign/vec4 v0x557f826bcf40_0, 0;
%load/vec4 v0x557f826bd100_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_4.15, 4;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x557f826bd3a0_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x557f826bd100_0, 0;
%jmp T_4.16;
T_4.15 ;
%load/vec4 v0x557f826bd100_0;
%pad/u 2;
%addi 1, 0, 2;
%pad/u 1;
%assign/vec4 v0x557f826bd100_0, 0;
T_4.16 ;
%jmp T_4.14;
T_4.13 ;
%load/vec4 v0x557f826bcf40_0;
%addi 1, 0, 3;
%assign/vec4 v0x557f826bcf40_0, 0;
T_4.14 ;
%jmp T_4.12;
T_4.11 ;
%load/vec4 v0x557f826bd020_0;
%addi 1, 0, 15;
%assign/vec4 v0x557f826bd020_0, 0;
T_4.12 ;
%jmp T_4.6;
T_4.5 ;
%load/vec4 v0x557f826bd020_0;
%cmpi/e 20832, 0, 15;
%jmp/0xz T_4.17, 4;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x557f826bd600_0, 0;
%pushi/vec4 0, 0, 15;
%assign/vec4 v0x557f826bd020_0, 0;
%jmp T_4.18;
T_4.17 ;
%load/vec4 v0x557f826bd020_0;
%addi 1, 0, 15;
%assign/vec4 v0x557f826bd020_0, 0;
T_4.18 ;
%jmp T_4.6;
T_4.6 ;
%pop/vec4 1;
T_4.1 ;
%jmp T_4;
.thread T_4;
.scope S_0x557f826b8240;
T_5 ;
%wait E_0x557f825f0e50;
%load/vec4 v0x557f826b9d80_0;
%flag_set/vec4 8;
%jmp/0xz T_5.0, 8;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826b9f20, 4;
%pad/s 7;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826ba3e0, 4;
%pad/s 7;
%mul;
%ix/load 3, 0, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x557f826ba180, 0, 4;
T_5.0 ;
%jmp T_5;
.thread T_5;
.scope S_0x557f826b8520;
T_6 ;
%wait E_0x557f825f0e50;
%load/vec4 v0x557f826b9d80_0;
%flag_set/vec4 8;
%jmp/0xz T_6.0, 8;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826b9f20, 4;
%pad/s 7;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826ba3e0, 4;
%pad/s 7;
%mul;
%ix/load 3, 1, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x557f826ba180, 0, 4;
T_6.0 ;
%jmp T_6;
.thread T_6;
.scope S_0x557f826b8ab0;
T_7 ;
%wait E_0x557f825f0e50;
%load/vec4 v0x557f826b9d80_0;
%flag_set/vec4 8;
%jmp/0xz T_7.0, 8;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826ba180, 4;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826ba180, 4;
%add;
%ix/load 3, 2, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x557f826ba180, 0, 4;
T_7.0 ;
%jmp T_7;
.thread T_7;
.scope S_0x557f826b9150;
T_8 ;
%wait E_0x557f825f0e50;
%load/vec4 v0x557f826b9d80_0;
%flag_set/vec4 8;
%jmp/0xz T_8.0, 8;
%ix/load 4, 2, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826b9f20, 4;
%pad/s 7;
%ix/load 4, 0, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826ba3e0, 4;
%pad/s 7;
%mul;
%ix/load 3, 4, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x557f826ba180, 0, 4;
T_8.0 ;
%jmp T_8;
.thread T_8;
.scope S_0x557f826b9430;
T_9 ;
%wait E_0x557f825f0e50;
%load/vec4 v0x557f826b9d80_0;
%flag_set/vec4 8;
%jmp/0xz T_9.0, 8;
%ix/load 4, 3, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826b9f20, 4;
%pad/s 7;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826ba3e0, 4;
%pad/s 7;
%mul;
%ix/load 3, 5, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x557f826ba180, 0, 4;
T_9.0 ;
%jmp T_9;
.thread T_9;
.scope S_0x557f826b99c0;
T_10 ;
%wait E_0x557f825f0e50;
%load/vec4 v0x557f826b9d80_0;
%flag_set/vec4 8;
%jmp/0xz T_10.0, 8;
%ix/load 4, 4, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826ba180, 4;
%ix/load 4, 5, 0;
%flag_set/imm 4, 0;
%load/vec4a v0x557f826ba180, 4;
%add;
%ix/load 3, 6, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0x557f826ba180, 0, 4;
T_10.0 ;
%jmp T_10;
.thread T_10;
.scope S_0x557f826ba760;
T_11 ;
%wait E_0x557f826bacd0;
%load/vec4 v0x557f826bb490_0;
%store/vec4 v0x557f826bb550_0, 0, 2;
%load/vec4 v0x557f826bb490_0;
%dup/vec4;
%pushi/vec4 0, 0, 2;
%cmp/u;
%jmp/1 T_11.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 2;
%cmp/u;
%jmp/1 T_11.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 2;
%cmp/u;
%jmp/1 T_11.2, 6;
%vpi_call/w 9 12 "$warning", "value is unhandled for priority or unique case statement" {0 0 0};
%jmp T_11.3;
T_11.0 ;
%load/vec4 v0x557f826bb3f0_0;
%flag_set/vec4 8;
%jmp/0xz T_11.4, 8;
%pushi/vec4 1, 0, 2;
%store/vec4 v0x557f826bb550_0, 0, 2;
T_11.4 ;
%jmp T_11.3;
T_11.1 ;
%load/vec4 v0x557f826baff0_0;
%nor/r;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_11.8, 9;
%load/vec4 v0x557f826bb3f0_0;
%and;
T_11.8;
%flag_set/vec4 8;
%jmp/0xz T_11.6, 8;
%pushi/vec4 2, 0, 2;
%store/vec4 v0x557f826bb550_0, 0, 2;
%jmp T_11.7;
T_11.6 ;
%load/vec4 v0x557f826baff0_0;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_11.11, 9;
%load/vec4 v0x557f826bb3f0_0;
%nor/r;
%and;
T_11.11;
%flag_set/vec4 8;
%jmp/0xz T_11.9, 8;
%pushi/vec4 0, 0, 2;
%store/vec4 v0x557f826bb550_0, 0, 2;
T_11.9 ;
T_11.7 ;
%jmp T_11.3;
T_11.2 ;
%load/vec4 v0x557f826baff0_0;
%flag_set/vec4 8;
%jmp/0xz T_11.12, 8;
%pushi/vec4 1, 0, 2;
%store/vec4 v0x557f826bb550_0, 0, 2;
T_11.12 ;
%jmp T_11.3;
T_11.3 ;
%pop/vec4 1;
%jmp T_11;
.thread T_11, $push;
.scope S_0x557f826ba760;
T_12 ;
%wait E_0x557f826bac70;
%load/vec4 v0x557f826bb1a0_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_12.0, 8;
%pushi/vec4 0, 0, 2;
%assign/vec4 v0x557f826bb490_0, 0;
%jmp T_12.1;
T_12.0 ;
%load/vec4 v0x557f826bb550_0;
%assign/vec4 v0x557f826bb490_0, 0;
T_12.1 ;
%jmp T_12;
.thread T_12;
.scope S_0x557f826ba760;
T_13 ;
%wait E_0x557f826bac70;
%load/vec4 v0x557f826bb1a0_0;
%nor/r;
%flag_set/vec4 8;
%jmp/0xz T_13.0, 8;
%pushi/vec4 0, 0, 30;
%split/vec4 14;
%assign/vec4 v0x557f826baf20_0, 0;
%split/vec4 14;
%assign/vec4 v0x557f826bad30_0, 0;
%split/vec4 1;
%assign/vec4 v0x557f826bb320_0, 0;
%assign/vec4 v0x557f826bb090_0, 0;
%jmp T_13.1;
T_13.0 ;
%load/vec4 v0x557f826bb550_0;
%pad/u 32;
%pushi/vec4 0, 0, 32;
%cmp/ne;
%flag_get/vec4 4;
%assign/vec4 v0x557f826bb090_0, 0;
%load/vec4 v0x557f826bb550_0;
%pad/u 32;
%pushi/vec4 2, 0, 32;
%cmp/ne;
%flag_get/vec4 4;