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I'm looking at integrating new bits into the SOC, so I want to check they work.
My design uses the 24 and 48 mhz clock, but only the 48 and 96 mhz clock is supplied by verilator.
Is there a reason for this?
The text was updated successfully, but these errors were encountered:
So for example, in your fork that includes the HUB75 core, if I want to test that in simulation I will have to add the 24mhz clock to verilator (and fix those parameter issues)
I'm looking at integrating new bits into the SOC, so I want to check they work.
My design uses the 24 and 48 mhz clock, but only the 48 and 96 mhz clock is supplied by verilator.
Is there a reason for this?
The text was updated successfully, but these errors were encountered: