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mir-gen-x86_64.c
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/* This file is a part of MIR project.
Copyright (C) 2018-2020 Vladimir Makarov <[email protected]>.
*/
#include <limits.h>
#define HREG_EL(h) h##_HARD_REG
#define REP_SEP ,
enum {
REP8 (HREG_EL, AX, CX, DX, BX, SP, BP, SI, DI),
REP8 (HREG_EL, R8, R9, R10, R11, R12, R13, R14, R15),
REP8 (HREG_EL, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7),
REP8 (HREG_EL, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15),
REP2 (HREG_EL, ST0, ST1),
};
#undef REP_SEP
static const MIR_reg_t MAX_HARD_REG = ST1_HARD_REG;
static const MIR_reg_t FP_HARD_REG = BP_HARD_REG;
static int target_locs_num (MIR_reg_t loc, MIR_type_t type) {
return loc > MAX_HARD_REG && type == MIR_T_LD ? 2 : 1;
}
/* Hard regs not used in machinized code, preferably call used ones. */
const MIR_reg_t TEMP_INT_HARD_REG1 = R10_HARD_REG, TEMP_INT_HARD_REG2 = R11_HARD_REG;
const MIR_reg_t TEMP_FLOAT_HARD_REG1 = XMM8_HARD_REG, TEMP_FLOAT_HARD_REG2 = XMM9_HARD_REG;
const MIR_reg_t TEMP_DOUBLE_HARD_REG1 = XMM8_HARD_REG, TEMP_DOUBLE_HARD_REG2 = XMM9_HARD_REG;
const MIR_reg_t TEMP_LDOUBLE_HARD_REG1 = MIR_NON_HARD_REG;
const MIR_reg_t TEMP_LDOUBLE_HARD_REG2 = MIR_NON_HARD_REG;
static inline int target_hard_reg_type_ok_p (MIR_reg_t hard_reg, MIR_type_t type) {
assert (hard_reg <= MAX_HARD_REG);
/* For LD we need x87 stack regs and it is too complicated so no
hard register allocation for LD: */
if (type == MIR_T_LD) return FALSE;
return MIR_int_type_p (type) ? hard_reg < XMM0_HARD_REG : hard_reg >= XMM0_HARD_REG;
}
static inline int target_fixed_hard_reg_p (MIR_reg_t hard_reg) {
assert (hard_reg <= MAX_HARD_REG);
return (hard_reg == BP_HARD_REG || hard_reg == SP_HARD_REG || hard_reg == TEMP_INT_HARD_REG1
|| hard_reg == TEMP_INT_HARD_REG2 || hard_reg == TEMP_FLOAT_HARD_REG1
|| hard_reg == TEMP_FLOAT_HARD_REG2 || hard_reg == TEMP_DOUBLE_HARD_REG1
|| hard_reg == TEMP_DOUBLE_HARD_REG2 || hard_reg == ST0_HARD_REG
|| hard_reg == ST1_HARD_REG);
}
static inline int target_call_used_hard_reg_p (MIR_reg_t hard_reg) {
assert (hard_reg <= MAX_HARD_REG);
return !(hard_reg == BX_HARD_REG || (hard_reg >= R12_HARD_REG && hard_reg <= R15_HARD_REG));
}
/* Stack layout (sp refers to the last reserved stack slot address)
from higher address to lower address memory:
| ... | prev func stack frame (start address should be aligned to 16 bytes)
|---------------|
| return pc | value of sp before prologue = start sp hard reg
|---------------|
| old bp | bp for previous func stack frame; new bp refers for here
|---------------|
| reg save | 176 bytes
| area | optional area for vararg func reg save area
|---------------|
| slots assigned| can be absent for small functions (known only after RA)
| to pseudos |
|---------------|
| saved regs | callee saved regs used in the func (known only after RA)
|---------------|
| alloca areas | optional
|---------------|
| slots for | dynamically allocated/deallocated by caller
| passing args |
size of slots and saved regs is multiple of 16 bytes
*/
static const int reg_save_area_size = 176;
static MIR_disp_t target_get_stack_slot_offset (MIR_context_t ctx, MIR_type_t type,
MIR_reg_t slot) {
/* slot is 0, 1, ... */
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
return -((MIR_disp_t) (slot + (type == MIR_T_LD ? 2 : 1)) * 8
+ (curr_func_item->u.func->vararg_p ? reg_save_area_size : 0));
}
static const MIR_insn_code_t target_io_dup_op_insn_codes[] = {
/* see possible patterns */
MIR_FADD, MIR_DADD, MIR_LDADD, MIR_SUB, MIR_SUBS, MIR_FSUB, MIR_DSUB,
MIR_LDSUB, MIR_MUL, MIR_MULS, MIR_FMUL, MIR_DMUL, MIR_LDMUL, MIR_DIV,
MIR_DIVS, MIR_UDIV, MIR_FDIV, MIR_DDIV, MIR_LDDIV, MIR_MOD, MIR_MODS,
MIR_UMOD, MIR_UMODS, MIR_AND, MIR_ANDS, MIR_OR, MIR_ORS, MIR_XOR,
MIR_XORS, MIR_LSH, MIR_LSHS, MIR_RSH, MIR_RSHS, MIR_URSH, MIR_URSHS,
MIR_NEG, MIR_NEGS, MIR_FNEG, MIR_DNEG, MIR_LDNEG, MIR_INSN_BOUND,
};
static MIR_insn_code_t get_ext_code (MIR_type_t type) {
switch (type) {
case MIR_T_I8: return MIR_EXT8;
case MIR_T_U8: return MIR_UEXT8;
case MIR_T_I16: return MIR_EXT16;
case MIR_T_U16: return MIR_UEXT16;
case MIR_T_I32: return MIR_EXT32;
case MIR_T_U32: return MIR_UEXT32;
default: return MIR_INVALID_INSN;
}
}
static MIR_reg_t get_fp_arg_reg (size_t fp_arg_num) {
switch (fp_arg_num) {
case 0:
case 1:
case 2:
case 3:
#ifndef _WIN64
case 4:
case 5:
case 6:
case 7:
#endif
return XMM0_HARD_REG + fp_arg_num;
default: return MIR_NON_HARD_REG;
}
}
static MIR_reg_t get_int_arg_reg (size_t int_arg_num) {
switch (int_arg_num
#ifdef _WIN64
+ 2
#endif
) {
case 0: return DI_HARD_REG;
case 1: return SI_HARD_REG;
#ifdef _WIN64
case 2: return CX_HARD_REG;
case 3: return DX_HARD_REG;
#else
case 2: return DX_HARD_REG;
case 3: return CX_HARD_REG;
#endif
case 4: return R8_HARD_REG;
case 5: return R9_HARD_REG;
default: return MIR_NON_HARD_REG;
}
}
static MIR_reg_t get_arg_reg (MIR_type_t arg_type, size_t *int_arg_num, size_t *fp_arg_num,
MIR_insn_code_t *mov_code) {
MIR_reg_t arg_reg;
if (arg_type == MIR_T_LD) {
arg_reg = MIR_NON_HARD_REG;
*mov_code = MIR_LDMOV;
} else if (arg_type == MIR_T_F || arg_type == MIR_T_D) {
arg_reg = get_fp_arg_reg (*fp_arg_num);
(*fp_arg_num)++;
#ifdef _WIN64
(*int_arg_num)++; /* arg slot used by fp, skip int register */
#endif
*mov_code = arg_type == MIR_T_F ? MIR_FMOV : MIR_DMOV;
} else {
arg_reg = get_int_arg_reg (*int_arg_num);
#ifdef _WIN64
(*fp_arg_num)++; /* arg slot used by int, skip fp register */
#endif
(*int_arg_num)++;
*mov_code = MIR_MOV;
}
return arg_reg;
}
static void machinize_call (MIR_context_t ctx, MIR_insn_t call_insn) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_func_t func = curr_func_item->u.func;
MIR_proto_t proto = call_insn->ops[0].u.ref->u.proto;
size_t nargs, nops = MIR_insn_nops (ctx, call_insn), start = proto->nres + 2;
size_t int_arg_num = 0, fp_arg_num = 0, mem_size = 0, xmm_args = 0;
MIR_type_t type, mem_type;
MIR_op_mode_t mode;
MIR_var_t *arg_vars = NULL;
MIR_reg_t arg_reg;
MIR_op_t arg_op, temp_op, arg_reg_op, ret_reg_op, mem_op;
MIR_insn_code_t new_insn_code, ext_code;
MIR_insn_t new_insn, prev_insn, next_insn, ext_insn;
MIR_insn_t prev_call_insn = DLIST_PREV (MIR_insn_t, call_insn);
uint32_t n_iregs, n_xregs, n_fregs;
if (call_insn->code == MIR_INLINE) call_insn->code = MIR_CALL;
if (proto->args == NULL) {
nargs = 0;
} else {
gen_assert (nops >= VARR_LENGTH (MIR_var_t, proto->args)
&& (proto->vararg_p || nops - start == VARR_LENGTH (MIR_var_t, proto->args)));
nargs = VARR_LENGTH (MIR_var_t, proto->args);
arg_vars = VARR_ADDR (MIR_var_t, proto->args);
}
#ifdef _WIN64
if (nargs > 4 || proto->vararg_p) mem_size = 32; /* spill space for register args */
#endif
if (call_insn->ops[1].mode != MIR_OP_REG && call_insn->ops[1].mode != MIR_OP_HARD_REG) {
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, func));
new_insn = MIR_new_insn (ctx, MIR_MOV, temp_op, call_insn->ops[1]);
call_insn->ops[1] = temp_op;
gen_add_insn_before (ctx, call_insn, new_insn);
}
for (size_t i = start; i < nops; i++) {
arg_op = call_insn->ops[i];
gen_assert (arg_op.mode == MIR_OP_REG || arg_op.mode == MIR_OP_HARD_REG);
if (i - start < nargs) {
type = arg_vars[i - start].type;
} else {
mode = call_insn->ops[i].value_mode; // ??? smaller ints
gen_assert (mode == MIR_OP_INT || mode == MIR_OP_UINT || mode == MIR_OP_FLOAT
|| mode == MIR_OP_DOUBLE || mode == MIR_OP_LDOUBLE);
if (mode == MIR_OP_FLOAT)
(*MIR_get_error_func (ctx)) (MIR_call_op_error,
"passing float variadic arg (should be passed as double)");
type = mode == MIR_OP_DOUBLE ? MIR_T_D : mode == MIR_OP_LDOUBLE ? MIR_T_LD : MIR_T_I64;
}
if (xmm_args < 8 && (type == MIR_T_F || type == MIR_T_D)) xmm_args++;
ext_insn = NULL;
if ((ext_code = get_ext_code (type)) != MIR_INVALID_INSN) { /* extend arg if necessary */
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, func));
ext_insn = MIR_new_insn (ctx, ext_code, temp_op, arg_op);
call_insn->ops[i] = arg_op = temp_op;
}
if ((arg_reg = get_arg_reg (type, &int_arg_num, &fp_arg_num, &new_insn_code))
!= MIR_NON_HARD_REG) {
/* put arguments to argument hard regs */
if (ext_insn != NULL) gen_add_insn_before (ctx, call_insn, ext_insn);
arg_reg_op = _MIR_new_hard_reg_op (ctx, arg_reg);
new_insn = MIR_new_insn (ctx, new_insn_code, arg_reg_op, arg_op);
gen_add_insn_before (ctx, call_insn, new_insn);
call_insn->ops[i] = arg_reg_op;
#ifdef _WIN64
/* copy fp reg varargs into corresponding int regs */
if (proto->vararg_p && type == MIR_T_D) {
gen_assert (int_arg_num > 0 && int_arg_num <= 4);
arg_reg = get_int_arg_reg (int_arg_num - 1);
setup_call_hard_reg_args (call_insn, arg_reg);
/* mir does not support moving fp to int regs directly, spill and load them instead */
mem_op = _MIR_new_hard_reg_mem_op (ctx, MIR_T_D, 8, SP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, MIR_DMOV, mem_op, arg_op);
gen_add_insn_before (ctx, call_insn, new_insn);
mem_op = _MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, 8, SP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, MIR_MOV, _MIR_new_hard_reg_op (ctx, arg_reg), mem_op);
gen_add_insn_before (ctx, call_insn, new_insn);
}
#endif
} else { /* put arguments on the stack */
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64;
new_insn_code
= (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV : type == MIR_T_LD ? MIR_LDMOV : MIR_MOV);
mem_op = _MIR_new_hard_reg_mem_op (ctx, mem_type, mem_size, SP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, new_insn_code, mem_op, arg_op);
gen_assert (prev_call_insn != NULL); /* call_insn should not be 1st after simplification */
MIR_insert_insn_after (ctx, curr_func_item, prev_call_insn, new_insn);
prev_insn = DLIST_PREV (MIR_insn_t, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (ctx, prev_insn, next_insn, call_insn);
call_insn->ops[i] = mem_op;
mem_size += type == MIR_T_LD ? 16 : 8;
if (ext_insn != NULL) gen_add_insn_after (ctx, prev_call_insn, ext_insn);
}
}
#ifndef _WIN64
if (proto->vararg_p) {
setup_call_hard_reg_args (call_insn, AX_HARD_REG);
new_insn = MIR_new_insn (ctx, MIR_MOV, _MIR_new_hard_reg_op (ctx, AX_HARD_REG),
MIR_new_int_op (ctx, xmm_args));
gen_add_insn_before (ctx, call_insn, new_insn);
}
#endif
n_iregs = n_xregs = n_fregs = 0;
for (size_t i = 0; i < proto->nres; i++) {
ret_reg_op = call_insn->ops[i + 2];
gen_assert (ret_reg_op.mode == MIR_OP_REG || ret_reg_op.mode == MIR_OP_HARD_REG);
if (proto->res_types[i] == MIR_T_F && n_xregs < 2) {
new_insn
= MIR_new_insn (ctx, MIR_FMOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, n_xregs == 0 ? XMM0_HARD_REG : XMM1_HARD_REG));
n_xregs++;
} else if (proto->res_types[i] == MIR_T_D && n_xregs < 2) {
new_insn
= MIR_new_insn (ctx, MIR_DMOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, n_xregs == 0 ? XMM0_HARD_REG : XMM1_HARD_REG));
n_xregs++;
} else if (proto->res_types[i] == MIR_T_LD && n_fregs < 2) {
new_insn
= MIR_new_insn (ctx, MIR_LDMOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, n_fregs == 0 ? ST0_HARD_REG : ST1_HARD_REG));
n_fregs++;
} else if (n_iregs < 2) {
new_insn
= MIR_new_insn (ctx, MIR_MOV, ret_reg_op,
_MIR_new_hard_reg_op (ctx, n_iregs == 0 ? AX_HARD_REG : DX_HARD_REG));
n_iregs++;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"x86-64 can not handle this combination of return values");
}
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
call_insn->ops[i + 2] = new_insn->ops[1];
if ((ext_code = get_ext_code (proto->res_types[i])) != MIR_INVALID_INSN) {
MIR_insert_insn_after (ctx, curr_func_item, new_insn,
MIR_new_insn (ctx, ext_code, ret_reg_op, ret_reg_op));
new_insn = DLIST_NEXT (MIR_insn_t, new_insn);
}
create_new_bb_insns (ctx, call_insn, DLIST_NEXT (MIR_insn_t, new_insn), call_insn);
}
if (mem_size != 0) { /* allocate/deallocate stack for args passed on stack */
mem_size = (mem_size + 15) / 16 * 16; /* make it of several 16 bytes */
new_insn
= MIR_new_insn (ctx, MIR_SUB, _MIR_new_hard_reg_op (ctx, SP_HARD_REG),
_MIR_new_hard_reg_op (ctx, SP_HARD_REG), MIR_new_int_op (ctx, mem_size));
MIR_insert_insn_after (ctx, curr_func_item, prev_call_insn, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (ctx, prev_call_insn, next_insn, call_insn);
new_insn
= MIR_new_insn (ctx, MIR_ADD, _MIR_new_hard_reg_op (ctx, SP_HARD_REG),
_MIR_new_hard_reg_op (ctx, SP_HARD_REG), MIR_new_int_op (ctx, mem_size));
MIR_insert_insn_after (ctx, curr_func_item, call_insn, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (ctx, call_insn, next_insn, call_insn);
}
}
static float mir_ui2f (uint64_t i) { return i; }
static double mir_ui2d (uint64_t i) { return i; }
static long double mir_ui2ld (uint64_t i) { return i; }
static int64_t mir_ld2i (long double ld) { return ld; }
static const char *UI2F = "mir.ui2f";
static const char *UI2D = "mir.ui2d";
static const char *UI2LD = "mir.ui2ld";
static const char *LD2I = "mir.ld2i";
static const char *UI2F_P = "mir.ui2f.p";
static const char *UI2D_P = "mir.ui2d.p";
static const char *UI2LD_P = "mir.ui2ld.p";
static const char *LD2I_P = "mir.ld2i.p";
static const char *VA_ARG_P = "mir.va_arg.p";
static const char *VA_ARG = "mir.va_arg";
static void get_builtin (MIR_context_t ctx, MIR_insn_code_t code, MIR_item_t *proto_item,
MIR_item_t *func_import_item) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_type_t res_type;
*func_import_item = *proto_item = NULL; /* to remove uninitialized warning */
switch (code) {
case MIR_UI2F:
res_type = MIR_T_F;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, UI2F_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, UI2F, mir_ui2f);
break;
case MIR_UI2D:
res_type = MIR_T_D;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, UI2D_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, UI2D, mir_ui2d);
break;
case MIR_UI2LD:
res_type = MIR_T_LD;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, UI2LD_P, 1, &res_type, 1, MIR_T_I64, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, UI2LD, mir_ui2ld);
break;
case MIR_LD2I:
res_type = MIR_T_I64;
*proto_item
= _MIR_builtin_proto (ctx, curr_func_item->module, LD2I_P, 1, &res_type, 1, MIR_T_LD, "v");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, LD2I, mir_ld2i);
break;
case MIR_VA_ARG:
res_type = MIR_T_I64;
*proto_item = _MIR_builtin_proto (ctx, curr_func_item->module, VA_ARG_P, 1, &res_type, 2,
MIR_T_I64, "va", MIR_T_I64, "type");
*func_import_item = _MIR_builtin_func (ctx, curr_func_item->module, VA_ARG, va_arg_builtin);
break;
default: assert (FALSE);
}
}
static void gen_mov (MIR_context_t ctx, MIR_insn_t anchor, MIR_insn_code_t code, MIR_op_t dst_op,
MIR_op_t src_op) {
gen_add_insn_before (ctx, anchor, MIR_new_insn (ctx, code, dst_op, src_op));
}
DEF_VARR (int);
DEF_VARR (uint8_t);
DEF_VARR (uint64_t);
struct insn_pattern_info {
int start, num;
};
typedef struct insn_pattern_info insn_pattern_info_t;
DEF_VARR (insn_pattern_info_t);
struct const_ref {
size_t pc; /* where rel32 address should be in code */
size_t next_insn_disp; /* displacement of the next insn */
size_t const_num;
};
typedef struct const_ref const_ref_t;
DEF_VARR (const_ref_t);
struct label_ref {
int abs_addr_p;
size_t label_val_disp, next_insn_disp;
MIR_label_t label;
};
typedef struct label_ref label_ref_t;
DEF_VARR (label_ref_t);
DEF_VARR (MIR_code_reloc_t);
struct target_ctx {
unsigned char alloca_p, stack_arg_func_p, leaf_p;
int start_sp_from_bp_offset;
VARR (int) * pattern_indexes;
VARR (insn_pattern_info_t) * insn_pattern_info;
VARR (uint8_t) * result_code;
VARR (uint64_t) * const_pool;
VARR (const_ref_t) * const_refs;
VARR (label_ref_t) * label_refs;
VARR (uint64_t) * abs_address_locs;
VARR (MIR_code_reloc_t) * relocs;
};
#define alloca_p gen_ctx->target_ctx->alloca_p
#define stack_arg_func_p gen_ctx->target_ctx->stack_arg_func_p
#define leaf_p gen_ctx->target_ctx->leaf_p
#define start_sp_from_bp_offset gen_ctx->target_ctx->start_sp_from_bp_offset
#define pattern_indexes gen_ctx->target_ctx->pattern_indexes
#define insn_pattern_info gen_ctx->target_ctx->insn_pattern_info
#define result_code gen_ctx->target_ctx->result_code
#define const_pool gen_ctx->target_ctx->const_pool
#define const_refs gen_ctx->target_ctx->const_refs
#define label_refs gen_ctx->target_ctx->label_refs
#define abs_address_locs gen_ctx->target_ctx->abs_address_locs
#define relocs gen_ctx->target_ctx->relocs
static void target_machinize (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_func_t func;
MIR_type_t type, mem_type, res_type;
MIR_insn_code_t code, new_insn_code;
MIR_insn_t insn, next_insn, new_insn;
MIR_reg_t ret_reg, arg_reg;
MIR_op_t ret_reg_op, arg_reg_op, mem_op;
size_t i, int_arg_num, fp_arg_num, mem_size;
assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
stack_arg_func_p = FALSE;
start_sp_from_bp_offset = 8;
for (i = int_arg_num = fp_arg_num = mem_size = 0; i < func->nargs; i++) {
/* Argument extensions is already done in simplify */
/* Prologue: generate arg_var = hard_reg|stack mem ... */
type = VARR_GET (MIR_var_t, func->vars, i).type;
arg_reg = get_arg_reg (type, &int_arg_num, &fp_arg_num, &new_insn_code);
if (arg_reg != MIR_NON_HARD_REG) {
arg_reg_op = _MIR_new_hard_reg_op (ctx, arg_reg);
new_insn = MIR_new_insn (ctx, new_insn_code, MIR_new_reg_op (ctx, i + 1), arg_reg_op);
MIR_prepend_insn (ctx, curr_func_item, new_insn);
create_new_bb_insns (ctx, NULL, DLIST_NEXT (MIR_insn_t, new_insn), NULL);
} else {
/* arg is on the stack */
stack_arg_func_p = TRUE;
mem_type = type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD ? type : MIR_T_I64;
new_insn_code
= (type == MIR_T_F ? MIR_FMOV
: type == MIR_T_D ? MIR_DMOV : type == MIR_T_LD ? MIR_LDMOV : MIR_MOV);
mem_op = _MIR_new_hard_reg_mem_op (ctx, mem_type,
mem_size + 8 /* ret */
+ start_sp_from_bp_offset,
FP_HARD_REG, MIR_NON_HARD_REG, 1);
new_insn = MIR_new_insn (ctx, new_insn_code, MIR_new_reg_op (ctx, i + 1), mem_op);
MIR_prepend_insn (ctx, curr_func_item, new_insn);
next_insn = DLIST_NEXT (MIR_insn_t, new_insn);
create_new_bb_insns (ctx, NULL, next_insn, NULL);
mem_size += type == MIR_T_LD ? 16 : 8;
}
}
alloca_p = FALSE;
leaf_p = TRUE;
for (insn = DLIST_HEAD (MIR_insn_t, func->insns); insn != NULL; insn = next_insn) {
next_insn = DLIST_NEXT (MIR_insn_t, insn);
code = insn->code;
if (code == MIR_UI2F || code == MIR_UI2D || code == MIR_UI2LD || code == MIR_LD2I) {
/* Use a builtin func call: mov freg, func ref; call proto, freg, res_reg, op_reg */
MIR_item_t proto_item, func_import_item;
MIR_op_t freg_op, res_reg_op = insn->ops[0], op_reg_op = insn->ops[1], ops[4];
get_builtin (ctx, code, &proto_item, &func_import_item);
assert (res_reg_op.mode == MIR_OP_REG && op_reg_op.mode == MIR_OP_REG);
freg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, curr_func_item->u.func));
next_insn = new_insn
= MIR_new_insn (ctx, MIR_MOV, freg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (ctx, insn, new_insn);
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = freg_op;
ops[2] = res_reg_op;
ops[3] = op_reg_op;
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, 4, ops);
gen_add_insn_before (ctx, insn, new_insn);
gen_delete_insn (ctx, insn);
} else if (code == MIR_VA_START) {
MIR_op_t treg_op
= MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, curr_func_item->u.func));
MIR_op_t va_op = insn->ops[0];
MIR_reg_t va_reg;
int gp_offset = 0, fp_offset = 48;
MIR_var_t var;
assert (func->vararg_p && (va_op.mode == MIR_OP_REG || va_op.mode == MIR_OP_HARD_REG));
for (uint32_t i = 0; i < func->nargs; i++) {
var = VARR_GET (MIR_var_t, func->vars, i);
if (var.type == MIR_T_F || var.type == MIR_T_D)
fp_offset += 16;
else
gp_offset += 8;
}
va_reg = va_op.mode == MIR_OP_REG ? va_op.u.reg : va_op.u.hard_reg;
/* Insns can be not simplified as soon as they match a machine insn. */
/* mem32[va_reg] = gp_offset; mem32[va_reg] = fp_offset */
gen_mov (ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_U32, 0, va_reg, 0, 1),
MIR_new_int_op (ctx, gp_offset));
next_insn = DLIST_PREV (MIR_insn_t, insn);
gen_mov (ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_U32, 4, va_reg, 0, 1),
MIR_new_int_op (ctx, fp_offset));
/* overflow_arg_area_reg: treg = start sp + 8; mem64[va_reg + 8] = treg */
new_insn = MIR_new_insn (ctx, MIR_ADD, treg_op, _MIR_new_hard_reg_op (ctx, FP_HARD_REG),
MIR_new_int_op (ctx, 8 /*ret*/ + start_sp_from_bp_offset));
gen_add_insn_before (ctx, insn, new_insn);
gen_mov (ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_I64, 8, va_reg, 0, 1), treg_op);
/* reg_save_area: treg = start sp - reg_save_area_size; mem64[va_reg + 16] = treg */
new_insn = MIR_new_insn (ctx, MIR_ADD, treg_op, _MIR_new_hard_reg_op (ctx, FP_HARD_REG),
MIR_new_int_op (ctx, -reg_save_area_size));
gen_add_insn_before (ctx, insn, new_insn);
gen_mov (ctx, insn, MIR_MOV, MIR_new_mem_op (ctx, MIR_T_I64, 16, va_reg, 0, 1), treg_op);
gen_delete_insn (ctx, insn);
} else if (code == MIR_VA_END) { /* do nothing */
gen_delete_insn (ctx, insn);
} else if (code == MIR_VA_ARG) { /* do nothing */
/* Use a builtin func call:
mov func_reg, func ref; mov flag_reg, <0|1>; call proto, func_reg, res_reg, va_reg,
flag_reg */
MIR_item_t proto_item, func_import_item;
MIR_op_t ops[5], func_reg_op, flag_reg_op;
MIR_op_t res_reg_op = insn->ops[0], va_reg_op = insn->ops[1], mem_op = insn->ops[2];
get_builtin (ctx, code, &proto_item, &func_import_item);
assert (res_reg_op.mode == MIR_OP_REG && va_reg_op.mode == MIR_OP_REG
&& mem_op.mode == MIR_OP_MEM);
func_reg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, curr_func_item->u.func));
flag_reg_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, MIR_T_I64, curr_func_item->u.func));
next_insn = new_insn
= MIR_new_insn (ctx, MIR_MOV, func_reg_op, MIR_new_ref_op (ctx, func_import_item));
gen_add_insn_before (ctx, insn, new_insn);
new_insn = MIR_new_insn (ctx, MIR_MOV, flag_reg_op,
MIR_new_int_op (ctx, (int64_t) mem_op.u.mem.type));
gen_add_insn_before (ctx, insn, new_insn);
ops[0] = MIR_new_ref_op (ctx, proto_item);
ops[1] = func_reg_op;
ops[2] = res_reg_op;
ops[3] = va_reg_op;
ops[4] = flag_reg_op;
new_insn = MIR_new_insn_arr (ctx, MIR_CALL, 5, ops);
gen_add_insn_before (ctx, insn, new_insn);
gen_delete_insn (ctx, insn);
} else if (MIR_call_code_p (code)) {
machinize_call (ctx, insn);
leaf_p = FALSE;
} else if (code == MIR_ALLOCA) {
alloca_p = TRUE;
} else if (code == MIR_RET) {
/* In simplify we already transformed code for one return insn
and added extension in return (if any). */
uint32_t n_iregs = 0, n_xregs = 0, n_fregs = 0;
assert (curr_func_item->u.func->nres == MIR_insn_nops (ctx, insn));
for (size_t i = 0; i < curr_func_item->u.func->nres; i++) {
assert (insn->ops[i].mode == MIR_OP_REG);
res_type = curr_func_item->u.func->res_types[i];
if ((res_type == MIR_T_F || res_type == MIR_T_D) && n_xregs < 2) {
new_insn_code = res_type == MIR_T_F ? MIR_FMOV : MIR_DMOV;
ret_reg = n_xregs++ == 0 ? XMM0_HARD_REG : XMM1_HARD_REG;
} else if (res_type == MIR_T_LD && n_fregs < 2) { // ???
new_insn_code = MIR_LDMOV;
ret_reg = n_fregs == 0 ? ST0_HARD_REG : ST1_HARD_REG;
n_fregs++;
} else if (n_iregs < 2) {
new_insn_code = MIR_MOV;
ret_reg = n_iregs++ == 0 ? AX_HARD_REG : DX_HARD_REG;
} else {
(*MIR_get_error_func (ctx)) (MIR_ret_error,
"x86-64 can not handle this combination of return values");
}
ret_reg_op = _MIR_new_hard_reg_op (ctx, ret_reg);
new_insn = MIR_new_insn (ctx, new_insn_code, ret_reg_op, insn->ops[i]);
gen_add_insn_before (ctx, insn, new_insn);
insn->ops[i] = ret_reg_op;
}
} else if (code == MIR_LSH || code == MIR_RSH || code == MIR_URSH || code == MIR_LSHS
|| code == MIR_RSHS || code == MIR_URSHS) {
/* We can access only cl as shift register: */
MIR_op_t creg_op = _MIR_new_hard_reg_op (ctx, CX_HARD_REG);
new_insn = MIR_new_insn (ctx, MIR_MOV, creg_op, insn->ops[2]);
gen_add_insn_before (ctx, insn, new_insn);
insn->ops[2] = creg_op;
} else if (code == MIR_DIV || code == MIR_UDIV || code == MIR_DIVS || code == MIR_UDIVS) {
/* Divide uses ax/dx as operands: */
MIR_op_t areg_op = _MIR_new_hard_reg_op (ctx, AX_HARD_REG);
new_insn = MIR_new_insn (ctx, MIR_MOV, areg_op, insn->ops[1]);
gen_add_insn_before (ctx, insn, new_insn);
new_insn = MIR_new_insn (ctx, MIR_MOV, insn->ops[0], areg_op);
gen_add_insn_after (ctx, insn, new_insn);
insn->ops[0] = insn->ops[1] = areg_op;
} else if (code == MIR_MOD || code == MIR_UMOD || code == MIR_MODS || code == MIR_UMODS) {
/* Divide uses ax/dx as operands: */
MIR_op_t areg_op = _MIR_new_hard_reg_op (ctx, AX_HARD_REG);
MIR_op_t dreg_op = _MIR_new_hard_reg_op (ctx, DX_HARD_REG);
new_insn = MIR_new_insn (ctx, MIR_MOV, areg_op, insn->ops[1]);
gen_add_insn_before (ctx, insn, new_insn);
insn->ops[1] = areg_op;
new_insn = MIR_new_insn (ctx, MIR_MOV, insn->ops[0], dreg_op);
gen_add_insn_after (ctx, insn, new_insn);
insn->ops[0] = dreg_op;
} else if (code == MIR_EQ || code == MIR_NE || code == MIR_LT || code == MIR_ULT
|| code == MIR_LE || code == MIR_ULE || code == MIR_GT || code == MIR_UGT
|| code == MIR_GE || code == MIR_UGE || code == MIR_EQS || code == MIR_NES
|| code == MIR_LTS || code == MIR_ULTS || code == MIR_LES || code == MIR_ULES
|| code == MIR_GTS || code == MIR_UGT || code == MIR_GES || code == MIR_UGES
|| code == MIR_FEQ || code == MIR_FNE || code == MIR_FLT || code == MIR_FLE
|| code == MIR_FGT || code == MIR_FGE || code == MIR_DEQ || code == MIR_DNE
|| code == MIR_DLT || code == MIR_DLE || code == MIR_DGT || code == MIR_DGE) {
/* We can access only 4 regs in setxx -- use ax as the result: */
MIR_op_t areg_op = _MIR_new_hard_reg_op (ctx, AX_HARD_REG);
new_insn = MIR_new_insn (ctx, MIR_MOV, insn->ops[0], areg_op);
gen_add_insn_after (ctx, insn, new_insn);
insn->ops[0] = areg_op;
}
}
}
static void isave (MIR_context_t ctx, MIR_insn_t anchor, int disp, MIR_reg_t hard_reg) {
gen_mov (ctx, anchor, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, disp, SP_HARD_REG, MIR_NON_HARD_REG, 1),
_MIR_new_hard_reg_op (ctx, hard_reg));
}
static void dsave (MIR_context_t ctx, MIR_insn_t anchor, int disp, MIR_reg_t hard_reg) {
gen_mov (ctx, anchor, MIR_DMOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_D, disp, SP_HARD_REG, MIR_NON_HARD_REG, 1),
_MIR_new_hard_reg_op (ctx, hard_reg));
}
static void target_make_prolog_epilog (MIR_context_t ctx, bitmap_t used_hard_regs,
size_t stack_slots_num) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_func_t func;
MIR_insn_t anchor, new_insn;
MIR_op_t sp_reg_op, fp_reg_op;
int64_t bp_saved_reg_offset, start;
size_t i, n, service_area_size, saved_hard_regs_num, stack_slots_size, block_size;
assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
for (i = saved_hard_regs_num = 0; i <= MAX_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i) && bitmap_bit_p (used_hard_regs, i)) saved_hard_regs_num++;
if (leaf_p && !alloca_p && !stack_arg_func_p && saved_hard_regs_num == 0 && !func->vararg_p
&& stack_slots_num == 0)
return;
sp_reg_op.mode = fp_reg_op.mode = MIR_OP_HARD_REG;
sp_reg_op.u.hard_reg = SP_HARD_REG;
fp_reg_op.u.hard_reg = FP_HARD_REG;
/* Prologue: */
anchor = DLIST_HEAD (MIR_insn_t, func->insns);
new_insn
= MIR_new_insn (ctx, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, -8, SP_HARD_REG, MIR_NON_HARD_REG, 1),
fp_reg_op);
gen_add_insn_before (ctx, anchor, new_insn); /* -8(sp) = bp */
/* Use add for matching LEA: */
new_insn = MIR_new_insn (ctx, MIR_ADD, fp_reg_op, sp_reg_op, MIR_new_int_op (ctx, -8));
gen_add_insn_before (ctx, anchor, new_insn); /* bp = sp - 8 */
if (!func->vararg_p) {
service_area_size = 8;
} else {
service_area_size = reg_save_area_size + 8;
start = -(int64_t) service_area_size;
isave (ctx, anchor, start, DI_HARD_REG);
isave (ctx, anchor, start + 8, SI_HARD_REG);
isave (ctx, anchor, start + 16, DX_HARD_REG);
isave (ctx, anchor, start + 24, CX_HARD_REG);
isave (ctx, anchor, start + 32, R8_HARD_REG);
isave (ctx, anchor, start + 40, R9_HARD_REG);
dsave (ctx, anchor, start + 48, XMM0_HARD_REG);
dsave (ctx, anchor, start + 64, XMM1_HARD_REG);
dsave (ctx, anchor, start + 80, XMM2_HARD_REG);
dsave (ctx, anchor, start + 96, XMM3_HARD_REG);
dsave (ctx, anchor, start + 112, XMM4_HARD_REG);
dsave (ctx, anchor, start + 128, XMM5_HARD_REG);
dsave (ctx, anchor, start + 144, XMM6_HARD_REG);
dsave (ctx, anchor, start + 160, XMM7_HARD_REG);
}
stack_slots_size = stack_slots_num * 8;
/* stack slots, and saved regs as multiple of 16 bytes: */
block_size = (stack_slots_size + 8 * saved_hard_regs_num + 15) / 16 * 16;
new_insn = MIR_new_insn (ctx, MIR_SUB, sp_reg_op, sp_reg_op,
MIR_new_int_op (ctx, block_size + service_area_size));
gen_add_insn_before (ctx, anchor, new_insn); /* sp -= block size + service_area_size */
bp_saved_reg_offset = block_size + (func->vararg_p ? reg_save_area_size : 0);
/* Saving callee saved hard registers: */
for (i = n = 0; i <= MAX_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i) && bitmap_bit_p (used_hard_regs, i)) {
assert (i <= R15_HARD_REG); /* xmm regs are always callee-clobbered */
new_insn = MIR_new_insn (ctx, MIR_MOV,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64,
(int64_t) (n++ * 8) - bp_saved_reg_offset,
FP_HARD_REG, MIR_NON_HARD_REG, 1),
_MIR_new_hard_reg_op (ctx, i));
gen_add_insn_before (ctx, anchor, new_insn); /* disp(sp) = saved hard reg */
}
/* Epilogue: */
anchor = DLIST_TAIL (MIR_insn_t, func->insns);
/* Restoring hard registers: */
for (i = n = 0; i <= MAX_HARD_REG; i++)
if (!target_call_used_hard_reg_p (i) && bitmap_bit_p (used_hard_regs, i)) {
new_insn = MIR_new_insn (ctx, MIR_MOV, _MIR_new_hard_reg_op (ctx, i),
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64,
(int64_t) (n++ * 8) - bp_saved_reg_offset,
FP_HARD_REG, MIR_NON_HARD_REG, 1));
gen_add_insn_before (ctx, anchor, new_insn); /* hard reg = disp(sp) */
}
new_insn = MIR_new_insn (ctx, MIR_ADD, sp_reg_op, fp_reg_op, MIR_new_int_op (ctx, 8));
gen_add_insn_before (ctx, anchor, new_insn); /* sp = bp + 8 */
new_insn = MIR_new_insn (ctx, MIR_MOV, fp_reg_op,
_MIR_new_hard_reg_mem_op (ctx, MIR_T_I64, -8, SP_HARD_REG,
MIR_NON_HARD_REG, 1));
gen_add_insn_before (ctx, anchor, new_insn); /* bp = -8(sp) */
}
struct pattern {
MIR_insn_code_t code;
/* Pattern elements:
blank - ignore
X - match everything
$ - finish successfully matching
r - register (we don't care about bp and sp because they are fixed and used correctly)
h[0-31] - hard register with given number
z - operand is zero
i[0-3] - immediate of size 8,16,32,64-bits
p[0-3] - reference
s - immediate 1, 2, 4, or 8 (scale)
m[0-3] - int (signed or unsigned) type memory of size 8,16,32,64-bits
ms[0-3] - signed int type memory of size 8,16,32,64-bits
mu[0-3] - unsigned int type memory of size 8,16,32,64-bits
mf - memory of float
md - memory of double
mld - memory of long double
l - label which can be present by 32-bit
[0-9] - an operand matching n-th operand (n should be less than given operand number)
Remember we have no float or (long) double immediate at this stage. They are represented by
a reference to data item. */
const char *pattern;
/* Replacement elements:
blank - ignore
; - insn separation
X - REX byte with W=1
Y - Optional REX byte with W=0
Z - Obligatory REX byte with W=0
[0-9A-F]+ pairs of hexidecimal digits opcode
r[0-2] = n-th operand in ModRM:reg
R[0-2] = n-th operand in ModRM:rm with mod == 3
m[0-2] = n-th operand is mem
mt = temp memory in red zone (-16(sp))
mT = switch table memory (h11,r,8)
ap = 2 and 3 operand forms address by plus (1st reg to base, 2nd reg to index, disp to disp)
am = 2 and 3 operand forms address by mult (1st reg to index and mult const to scale)
ad<value> - forms address: 1th operand is base reg and <value> is displacement
i[0-2] - n-th operand in byte immediate (should be imm of type i8)
I[0-2] - n-th operand in 4 byte immediate (should be imm of type i32)
J[0-2] - n-th operand in 8 byte immediate
P[0-2] - n-th operand in 8 byte address
T - absolute 8-byte switch table address
l[0-2] - n-th operand-label in 32-bit
/[0-7] - opmod with given value (reg of MOD-RM)
+[0-2] - lower 3-bit part of opcode used for n-th reg operand
c<value> - address of 32-bit or 64-bit constant in memory pool (we keep always 64-bit
in memory pool. x86_64 is LE)
h<one or two hex digits> - hardware register with given number in reg of ModRM:reg;
one bit of 8-15 in REX.R
H<one or two hex digits> - hardware register with given number in rm of MOD-RM with and mod=3
(register); one bit of 8-15 in REX.B v<value> - 8-bit immediate with given hex value V<value> -
32-bit immediate with given hex value
*/
const char *replacement;
};
// make imm always second operand (symplify for cmp and commutative op)
// make result of cmp op always a register and memory only the 2nd operand if first is reg,
// but not for FP (NAN) (simplify)
// for FP cmp first operand should be always reg (machinize)
#define IOP0(ICODE, SUFF, PREF, RRM_CODE, MR_CODE, RMI8_CODE, RMI32_CODE) \
{ICODE##SUFF, "r 0 r", #PREF " " RRM_CODE " r0 R2"}, /* op r0,r2*/ \
{ICODE##SUFF, "r 0 m3", #PREF " " RRM_CODE " r0 m2"}, /* op r0,m2*/ \
{ICODE##SUFF, "m3 0 r", #PREF " " MR_CODE " r2 m0"}, /* op m0,r2*/ \
{ICODE##SUFF, "r 0 i0", #PREF " " RMI8_CODE " R0 i2"}, /* op r0,i2*/ \
{ICODE##SUFF, "m3 0 i0", #PREF " " RMI8_CODE " m0 i2"}, /* op m0,i2*/ \
{ICODE##SUFF, "r 0 i2", #PREF " " RMI32_CODE " R0 I2"}, /* op r0,i2*/ \
{ICODE##SUFF, "m3 0 i2", #PREF " " RMI32_CODE " m0 I2"}, /* op m0,i2*/
#define IOP(ICODE, RRM_CODE, MR_CODE, RMI8_CODE, RMI32_CODE) \
IOP0 (ICODE, , X, RRM_CODE, MR_CODE, RMI8_CODE, RMI32_CODE) \
IOP0 (ICODE, S, Y, RRM_CODE, MR_CODE, RMI8_CODE, RMI32_CODE)
#define FOP(ICODE, OP_CODE) {ICODE, "r 0 r", OP_CODE " r0 R2"}, {ICODE, "r 0 mf", OP_CODE " r0 m2"},
#define DOP(ICODE, OP_CODE) {ICODE, "r 0 r", OP_CODE " r0 R2"}, {ICODE, "r 0 md", OP_CODE " r0 m2"},
#define LDOP(ICODE, OP_CODE) \
/* fld m1;fld m2;op;fstp m0: */ \
{ICODE, "mld mld mld", "DB /5 m1; DB /5 m2; " OP_CODE "; DB /7 m0"},
#define SHOP0(ICODE, SUFF, PREF, CL_OP_CODE, I8_OP_CODE) \
{ICODE##SUFF, "r 0 h1", #PREF " " CL_OP_CODE " R0"}, /* sh r0,cl */ \
{ICODE##SUFF, "m3 0 h1", #PREF " " CL_OP_CODE " m0"}, /* sh m0,cl */ \
{ICODE##SUFF, "r 0 i0", #PREF " " I8_OP_CODE " R0 i2"}, /* sh r0,i2 */ \
{ICODE##SUFF, "m3 0 i0", #PREF " " I8_OP_CODE " m0 i2"}, /* sh m0,i2 */
#define SHOP(ICODE, CL_OP_CODE, I8_OP_CODE) \
SHOP0 (ICODE, , X, CL_OP_CODE, I8_OP_CODE) \
SHOP0 (ICODE, S, Y, CL_OP_CODE, I8_OP_CODE)
/* cmp ...; setx r0; movzbl r0,r0: */
#define CMP0(ICODE, SUFF, PREF, SETX) \
{ICODE##SUFF, "r r r", #PREF " 3B r1 R2;" SETX " R0;X 0F B6 r0 R0"}, /* cmp r1,r2;...*/ \
{ICODE##SUFF, "r r m3", #PREF " 3B r1 m2;" SETX " R0;X 0F B6 r0 R0"}, /* cmp r1,m2;...*/ \
{ICODE##SUFF, "r r i0", #PREF " 83 /7 R1 i2;" SETX " R0;X 0F B6 r0 R0"}, /* cmp r1,i2;...*/ \
{ICODE##SUFF, "r r i2", #PREF " 81 /7 R1 I2;" SETX " R0;X 0F B6 r0 R0"}, /* cmp r1,i2;...*/ \
{ICODE##SUFF, "r m3 i0", #PREF " 83 /7 m1 i2;" SETX " R0;X 0F B6 r0 R0"}, /* cmp m1,i2;...*/ \
{ICODE##SUFF, "r m3 i2", #PREF " 81 /7 m1 I2;" SETX " R0;X 0F B6 r0 R0"}, /* cmp m1,i2;...*/
#define CMP(ICODE, SET_OPCODE) \
CMP0 (ICODE, , X, SET_OPCODE) \
CMP0 (ICODE, S, Y, SET_OPCODE)
#define FEQ(ICODE, V, SET_OPCODE) \
/*xor %eax,%eax;ucomiss r1,{r,m2};mov V,%edx;set[n]p r0;cmovne %rdx,%rax; mov %rax,r0: */ \
{ICODE, "r r r", \
"33 h0 H0; 0F 2E r1 R2; BA " V "; " SET_OPCODE " H0; X 0F 45 h0 H2; X 8B r0 H0"}, \
{ICODE, "r r md", \
"33 h0 H0; 0F 2E r1 m2; BA " V "; " SET_OPCODE " H0; X 0F 45 h0 H2; X 8B r0 H0"},
#define DEQ(ICODE, V, SET_OPCODE) \
/*xor %eax,%eax;ucomisd r1,{r,m2};mov V,%edx;set[n]p r0;cmovne %rdx,%rax; mov %rax,r0: */ \
{ICODE, "r r r", \
"33 h0 H0; 66 Y 0F 2E r1 R2; BA " V "; " SET_OPCODE " H0; X 0F 45 h0 H2; X 8B r0 H0"}, \
{ICODE, "r r md", \
"33 h0 H0; 66 Y 0F 2E r1 m2; BA " V "; " SET_OPCODE " H0; X 0F 45 h0 H2; X 8B r0 H0"},
#define LDEQ(ICODE, V, SET_OPCODE) \
/*fld m2;fld m1;xor %eax,%eax;fucomip st,st(1);fstp %st;mov V,%edx; \
set[n]p r0;cmovne %rdx,%rax;mov %rax,r0: */ \
{ICODE, "r mld mld", \
"DB /5 m2; DB /5 m1; 33 h0 H0; DF E9; DD D8; BA " V "; " SET_OPCODE \
" H0; X 0F 45 h0 H2; X 8B r0 H0"},
#define FCMP(ICODE, SET_OPCODE) \
/*xor %eax,%eax;ucomiss r1,r2;setx az; mov %rax,r0: */ \
{ICODE, "r r r", "33 h0 H0; Y 0F 2E r1 R2; " SET_OPCODE " H0;X 8B r0 H0"}, \
{ICODE, "r r mf", "33 h0 H0; Y 0F 2E r1 m2; " SET_OPCODE " H0;X 8B r0 H0"},
#define DCMP(ICODE, SET_OPCODE) \
/*xor %eax,%eax;ucomisd r1,r2;setx az; mov %rax,r0: */ \
{ICODE, "r r r", "33 h0 H0; 66 Y 0F 2F r1 R2; " SET_OPCODE " H0;X 8B r0 H0"}, \
{ICODE, "r r md", "33 h0 H0; 66 Y 0F 2F r1 m2; " SET_OPCODE " H0;X 8B r0 H0"},
#define LDCMP(ICODE, SET_OPCODE) \
/*fld m2;fld m1;xor %eax,%eax;fcomip st,st(1);fstp %st;setx az; mov %rax,r0: */ \
{ICODE, "r mld mld", "DB /5 m2; DB /5 m1; 33 h0 H0; DF F1; DD D8; " SET_OPCODE " H0;X 8B r0 H0"},
#define BR0(ICODE, SUFF, PREF, LONG_JMP_OPCODE) \
{ICODE##SUFF, "l r", #PREF " 83 /7 R1 v0;" LONG_JMP_OPCODE " l0"}, /*cmp r0,$0;jxx rel32*/ \
{ICODE##SUFF, "l m3", #PREF " 83 /7 m1 v0;" LONG_JMP_OPCODE " l0"}, /*cmp m0,$0;jxx rel8*/
#define BR(ICODE, LONG_JMP_OPCODE) \
BR0 (ICODE, , X, LONG_JMP_OPCODE) \
BR0 (ICODE, S, Y, LONG_JMP_OPCODE)
#define BCMP0(ICODE, SUFF, PREF, LONG_JMP_OPCODE) \
{ICODE##SUFF, "l r r", #PREF " 3B r1 R2;" LONG_JMP_OPCODE " l0"}, /*cmp r0,r1;jxx rel32*/ \
{ICODE##SUFF, "l r m3", #PREF " 3B r1 m2;" LONG_JMP_OPCODE " l0"}, /*cmp r0,m1;jxx rel8*/ \
{ICODE##SUFF, "l r i0", #PREF " 83 /7 R1 i2;" LONG_JMP_OPCODE " l0"}, /*cmp r0,i1;jxx rel32*/ \
{ICODE##SUFF, "l r i2", #PREF " 81 /7 R1 I2;" LONG_JMP_OPCODE " l0"}, /*cmp r0,i1;jxx rel32*/ \
{ICODE##SUFF, "l m3 i0", #PREF " 83 /7 m1 i2;" LONG_JMP_OPCODE " l0"}, /*cmp m0,i1;jxx rel32*/ \
{ICODE##SUFF, "l m3 i2", #PREF " 81 /7 m1 I2;" LONG_JMP_OPCODE " l0"}, /*cmp m0,i1;jxx rel32*/
#define BCMP(ICODE, LONG_JMP_OPCODE) \
BCMP0 (ICODE, , X, LONG_JMP_OPCODE) \
BCMP0 (ICODE, S, Y, LONG_JMP_OPCODE)
#define FBCMP(ICODE, LONG_JMP_OPCODE) \
{ICODE, "l r r", "Y 0F 2E r1 R2;" LONG_JMP_OPCODE " l0"}, /* ucomiss r0,r1;jxx rel32*/
#define DBCMP(ICODE, LONG_JMP_OPCODE) \
{ICODE, "l r r", "66 Y 0F 2E r1 R2;" LONG_JMP_OPCODE " l0"}, /* ucomisd r0,r1;jxx rel32*/
#define LDBCMP(ICODE, LONG_JMP_OPCODE) \
/* fld m2;fld m1; fcomip st,st(1); fstp st; jxx rel32*/ \
{ICODE, "l mld mld", "DB /5 m2; DB /5 m1; DF F1; DD D8; " LONG_JMP_OPCODE " l0"},
static const struct pattern patterns[] = {
{MIR_MOV, "r z", "Y 33 r0 R0"}, /* xor r0,r0 -- 32 bit xor */
{MIR_MOV, "r r", "X 8B r0 R1"}, /* mov r0,r1 */
{MIR_MOV, "r m3", "X 8B r0 m1"}, /* mov r0,m1 */
{MIR_MOV, "m3 r", "X 89 r1 m0"}, /* mov m0,r1 */
{MIR_MOV, "r i2", "X C7 /0 R0 I1"}, /* mov r0,i32 */
{MIR_MOV, "m3 i2", "X C7 /0 m0 I1"}, /* mov m0,i32 */
{MIR_MOV, "r i3", "X B8 +0 J1"}, /* mov r0,i64 */
{MIR_MOV, "r p", "X B8 +0 P1"}, /* mov r0,a64 */
{MIR_MOV, "m0 r", "Z 88 r1 m0"}, /* mov m0, r1 */
{MIR_MOV, "m1 r", "66 Y 89 r1 m0"}, /* mov m0, r1 */
{MIR_MOV, "m2 r", "Y 89 r1 m0"}, /* mov m0, r1 */
{MIR_MOV, "r ms0", "X 0F BE r0 m1"}, /* movsx r0, m1 */
{MIR_MOV, "r ms1", "X 0F BF r0 m1"}, /* movsx r0, m1 */
{MIR_MOV, "r ms2", "X 63 r0 m1"}, /* movsx r0, m1 */
{MIR_MOV, "r mu0", "X 0F B6 r0 m1"}, /* movzx r0, m1 */
{MIR_MOV, "r mu1", "X 0F B7 r0 m1"}, /* movzx r0, m1 */
{MIR_MOV, "r mu2", "8B r0 m1"}, /* mov r0, m1 */
{MIR_MOV, "m0 i0", "Y C6 /0 m0 i1"}, /* mov m0,i8 */
{MIR_MOV, "m2 i2", "Y C7 /0 m0 I1"}, /* mov m0,i32 */
{MIR_FMOV, "r r", "F3 Y 0F 10 r0 R1"}, /* movss r0,r1 */
{MIR_FMOV, "r mf", "F3 Y 0F 10 r0 m1"}, /* movss r0,m32 */
{MIR_FMOV, "mf r", "F3 Y 0F 11 r1 m0"}, /* movss r0,m32 */
{MIR_DMOV, "r r", "F2 Y 0F 10 r0 R1"}, /* movsd r0,r1 */
{MIR_DMOV, "r md", "F2 Y 0F 10 r0 m1"}, /* movsd r0,m64 */
{MIR_DMOV, "md r", "F2 Y 0F 11 r1 m0"}, /* movsd r0,m64 */
{MIR_LDMOV, "mld h32", "DB /7 m0"}, /*only for ret and calls in given order: fstp m0 */
{MIR_LDMOV, "h32 mld", "DB /5 m1"}, /*only for ret and calls in given order: fld m1 */
{MIR_LDMOV, "mld h33", "D9 C9; DB /7 m0"}, /*only for ret and calls: fxch;fstp m0 */
{MIR_LDMOV, "h33 mld", "DB /5 m1; D9 C9"}, /*only for ret and calls: fld m1; fxch */
{MIR_LDMOV, "mld mld", "DB /5 m1; DB /7 m0"}, /* fld m1; fstp m0 */
{MIR_EXT8, "r r", "X 0F BE r0 R1"}, /* movsx r0,r1 */
{MIR_EXT8, "r m0", "X 0F BE r0 m1"}, /* movsx r0,m1 */
{MIR_EXT16, "r r", "X 0F BF r0 R1"}, /* movsx r0,r1 */
{MIR_EXT16, "r m1", "X 0F BF r0 m1"}, /* movsx r0,m1 */
{MIR_EXT32, "r r", "X 63 r0 R1"}, /* movsx r0,r1 */
{MIR_EXT32, "r m2", "X 63 r0 m1"}, /* movsx r0,m1 */
{MIR_UEXT8, "r r", "X 0F B6 r0 R1"}, /* movzx r0,r1 */
{MIR_UEXT8, "r m0", "X 0F B6 r0 m1"}, /* movzx r0,m1 */
{MIR_UEXT16, "r r", "X 0F B7 r0 R1"}, /* movzx r0,r1 */
{MIR_UEXT16, "r m1", "X 0F B7 r0 m1"}, /* movzx r0,m1 */
{MIR_UEXT32, "r r", "Y 8B r0 R1"}, /* mov r0,r1 */
{MIR_UEXT32, "r m2", "Y 8B r0 m1"}, /* mov r0,m1 */
{MIR_I2F, "r r", "F3 X 0F 2A r0 R1"}, /* cvtsi2ss r0,r1 */
{MIR_I2F, "r mf", "F3 X 0F 2A r0 m1"}, /* cvtsi2ss r0,m1 */
{MIR_I2D, "r r", "F2 X 0F 2A r0 R1"}, /* cvtsi2sd r0,r1 */
{MIR_I2D, "r md", "F2 X 0F 2A r0 m1"}, /* cvtsi2sd r0,m1 */
{MIR_I2LD, "mld r", "X 89 r1 mt; DF /5 mt; DB /7 m0"}, /*mov -16(sp),r1;fild -16(sp);fstp m0 */
{MIR_F2I, "r r", "F3 X 0F 2C r0 R1"}, /* cvttss2si r0,r1 */
{MIR_F2I, "r mf", "F3 X 0F 2C r0 m1"}, /* cvttss2si r0,m1 */
{MIR_D2I, "r r", "F2 X 0F 2C r0 R1"}, /* cvttsd2si r0,r1 */
{MIR_D2I, "r md", "F2 X 0F 2C r0 m1"}, /* cvttsd2si r0,m1 */
{MIR_F2D, "r r", "F3 0F 5A r0 R1"}, /* cvtss2sd r0,r1 */
{MIR_F2D, "r mf", "F3 Y 0F 5A r0 m1"}, /* cvtss2sd r0,m1 */
/* fld m1;fstpl -16(sp);movsd r0,-16(sp): */
{MIR_LD2D, "r mld", "DB /5 m1; DD /3 mt; F2 Y 0F 10 r0 mt"},
{MIR_D2F, "r r", "F2 0F 5A r0 R1"}, /* cvtsd2ss r0,r1 */
{MIR_D2F, "r md", "F2 Y 0F 5A r0 m1"}, /* cvtsd2ss r0,m1 */