cts fails to build clock tree when clock is also an output port

[gadfort]

Describe the bug

In this design the clock is getting forwarded to an output port, ie. assign mclk = dco_clk
This causes openroad to put a buffer between the two ports, which appears to cause CTS to skip clock tree generation all together.

Expected Behavior

Build a clock tree on dco_clk

Environment

OpenROAD v2.0-17598-ga008522d8 
Features included (+) or not (-): +GPU +GUI +Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.

To Reproduce

https://drive.google.com/file/d/1GijuZkVXgaxFMtEAyJejZCT3I8CQEH9k/view?usp=sharing

tar xvf sc_issue_openmsp430_job0_cts.clock_tree_synthesis0_20241213-143445.tar.gz
cd sc_issue_openmsp430_job0_cts.clock_tree_synthesis0_20241213-143445
./run.sh

Relevant log output

[INFO CTS-0007] Net "dco_clk" found for clock "clk".
[WARNING CTS-0105] Net "dco_clk" already has clock buffer _12043_. Skipping...
[WARNING CTS-0105] Net "smclk" already has clock buffer _12043_. Skipping...
[WARNING CTS-0105] Net "mclk" already has clock buffer _12036_. Skipping...
[WARNING CTS-0105] Net "aclk" already has clock buffer _12029_. Skipping...
[WARNING CTS-0083] No clock nets have been found.
[INFO CTS-0008] TritonCTS found 0 clock nets.
[WARNING CTS-0082] No valid clock nets in the design.
[INFO RSZ-0058] Using max wire length 232um.

Screenshots

No response

Additional Context

No response