diff --git a/.doctrees/developer/arch/supported/aarch64.doctree b/.doctrees/developer/arch/supported/aarch64.doctree index 111d5ef396..4e80548e58 100644 Binary files a/.doctrees/developer/arch/supported/aarch64.doctree and b/.doctrees/developer/arch/supported/aarch64.doctree differ diff --git a/.doctrees/environment.pickle b/.doctrees/environment.pickle index 1d4af35c84..b7a7bb08bd 100644 Binary files a/.doctrees/environment.pickle and b/.doctrees/environment.pickle differ diff --git a/.doctrees/index.doctree b/.doctrees/index.doctree index 3d4d5340c1..e0037782d0 100644 Binary files a/.doctrees/index.doctree and b/.doctrees/index.doctree differ diff --git a/_downloads/modsim23_poster.pdf b/_downloads/modsim23_poster.pdf new file mode 100644 index 0000000000..1ee43e37cd Binary files /dev/null and b/_downloads/modsim23_poster.pdf differ diff --git a/_sources/developer/arch/supported/aarch64.rst.txt b/_sources/developer/arch/supported/aarch64.rst.txt index 8b64d38306..8754f35e74 100644 --- a/_sources/developer/arch/supported/aarch64.rst.txt +++ b/_sources/developer/arch/supported/aarch64.rst.txt @@ -211,9 +211,15 @@ Loads and stores In addition to an execution behaviour, memory instructions also require a new entry in the address generation behaviour table found in ``src/lib/arch/aarch64/Instruction_address.cc``. These entries are responsible for describing the method used to generate the addresses that these instructions will read from or write to. -Address generation is expected to generate one or more instances of ``MemoryAddressTarget``, containing an address and the number of bytes to access. The same variables described above (``operands``, ``metadata``) are available to use to generate these addresses. +Address generation is expected to generate one or more instances of ``MemoryAccessTarget``, containing an address and the number of bytes to access. The same variables described above (``operands``, ``metadata``) are available to use to generate these addresses. -Once the addresses have been generated, they should be supplied in a vector to the ``setMemoryAddresses`` helper function. +Once the addresses have been generated, they should be supplied in a vector to the ``setMemoryAddresses`` helper function. + +For loads, data can be read from the ``memoryData`` vector in ``Instruction_execute.cc``, with each index holding a ``RegisterValue`` for a corresponding ``MemoryAccessTarget``. For stores, a ``RegisterValue`` must be placed in each index of the ``memoryData`` vector, again one per ``MemoryAccessTarget`` generated. + +To best match modelled hardware, contiguous Load and Store instructions use one ``MemoryAccessTarget`` per destination/source register. For NEON instructions this should always be the case, including interleaved multi-structure loads / stores. + +Concerning SVE & SME loads and stores, an effort should be made to merge contiguous active elements into as few ``MemoryAccessTarget``'s as possible by evaluating the predicate information (if applicable). Helper functions ``sve_merge_store_data`` and ``generatePredicatedContiguousAddressBlocks`` can be used to support this. Instruction aliases diff --git a/_sources/index.rst.txt b/_sources/index.rst.txt index 263d95ed93..c697b0e95b 100644 --- a/_sources/index.rst.txt +++ b/_sources/index.rst.txt @@ -70,6 +70,7 @@ SimEng was first presented by `Professor Simon McIntosh-Smith ` - ModSim 2022 - :download:`A design space exploration for optimal vector unit composition ` - :download:`Modelling Advanced Arm-based CPUs with SimEng ` diff --git a/_static/pygments.css b/_static/pygments.css index 08bec689d3..84ab3030a9 100644 --- a/_static/pygments.css +++ b/_static/pygments.css @@ -17,6 +17,7 @@ span.linenos.special { color: #000000; background-color: #ffffc0; padding-left: .highlight .cs { color: #3D7B7B; font-style: italic } /* Comment.Special */ .highlight .gd { color: #A00000 } /* Generic.Deleted */ .highlight .ge { font-style: italic } /* Generic.Emph */ +.highlight .ges { font-weight: bold; font-style: italic } /* Generic.EmphStrong */ .highlight .gr { color: #E40000 } /* Generic.Error */ .highlight .gh { color: #000080; font-weight: bold } /* Generic.Heading */ .highlight .gi { color: #008400 } /* Generic.Inserted */ diff --git a/developer/arch/supported/aarch64.html b/developer/arch/supported/aarch64.html index 7d8a238768..c79575d5b4 100644 --- a/developer/arch/supported/aarch64.html +++ b/developer/arch/supported/aarch64.html @@ -420,8 +420,11 @@

Zero registers

Loads and stores

In addition to an execution behaviour, memory instructions also require a new entry in the address generation behaviour table found in src/lib/arch/aarch64/Instruction_address.cc. These entries are responsible for describing the method used to generate the addresses that these instructions will read from or write to.

-

Address generation is expected to generate one or more instances of MemoryAddressTarget, containing an address and the number of bytes to access. The same variables described above (operands, metadata) are available to use to generate these addresses.

+

Address generation is expected to generate one or more instances of MemoryAccessTarget, containing an address and the number of bytes to access. The same variables described above (operands, metadata) are available to use to generate these addresses.

Once the addresses have been generated, they should be supplied in a vector to the setMemoryAddresses helper function.

+

For loads, data can be read from the memoryData vector in Instruction_execute.cc, with each index holding a RegisterValue for a corresponding MemoryAccessTarget. For stores, a RegisterValue must be placed in each index of the memoryData vector, again one per MemoryAccessTarget generated.

+

To best match modelled hardware, contiguous Load and Store instructions use one MemoryAccessTarget per destination/source register. For NEON instructions this should always be the case, including interleaved multi-structure loads / stores.

+

Concerning SVE & SME loads and stores, an effort should be made to merge contiguous active elements into as few MemoryAccessTarget’s as possible by evaluating the predicate information (if applicable). Helper functions sve_merge_store_data and generatePredicatedContiguousAddressBlocks can be used to support this.

Instruction aliases

diff --git a/index.html b/index.html index e994425481..d50d08c22f 100644 --- a/index.html +++ b/index.html @@ -217,6 +217,7 @@

Talks and presentations

Additionally, other works concerning SimEng and its use can be found below:

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