Unimplemented tricore EXTR.U using extended register

[emesare]

Need to implement the EXTR.U using extended register.

even register: pos
odd register: width

Same semantics otherwise.

Instruction dump:

Instruction {
    address: 2149729656,
    format: Rrrr,
    operation: Extr,
    operation_modifiers: [],
    data_type_modifiers: [
        Unsigned,
    ],
    operands: [
        Operand {
            usage: Source,
            variant: Register(
                Data(
                    D8,
                ),
            ),
        },
        Operand {
            usage: Source,
            variant: Register(
                Unused,
            ),
        },
        Operand {
            usage: Source,
            variant: Register(
                ExtendedData(
                    ExtendedRegister {
                        even: D14,
                        odd: D15,
                    },
                ),
            ),
        },
        Operand {
            usage: Destination,
            variant: Register(
                Data(
                    D3,
                ),
            ),
        },
    ],
    addressing_mode: None,
}