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Flexible vectors: Tracking issue for feedback after CG presentation #60

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dtig opened this issue Jun 20, 2023 · 5 comments
Open

Flexible vectors: Tracking issue for feedback after CG presentation #60

dtig opened this issue Jun 20, 2023 · 5 comments

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@dtig
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dtig commented Jun 20, 2023

The flexible vectors proposal was presented today (notes will be uploaded after a couple days of lead time, to be linked here after), with a poll for Phase 2. The poll was inconclusive, but we ran out of time in the meeting to address concrete next steps, filing this issue as a tracker to collect feedback, action items if any.

One thing that that would be useful, would be to have example code, and what the resulting codegen would be on popular architectures (potentially with edge cases for when length checks and/or bounds checks are included). Please add other items or data points folks would find useful.

cc: @conrad-watt, @dschuff, @rossberg

@penzn
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penzn commented Jul 13, 2023

Sorry for taking this long to response :)

Completely agree with your suggestions, I should have probably added that to the presentation. Trying to schedule a slot to present this follow up.

@penzn
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penzn commented Aug 16, 2023

I've presented an update on 2023-08-01, mostly focused on theoretical speedups for existing application classes.

Should we go forward with a vote or a little more data is better (can be combined)?

@dtig you had a question about APX or AMX (I think) that I didn't get to in the meeting

CC @ngzhian @Maratyszcza @conrad-watt @justinmichaud

@jan-wassenberg
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Great to see this making progress. I regularly see 1.3x or more speedups from 256-bit AVX2 vs 128-bit, including in libjpeg-turbo. It seems very worthwhile to have wider vectors in WASM.

@akirilov-arm
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Is there a place where the collection of code generation samples for the operations that are currently defined by the proposal would be hosted? I would be quite happy to contribute examples for the 64-bit Arm architecture, and in fact I have already written down (non-public) examples that cover a significant part of the proposal.

Also, my assumption is that if someone would like to implement the proposal today (even though it is not in phase 3 yet), then they would just need to cover the first tier operations (Maybe the second one as well?), and could ignore the rest. Is that correct?

@penzn
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penzn commented Oct 20, 2023

I would be quite happy to contribute examples for the 64-bit Arm architecture, and in fact I have already written down (non-public) examples that cover a significant part of the proposal.

@akirilov-arm that is great news! @talg and myself are so far trying to put together a CG presentation on the subject, but we haven't thought of official place to host these. So far Wasm SIMD has avoided doing that, but it might not be such a bad idea. I'd suggest we plan and subgroup meeting and decide how we can organize this.

Also, my assumption is that if someone would like to implement the proposal today (even though it is not in phase 3 yet), then they would just need to cover the first tier operations (Maybe the second one as well?), and could ignore the rest. Is that correct?

Correct, Tier 1 is "MVP", if something in Tier 2 (or even 3, though I won't hold my breath) looks very appealing we will move it to Tier 1.

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