diff --git a/run-docker.sh b/run-docker.sh index 88fabff2fa..d7785fe9a7 100755 --- a/run-docker.sh +++ b/run-docker.sh @@ -139,6 +139,7 @@ elif [ "$1" = "build_custom" ]; then BUILD_CUSTOM_DIR=$(readlink -f "$2") FLOW_NAME=${3:-build} FINN_DOCKER_EXTRA+="-v $BUILD_CUSTOM_DIR:$BUILD_CUSTOM_DIR -w $BUILD_CUSTOM_DIR " + FINN_DOCKER_EXTRA+="-v $BUILD_CUSTOM_DIR/../../ci:$BUILD_CUSTOM_DIR/../../ci " DOCKER_INTERACTIVE="-it" #FINN_HOST_BUILD_DIR=$BUILD_DATAFLOW_DIR/build gecho "Running build_custom: $BUILD_CUSTOM_DIR/$FLOW_NAME.py" @@ -214,6 +215,7 @@ DOCKER_EXEC+="-v $SCRIPTPATH:$SCRIPTPATH " DOCKER_EXEC+="-v $FINN_HOST_BUILD_DIR:$FINN_HOST_BUILD_DIR " DOCKER_EXEC+="-e FINN_BUILD_DIR=$FINN_HOST_BUILD_DIR " DOCKER_EXEC+="-e FINN_ROOT="$SCRIPTPATH" " +DOCKER_EXEC+="-e VERIFICATION_EN=$VERIFICATION_EN " DOCKER_EXEC+="-e LOCALHOST_URL=$LOCALHOST_URL " DOCKER_EXEC+="-e VIVADO_IP_CACHE=$VIVADO_IP_CACHE " DOCKER_EXEC+="-e PYNQ_BOARD=$PYNQ_BOARD " diff --git a/src/finn/builder/build_dataflow_config.py b/src/finn/builder/build_dataflow_config.py index e35c1cd346..5d69802337 100644 --- a/src/finn/builder/build_dataflow_config.py +++ b/src/finn/builder/build_dataflow_config.py @@ -96,6 +96,8 @@ class VerificationStepType(str, Enum): STREAMLINED_PYTHON = "streamlined_python" #: verify after step_apply_folding_config, using C++ for each HLS node FOLDED_HLS_CPPSIM = "folded_hls_cppsim" + #: verify after step_hw_ipgen + NODE_BY_NODE_RTLSIM = "node_by_node_rtlsim" #: verify after step_create_stitched_ip, using stitched-ip Verilog STITCHED_IP_RTLSIM = "stitched_ip_rtlsim" diff --git a/src/finn/builder/build_dataflow_steps.py b/src/finn/builder/build_dataflow_steps.py index e202a74956..b8ed8daec7 100644 --- a/src/finn/builder/build_dataflow_steps.py +++ b/src/finn/builder/build_dataflow_steps.py @@ -527,6 +527,11 @@ def step_hw_ipgen(model: ModelWrapper, cfg: DataflowBuildConfig): estimate_layer_resources_hls = model.analysis(hls_synth_res_estimation) with open(report_dir + "/estimate_layer_resources_hls.json", "w") as f: json.dump(estimate_layer_resources_hls, f, indent=2) + + if VerificationStepType.NODE_BY_NODE_RTLSIM in cfg._resolve_verification_steps(): + model = model.transform(PrepareRTLSim()) + model = model.transform(SetExecMode("rtlsim")) + verify_step(model, cfg, "node_by_node_rtlsim", need_parent=True) return model