A question about extractSitePins (in nxroute-poc.py)

[xxccxcxc]

In rosetta_fd_unrouted.phys, net 125669 has a route segment that connects "SLICE_X162Y295 / D6" via a few BELs to "SLICE_X162Y295 / D_O".

The extractSitePins function seems extract both site pins ("SLICE_X162Y295 / D6" and "SLICE_X162Y295 / D_O"). Should we only need to find a route from the source to "SLICE_X162Y295 / D6" in the FPGA'24 contest?

The decoded physical netlist is attached below:

( part = "xcvu3p-ffvc1517-3-e",
  ...,
  physNets = [
    ...,
    ( name = 125669,
      sources = [ ... ],
      stubs = [
        ( routeSegment = (
            sitePin = (site = 7938, pin = 110938) ),
          branches = [
            ( routeSegment = (
                belPin = (site = 7938, bel = 110938, pin = 110938) ),
              branches = [
                ( routeSegment = (
                    belPin = (site = 7938, bel = 9360, pin = 9274) ),
                  branches = [
                    ( routeSegment = (
                        belPin = (site = 7938, bel = 9360, pin = 9259) ),
                      branches = [
                        ( routeSegment = (
                            belPin = (site = 7938, bel = 9276, pin = 9278) ) ),
                        ( routeSegment = (
                            belPin = (site = 7938, bel = 111003, pin = 111003) ),
                          branches = [
                            ( routeSegment = (
                                sitePin = (site = 7938, pin = 111003) ) ) ] ) ] ) ] ) ] ) ] ),
        ... ],
      type = signal ),
      ... ],
  ...
  strList = [
    ...
    "SLICE_X162Y295",  # 7938
    ...
    "D6",  # 110938
    ...
    "D_O",  # 111003
    ...
    "grp_processImage_fu_310/dmul_64ns_64ns_64_3_max_dsp_1_U757/face_detect_dmul_64ns_64ns_64_3_max_dsp_1_ip_u/inst/i_synth/MULT.OP/i_non_prim.EXP/EXP_ADD.C_CHAIN/A[3]",  # 125669
    ... ],
  ...
)

[eddieh-xlnx]

Hi @xxccxcxc, thanks for posting!

Firstly, are you aware of our net_printer utility? Using it on the net in question gives us this output:

$ python3 net_printer/np.py rosetta_fd_unrouted.phys grp_processImage_fu_310/dmul_64ns_64ns_64_3_max_dsp_1_U757/face_detect_dmul_64ns_64ns_64_3_max_dsp_1_ip_u/inst/i_synth/MULT.OP/i_non_prim.EXP/EXP_ADD.C_CHAIN/A[3]
============================================================
Route tree for net: grp_processImage_fu_310/dmul_64ns_64ns_64_3_max_dsp_1_U757/face_detect_dmul_64ns_64ns_64_3_max_dsp_1_ip_u/inst/i_synth/MULT.OP/i_non_prim.EXP/EXP_ADD.C_CHAIN/A[3]

    Source: 0
    [{      belPin  SLICE_X160Y296 CARRY8 O3
            belPin  SLICE_X160Y296 OUTMUXD XORIN
            sitePIP SLICE_X160Y296 OUTMUXD XORIN False
            belPin  SLICE_X160Y296 OUTMUXD OUT
            belPin  SLICE_X160Y296 DMUX DMUX
         }] sitePin SLICE_X160Y296 DMUX

    Stub: 0
    [{      sitePin SLICE_X162Y295 D6
            belPin  SLICE_X162Y295 D6 D6
            belPin  SLICE_X162Y295 D6LUT A6
            belPin  SLICE_X162Y295 D6LUT O6
     {      belPin  SLICE_X162Y295 D_O D_O
         }  sitePin SLICE_X162Y295 D_O
         }] belPin  SLICE_X162Y295 CARRY8 S3

    Stub: 1
    [{      sitePin SLICE_X163Y295 D6
            belPin  SLICE_X163Y295 D6 D6
            belPin  SLICE_X163Y295 D6LUT A6
            belPin  SLICE_X163Y295 D6LUT O6
     {   }  belPin  SLICE_X163Y295 D_O D_O
         }] belPin  SLICE_X163Y295 CARRY8 S3

    Stub: 2
    [{      sitePin SLICE_X162Y298 E1
            belPin  SLICE_X162Y298 E1 E1
         }] belPin  SLICE_X162Y298 E6LUT A1

    Stub: 3
    [{      sitePin SLICE_X162Y298 F2
            belPin  SLICE_X162Y298 F2 F2
         }] belPin  SLICE_X162Y298 F6LUT A2
============================================================

Stub 0 exhibits what you're describing where D6 is the input site pin, but it also contains the D_O output site pin. Stub 1 looks like it's almost the same, but for some reason D_O is not marked as a site pin there.

To your original question, for stub 0, the output D_O site pin can be safely ignored. There is no routing needing to be done from stubs, and the existence of this site pin is an artifact of the need to route-through the LUT in order to reach the CARRY8 carry chain.

Let me update this thread once I've looked into why Stub 0 has a site pin and Stub 1 doesn't.

[eddieh-xlnx]

The situation with Stub 0 is shown in the Vivado Device view here:

where the net comes in from D6 and routes thru the LUT in order to get to the D_O sitewire that connects to CARRY8.S3. That same sitewire also services the D_O output site pin, which gets inadvertently picked up.

For Stub 1, the same situation exists:

(slightly different image because SLICE_X163Y295 is a SLICEM whereas SLICE_X162Y295 is a SLICEL) but because it was trying to add a third source pin to the net, and that third source pin was being (rightly or wrongly) silently dropped by RapidWright.

[eddieh-xlnx]

Using the proposed fix in Xilinx/RapidWright#936 to re-generate the benchmark netlists, the net_printer output is now:

$ python3 net_printer/np.py rosetta_fd_unrouted.phys grp_processImage_fu_310/dmul_64ns_64ns_64_3_max_dsp_1_U757/face_detect_dmul_64ns_64ns_64_3_max_dsp_1_ip_u/inst/i_synth/MULT.OP/i_non_prim.EXP/EXP_ADD.C_CHAIN/A[3]
============================================================
Route tree for net: grp_processImage_fu_310/dmul_64ns_64ns_64_3_max_dsp_1_U757/face_detect_dmul_64ns_64ns_64_3_max_dsp_1_ip_u/inst/i_synth/MULT.OP/i_non_prim.EXP/EXP_ADD.C_CHAIN/A[3]

    Source: 0
    [{      belPin  SLICE_X160Y296 CARRY8 O3
            belPin  SLICE_X160Y296 OUTMUXD XORIN
            sitePIP SLICE_X160Y296 OUTMUXD XORIN False
            belPin  SLICE_X160Y296 OUTMUXD OUT
            belPin  SLICE_X160Y296 DMUX DMUX
         }] sitePin SLICE_X160Y296 DMUX

    Stub: 0
    [{      sitePin SLICE_X162Y295 D6
            belPin  SLICE_X162Y295 D6 D6
            belPin  SLICE_X162Y295 D6LUT A6
            belPin  SLICE_X162Y295 D6LUT O6
         }] belPin  SLICE_X162Y295 CARRY8 S3

    Stub: 1
    [{      sitePin SLICE_X163Y295 D6
            belPin  SLICE_X163Y295 D6 D6
            belPin  SLICE_X163Y295 D6LUT A6
            belPin  SLICE_X163Y295 D6LUT O6
         }] belPin  SLICE_X163Y295 CARRY8 S3

    Stub: 2
    [{      sitePin SLICE_X162Y298 F2
            belPin  SLICE_X162Y298 F2 F2
         }] belPin  SLICE_X162Y298 F6LUT A2

    Stub: 3
    [{      sitePin SLICE_X162Y298 E1
            belPin  SLICE_X162Y298 E1 E1
         }] belPin  SLICE_X162Y298 E6LUT A1
============================================================

which looks a lot more correct!

[eddieh-xlnx]

Benchmarks released as part of v1.5.1 now contains this fix. Thanks for bringing it to my attention!