[destination] ← <literal> + [destination]
ORI #<data>,<ea>Size byte, word, longword
OR the immediate data with the destination operand. Store the result in the destination operand.
| X | N | Z | V | C |
|---|---|---|---|---|
| - | * | * | 0 | 0 |
ORI forms the logical OR of the immediate source with the effective address, which may be a memory location. For example,
ORI.B #%00000011,(A0)+
| Dn | An | (An) | (An)+ | ‑(An) | (d,An) | (d,An,Xi) | ABS.W | ABS.L | (d,PC) | (d,PC,Xn) | imm |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
[CCR] ← <literal> + [CCR]
ORI #<data>,CCRSize byte
OR the immediate data with the condition code register (i.e., the least-significant byte of the status register). For example, the Z flag of the CCR can be set by ORI #$04,CCR.
| X | N | Z | V | C |
|---|---|---|---|---|
| * | * | * | * | * |
X is set if bit 4 of data = 1; unchanged otherwise
N is set if bit 3 of data = 1; unchanged otherwise
Z is set if bit 2 of data = 1; unchanged otherwise
V is set if bit 1 of data = 1; unchanged otherwise
C is set if bit 0 of data = 1; unchanged otherwise
IF [S] = 1
THEN
[SR] ← <literal> + [SR]
ELSE TRAP
ORI #<data>,SRSize word
OR the immediate data to the status register and store the result in the status register. All bits of the status register are affected.
Used to set bits in the SR (i.e., the S, T, and interrupt mask bits). For example, ORI #$8000,SR sets bit 15 of the SR (i.e., the trace bit).
| X | N | Z | V | C |
|---|---|---|---|---|
| * | * | * | * | * |
X is set if bit 4 of data = 1; unchanged otherwise
N is set if bit 3 of data = 1; unchanged otherwise
Z is set if bit 2 of data = 1; unchanged otherwise
V is set if bit 1 of data = 1; unchanged otherwise
C is set if bit 0 of data = 1; unchanged otherwise
From MOTOROLA M68000 FAMILY Programmer's reference manual. Copyright 1992 by Motorola Inc./NXP. Adapted with permission.