lwuib.adoc

th.lwuib

Synopsis

Load indexed unsigned word, increment address before loading.

Mnemonic

th.lwuib rd, (rs1), imm5, imm2

Encoding

{reg:[
    { bits:  7, name: 0xb, attr: ['custom-0, 32 bit'] },
    { bits:  5, name: 'rd' },
    { bits:  3, name: 0x4, attr: ['Mem-Load'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 'imm5' },
    { bits:  2, name: 'imm2' },
    { bits:  5, name: 0x19 },
]}

Description

This instruction increments the value in rs1 by (sign_extend(imm5) << imm2) and writes the result back to rs1. After the increment of rs1, this instruction loads a zero extended 32-bit value into the GP register rd from the (incremented) address rs1.

The encoding of this instruction with equal rd and rs1 is reserved.

Operation

if (rs1 != rd) {
    rs1 := rs1 + (sign_extend(imm5) << imm2)
    rd := zero_extend(mem[rs1+3:rs1])
}

Permission

This instruction can be executed in all privilege levels.

Exceptions

This instruction triggers the same exceptions that a corresponding LWU instruction would trigger.

Included in

Extension
XTheadMemIdx ([xtheadmemidx])