notes

uart is a 16550 like

CPU

- Cortex-A53 (used in RPI 3)
- 4 cores
- 512 KB L2-cache

gic-400 interrupt controller
GIC			0x01C80000
	GICD_ + 0x1000
	GICC_ + 0x2000
	

Memory mapping: a64man.pdf!73
0x01c00000 - 0x01f04000

all "module registers" are mapped in memory
SDRAM is the last "register" with 3GB


bootloader: DRAM clock freq 528

Booting:
fatload mmc 0 0x60000000 9pinephone
go 0x60000000


MMAP:

0x5f80 0000 	KZERO (KTZERO-0x800000)
0x6000 0000 	KTZERO


KZERO:
0x0000 0000 	Machs

ddr starts at 0x40000000
2gb goes to 0xC0000000



delay chain
			phy-mode = "rgmii";
			tx-delay = <0x3>;
			rx-delay = <0x0>;


old mmu meminit
I really would like something 
better for uncached ram
	pa = PGROUND((uintptr)end)-KZERO;
	for(i=0; i<nelem(conf.mem); i++){
		if(conf.mem[i].limit >= KMAPEND-KMAP)
			conf.mem[i].limit = KMAPEND-KMAP;

		if(conf.mem[i].limit <= conf.mem[i].base){
			conf.mem[i].limit = conf.mem[i].base = 0;
			continue;
		}

		if(conf.mem[i].base < PHYSDRAM + DRAMSIZE
		&& conf.mem[i].limit > PHYSDRAM + DRAMSIZE)
			conf.mem[i].limit = PHYSDRAM + DRAMSIZE;

		/* take kernel out of allocatable space */
		if(pa > conf.mem[i].base && pa < conf.mem[i].limit)
			conf.mem[i].base = pa;

		kmapram(conf.mem[i].base, conf.mem[i].limit);
	}

new mmu meminit,
seems to cause ilock issues
	conf.mem[0].base = PGROUND((uintptr)end - KZERO);

	/* exclude uncached dram for ucalloc() */
	conf.mem[0].limit = UCRAMBASE;
	conf.mem[1].base = UCRAMBASE+UCRAMSIZE;

	conf.mem[1].limit = PHYSDRAM + DRAMSIZE;

	kmapram(conf.mem[0].base, conf.mem[0].limit);
	kmapram(conf.mem[1].base, conf.mem[1].limit);

	conf.mem[0].npage = (conf.mem[0].limit - conf.mem[0].base)/BY2PG;
	conf.mem[1].npage = (conf.mem[1].limit - conf.mem[1].base)/BY2PG;

enum {
	Phyidr1		= 0x02,		/* PHY Identifier #1 */
	Phyidr2		= 0x03,		/* PHY Identifier #2 */
};


mw.b 0x40010000 0x0 0x10000; load usb 0 0x40010000 plan9.ini; load usb 0 0x40080000 9pine64; go 0x40080000