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mem_file.do
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_top_level/test_bench_state_machine
add wave -noupdate /tb_top_level/test_bench_state_machine
add wave -noupdate -divider {New Divider}
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineDecode/alu_opcode_i
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/instr_opcode_re
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/next_pc_out
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/next_pc_i
add wave -noupdate /tb_top_level/uGPGPU/shmem_size
add wave -noupdate -divider {New Divider}
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/read_data_o
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uGlobalMemory/addr_a
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uGlobalMemory/dout_a
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uGlobalMemory/addr_b
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uGlobalMemory/din_b
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uGlobalMemory/dout_b
add wave -noupdate /tb_top_level/uGPGPU/uGlobalMemory/we_b
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineDecode/src1_i
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineDecode/src2_i
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uSystemMemoryController/mem_data_in_a
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uSystemMemoryController/mem_data_out_a
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uSystemMemoryController/mem_addr_in_a
add wave -noupdate /tb_top_level/uGPGPU/uSystemMemoryController/mem_wr_en_a
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uSharedMemory/mem
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineDecode/dest_out
add wave -noupdate -radix hexadecimal -childformat {{/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(63) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(62) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(61) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(60) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(59) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(58) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(57) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(56) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(55) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(54) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(53) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(52) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(51) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(50) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(49) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(48) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(47) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(46) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(45) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(44) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(43) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(42) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(41) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(40) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(39) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(38) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(37) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(36) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(35) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(34) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(33) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(32) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(31) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(30) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(29) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(28) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(27) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(26) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(25) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(24) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(23) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(22) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(21) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(20) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(19) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(18) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(17) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(16) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(15) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(14) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(13) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(12) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(11) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(10) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(9) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(8) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(7) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(6) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(5) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(4) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(3) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(2) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(1) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(0) -radix hexadecimal}} -radixshowbase 0 -subitemconfig {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(63) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(62) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(61) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(60) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(59) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(58) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(57) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(56) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(55) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(54) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(53) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(52) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(51) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(50) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(49) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(48) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(47) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(46) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(45) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(44) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(43) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(42) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(41) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(40) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(39) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(38) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(37) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(36) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(35) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(34) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(33) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(32) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(31) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(30) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(29) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(28) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(27) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(26) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(25) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(24) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(23) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(22) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(21) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(20) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(19) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(18) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(17) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(16) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(15) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(14) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(13) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(12) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(11) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(10) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(9) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(8) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(7) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(6) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(5) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(4) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(3) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(2) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(1) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out(0) {-height 15 -radix hexadecimal -radixshowbase 0}} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineFetch/instruction_out
add wave -noupdate -divider {shared mem}
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/uMemoryController/mem_rd_data_in
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/uMemoryController/mem_rd_data_out
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_wr_done_o
add wave -noupdate -radix hexadecimal -childformat {{/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(31) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(30) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(29) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(28) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(27) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(26) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(25) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(24) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(23) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(22) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(21) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(20) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(19) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(18) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(17) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(16) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(15) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(14) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(13) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(12) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(11) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(10) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineRead/uSharedMemoryController/shmem_rd_data_o(9) -radix hexadecimal} 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add wave -noupdate -radix hexadecimal -childformat {{/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(7) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(6) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(5) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(4) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(3) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(2) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(1) -radix hexadecimal} {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(0) -radix hexadecimal}} -radixshowbase 0 -expand -subitemconfig {/tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(7) {-radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(6) {-radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(5) {-radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(4) {-radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(3) {-radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(2) {-radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(1) {-radix hexadecimal -radixshowbase 0} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i(0) {-radix hexadecimal -radixshowbase 0}} /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/src2_i
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/uGPGPU/uStreamingMultiProcessor/uPipelineExecute/gScalarProcessor(0)/uScalarProcessor/result_out
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add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/kernel_block_y
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/kernel_block_z
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/kernel_grid_x
add wave -noupdate -radix hexadecimal -radixshowbase 0 /tb_top_level/kernel_grid_y
add wave -noupdate -radix hexadecimal -childformat {{/tb_top_level/blocks_per_core(3) -radix hexadecimal} {/tb_top_level/blocks_per_core(2) -radix hexadecimal} {/tb_top_level/blocks_per_core(1) -radix hexadecimal} {/tb_top_level/blocks_per_core(0) -radix hexadecimal}} -radixshowbase 0 -subitemconfig {/tb_top_level/blocks_per_core(3) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/blocks_per_core(2) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/blocks_per_core(1) {-height 15 -radix hexadecimal -radixshowbase 0} /tb_top_level/blocks_per_core(0) {-height 15 -radix hexadecimal -radixshowbase 0}} /tb_top_level/blocks_per_core
add wave -noupdate -radix decimal -radixshowbase 0 /tb_top_level/uGPGPU/uStreamingMultiProcessor/threads_per_block_in
add wave -noupdate /tb_top_level/kernel_done
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uWarpUnit/shared_mem_base_addr_in
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uWarpUnit/program_cntr_out
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uWarpUnit/pipeline_stall_out
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uWarpUnit/pipeline_stall_in
add wave -noupdate /tb_top_level/uGPGPU/uStreamingMultiProcessor/uWarpUnit/pipeline_write_done
TreeUpdate [SetDefaultTree]
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update
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