From 98eb09644664157a6c57e50e432c76a1e0ee7b76 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 16 Aug 2023 10:50:16 +0100 Subject: [PATCH 01/45] Add second verion of glossary documentation --- docs/glossary.rst | 213 ++++++++++++++++++++++++++++++++++++++++++++++ docs/index.rst | 1 + 2 files changed, 214 insertions(+) create mode 100644 docs/glossary.rst diff --git a/docs/glossary.rst b/docs/glossary.rst new file mode 100644 index 000000000..2f01b91d6 --- /dev/null +++ b/docs/glossary.rst @@ -0,0 +1,213 @@ +Glossary +======== + +**Amaranth** + +| An open-source toolchain that uses the Python programming language. +| Amaranth makes developing hardware definitions, based on synchronous + digital logic, more intuitive by using the popular Python programming + language. The toolchain consists of the Amaranth language, the + standard library, the simulator, and the build system, covering all + steps of a typical FPGA development workflow. + +**ASIC (Application-specific integrated circuit)** + +| A non-standard integrated circuit chip made for a specific task or + product. +| The term *application* refers to the function the circuit will + perform, not to a software application. +| ASICs can be configured to be more power efficient and have better + performance than an off-the-shelf general purpose integrated circuit. + However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive + to produce so design and testing are critical to the success of ASIC + development. +| Rather than designing and building them from the ground up, ASICs can + be created by interconnecting functional components from cell + libraries. The resulting system can then be verified via simulation. + +**CLB (Configurable logic block)** + +| The basic repeating logic block on an FPGA, the purpose of CLBs is to + implement combinational and sequential logic on an FPGA. +| Each FPGA contains many logic blocks that are surrounded by a system + of programmable interconnects (I/O blocks), called a fabric, that + routes signals between the CLBs. +| The three essential components of a logic block are flip-flops, LUTs, + and multiplexers. + +**Clock signal** + +| An electronic logic signal that oscillates between a high and a low + state at a constant frequency, used to synchronise the actions of + digital circuits +| The clock signal enters the FPGA system through a single physical + connecting pin and is responsible for the speed at which an FPGA can + run and process data. +| A wave at a particular frequency is distributed across the FPGA to + produce a synchronised response from all the flip-flops in the design. + Performance of the system will be affected if the flip-flops do not + all receive the clock signal at the same time. It’s possible to use + more than one clock in an FPGA design but it is complicated and + requires a degree of skill in circuit design. + +**DUT (Device under test)** + +| A manufactured device that is being tested for performance and + proficiency. +| The device fails testing as soon the first out-of-tolerance value is + identified. The aim is to ensure damaged devices don’t enter the + market. + +**Finite state machine** + +| A mathematical model describing a system with a limited number of + conditional states of being. +| A finite state machine reads a series of inputs. For each input, it + will transition to a different state. Each state specifies which state + to transition to next, for the given input. When the processing is + complete, a ‘then’ action is taken. The abstract machine can process + only one state at a time. +| This approach enables engineers to study and test each input and + output scenario. + +**Flip-flop** + +| The basic memory element for storing a single bit of information. +| An edge-triggered device, it reacts to the edge of a pulse. Flip-flops + synchronise logic and save logical states between clock cycles within + an FPGA circuit. On every rising or falling clock edge, a flip-flop + latches the 1 or 0 (TRUE or FALSE) value on its input and holds that + value constant until the next clock edge. + +**FPGA (Field Programmable Gate Array)** + +| A reconfigurable integrated circuit containing internal hardware + blocks with user-programmable interconnects to create a customised + application. +| The device’s physical attributes are programmed using a hardware + definition language. I /O blocks interface between the FPGA and + external devices. +| FPGAs combine speed, programmability, and flexibility: FPGAs don't + jump between memory and programming in the way ASICSs and CPUs do, so + storing and retrieving data is more efficient. In addition, they can + process very large volumes of data by duplicating circuits and running + them in parallel. + +**Hardware register** + +| Circuits, typically composed of flip flops, often with characteristics + similar to memory and having additional hardware-related functions. +| Hardware registers are used in the interface between software and + peripherals. + +**HDL (Hardware description language)** + +| Hardware description languages describe the structure, behaviour, and + timing of electronic circuits and digital logic circuits. +| HDLs describe behavioural, register transfer, gate, and switch-level + logic. Behavioural level logic enables the sequential execution of + instructions; and register transfer logic enables the transfer of data + between registers. These actions are driven by an explicit clock and + gate level logic that defines the individual gate level logic. HDLs + can also be used to simulate a circuit and verify its response. + +**IC (Integrated circuit)** + +| An integrated circuit is a computer chip that has an electronic + circuit embedded in it. +| The circuit is a small wafer, usually made of silicon, that can hold + anywhere from hundreds to millions of transistors, resistors, and + capacitors. These components can perform calculations and store data + using either digital or analog technology. +| Digital ICs use logic gates that work only with values of 1s and 0s. A + low signal sent to a component on a digital IC will result in a value + of 0, while a high signal creates a value of 1. + +**Logic gate** + +| An elementary building block of integrated circuits, logic gates + perform logical operations on binary inputs and outputs. +| Based on a Boolean function that computes TRUE or FALSE, each output + is based on the input or combination of inputs supplied to it. +| **LUT (Look up table)** + +| An elementary building block of integrated circuits, a LUT is a truth + table that defines how combinatorial logic behaves: the output for + every combination of inputs. +| The computation is very fast because the function requires only a + single memory lookup regardless of the complexity of the function. + +**MCU (Microcontroller unit)** + +| A compact integrated circuit designed to govern a specific operation + in an embedded system. +| An MCU typically comprises a processor unit, memory modules, + communication interfaces, and peripherals. + +**Multiplexer** + +| A combinational logic circuit designed to switch one of several inputs + through to a single common output by the application of a control + signal. +| A multiplexer makes it possible for several input signals to share one + device or resource instead of having one device per input signal. They + use high speed logic gates to switch digital or binary data through to + a single output. + +**Propagation delay** + +| The time required to change the output from one logic state to another + logic state after input is applied. +| In simplified terms, the time it takes for a signal to move from + source to destination. The timing begins when the input to a logic + gate becomes stable and valid to change and ends when the output of + that logic gate is stable and valid to change. +| The propagation delay of a complete circuit is calculated by + identifying the longest path of propagation delay from input to output + and adding each propagation delay along the path. + +**RTL (Register transfer level)** + +| RTL is used to create high-level representations of a circuit, from + which lower-level representations and wiring can be derived. +| It models a synchronous digital circuit in terms of the flow of + digital signals between hardware registers, and the logical operations + performed on those signals. + +**Simulation** + +| A process in which a model of an electronic circuit is replicated and + analysed to verify its functionality. +| Simulation is an invaluable tool for ensuring a circuit works the way + it was intended to by checking accuracy, capacity, and performance. It + also enables designers to rapidly iterate designs and test them to + find the optimal configuration. + +**SoC (System on Chip)** + +| An integrated circuit, containing all the circuitry and components an + electronic system requires. +| In contrast to a traditional computer system that is made up of many + distinct components, an SoC integrates the required resources — CPU, + memory interfaces, I/O devices, I/O interfaces, secondary storage + interfaces — into a single chip. SoCs are typically built around a + microprocessor, microcontroller, or specialised integrated circuit. + This increases performance, reduces power consumption, and requires a + smaller semiconductor die area. + +**Wave form** + +| A visual representation of the variation of a voltage or current over + time. +| Periodic waveforms vary at a given frequency, for example, the voltage + or current of a signal is amplified or reduced to provide a clock + signal for an FPGA. +| Waveforms have three main characteristics: period, the length of time + the waveform takes to repeat; frequency, the number of times the + waveform repeats within a one second time period; and amplitude, the + magnitude or intensity of the signal waveform measured in volts or + amps. +| The waveform of an electrical signal can be visualised in an + oscilloscope or similar instrument that can capture and plot the + variations in the signal. The square waveform is commonly used to + represent digital information. diff --git a/docs/index.rst b/docs/index.rst index 0e6e0dfc3..cf0f772a5 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -17,3 +17,4 @@ Language & toolchain platform changes contrib + glossary From 21bd9b45e7b535eb7a7248d81f1e49541bfa6f20 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 16 Aug 2023 10:58:58 +0100 Subject: [PATCH 02/45] Change wave form to waveform --- docs/glossary.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 2f01b91d6..5ca0e20f5 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -195,7 +195,7 @@ Glossary This increases performance, reduces power consumption, and requires a smaller semiconductor die area. -**Wave form** +**Waveform** | A visual representation of the variation of a voltage or current over time. From 9c25ed893a9605b9648c56826c77b29f1df971e5 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Fri, 18 Aug 2023 12:01:04 +0100 Subject: [PATCH 03/45] Fully-edited, version 3, of Glossary --- docs/glossary.rst | 219 ++++++++++++++-------------------------------- 1 file changed, 64 insertions(+), 155 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 5ca0e20f5..0b6ef87cd 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -3,211 +3,120 @@ Glossary **Amaranth** -| An open-source toolchain that uses the Python programming language. -| Amaranth makes developing hardware definitions, based on synchronous - digital logic, more intuitive by using the popular Python programming - language. The toolchain consists of the Amaranth language, the - standard library, the simulator, and the build system, covering all - steps of a typical FPGA development workflow. + An open-source toolchain that uses the Python programming language. + Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical FPGA development workflow. **ASIC (Application-specific integrated circuit)** -| A non-standard integrated circuit chip made for a specific task or - product. -| The term *application* refers to the function the circuit will - perform, not to a software application. -| ASICs can be configured to be more power efficient and have better - performance than an off-the-shelf general purpose integrated circuit. - However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive - to produce so design and testing are critical to the success of ASIC - development. -| Rather than designing and building them from the ground up, ASICs can - be created by interconnecting functional components from cell - libraries. The resulting system can then be verified via simulation. + A non-standard integrated circuit chip made for a specific task or product. + The term *application* refers to the function the circuit will perform, not to a software application. + ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce so design and testing are critical to the success of ASIC development. + Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. **CLB (Configurable logic block)** -| The basic repeating logic block on an FPGA, the purpose of CLBs is to - implement combinational and sequential logic on an FPGA. -| Each FPGA contains many logic blocks that are surrounded by a system - of programmable interconnects (I/O blocks), called a fabric, that - routes signals between the CLBs. -| The three essential components of a logic block are flip-flops, LUTs, - and multiplexers. + The basic repeating logic block on an FPGA, the purpose of CLBs is to implement combinational and sequential logic on an FPGA. + Be aware that different FPGA manufacturers use different names for this component. + Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. + The three essential components of a logic block are flip-flops, LUTs, and multiplexers. **Clock signal** -| An electronic logic signal that oscillates between a high and a low - state at a constant frequency, used to synchronise the actions of - digital circuits -| The clock signal enters the FPGA system through a single physical - connecting pin and is responsible for the speed at which an FPGA can - run and process data. -| A wave at a particular frequency is distributed across the FPGA to - produce a synchronised response from all the flip-flops in the design. - Performance of the system will be affected if the flip-flops do not - all receive the clock signal at the same time. It’s possible to use - more than one clock in an FPGA design but it is complicated and - requires a degree of skill in circuit design. + An electronic logic signal that oscillates between a high and a low state at a constant frequency. + Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard, a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks use a ring oscillator to monitor an input signal strength and try to balance any fluctuations in the voltage by making its signal faster or slower. **DUT (Device under test)** -| A manufactured device that is being tested for performance and - proficiency. -| The device fails testing as soon the first out-of-tolerance value is - identified. The aim is to ensure damaged devices don’t enter the - market. + A module that is being tested for performance and proficiency. + The module fails testing as soon the first out-of-tolerance value is identified. The aim is to ensure damaged devices don’t enter the market. **Finite state machine** -| A mathematical model describing a system with a limited number of - conditional states of being. -| A finite state machine reads a series of inputs. For each input, it - will transition to a different state. Each state specifies which state - to transition to next, for the given input. When the processing is - complete, a ‘then’ action is taken. The abstract machine can process - only one state at a time. -| This approach enables engineers to study and test each input and - output scenario. + A mathematical model describing a system with a limited number of conditional states of being. + A finite state machine reads a series of inputs. For each input, it will transition to a different state. Each state specifies which state to transition to next, for the given input. When the processing is complete, a ‘then’ action is taken. The abstract machine can process only one state at a time. + This approach enables engineers to study and test each input and output scenario. **Flip-flop** -| The basic memory element for storing a single bit of information. -| An edge-triggered device, it reacts to the edge of a pulse. Flip-flops - synchronise logic and save logical states between clock cycles within - an FPGA circuit. On every rising or falling clock edge, a flip-flop - latches the 1 or 0 (TRUE or FALSE) value on its input and holds that - value constant until the next clock edge. + An elementary building block of integrated circuits, flip-flops are the basic memory element for storing a single bit of binary data. + An edge-triggered device, flip-flops react to the edge of a pulse and have two stable states that they ‘flip’ and ‘flop’ between. + There are different kinds of flip-flops: SR (set or reset), D (data or delay), JK (a modified SR flip-flop that acts as a toggle), and T(a single input JK flip-flop). **FPGA (Field Programmable Gate Array)** -| A reconfigurable integrated circuit containing internal hardware - blocks with user-programmable interconnects to create a customised - application. -| The device’s physical attributes are programmed using a hardware - definition language. I /O blocks interface between the FPGA and - external devices. -| FPGAs combine speed, programmability, and flexibility: FPGAs don't - jump between memory and programming in the way ASICSs and CPUs do, so - storing and retrieving data is more efficient. In addition, they can - process very large volumes of data by duplicating circuits and running - them in parallel. + A reconfigurable integrated circuit containing internal hardware blocks with user-programmable interconnects to create a customised application. + The device’s physical attributes are programmed using a hardware definition language. I/O blocks interface between the FPGA and external devices. + FPGAs combine speed, programmability, and flexibility. In addition, they can process very large volumes of data by duplicating circuits and running them in parallel. **Hardware register** -| Circuits, typically composed of flip flops, often with characteristics - similar to memory and having additional hardware-related functions. -| Hardware registers are used in the interface between software and - peripherals. + Circuits, typically composed of flip flops, that hold configuration and status information. + Hardware registers are used in the interface between software and peripherals: data passed between peripherals and the FPGA is stored temporarily in the hardware register. +**HDL (Hardware definition language)** -**HDL (Hardware description language)** - -| Hardware description languages describe the structure, behaviour, and - timing of electronic circuits and digital logic circuits. -| HDLs describe behavioural, register transfer, gate, and switch-level - logic. Behavioural level logic enables the sequential execution of - instructions; and register transfer logic enables the transfer of data - between registers. These actions are driven by an explicit clock and - gate level logic that defines the individual gate level logic. HDLs - can also be used to simulate a circuit and verify its response. + A hardware definition language, such as Amaranth, describes the structure and timing of electronic circuits and digital logic circuits. + HDLs describe register transfer, gate, and switch-level logic. Register transfer logic enables the transfer of data between registers. These actions are driven by an explicit clock and gate level logic that defines the individual gate level logic. **IC (Integrated circuit)** -| An integrated circuit is a computer chip that has an electronic - circuit embedded in it. -| The circuit is a small wafer, usually made of silicon, that can hold - anywhere from hundreds to millions of transistors, resistors, and - capacitors. These components can perform calculations and store data - using either digital or analog technology. -| Digital ICs use logic gates that work only with values of 1s and 0s. A - low signal sent to a component on a digital IC will result in a value - of 0, while a high signal creates a value of 1. + An integrated circuit is a computer chip that has an electronic circuit embedded in it. + The circuit is a small wafer, usually made of silicon, that can hold anywhere from hundreds to millions of transistors, resistors, and capacitors. These components can perform calculations and store data using either digital or analog technology. + Digital ICs use logic gates that work only with values of 1s and 0s. **Logic gate** -| An elementary building block of integrated circuits, logic gates - perform logical operations on binary inputs and outputs. -| Based on a Boolean function that computes TRUE or FALSE, each output - is based on the input or combination of inputs supplied to it. -| **LUT (Look up table)** + An elementary building block of integrated circuits, logic gates perform logical operations on binary inputs and outputs. + Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. +**LUT (Look up table)** -| An elementary building block of integrated circuits, a LUT is a truth - table that defines how combinatorial logic behaves: the output for - every combination of inputs. -| The computation is very fast because the function requires only a - single memory lookup regardless of the complexity of the function. + An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. + A single input LUT is made up of two flip-flops and a multiplexer. This structure can be expanded into a tree to provide the required capacity. The larger the number of multiplexers, the longer the associated propagation delay. **MCU (Microcontroller unit)** -| A compact integrated circuit designed to govern a specific operation - in an embedded system. -| An MCU typically comprises a processor unit, memory modules, - communication interfaces, and peripherals. + A compact integrated circuit designed to govern a specific operation in an embedded system. + An MCU may be comprised of a processor unit, communication interfaces, and peripherals. Memory and clock functions are usually external to an MCU. **Multiplexer** -| A combinational logic circuit designed to switch one of several inputs - through to a single common output by the application of a control - signal. -| A multiplexer makes it possible for several input signals to share one - device or resource instead of having one device per input signal. They - use high speed logic gates to switch digital or binary data through to - a single output. + A combinational logic circuit designed to switch one of several inputs through to a single common output by the application of a control signal. + A multiplexer selects between several input signals and forwards the selected input to a single output. + This makes it possible for several input signals to access one device or resource instead of having one device per input signal. They use high speed logic gates to switch digital or binary data through to a single output. + +**PLL (Phase-locked loop)** + A phase-locked loop is an electronic circuit with a voltage-driven oscillator that constantly adjusts in response to an input signal. + Its purpose is to increase or decrease its output to stabilise a signal on a noisy channel or where data transfer has been interrupted. **Propagation delay** -| The time required to change the output from one logic state to another - logic state after input is applied. -| In simplified terms, the time it takes for a signal to move from - source to destination. The timing begins when the input to a logic - gate becomes stable and valid to change and ends when the output of - that logic gate is stable and valid to change. -| The propagation delay of a complete circuit is calculated by - identifying the longest path of propagation delay from input to output - and adding each propagation delay along the path. + The time required to change the output from one logic state to another logic state after input is applied. + In simplified terms, the time it takes for a signal to move from source to destination. The timing begins when the input to a logic gate becomes stable and valid to change and ends when the output of that logic gate is stable and valid to change. + The propagation delay of a complete circuit is calculated by identifying the longest path of propagation delay from input to output and adding each propagation delay along the path. + +**Register** + A memory device that can store a specific number of data bits. + Made up of a series of flip-flops, a register can temporarily store data or a set of instructions for a processor. A register can enable both serial and parallel data transfers, allowing logic operations to be performed on the data stored in it. + A number of flip-flops can be combined to store binary words. The length of the stored binary word depends on the number of flip-flops that make up the register. **RTL (Register transfer level)** -| RTL is used to create high-level representations of a circuit, from - which lower-level representations and wiring can be derived. -| It models a synchronous digital circuit in terms of the flow of - digital signals between hardware registers, and the logical operations - performed on those signals. + RTL is used to create high-level representations of a circuit, from which lower-level representations and wiring can be derived. + It models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. **Simulation** -| A process in which a model of an electronic circuit is replicated and - analysed to verify its functionality. -| Simulation is an invaluable tool for ensuring a circuit works the way - it was intended to by checking accuracy, capacity, and performance. It - also enables designers to rapidly iterate designs and test them to - find the optimal configuration. + A process in which a model of an electronic circuit is replicated and analysed to verify its functionality. + Simulation is an invaluable tool for ensuring a circuit works the way it was intended to by checking accuracy, capacity, and performance. It also enables designers to rapidly iterate designs and test them to find the optimal configuration. **SoC (System on Chip)** -| An integrated circuit, containing all the circuitry and components an - electronic system requires. -| In contrast to a traditional computer system that is made up of many - distinct components, an SoC integrates the required resources — CPU, - memory interfaces, I/O devices, I/O interfaces, secondary storage - interfaces — into a single chip. SoCs are typically built around a - microprocessor, microcontroller, or specialised integrated circuit. - This increases performance, reduces power consumption, and requires a - smaller semiconductor die area. + An integrated circuit, containing almost all the circuitry and components an electronic system requires. + In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces, secondary storage interfaces — into a single chip. SoCs are typically built around a microprocessor, microcontroller, or specialised integrated circuit. This increases performance, reduces power consumption, and requires a smaller semiconductor die area. **Waveform** -| A visual representation of the variation of a voltage or current over - time. -| Periodic waveforms vary at a given frequency, for example, the voltage - or current of a signal is amplified or reduced to provide a clock - signal for an FPGA. -| Waveforms have three main characteristics: period, the length of time - the waveform takes to repeat; frequency, the number of times the - waveform repeats within a one second time period; and amplitude, the - magnitude or intensity of the signal waveform measured in volts or - amps. -| The waveform of an electrical signal can be visualised in an - oscilloscope or similar instrument that can capture and plot the - variations in the signal. The square waveform is commonly used to - represent digital information. + A mathematical (logical) description of a signal. + Periodic waveforms provide a clock signal for FPGAs. + Waveforms have three main characteristics: period, the length of time the waveform takes to repeat; frequency, the number of times the waveform repeats within a one second time period; and amplitude, the magnitude or intensity of the signal waveform measured in volts or amps. + The waveform of an electrical signal can be visualised in an oscilloscope or instrument that can capture and plot the variations in the signal. The square waveform is commonly used to represent digital information. + A waveform dump, one of the outputs of simulation, is used in problem resolution. \ No newline at end of file From 9e7d6a9a95ee741ffa0ae1e693668ecafec21435 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Fri, 18 Aug 2023 13:25:35 +0100 Subject: [PATCH 04/45] Removing double spaces --- docs/glossary.rst | 74 +++++++++++++++++++++++------------------------ 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 0b6ef87cd..595eccd78 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -4,119 +4,119 @@ Glossary **Amaranth** An open-source toolchain that uses the Python programming language. - Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical FPGA development workflow. + Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical FPGA development workflow. **ASIC (Application-specific integrated circuit)** A non-standard integrated circuit chip made for a specific task or product. - The term *application* refers to the function the circuit will perform, not to a software application. - ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce so design and testing are critical to the success of ASIC development. - Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. + The term *application* refers to the function the circuit will perform, not to a software application. + ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce so design and testing are critical to the success of ASIC development. + Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. **CLB (Configurable logic block)** The basic repeating logic block on an FPGA, the purpose of CLBs is to implement combinational and sequential logic on an FPGA. - Be aware that different FPGA manufacturers use different names for this component. - Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. - The three essential components of a logic block are flip-flops, LUTs, and multiplexers. + Be aware that different FPGA manufacturers use different names for this component. + Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. + The three essential components of a logic block are flip-flops, LUTs, and multiplexers. **Clock signal** An electronic logic signal that oscillates between a high and a low state at a constant frequency. - Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard, a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks use a ring oscillator to monitor an input signal strength and try to balance any fluctuations in the voltage by making its signal faster or slower. + Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard, a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks use a ring oscillator to monitor an input signal strength and try to balance any fluctuations in the voltage by making its signal faster or slower. **DUT (Device under test)** A module that is being tested for performance and proficiency. - The module fails testing as soon the first out-of-tolerance value is identified. The aim is to ensure damaged devices don’t enter the market. + The module fails testing as soon the first out-of-tolerance value is identified. The aim is to ensure damaged devices don’t enter the market. **Finite state machine** A mathematical model describing a system with a limited number of conditional states of being. - A finite state machine reads a series of inputs. For each input, it will transition to a different state. Each state specifies which state to transition to next, for the given input. When the processing is complete, a ‘then’ action is taken. The abstract machine can process only one state at a time. - This approach enables engineers to study and test each input and output scenario. + A finite state machine reads a series of inputs. For each input, it will transition to a different state. Each state specifies which state to transition to next, for the given input. When the processing is complete, a ‘then’ action is taken. The abstract machine can process only one state at a time. + This approach enables engineers to study and test each input and output scenario. **Flip-flop** An elementary building block of integrated circuits, flip-flops are the basic memory element for storing a single bit of binary data. - An edge-triggered device, flip-flops react to the edge of a pulse and have two stable states that they ‘flip’ and ‘flop’ between. - There are different kinds of flip-flops: SR (set or reset), D (data or delay), JK (a modified SR flip-flop that acts as a toggle), and T(a single input JK flip-flop). + An edge-triggered device, flip-flops react to the edge of a pulse and have two stable states that they ‘flip’ and ‘flop’ between. + There are different kinds of flip-flops: SR (set or reset), D (data or delay), JK (a modified SR flip-flop that acts as a toggle), and T(a single input JK flip-flop). **FPGA (Field Programmable Gate Array)** A reconfigurable integrated circuit containing internal hardware blocks with user-programmable interconnects to create a customised application. - The device’s physical attributes are programmed using a hardware definition language. I/O blocks interface between the FPGA and external devices. - FPGAs combine speed, programmability, and flexibility. In addition, they can process very large volumes of data by duplicating circuits and running them in parallel. + The device’s physical attributes are programmed using a hardware definition language. I/O blocks interface between the FPGA and external devices. + FPGAs combine speed, programmability, and flexibility. In addition, they can process very large volumes of data by duplicating circuits and running them in parallel. **Hardware register** Circuits, typically composed of flip flops, that hold configuration and status information. - Hardware registers are used in the interface between software and peripherals: data passed between peripherals and the FPGA is stored temporarily in the hardware register. + Hardware registers are used in the interface between software and peripherals: data passed between peripherals and the FPGA is stored temporarily in the hardware register. **HDL (Hardware definition language)** A hardware definition language, such as Amaranth, describes the structure and timing of electronic circuits and digital logic circuits. - HDLs describe register transfer, gate, and switch-level logic. Register transfer logic enables the transfer of data between registers. These actions are driven by an explicit clock and gate level logic that defines the individual gate level logic. + HDLs describe register transfer, gate, and switch-level logic. Register transfer logic enables the transfer of data between registers. These actions are driven by an explicit clock and gate level logic that defines the individual gate level logic. **IC (Integrated circuit)** An integrated circuit is a computer chip that has an electronic circuit embedded in it. - The circuit is a small wafer, usually made of silicon, that can hold anywhere from hundreds to millions of transistors, resistors, and capacitors. These components can perform calculations and store data using either digital or analog technology. - Digital ICs use logic gates that work only with values of 1s and 0s. + The circuit is a small wafer, usually made of silicon, that can hold anywhere from hundreds to millions of transistors, resistors, and capacitors. These components can perform calculations and store data using either digital or analog technology. + Digital ICs use logic gates that work only with values of 1s and 0s. **Logic gate** An elementary building block of integrated circuits, logic gates perform logical operations on binary inputs and outputs. - Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. + Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. **LUT (Look up table)** An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. - A single input LUT is made up of two flip-flops and a multiplexer. This structure can be expanded into a tree to provide the required capacity. The larger the number of multiplexers, the longer the associated propagation delay. + A single input LUT is made up of two flip-flops and a multiplexer. This structure can be expanded into a tree to provide the required capacity. The larger the number of multiplexers, the longer the associated propagation delay. **MCU (Microcontroller unit)** A compact integrated circuit designed to govern a specific operation in an embedded system. - An MCU may be comprised of a processor unit, communication interfaces, and peripherals. Memory and clock functions are usually external to an MCU. + An MCU may be comprised of a processor unit, communication interfaces, and peripherals. Memory and clock functions are usually external to an MCU. **Multiplexer** A combinational logic circuit designed to switch one of several inputs through to a single common output by the application of a control signal. - A multiplexer selects between several input signals and forwards the selected input to a single output. - This makes it possible for several input signals to access one device or resource instead of having one device per input signal. They use high speed logic gates to switch digital or binary data through to a single output. + A multiplexer selects between several input signals and forwards the selected input to a single output. + This makes it possible for several input signals to access one device or resource instead of having one device per input signal. They use high speed logic gates to switch digital or binary data through to a single output. **PLL (Phase-locked loop)** - A phase-locked loop is an electronic circuit with a voltage-driven oscillator that constantly adjusts in response to an input signal. - Its purpose is to increase or decrease its output to stabilise a signal on a noisy channel or where data transfer has been interrupted. + A phase-locked loop is an electronic circuit with a voltage-driven oscillator that constantly adjusts in response to an input signal. + Its purpose is to increase or decrease its output to stabilise a signal on a noisy channel or where data transfer has been interrupted. **Propagation delay** The time required to change the output from one logic state to another logic state after input is applied. - In simplified terms, the time it takes for a signal to move from source to destination. The timing begins when the input to a logic gate becomes stable and valid to change and ends when the output of that logic gate is stable and valid to change. - The propagation delay of a complete circuit is calculated by identifying the longest path of propagation delay from input to output and adding each propagation delay along the path. + In simplified terms, the time it takes for a signal to move from source to destination. The timing begins when the input to a logic gate becomes stable and valid to change and ends when the output of that logic gate is stable and valid to change. + The propagation delay of a complete circuit is calculated by identifying the longest path of propagation delay from input to output and adding each propagation delay along the path. **Register** A memory device that can store a specific number of data bits. - Made up of a series of flip-flops, a register can temporarily store data or a set of instructions for a processor. A register can enable both serial and parallel data transfers, allowing logic operations to be performed on the data stored in it. - A number of flip-flops can be combined to store binary words. The length of the stored binary word depends on the number of flip-flops that make up the register. + Made up of a series of flip-flops, a register can temporarily store data or a set of instructions for a processor. A register can enable both serial and parallel data transfers, allowing logic operations to be performed on the data stored in it. + A number of flip-flops can be combined to store binary words. The length of the stored binary word depends on the number of flip-flops that make up the register. **RTL (Register transfer level)** RTL is used to create high-level representations of a circuit, from which lower-level representations and wiring can be derived. - It models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. + It models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. **Simulation** A process in which a model of an electronic circuit is replicated and analysed to verify its functionality. - Simulation is an invaluable tool for ensuring a circuit works the way it was intended to by checking accuracy, capacity, and performance. It also enables designers to rapidly iterate designs and test them to find the optimal configuration. + Simulation is an invaluable tool for ensuring a circuit works the way it was intended to by checking accuracy, capacity, and performance. It also enables designers to rapidly iterate designs and test them to find the optimal configuration. **SoC (System on Chip)** An integrated circuit, containing almost all the circuitry and components an electronic system requires. - In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces, secondary storage interfaces — into a single chip. SoCs are typically built around a microprocessor, microcontroller, or specialised integrated circuit. This increases performance, reduces power consumption, and requires a smaller semiconductor die area. + In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces, secondary storage interfaces — into a single chip. SoCs are typically built around a microprocessor, microcontroller, or specialised integrated circuit. This increases performance, reduces power consumption, and requires a smaller semiconductor die area. **Waveform** A mathematical (logical) description of a signal. - Periodic waveforms provide a clock signal for FPGAs. - Waveforms have three main characteristics: period, the length of time the waveform takes to repeat; frequency, the number of times the waveform repeats within a one second time period; and amplitude, the magnitude or intensity of the signal waveform measured in volts or amps. - The waveform of an electrical signal can be visualised in an oscilloscope or instrument that can capture and plot the variations in the signal. The square waveform is commonly used to represent digital information. - A waveform dump, one of the outputs of simulation, is used in problem resolution. \ No newline at end of file + Periodic waveforms provide a clock signal for FPGAs. + Waveforms have three main characteristics: period, the length of time the waveform takes to repeat; frequency, the number of times the waveform repeats within a one second time period; and amplitude, the magnitude or intensity of the signal waveform measured in volts or amps. + The waveform of an electrical signal can be visualised in an oscilloscope or instrument that can capture and plot the variations in the signal. The square waveform is commonly used to represent digital information. + A waveform dump, one of the outputs of simulation, is used in problem resolution. \ No newline at end of file From 6f51d98b6bb182017608334edca4079bd29dcfe3 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 23 Aug 2023 14:43:55 +0100 Subject: [PATCH 05/45] Testing cross referencing within text --- docs/glossary.rst | 37 ++++++++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 595eccd78..c5057a18c 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -23,12 +23,12 @@ Glossary **Clock signal** An electronic logic signal that oscillates between a high and a low state at a constant frequency. - Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard, a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks use a ring oscillator to monitor an input signal strength and try to balance any fluctuations in the voltage by making its signal faster or slower. + Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard, a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks can be made by dividing another clock signal or using a :ref:`PLL`. **DUT (Device under test)** - A module that is being tested for performance and proficiency. - The module fails testing as soon the first out-of-tolerance value is identified. The aim is to ensure damaged devices don’t enter the market. + A physical chip or logic circuit being tested at simulation. + The results of the testing can result in a chip being given a grade to represent the extent to which it met the tolerance values. **Finite state machine** @@ -40,42 +40,55 @@ Glossary An elementary building block of integrated circuits, flip-flops are the basic memory element for storing a single bit of binary data. An edge-triggered device, flip-flops react to the edge of a pulse and have two stable states that they ‘flip’ and ‘flop’ between. - There are different kinds of flip-flops: SR (set or reset), D (data or delay), JK (a modified SR flip-flop that acts as a toggle), and T(a single input JK flip-flop). + Modern digital design centres around the D flip-flop (DFF) with Set, Reset, and Enable inputs. **FPGA (Field Programmable Gate Array)** A reconfigurable integrated circuit containing internal hardware blocks with user-programmable interconnects to create a customised application. - The device’s physical attributes are programmed using a hardware definition language. I/O blocks interface between the FPGA and external devices. + The device’s physical attributes are programmed using a hardware definition language. User-programmable I/O blocks interface between the FPGA and external devices. FPGAs combine speed, programmability, and flexibility. In addition, they can process very large volumes of data by duplicating circuits and running them in parallel. **Hardware register** - Circuits, typically composed of flip flops, that hold configuration and status information. - Hardware registers are used in the interface between software and peripherals: data passed between peripherals and the FPGA is stored temporarily in the hardware register. + Circuits, typically composed of D flip-flops (DFF), that hold configuration and status information. + At a lower level, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. + **HDL (Hardware definition language)** A hardware definition language, such as Amaranth, describes the structure and timing of electronic circuits and digital logic circuits. - HDLs describe register transfer, gate, and switch-level logic. Register transfer logic enables the transfer of data between registers. These actions are driven by an explicit clock and gate level logic that defines the individual gate level logic. + Modern HDLs include synthesizable code that describes the synchronous logic (registers), combinational logic (logic gates), and behavioural code (used in testing) to describe a circuit. **IC (Integrated circuit)** An integrated circuit is a computer chip that has an electronic circuit embedded in it. - The circuit is a small wafer, usually made of silicon, that can hold anywhere from hundreds to millions of transistors, resistors, and capacitors. These components can perform calculations and store data using either digital or analog technology. + The circuit is a small wafer, usually made of semiconducting material, that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). These components can perform calculations and store data using either digital or analog technology. Digital ICs use logic gates that work only with values of 1s and 0s. **Logic gate** An elementary building block of integrated circuits, logic gates perform logical operations on binary inputs and outputs. Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. + +**Logic synthesizers** +The process of translating a high-level logic definition to lower level flip-flops and logic gates. +High-level language, written in a program like Python, is translated to register transfer level language. + **LUT (Look up table)** An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. A single input LUT is made up of two flip-flops and a multiplexer. This structure can be expanded into a tree to provide the required capacity. The larger the number of multiplexers, the longer the associated propagation delay. + LUTs can be used to implement an arbitrary logic gate with the same or fewer inputs: a 4-LUT can implement 1, 2, 3, or 4 inputs. If five inputs are required, two 4-LUTS can be combined but at the expense of propogation delay. **MCU (Microcontroller unit)** - A compact integrated circuit designed to govern a specific operation in an embedded system. - An MCU may be comprised of a processor unit, communication interfaces, and peripherals. Memory and clock functions are usually external to an MCU. + An integrated circuit designed to govern a specific operation in an embedded system. + An MCU is comprised of a CPU, onboard memory (SRAM, peripherals, and, usually, clock functions. + +**Memory-mapped peripheral** + +Hardware devices mapped to the memory address space of a microprocessor. +The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. +A memory-mapped peripheral behaves and looks like physical memory but isn't physical memory. **Multiplexer** @@ -83,6 +96,8 @@ Glossary A multiplexer selects between several input signals and forwards the selected input to a single output. This makes it possible for several input signals to access one device or resource instead of having one device per input signal. They use high speed logic gates to switch digital or binary data through to a single output. +.. _PLL: + **PLL (Phase-locked loop)** A phase-locked loop is an electronic circuit with a voltage-driven oscillator that constantly adjusts in response to an input signal. Its purpose is to increase or decrease its output to stabilise a signal on a noisy channel or where data transfer has been interrupted. From e4a0f963da62f332e659540e7933ac597aca2db3 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 23 Aug 2023 15:08:11 +0100 Subject: [PATCH 06/45] Testing expansion of text on rollover --- docs/glossary.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index c5057a18c..e7cab74a2 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -4,7 +4,7 @@ Glossary **Amaranth** An open-source toolchain that uses the Python programming language. - Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical FPGA development workflow. + Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA (Field Programmable Gate Array)`:ref:`FPGA` development workflow. **ASIC (Application-specific integrated circuit)** @@ -42,6 +42,8 @@ Glossary An edge-triggered device, flip-flops react to the edge of a pulse and have two stable states that they ‘flip’ and ‘flop’ between. Modern digital design centres around the D flip-flop (DFF) with Set, Reset, and Enable inputs. +.. _FPGA: + **FPGA (Field Programmable Gate Array)** A reconfigurable integrated circuit containing internal hardware blocks with user-programmable interconnects to create a customised application. From 20583350342a79384deb3bce79f93c232e4b7eb9 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 23 Aug 2023 15:10:26 +0100 Subject: [PATCH 07/45] Retry abbreviation text --- docs/glossary.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index e7cab74a2..4161965ee 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -4,7 +4,7 @@ Glossary **Amaranth** An open-source toolchain that uses the Python programming language. - Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA (Field Programmable Gate Array)`:ref:`FPGA` development workflow. + Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA (Field Programmable Gate Array)` development workflow. **ASIC (Application-specific integrated circuit)** From c091bc108d31332877dfbaf167d622d06b612156 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 23 Aug 2023 15:44:34 +0100 Subject: [PATCH 08/45] Attemp to fix abbr --- docs/glossary.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 4161965ee..95601b488 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -4,7 +4,7 @@ Glossary **Amaranth** An open-source toolchain that uses the Python programming language. - Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA (Field Programmable Gate Array)` development workflow. + Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. **ASIC (Application-specific integrated circuit)** From 62b8ba5794e89cc8be5c2a92285e3cf231e7ea55 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 23 Aug 2023 16:14:15 +0100 Subject: [PATCH 09/45] testing :term: --- docs/glossary.rst | 6 ++++-- docs/intro.rst | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 95601b488..f7df38675 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -1,6 +1,8 @@ -Glossary +Glossary ======== +.. glossary:: + **Amaranth** An open-source toolchain that uses the Python programming language. @@ -115,7 +117,7 @@ A memory-mapped peripheral behaves and looks like physical memory but isn't phys Made up of a series of flip-flops, a register can temporarily store data or a set of instructions for a processor. A register can enable both serial and parallel data transfers, allowing logic operations to be performed on the data stored in it. A number of flip-flops can be combined to store binary words. The length of the stored binary word depends on the number of flip-flops that make up the register. -**RTL (Register transfer level)** +**Register transfer level (RTL)** RTL is used to create high-level representations of a circuit, from which lower-level representations and wiring can be derived. It models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. diff --git a/docs/intro.rst b/docs/intro.rst index 2fed04407..84c4943f8 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -16,7 +16,7 @@ The Amaranth toolchain consists of the :ref:`Amaranth language `, th The Amaranth language ===================== -The :doc:`Amaranth hardware description language ` is a Python library for register transfer level modeling of synchronous logic. Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys_, or converted to human-readable Verilog code for use with industry-standard toolchains. +The :doc:`Amaranth hardware description language ` is a Python library for :term:`register transfer level` modeling of synchronous logic. Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys_, or converted to human-readable Verilog code for use with industry-standard toolchains. By relying on the flexibility, rich functionality and widespread adoption of the Python language, the Amaranth language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and finite state machines, and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs; Python libraries can be seamlessly used with Amaranth during design or verification; and Python development tools can process Amaranth code. From 11755605fc6615b321f4d8a84034842c8325db54 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 23 Aug 2023 16:35:36 +0100 Subject: [PATCH 10/45] glossary tag --- docs/glossary.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index f7df38675..cc8ab8198 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -1,8 +1,8 @@ +.. glossary:: + Glossary ======== -.. glossary:: - **Amaranth** An open-source toolchain that uses the Python programming language. From 72f5380fcc8d253108e78dd1d28114b73c6cdd52 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 23 Aug 2023 16:46:21 +0100 Subject: [PATCH 11/45] Was it a blank line? --- docs/glossary.rst | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index cc8ab8198..ca9a71dee 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -1,8 +1,8 @@ -.. glossary:: - Glossary ======== +.. glossary:: + **Amaranth** An open-source toolchain that uses the Python programming language. @@ -118,7 +118,6 @@ A memory-mapped peripheral behaves and looks like physical memory but isn't phys A number of flip-flops can be combined to store binary words. The length of the stored binary word depends on the number of flip-flops that make up the register. **Register transfer level (RTL)** - RTL is used to create high-level representations of a circuit, from which lower-level representations and wiring can be derived. It models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. From 90f528c53289f1c4fcb379f456daa8911a385fae Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 24 Aug 2023 09:45:43 +0100 Subject: [PATCH 12/45] testing indent --- docs/glossary.rst | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index ca9a71dee..15bc22323 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -4,42 +4,35 @@ Glossary .. glossary:: **Amaranth** - An open-source toolchain that uses the Python programming language. Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. **ASIC (Application-specific integrated circuit)** - A non-standard integrated circuit chip made for a specific task or product. The term *application* refers to the function the circuit will perform, not to a software application. ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce so design and testing are critical to the success of ASIC development. Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. **CLB (Configurable logic block)** - The basic repeating logic block on an FPGA, the purpose of CLBs is to implement combinational and sequential logic on an FPGA. Be aware that different FPGA manufacturers use different names for this component. Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. The three essential components of a logic block are flip-flops, LUTs, and multiplexers. **Clock signal** - An electronic logic signal that oscillates between a high and a low state at a constant frequency. Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard, a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks can be made by dividing another clock signal or using a :ref:`PLL`. **DUT (Device under test)** - A physical chip or logic circuit being tested at simulation. The results of the testing can result in a chip being given a grade to represent the extent to which it met the tolerance values. **Finite state machine** - A mathematical model describing a system with a limited number of conditional states of being. A finite state machine reads a series of inputs. For each input, it will transition to a different state. Each state specifies which state to transition to next, for the given input. When the processing is complete, a ‘then’ action is taken. The abstract machine can process only one state at a time. This approach enables engineers to study and test each input and output scenario. **Flip-flop** - An elementary building block of integrated circuits, flip-flops are the basic memory element for storing a single bit of binary data. An edge-triggered device, flip-flops react to the edge of a pulse and have two stable states that they ‘flip’ and ‘flop’ between. Modern digital design centres around the D flip-flop (DFF) with Set, Reset, and Enable inputs. @@ -47,29 +40,24 @@ Glossary .. _FPGA: **FPGA (Field Programmable Gate Array)** - A reconfigurable integrated circuit containing internal hardware blocks with user-programmable interconnects to create a customised application. The device’s physical attributes are programmed using a hardware definition language. User-programmable I/O blocks interface between the FPGA and external devices. FPGAs combine speed, programmability, and flexibility. In addition, they can process very large volumes of data by duplicating circuits and running them in parallel. **Hardware register** - Circuits, typically composed of D flip-flops (DFF), that hold configuration and status information. At a lower level, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. **HDL (Hardware definition language)** - A hardware definition language, such as Amaranth, describes the structure and timing of electronic circuits and digital logic circuits. Modern HDLs include synthesizable code that describes the synchronous logic (registers), combinational logic (logic gates), and behavioural code (used in testing) to describe a circuit. **IC (Integrated circuit)** - An integrated circuit is a computer chip that has an electronic circuit embedded in it. The circuit is a small wafer, usually made of semiconducting material, that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). These components can perform calculations and store data using either digital or analog technology. Digital ICs use logic gates that work only with values of 1s and 0s. **Logic gate** - An elementary building block of integrated circuits, logic gates perform logical operations on binary inputs and outputs. Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. @@ -78,24 +66,20 @@ The process of translating a high-level logic definition to lower level flip-flo High-level language, written in a program like Python, is translated to register transfer level language. **LUT (Look up table)** - An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. A single input LUT is made up of two flip-flops and a multiplexer. This structure can be expanded into a tree to provide the required capacity. The larger the number of multiplexers, the longer the associated propagation delay. LUTs can be used to implement an arbitrary logic gate with the same or fewer inputs: a 4-LUT can implement 1, 2, 3, or 4 inputs. If five inputs are required, two 4-LUTS can be combined but at the expense of propogation delay. **MCU (Microcontroller unit)** - An integrated circuit designed to govern a specific operation in an embedded system. An MCU is comprised of a CPU, onboard memory (SRAM, peripherals, and, usually, clock functions. **Memory-mapped peripheral** - Hardware devices mapped to the memory address space of a microprocessor. The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. A memory-mapped peripheral behaves and looks like physical memory but isn't physical memory. **Multiplexer** - A combinational logic circuit designed to switch one of several inputs through to a single common output by the application of a control signal. A multiplexer selects between several input signals and forwards the selected input to a single output. This makes it possible for several input signals to access one device or resource instead of having one device per input signal. They use high speed logic gates to switch digital or binary data through to a single output. @@ -107,7 +91,6 @@ A memory-mapped peripheral behaves and looks like physical memory but isn't phys Its purpose is to increase or decrease its output to stabilise a signal on a noisy channel or where data transfer has been interrupted. **Propagation delay** - The time required to change the output from one logic state to another logic state after input is applied. In simplified terms, the time it takes for a signal to move from source to destination. The timing begins when the input to a logic gate becomes stable and valid to change and ends when the output of that logic gate is stable and valid to change. The propagation delay of a complete circuit is calculated by identifying the longest path of propagation delay from input to output and adding each propagation delay along the path. @@ -117,22 +100,19 @@ A memory-mapped peripheral behaves and looks like physical memory but isn't phys Made up of a series of flip-flops, a register can temporarily store data or a set of instructions for a processor. A register can enable both serial and parallel data transfers, allowing logic operations to be performed on the data stored in it. A number of flip-flops can be combined to store binary words. The length of the stored binary word depends on the number of flip-flops that make up the register. -**Register transfer level (RTL)** - RTL is used to create high-level representations of a circuit, from which lower-level representations and wiring can be derived. - It models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. + **Register transfer level (RTL)** + RTL is used to create high-level representations of a circuit, from which lower-level representations and wiring can be derived. + It models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. **Simulation** - A process in which a model of an electronic circuit is replicated and analysed to verify its functionality. Simulation is an invaluable tool for ensuring a circuit works the way it was intended to by checking accuracy, capacity, and performance. It also enables designers to rapidly iterate designs and test them to find the optimal configuration. **SoC (System on Chip)** - An integrated circuit, containing almost all the circuitry and components an electronic system requires. In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces, secondary storage interfaces — into a single chip. SoCs are typically built around a microprocessor, microcontroller, or specialised integrated circuit. This increases performance, reduces power consumption, and requires a smaller semiconductor die area. **Waveform** - A mathematical (logical) description of a signal. Periodic waveforms provide a clock signal for FPGAs. Waveforms have three main characteristics: period, the length of time the waveform takes to repeat; frequency, the number of times the waveform repeats within a one second time period; and amplitude, the magnitude or intensity of the signal waveform measured in volts or amps. From 4a41fa893d892e28dececc47be3c5ef0b0a1392e Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 24 Aug 2023 09:57:21 +0100 Subject: [PATCH 13/45] indentation --- docs/glossary.rst | 242 +++++++++++++++++++++++++++------------------- 1 file changed, 142 insertions(+), 100 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 15bc22323..4499b5655 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -3,118 +3,160 @@ Glossary .. glossary:: -**Amaranth** - An open-source toolchain that uses the Python programming language. - Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. - -**ASIC (Application-specific integrated circuit)** - A non-standard integrated circuit chip made for a specific task or product. - The term *application* refers to the function the circuit will perform, not to a software application. - ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce so design and testing are critical to the success of ASIC development. - Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. - -**CLB (Configurable logic block)** - The basic repeating logic block on an FPGA, the purpose of CLBs is to implement combinational and sequential logic on an FPGA. - Be aware that different FPGA manufacturers use different names for this component. - Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. - The three essential components of a logic block are flip-flops, LUTs, and multiplexers. - -**Clock signal** - An electronic logic signal that oscillates between a high and a low state at a constant frequency. - Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard, a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks can be made by dividing another clock signal or using a :ref:`PLL`. - -**DUT (Device under test)** - A physical chip or logic circuit being tested at simulation. - The results of the testing can result in a chip being given a grade to represent the extent to which it met the tolerance values. - -**Finite state machine** - A mathematical model describing a system with a limited number of conditional states of being. - A finite state machine reads a series of inputs. For each input, it will transition to a different state. Each state specifies which state to transition to next, for the given input. When the processing is complete, a ‘then’ action is taken. The abstract machine can process only one state at a time. - This approach enables engineers to study and test each input and output scenario. - -**Flip-flop** - An elementary building block of integrated circuits, flip-flops are the basic memory element for storing a single bit of binary data. - An edge-triggered device, flip-flops react to the edge of a pulse and have two stable states that they ‘flip’ and ‘flop’ between. - Modern digital design centres around the D flip-flop (DFF) with Set, Reset, and Enable inputs. + **Amaranth** + An open-source toolchain that uses the Python programming language. + + Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. + + **ASIC (Application-specific integrated circuit)** + A non-standard integrated circuit chip made for a specific task or product. + + The term *application* refers to the function the circuit will perform, not to a software application. + + ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce so design and testing are critical to the success of ASIC development. + + Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. + + **CLB (Configurable logic block)** + The basic repeating logic block on an FPGA, the purpose of CLBs is to implement combinational and sequential logic on an FPGA. + + Be aware that different FPGA manufacturers use different names for this component. + + Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. + + The three essential components of a logic block are flip-flops, LUTs, and multiplexers. + + **Clock signal** + An electronic logic signal that oscillates between a high and a low state at a constant frequency. + + Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard, a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks can be made by dividing another clock signal or using a :ref:`PLL`. + + **DUT (Device under test)** + A physical chip or logic circuit being tested at simulation. + + The results of the testing can result in a chip being given a grade to represent the extent to which it met the tolerance values. + + **Finite state machine** + A mathematical model describing a system with a limited number of conditional states of being. + + A finite state machine reads a series of inputs. For each input, it will transition to a different state. Each state specifies which state to transition to next, for the given input. When the processing is complete, a ‘then’ action is taken. The abstract machine can process only one state at a time. + + This approach enables engineers to study and test each input and output scenario. + + **Flip-flop** + An elementary building block of integrated circuits, flip-flops are the basic memory element for storing a single bit of binary data. + + An edge-triggered device, flip-flops react to the edge of a pulse and have two stable states that they ‘flip’ and ‘flop’ between. + + Modern digital design centres around the D flip-flop (DFF) with Set, Reset, and Enable inputs. .. _FPGA: -**FPGA (Field Programmable Gate Array)** - A reconfigurable integrated circuit containing internal hardware blocks with user-programmable interconnects to create a customised application. - The device’s physical attributes are programmed using a hardware definition language. User-programmable I/O blocks interface between the FPGA and external devices. - FPGAs combine speed, programmability, and flexibility. In addition, they can process very large volumes of data by duplicating circuits and running them in parallel. + **FPGA (Field Programmable Gate Array)** + A reconfigurable integrated circuit containing internal hardware blocks with user-programmable interconnects to create a customised application. + + The device’s physical attributes are programmed using a hardware definition language. User-programmable I/O blocks interface between the FPGA and external devices. + + FPGAs combine speed, programmability, and flexibility. In addition, they can process very large volumes of data by duplicating circuits and running them in parallel. + + **Hardware register** + Circuits, typically composed of D flip-flops (DFF), that hold configuration and status information. + + At a lower level, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. + + **HDL (Hardware definition language)** + A hardware definition language, such as Amaranth, describes the structure and timing of electronic circuits and digital logic circuits. + + Modern HDLs include synthesizable code that describes the synchronous logic (registers), combinational logic (logic gates), and behavioural code (used in testing) to describe a circuit. + + **IC (Integrated circuit)** + An integrated circuit is a computer chip that has an electronic circuit embedded in it. -**Hardware register** - Circuits, typically composed of D flip-flops (DFF), that hold configuration and status information. - At a lower level, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. + The circuit is a small wafer, usually made of semiconducting material, that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). + + These components can perform calculations and store data using either digital or analog technology. + + Digital ICs use logic gates that work only with values of 1s and 0s. -**HDL (Hardware definition language)** - A hardware definition language, such as Amaranth, describes the structure and timing of electronic circuits and digital logic circuits. - Modern HDLs include synthesizable code that describes the synchronous logic (registers), combinational logic (logic gates), and behavioural code (used in testing) to describe a circuit. + **Logic gate** + An elementary building block of integrated circuits, logic gates perform logical operations on binary inputs and outputs. -**IC (Integrated circuit)** - An integrated circuit is a computer chip that has an electronic circuit embedded in it. - The circuit is a small wafer, usually made of semiconducting material, that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). These components can perform calculations and store data using either digital or analog technology. - Digital ICs use logic gates that work only with values of 1s and 0s. + Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. -**Logic gate** - An elementary building block of integrated circuits, logic gates perform logical operations on binary inputs and outputs. - Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. + **Logic synthesizers** + The process of translating a high-level logic definition to lower level flip-flops and logic gates. -**Logic synthesizers** -The process of translating a high-level logic definition to lower level flip-flops and logic gates. -High-level language, written in a program like Python, is translated to register transfer level language. + High-level language, written in a program like Python, is translated to register transfer level language. -**LUT (Look up table)** - An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. - A single input LUT is made up of two flip-flops and a multiplexer. This structure can be expanded into a tree to provide the required capacity. The larger the number of multiplexers, the longer the associated propagation delay. - LUTs can be used to implement an arbitrary logic gate with the same or fewer inputs: a 4-LUT can implement 1, 2, 3, or 4 inputs. If five inputs are required, two 4-LUTS can be combined but at the expense of propogation delay. + **LUT (Look up table)** + An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. -**MCU (Microcontroller unit)** - An integrated circuit designed to govern a specific operation in an embedded system. - An MCU is comprised of a CPU, onboard memory (SRAM, peripherals, and, usually, clock functions. + A single input LUT is made up of two flip-flops and a multiplexer. This structure can be expanded into a tree to provide the required capacity. The larger the number of multiplexers, the longer the associated propagation delay. -**Memory-mapped peripheral** -Hardware devices mapped to the memory address space of a microprocessor. -The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. -A memory-mapped peripheral behaves and looks like physical memory but isn't physical memory. + LUTs can be used to implement an arbitrary logic gate with the same or fewer inputs: a 4-LUT can implement 1, 2, 3, or 4 inputs. If five inputs are required, two 4-LUTS can be combined but at the expense of propogation delay. -**Multiplexer** - A combinational logic circuit designed to switch one of several inputs through to a single common output by the application of a control signal. - A multiplexer selects between several input signals and forwards the selected input to a single output. - This makes it possible for several input signals to access one device or resource instead of having one device per input signal. They use high speed logic gates to switch digital or binary data through to a single output. + **MCU (Microcontroller unit)** + An integrated circuit designed to govern a specific operation in an embedded system. + + An MCU is comprised of a CPU, onboard memory (SRAM, peripherals, and, usually, clock functions. + + **Memory-mapped peripheral** + Hardware devices mapped to the memory address space of a microprocessor. + + The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. + + A memory-mapped peripheral behaves and looks like physical memory but isn't physical memory. + + **Multiplexer** + A combinational logic circuit designed to switch one of several inputs through to a single common output by the application of a control signal. + + A multiplexer selects between several input signals and forwards the selected input to a single output. + + This makes it possible for several input signals to access one device or resource instead of having one device per input signal. They use high speed logic gates to switch digital or binary data through to a single output. .. _PLL: -**PLL (Phase-locked loop)** - A phase-locked loop is an electronic circuit with a voltage-driven oscillator that constantly adjusts in response to an input signal. - Its purpose is to increase or decrease its output to stabilise a signal on a noisy channel or where data transfer has been interrupted. - -**Propagation delay** - The time required to change the output from one logic state to another logic state after input is applied. - In simplified terms, the time it takes for a signal to move from source to destination. The timing begins when the input to a logic gate becomes stable and valid to change and ends when the output of that logic gate is stable and valid to change. - The propagation delay of a complete circuit is calculated by identifying the longest path of propagation delay from input to output and adding each propagation delay along the path. - -**Register** - A memory device that can store a specific number of data bits. - Made up of a series of flip-flops, a register can temporarily store data or a set of instructions for a processor. A register can enable both serial and parallel data transfers, allowing logic operations to be performed on the data stored in it. - A number of flip-flops can be combined to store binary words. The length of the stored binary word depends on the number of flip-flops that make up the register. - - **Register transfer level (RTL)** - RTL is used to create high-level representations of a circuit, from which lower-level representations and wiring can be derived. - It models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. - -**Simulation** - A process in which a model of an electronic circuit is replicated and analysed to verify its functionality. - Simulation is an invaluable tool for ensuring a circuit works the way it was intended to by checking accuracy, capacity, and performance. It also enables designers to rapidly iterate designs and test them to find the optimal configuration. - -**SoC (System on Chip)** - An integrated circuit, containing almost all the circuitry and components an electronic system requires. - In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces, secondary storage interfaces — into a single chip. SoCs are typically built around a microprocessor, microcontroller, or specialised integrated circuit. This increases performance, reduces power consumption, and requires a smaller semiconductor die area. - -**Waveform** - A mathematical (logical) description of a signal. - Periodic waveforms provide a clock signal for FPGAs. - Waveforms have three main characteristics: period, the length of time the waveform takes to repeat; frequency, the number of times the waveform repeats within a one second time period; and amplitude, the magnitude or intensity of the signal waveform measured in volts or amps. - The waveform of an electrical signal can be visualised in an oscilloscope or instrument that can capture and plot the variations in the signal. The square waveform is commonly used to represent digital information. - A waveform dump, one of the outputs of simulation, is used in problem resolution. \ No newline at end of file + **PLL (Phase-locked loop)** + A phase-locked loop is an electronic circuit with a voltage-driven oscillator that constantly adjusts in response to an input signal. + + Its purpose is to increase or decrease its output to stabilise a signal on a noisy channel or where data transfer has been interrupted. + + **Propagation delay** + The time required to change the output from one logic state to another logic state after input is applied. + + In simplified terms, the time it takes for a signal to move from source to destination. The timing begins when the input to a logic gate becomes stable and valid to change and ends when the output of that logic gate is stable and valid to change. + + The propagation delay of a complete circuit is calculated by identifying the longest path of propagation delay from input to output and adding each propagation delay along the path. + + **Register** + A memory device that can store a specific number of data bits. + + Made up of a series of flip-flops, a register can temporarily store data or a set of instructions for a processor. A register can enable both serial and parallel data transfers, allowing logic operations to be performed on the data stored in it. + + A number of flip-flops can be combined to store binary words. The length of the stored binary word depends on the number of flip-flops that make up the register. + + **Register transfer level (RTL)** + RTL is used to create high-level representations of a circuit, from which lower-level representations and wiring can be derived. + + It models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. + + **Simulation** + A process in which a model of an electronic circuit is replicated and analysed to verify its functionality. + + Simulation is an invaluable tool for ensuring a circuit works the way it was intended to by checking accuracy, capacity, and performance. It also enables designers to rapidly iterate designs and test them to find the optimal configuration. + + **SoC (System on Chip)** + An integrated circuit, containing almost all the circuitry and components an electronic system requires. + + In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces, secondary storage interfaces — into a single chip. SoCs are typically built around a microprocessor, microcontroller, or specialised integrated circuit. This increases performance, reduces power consumption, and requires a smaller semiconductor die area. + + **Waveform** + A mathematical (logical) description of a signal. + + Periodic waveforms provide a clock signal for FPGAs. + + Waveforms have three main characteristics: period, the length of time the waveform takes to repeat; frequency, the number of times the waveform repeats within a one second time period; and amplitude, the magnitude or intensity of the signal waveform measured in volts or amps. + + The waveform of an electrical signal can be visualised in an oscilloscope or instrument that can capture and plot the variations in the signal. The square waveform is commonly used to represent digital information. + + A waveform dump, one of the outputs of simulation, is used in problem resolution. \ No newline at end of file From 0637067f97c0f8f5e85adc7a04b719ce1deff352 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 24 Aug 2023 10:29:22 +0100 Subject: [PATCH 14/45] more testing --- docs/glossary.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 4499b5655..f1e74bec4 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -1,8 +1,8 @@ +.. glossary:: + Glossary ======== -.. glossary:: - **Amaranth** An open-source toolchain that uses the Python programming language. From a7409a2b08f531dd294dcaaf800a4e2f2577b5c6 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 24 Aug 2023 10:29:59 +0100 Subject: [PATCH 15/45] more testing --- docs/intro.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/intro.rst b/docs/intro.rst index 84c4943f8..4fe84a79a 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -6,7 +6,7 @@ Introduction The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. -The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical FPGA development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. +The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical :term: `FPGA` development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. .. TODO: add links to connect_rpc docs once they exist From 2fb4a9560379f45abd3bedadd03873123d4789b3 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 24 Aug 2023 10:33:58 +0100 Subject: [PATCH 16/45] angle brackets --- docs/intro.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/intro.rst b/docs/intro.rst index 4fe84a79a..e2bf93011 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -6,7 +6,7 @@ Introduction The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. -The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical :term: `FPGA` development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. +The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical :term:`FPGA` development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. .. TODO: add links to connect_rpc docs once they exist @@ -16,7 +16,7 @@ The Amaranth toolchain consists of the :ref:`Amaranth language `, th The Amaranth language ===================== -The :doc:`Amaranth hardware description language ` is a Python library for :term:`register transfer level` modeling of synchronous logic. Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys_, or converted to human-readable Verilog code for use with industry-standard toolchains. +The :doc:`Amaranth hardware description language ` is a Python library for :term:`register transfer level` modeling of synchronous logic. Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys_, or converted to human-readable Verilog code for use with industry-standard toolchains. By relying on the flexibility, rich functionality and widespread adoption of the Python language, the Amaranth language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and finite state machines, and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs; Python libraries can be seamlessly used with Amaranth during design or verification; and Python development tools can process Amaranth code. From 39144b2cba10a68c4b81c033cf13cabd1899bf74 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 24 Aug 2023 11:47:54 +0100 Subject: [PATCH 17/45] changing link --- docs/intro.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/intro.rst b/docs/intro.rst index e2bf93011..c90b468d6 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -6,7 +6,7 @@ Introduction The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. -The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical :term:`FPGA` development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. +The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical :term:`FPGA ` FPGA development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. .. TODO: add links to connect_rpc docs once they exist @@ -16,7 +16,7 @@ The Amaranth toolchain consists of the :ref:`Amaranth language `, th The Amaranth language ===================== -The :doc:`Amaranth hardware description language ` is a Python library for :term:`register transfer level` modeling of synchronous logic. Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys_, or converted to human-readable Verilog code for use with industry-standard toolchains. +The :doc:`Amaranth hardware description language ` is a Python library for modeling of synchronous logic. Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys_, or converted to human-readable Verilog code for use with industry-standard toolchains. By relying on the flexibility, rich functionality and widespread adoption of the Python language, the Amaranth language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and finite state machines, and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs; Python libraries can be seamlessly used with Amaranth during design or verification; and Python development tools can process Amaranth code. From d3ebf349165a76f6596a228d4f30ad0d57964f4d Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 24 Aug 2023 11:54:26 +0100 Subject: [PATCH 18/45] use amaranth --- docs/glossary.rst | 2 +- docs/intro.rst | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index f1e74bec4..c43ace882 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -3,7 +3,7 @@ Glossary ======== - **Amaranth** + Amaranth An open-source toolchain that uses the Python programming language. Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. diff --git a/docs/intro.rst b/docs/intro.rst index c90b468d6..983c693ab 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -4,9 +4,9 @@ Introduction ############ -The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. +The :term:`Amaranth` Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. -The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical :term:`FPGA ` FPGA development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. +The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical FPGA development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. .. TODO: add links to connect_rpc docs once they exist From d6659d43a057298d6c9f39295be6a4e58699f06f Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 24 Aug 2023 11:56:47 +0100 Subject: [PATCH 19/45] roll back --- docs/glossary.rst | 2 +- docs/intro.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index c43ace882..f1e74bec4 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -3,7 +3,7 @@ Glossary ======== - Amaranth + **Amaranth** An open-source toolchain that uses the Python programming language. Amaranth makes developing hardware definitions, based on synchronous digital logic, more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. diff --git a/docs/intro.rst b/docs/intro.rst index 983c693ab..4598d9f6d 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -4,7 +4,7 @@ Introduction ############ -The :term:`Amaranth` Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. +The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical FPGA development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. 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The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. + Amaranth makes developing hardware definitions based on synchronous digital logic more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. **ASIC (Application-specific integrated circuit)** A non-standard integrated circuit chip made for a specific task or product. @@ -17,24 +17,59 @@ Glossary Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. +.. _Bitstream generation: + **Bitstream generation** + + + + **Block RAM (BRAM)** + Block RAM is on-chip random access memory that stores large amounts of data and is distributed evenly across a chip. + + BRAM, sometimes called embedded RAM, doesn't need refreshing (as DRAM does) and, like SRAM, doesn't need a memory controller. Single-port BRAM can either read or write on the port; dual-port BRAM supports read and write for any two addresses and both ports can read *and* write. + + BRAM :ref:`FIFO`s are used to cross clock domains or to buffer data between two interfaces. + **CLB (Configurable logic block)** The basic repeating logic block on an FPGA, the purpose of CLBs is to implement combinational and sequential logic on an FPGA. Be aware that different FPGA manufacturers use different names for this component. - Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. - - The three essential components of a logic block are flip-flops, LUTs, and multiplexers. + Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. The three essential components of a logic block are flip-flops, LUTs, and multiplexers. **Clock signal** An electronic logic signal that oscillates between a high and a low state at a constant frequency. Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard, a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks can be made by dividing another clock signal or using a :ref:`PLL`. +.. _DRAM: + + **DRAM (Dynamic Random Access Memory)** + DRAM is memory that is stored in capacitors and is constantly refreshed. + + Rather than store data in flip-flops, as :ref:`SRAM` does, DRAM constantly reads data into capacitors, row-by-row, in sequence, even when no processing is taking place. Racing the decay of the refresh, the continual refreshing has a negative impact on speed and perforamance and the write process produces extra heat as it uses a strong charge. + + DRAM has a higher storage capacity than other kinds of memory, is cheaper and smaller than SRAM, and memory can be deleted and refreshed while running a program. + + DRAM is incompatible with SRAM. To create a :ref:`SoC` with DRAM requires the design of capacitors; creating a SoC with SRAM requires the design of flip-flops. + **DUT (Device under test)** A physical chip or logic circuit being tested at simulation. - The results of the testing can result in a chip being given a grade to represent the extent to which it met the tolerance values. + The results of the testing can result in a chip being given a grade to represent the extent to which it meets tolerance values. + + **Elaboration** + Elaboration is the process of constructing a design hierarchy from pre-built modules. + + Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the HDL code is analyzed to produce a netlist that lists the required logic elements and interconnects. + + Elaboration is followed by :ref:`synthesis`, :ref:`Place and route`, and :ref:`bistream generation`. + +.. _FIFO: + + **FIFO (First In First Out)** + First in, first out is a method for organizing the manipulation of data, especially in a buffer, where the first (oldest) entry is processed first. + + An elementary building block of integrated circuits, FIFOs are used when crossing clock domains, buffering data, or storing data for use at a later time. **Finite state machine** A mathematical model describing a system with a limited number of conditional states of being. @@ -48,7 +83,7 @@ Glossary An edge-triggered device, flip-flops react to the edge of a pulse and have two stable states that they ‘flip’ and ‘flop’ between. - Modern digital design centres around the D flip-flop (DFF) with Set, Reset, and Enable inputs. + Modern digital design centres around the D flip-flop (DFF) with Set, Reset, and Enable inputs. The D stands for data or delay, the signals to be stored. .. _FPGA: @@ -62,19 +97,17 @@ Glossary **Hardware register** Circuits, typically composed of D flip-flops (DFF), that hold configuration and status information. - At a lower level, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. + Written in low level HDL code, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. **HDL (Hardware definition language)** A hardware definition language, such as Amaranth, describes the structure and timing of electronic circuits and digital logic circuits. - Modern HDLs include synthesizable code that describes the synchronous logic (registers), combinational logic (logic gates), and behavioural code (used in testing) to describe a circuit. + Modern HDLs include synthesizable code that characterises the synchronous logic (registers), combinational logic (logic gates), and behavioural code (used in testing) that describe a circuit. **IC (Integrated circuit)** - An integrated circuit is a computer chip that has an electronic circuit embedded in it. + An integrated circuit has many electronic components embedded on a single chip. - The circuit is a small wafer, usually made of semiconducting material, that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). - - These components can perform calculations and store data using either digital or analog technology. + The circuit is a small wafer, usually made of semiconducting material, that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). These components can perform calculations and store data using either digital or analog technology. Digital ICs use logic gates that work only with values of 1s and 0s. @@ -83,10 +116,10 @@ Glossary Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. - **Logic synthesizers** - The process of translating a high-level logic definition to lower level flip-flops and logic gates. + **Logic synthesis** + The process of translating a high-level logic definition to lower-level flip-flops and logic gates. - High-level language, written in a program like Python, is translated to register transfer level language. +To achieve this, high-level language, written in a program like Python, is translated to lower-level register transfer level language (:ref:`RTL`) to simulate the behaviour of the circuit for testing. **LUT (Look up table)** An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. @@ -98,35 +131,52 @@ Glossary **MCU (Microcontroller unit)** An integrated circuit designed to govern a specific operation in an embedded system. - An MCU is comprised of a CPU, onboard memory (SRAM, peripherals, and, usually, clock functions. + An MCU integrates a CPU, onboard memory (may be volatile, may be non-volatile), peripherals for communication, and, usually, clock functions. A complex MCU can be described as a system on chip :ref:`SoC(). **Memory-mapped peripheral** Hardware devices mapped to the memory address space of a microprocessor. The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. - A memory-mapped peripheral behaves and looks like physical memory but isn't physical memory. + A memory-mapped peripheral behaves (and looks) like physical memory but isn't physical memory. + + **Microprocessor** + A microprocessor is a miniature, programmable digital device — a tiny computer on a chip — that retrieves instructions from memory, decodes and executes them, and returns the output. + + Microprocessors contain the arithmetic, logic, and control circuitry necessary to perform the functions of a digital computer’s central processing unit. **Multiplexer** - A combinational logic circuit designed to switch one of several inputs through to a single common output by the application of a control signal. + A combinational logic circuit designed to switch one of several control signals to a single common output by the application of a control signal. A multiplexer selects between several input signals and forwards the selected input to a single output. - This makes it possible for several input signals to access one device or resource instead of having one device per input signal. They use high speed logic gates to switch digital or binary data through to a single output. + **Netlist** + Netlists describe the components and connectivity of an electronic circuit. + + Netlists can be generated at different points in the toolchain process: after synthesis, where the placement information will not be available; and after place and route, when the placement information will be included. .. _PLL: **PLL (Phase-locked loop)** - A phase-locked loop is an electronic circuit with a voltage-driven oscillator that constantly adjusts in response to an input signal. + A phase-locked loop is an electronic circuit with a controllable oscillator that constantly adjusts in response to an input signal. - Its purpose is to increase or decrease its output to stabilise a signal on a noisy channel or where data transfer has been interrupted. + Its purpose is to generate a derived clock signal that can be faster or slower than the input signal. The derived clock signal can be the result of dividing an input frequency. PLLs can also increae frequency by a non-integer factor. + + Where multiple clock domains are interacting synchronously, PLLs use a fixed phase relationship. + +.. _Place and route: + + **Place and route** + The process of deciding the placement of components on a chip and the related wiring between those components. + + Place and route involved complicated maths problems that require optimization and are usually performed by software to produce a layout schema for a chip. **Propagation delay** - The time required to change the output from one logic state to another logic state after input is applied. + The time required to change the output from one logic state to another logic state after input is changed. - In simplified terms, the time it takes for a signal to move from source to destination. The timing begins when the input to a logic gate becomes stable and valid to change and ends when the output of that logic gate is stable and valid to change. + In simplified terms, the time it takes for a signal to move from source to destination. - The propagation delay of a complete circuit is calculated by identifying the longest path of propagation delay from input to output and adding each propagation delay along the path. + The maximum speed at which a synchronous logic circuit works can be determined by combining the longest path of propagation delay from input to output with the maximum combined propagation delay. Bear in mind that, alongside logic gates, wires also have propogation delay. **Register** A memory device that can store a specific number of data bits. @@ -135,28 +185,55 @@ Glossary A number of flip-flops can be combined to store binary words. The length of the stored binary word depends on the number of flip-flops that make up the register. - **Register transfer level (RTL)** - RTL is used to create high-level representations of a circuit, from which lower-level representations and wiring can be derived. +.. _RTL: + + **Register transfer level (RTL)** + RTL, the lowest abstraction level for developing FPGAs, is used to create a representation of synchronous digital circuits between hardware registers. + + Hardware definition language is tranformed to RTL which then defines the circuit at gate level. The representation can be verified via simulation. - It models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. +.. _Simulation: **Simulation** - A process in which a model of an electronic circuit is replicated and analysed to verify its functionality. + A process in which a model of an electronic circuit is analysed by a computer program to validate its functionality. + + Simulation models the behaviour of a circuit; it does not model the hardware components described by the HDL. Despite being written in HDL, the simulator treats the code as event-driven parallel programming language to run programs on a particular operating system or to port a system that doesn't have an FPGA. + + Simulation is an invaluable tool for ensuring a circuit works the way it was intended to and enables designers to rapidly iterate designs. - Simulation is an invaluable tool for ensuring a circuit works the way it was intended to by checking accuracy, capacity, and performance. It also enables designers to rapidly iterate designs and test them to find the optimal configuration. +.. _SoC: **SoC (System on Chip)** - An integrated circuit, containing almost all the circuitry and components an electronic system requires. + An integrated circuit, containing almost all the circuitry and components an electronic system (smartphone, small embedded devices) requires. + + In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces — into a single chip. + + SoCs are typically built around a microprocessor, microcontroller, or specialised integrated circuit. This increases performance, reduces power consumption, and requires a smaller footprint on a printed circuit board. + + SoCs are more complex than a microcontroller with a higher degree of integration and a greater variety of perhipherals. - In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces, secondary storage interfaces — into a single chip. SoCs are typically built around a microprocessor, microcontroller, or specialised integrated circuit. This increases performance, reduces power consumption, and requires a smaller semiconductor die area. +.. _SRAM: + + **SRAM** + Static Random Access Memory (SRAM) is volatile memory that stores data whilst power is supplied (if the power is turned off, data is lost). + + SRAM uses flip-flops to store bits and holds that value until the opposite value replaces it. SRAM is faster in operation than :ref:`DRAM` as it doesn't require a refresh process. + + In comparison with DRAM, SRAM has a lower power consumption, is more expensive to purchase, has lower storaage capacity, and is more complex in design. + + SRAM is incompatible with DRAM. + + +.. _Synthesis: + + **Synthesis** + Synthesis is the process of building a netlist from a circuit design model. + + Synthesis represents the hardware definition language as register transfer level which automatically transfers into gates. **Waveform** A mathematical (logical) description of a signal. - Periodic waveforms provide a clock signal for FPGAs. - Waveforms have three main characteristics: period, the length of time the waveform takes to repeat; frequency, the number of times the waveform repeats within a one second time period; and amplitude, the magnitude or intensity of the signal waveform measured in volts or amps. - The waveform of an electrical signal can be visualised in an oscilloscope or instrument that can capture and plot the variations in the signal. The square waveform is commonly used to represent digital information. - - A waveform dump, one of the outputs of simulation, is used in problem resolution. \ No newline at end of file + The waveform of an electrical signal can be visualised using an oscilloscope. The square waveform is commonly used to represent digital information. A waveform dump, one of the outputs of simulation, can be used to measure the performance of devices a CPU. \ No newline at end of file From fa750d5bb3e57536b7375c4abd4e21d2d384a714 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 30 Aug 2023 16:06:03 +0100 Subject: [PATCH 21/45] Expanded new terms --- docs/glossary.rst | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 44d8b2b2b..e5c4614a4 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -18,8 +18,11 @@ Glossary Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. .. _Bitstream generation: + **Bitstream generation** - + The code that configures the flash memomory or external storage device to boot the FPGA at power on. + + The final step in translating requirements into circuits on a chip, the code in the bitstream operationalises requirements into logic blocks and interconnects on the FPGA chip. **Block RAM (BRAM)** @@ -27,7 +30,7 @@ Glossary BRAM, sometimes called embedded RAM, doesn't need refreshing (as DRAM does) and, like SRAM, doesn't need a memory controller. Single-port BRAM can either read or write on the port; dual-port BRAM supports read and write for any two addresses and both ports can read *and* write. - BRAM :ref:`FIFO`s are used to cross clock domains or to buffer data between two interfaces. + BRAM :ref:`FIFO` is used to cross clock domains or to buffer data between two interfaces. **CLB (Configurable logic block)** The basic repeating logic block on an FPGA, the purpose of CLBs is to implement combinational and sequential logic on an FPGA. @@ -60,14 +63,14 @@ Glossary **Elaboration** Elaboration is the process of constructing a design hierarchy from pre-built modules. - Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the HDL code is analyzed to produce a netlist that lists the required logic elements and interconnects. + Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the HDL code is analyzed to produce a netlist that itemizes the required logic elements and interconnects. - Elaboration is followed by :ref:`synthesis`, :ref:`Place and route`, and :ref:`bistream generation`. + In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`place and route`, and :ref:`bistream generation`. .. _FIFO: **FIFO (First In First Out)** - First in, first out is a method for organizing the manipulation of data, especially in a buffer, where the first (oldest) entry is processed first. + First in, first out is a method for organizing the processing of data, especially in a buffer, where the first (oldest) entry is processed first. An elementary building block of integrated circuits, FIFOs are used when crossing clock domains, buffering data, or storing data for use at a later time. @@ -111,6 +114,11 @@ Glossary Digital ICs use logic gates that work only with values of 1s and 0s. + **JTAG** + JTAG (Joint Test Action Group) is an industry standard for verifying designs and testing devices like micro controllers and FPGAs after manufacture. + + JTAG is a hardware interface that provides a way to communicate directly with the microchips on a board. It enables the testing, via software, of all the different interconnects without having to physically probe the connections. + **Logic gate** An elementary building block of integrated circuits, logic gates perform logical operations on binary inputs and outputs. @@ -118,8 +126,8 @@ Glossary **Logic synthesis** The process of translating a high-level logic definition to lower-level flip-flops and logic gates. - -To achieve this, high-level language, written in a program like Python, is translated to lower-level register transfer level language (:ref:`RTL`) to simulate the behaviour of the circuit for testing. + + To achieve this, high-level language, written in a program like Python, is translated to lower-level register transfer level (:ref:`RTL`) to simulate the behaviour of the circuit for testing. **LUT (Look up table)** An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. @@ -134,17 +142,16 @@ To achieve this, high-level language, written in a program like Python, is trans An MCU integrates a CPU, onboard memory (may be volatile, may be non-volatile), peripherals for communication, and, usually, clock functions. A complex MCU can be described as a system on chip :ref:`SoC(). **Memory-mapped peripheral** - Hardware devices mapped to the memory address space of a microprocessor. - - The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. + Hardware devices, mapped to the memory address space of a microprocessor, are known as memory-mapped peripherals. - A memory-mapped peripheral behaves (and looks) like physical memory but isn't physical memory. + The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. A memory-mapped peripheral behaves like physical memory but isn't physical memory. **Microprocessor** A microprocessor is a miniature, programmable digital device — a tiny computer on a chip — that retrieves instructions from memory, decodes and executes them, and returns the output. Microprocessors contain the arithmetic, logic, and control circuitry necessary to perform the functions of a digital computer’s central processing unit. + **Multiplexer** A combinational logic circuit designed to switch one of several control signals to a single common output by the application of a control signal. @@ -160,16 +167,16 @@ To achieve this, high-level language, written in a program like Python, is trans **PLL (Phase-locked loop)** A phase-locked loop is an electronic circuit with a controllable oscillator that constantly adjusts in response to an input signal. - Its purpose is to generate a derived clock signal that can be faster or slower than the input signal. The derived clock signal can be the result of dividing an input frequency. PLLs can also increae frequency by a non-integer factor. + Its purpose is to generate a derived clock signal that can be faster or slower than the input signal. The derived clock signal can be the result of dividing an input frequency. PLLs can also increase frequency by a non-integer factor. Where multiple clock domains are interacting synchronously, PLLs use a fixed phase relationship. .. _Place and route: **Place and route** - The process of deciding the placement of components on a chip and the related wiring between those components. - - Place and route involved complicated maths problems that require optimization and are usually performed by software to produce a layout schema for a chip. + The process of deciding the placement of components on a chip and the related wiring between those components. + + Place and route routines involve complicated maths problems that require optimization. These routines are usually performed by software and produce a layout schema for a chip. **Propagation delay** The time required to change the output from one logic state to another logic state after input is changed. @@ -229,7 +236,7 @@ To achieve this, high-level language, written in a program like Python, is trans **Synthesis** Synthesis is the process of building a netlist from a circuit design model. - Synthesis represents the hardware definition language as register transfer level which automatically transfers into gates. + Synthesis represents the hardware definition language as register transfer level that is automatically transfered into gates. **Waveform** A mathematical (logical) description of a signal. From e43488674990d78fc75226f5e0e11d224339a6dc Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 30 Aug 2023 16:21:33 +0100 Subject: [PATCH 22/45] typos --- docs/glossary.rst | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index e5c4614a4..4fe99e81f 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -17,7 +17,7 @@ Glossary Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. -.. _Bitstream generation: +.. _Bistream generation: **Bitstream generation** The code that configures the flash memomory or external storage device to boot the FPGA at power on. @@ -65,7 +65,7 @@ Glossary Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the HDL code is analyzed to produce a netlist that itemizes the required logic elements and interconnects. - In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`place and route`, and :ref:`bistream generation`. + In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`place and route`, and :ref:`bitstream generation`. .. _FIFO: @@ -115,9 +115,9 @@ Glossary Digital ICs use logic gates that work only with values of 1s and 0s. **JTAG** - JTAG (Joint Test Action Group) is an industry standard for verifying designs and testing devices like micro controllers and FPGAs after manufacture. - - JTAG is a hardware interface that provides a way to communicate directly with the microchips on a board. It enables the testing, via software, of all the different interconnects without having to physically probe the connections. + JTAG (Joint Test Action Group) is an industry standard for verifying designs and testing devices like micro controllers and FPGAs after manufacture. + + JTAG is a hardware interface that provides a way to communicate directly with the microchips on a board. It enables the testing, via software, of all the different interconnects without having to physically probe the connections. **Logic gate** An elementary building block of integrated circuits, logic gates perform logical operations on binary inputs and outputs. @@ -125,9 +125,9 @@ Glossary Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. **Logic synthesis** - The process of translating a high-level logic definition to lower-level flip-flops and logic gates. - - To achieve this, high-level language, written in a program like Python, is translated to lower-level register transfer level (:ref:`RTL`) to simulate the behaviour of the circuit for testing. + The process of translating a high-level logic definition to lower-level flip-flops and logic gates. + + To achieve this, high-level language, written in a program like Python, is translated to lower-level register transfer level (:ref:`RTL`) to simulate the behaviour of the circuit for testing. **LUT (Look up table)** An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. From 13f064acf550afdf8fc814e4bca907e4b17503d9 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 30 Aug 2023 16:24:06 +0100 Subject: [PATCH 23/45] links in a row --- docs/glossary.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 4fe99e81f..dc76ee54d 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -65,7 +65,7 @@ Glossary Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the HDL code is analyzed to produce a netlist that itemizes the required logic elements and interconnects. - In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`place and route`, and :ref:`bitstream generation`. + In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`Place and route`, and :ref:`Bitstream generation`. .. _FIFO: From 99a97e49df4b0577802b3212419831db53e3129e Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 30 Aug 2023 16:28:32 +0100 Subject: [PATCH 24/45] test --- docs/glossary.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index dc76ee54d..9b05b2361 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -65,7 +65,7 @@ Glossary Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the HDL code is analyzed to produce a netlist that itemizes the required logic elements and interconnects. - In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`Place and route`, and :ref:`Bitstream generation`. + In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`place and route`, and :ref:`bitstream generation`. .. _FIFO: @@ -103,7 +103,7 @@ Glossary Written in low level HDL code, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. **HDL (Hardware definition language)** - A hardware definition language, such as Amaranth, describes the structure and timing of electronic circuits and digital logic circuits. + A hardware definition language, such as :ref:`Amaranth` describes the structure and timing of electronic circuits and digital logic circuits. Modern HDLs include synthesizable code that characterises the synchronous logic (registers), combinational logic (logic gates), and behavioural code (used in testing) that describe a circuit. From b7186e768413d7b833f1a139e72111767666bc9e Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 30 Aug 2023 16:32:17 +0100 Subject: [PATCH 25/45] more testing --- docs/glossary.rst | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 9b05b2361..75ff893d5 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -3,6 +3,8 @@ Glossary ======== +.. _Amaranth: + **Amaranth** An open-source toolchain that uses the Python programming language. @@ -17,7 +19,7 @@ Glossary Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. -.. _Bistream generation: +.. _Bitstream generation: **Bitstream generation** The code that configures the flash memomory or external storage device to boot the FPGA at power on. @@ -65,7 +67,7 @@ Glossary Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the HDL code is analyzed to produce a netlist that itemizes the required logic elements and interconnects. - In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`place and route`, and :ref:`bitstream generation`. + In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`place and route`, and :ref:`bitstream generation`. .. _FIFO: @@ -103,7 +105,7 @@ Glossary Written in low level HDL code, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. **HDL (Hardware definition language)** - A hardware definition language, such as :ref:`Amaranth` describes the structure and timing of electronic circuits and digital logic circuits. + A hardware definition language, such as :ref:`Amaranth`, describes the structure and timing of electronic circuits and digital logic circuits. Modern HDLs include synthesizable code that characterises the synchronous logic (registers), combinational logic (logic gates), and behavioural code (used in testing) that describe a circuit. From 8f5f4ff87537c5c3a9263ffa1995ff2eba2b1abe Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 30 Aug 2023 16:39:56 +0100 Subject: [PATCH 26/45] spacing --- docs/glossary.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/docs/glossary.rst b/docs/glossary.rst index 75ff893d5..cfca4b691 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -10,6 +10,8 @@ Glossary Amaranth makes developing hardware definitions based on synchronous digital logic more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. +.. _ASIC: + **ASIC (Application-specific integrated circuit)** A non-standard integrated circuit chip made for a specific task or product. @@ -26,6 +28,7 @@ Glossary The final step in translating requirements into circuits on a chip, the code in the bitstream operationalises requirements into logic blocks and interconnects on the FPGA chip. +.. _BRAM: **Block RAM (BRAM)** Block RAM is on-chip random access memory that stores large amounts of data and is distributed evenly across a chip. @@ -34,6 +37,8 @@ Glossary BRAM :ref:`FIFO` is used to cross clock domains or to buffer data between two interfaces. +.. _CLB: + **CLB (Configurable logic block)** The basic repeating logic block on an FPGA, the purpose of CLBs is to implement combinational and sequential logic on an FPGA. From f51b9cf454d057be4f279328702eaed6f37283be Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 30 Aug 2023 16:42:08 +0100 Subject: [PATCH 27/45] more spacing --- docs/glossary.rst | 4 ---- 1 file changed, 4 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index cfca4b691..12299b85b 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -9,7 +9,6 @@ Glossary An open-source toolchain that uses the Python programming language. Amaranth makes developing hardware definitions based on synchronous digital logic more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. - .. _ASIC: **ASIC (Application-specific integrated circuit)** @@ -20,14 +19,12 @@ Glossary ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce so design and testing are critical to the success of ASIC development. Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. - .. _Bitstream generation: **Bitstream generation** The code that configures the flash memomory or external storage device to boot the FPGA at power on. The final step in translating requirements into circuits on a chip, the code in the bitstream operationalises requirements into logic blocks and interconnects on the FPGA chip. - .. _BRAM: **Block RAM (BRAM)** @@ -36,7 +33,6 @@ Glossary BRAM, sometimes called embedded RAM, doesn't need refreshing (as DRAM does) and, like SRAM, doesn't need a memory controller. Single-port BRAM can either read or write on the port; dual-port BRAM supports read and write for any two addresses and both ports can read *and* write. BRAM :ref:`FIFO` is used to cross clock domains or to buffer data between two interfaces. - .. _CLB: **CLB (Configurable logic block)** From 04551f0be22c52a163eb590196bfc388df14479b Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Wed, 30 Aug 2023 16:47:47 +0100 Subject: [PATCH 28/45] more spacing testing --- docs/glossary.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 12299b85b..4dff2bf19 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -9,6 +9,7 @@ Glossary An open-source toolchain that uses the Python programming language. Amaranth makes developing hardware definitions based on synchronous digital logic more intuitive by using the popular Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. + .. _ASIC: **ASIC (Application-specific integrated circuit)** @@ -19,12 +20,14 @@ Glossary ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce so design and testing are critical to the success of ASIC development. Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. + .. _Bitstream generation: **Bitstream generation** The code that configures the flash memomory or external storage device to boot the FPGA at power on. The final step in translating requirements into circuits on a chip, the code in the bitstream operationalises requirements into logic blocks and interconnects on the FPGA chip. + .. _BRAM: **Block RAM (BRAM)** @@ -33,6 +36,7 @@ Glossary BRAM, sometimes called embedded RAM, doesn't need refreshing (as DRAM does) and, like SRAM, doesn't need a memory controller. Single-port BRAM can either read or write on the port; dual-port BRAM supports read and write for any two addresses and both ports can read *and* write. BRAM :ref:`FIFO` is used to cross clock domains or to buffer data between two interfaces. + .. _CLB: **CLB (Configurable logic block)** @@ -233,7 +237,6 @@ Glossary SRAM is incompatible with DRAM. - .. _Synthesis: **Synthesis** From 65434cdf2acf0512eafcd26b959121f66d760ed4 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 31 Aug 2023 12:21:52 +0100 Subject: [PATCH 29/45] testing :term: --- docs/glossary.rst | 39 +++++++++++++++++++++++++++++++++++++++ docs/intro.rst | 2 +- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 4dff2bf19..6f71fd642 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -46,6 +46,8 @@ Glossary Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. The three essential components of a logic block are flip-flops, LUTs, and multiplexers. +.. _Clock signal: + **Clock signal** An electronic logic signal that oscillates between a high and a low state at a constant frequency. @@ -62,11 +64,15 @@ Glossary DRAM is incompatible with SRAM. To create a :ref:`SoC` with DRAM requires the design of capacitors; creating a SoC with SRAM requires the design of flip-flops. +.. _DUT: + **DUT (Device under test)** A physical chip or logic circuit being tested at simulation. The results of the testing can result in a chip being given a grade to represent the extent to which it meets tolerance values. +.. _Elaboration: + **Elaboration** Elaboration is the process of constructing a design hierarchy from pre-built modules. @@ -81,6 +87,8 @@ Glossary An elementary building block of integrated circuits, FIFOs are used when crossing clock domains, buffering data, or storing data for use at a later time. +.. _Finite state machine: + **Finite state machine** A mathematical model describing a system with a limited number of conditional states of being. @@ -88,6 +96,8 @@ Glossary This approach enables engineers to study and test each input and output scenario. +.. _Flip-flop: + **Flip-flop** An elementary building block of integrated circuits, flip-flops are the basic memory element for storing a single bit of binary data. @@ -104,16 +114,22 @@ Glossary FPGAs combine speed, programmability, and flexibility. In addition, they can process very large volumes of data by duplicating circuits and running them in parallel. +.. _Hardware register: + **Hardware register** Circuits, typically composed of D flip-flops (DFF), that hold configuration and status information. Written in low level HDL code, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. +.. _HDL: + **HDL (Hardware definition language)** A hardware definition language, such as :ref:`Amaranth`, describes the structure and timing of electronic circuits and digital logic circuits. Modern HDLs include synthesizable code that characterises the synchronous logic (registers), combinational logic (logic gates), and behavioural code (used in testing) that describe a circuit. +.. _IC: + **IC (Integrated circuit)** An integrated circuit has many electronic components embedded on a single chip. @@ -121,21 +137,29 @@ Glossary Digital ICs use logic gates that work only with values of 1s and 0s. +.. _JTAG: + **JTAG** JTAG (Joint Test Action Group) is an industry standard for verifying designs and testing devices like micro controllers and FPGAs after manufacture. JTAG is a hardware interface that provides a way to communicate directly with the microchips on a board. It enables the testing, via software, of all the different interconnects without having to physically probe the connections. +.. _Logic gate: + **Logic gate** An elementary building block of integrated circuits, logic gates perform logical operations on binary inputs and outputs. Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. +.. _Logic synthesis: + **Logic synthesis** The process of translating a high-level logic definition to lower-level flip-flops and logic gates. To achieve this, high-level language, written in a program like Python, is translated to lower-level register transfer level (:ref:`RTL`) to simulate the behaviour of the circuit for testing. +.. _LUT: + **LUT (Look up table)** An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. @@ -143,27 +167,36 @@ Glossary LUTs can be used to implement an arbitrary logic gate with the same or fewer inputs: a 4-LUT can implement 1, 2, 3, or 4 inputs. If five inputs are required, two 4-LUTS can be combined but at the expense of propogation delay. +.. _MCU: + **MCU (Microcontroller unit)** An integrated circuit designed to govern a specific operation in an embedded system. An MCU integrates a CPU, onboard memory (may be volatile, may be non-volatile), peripherals for communication, and, usually, clock functions. A complex MCU can be described as a system on chip :ref:`SoC(). +.. _Memory-mapped peripheral: + **Memory-mapped peripheral** Hardware devices, mapped to the memory address space of a microprocessor, are known as memory-mapped peripherals. The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. A memory-mapped peripheral behaves like physical memory but isn't physical memory. +.. _Microprocessor: + **Microprocessor** A microprocessor is a miniature, programmable digital device — a tiny computer on a chip — that retrieves instructions from memory, decodes and executes them, and returns the output. Microprocessors contain the arithmetic, logic, and control circuitry necessary to perform the functions of a digital computer’s central processing unit. +.. _Multiplexer: **Multiplexer** A combinational logic circuit designed to switch one of several control signals to a single common output by the application of a control signal. A multiplexer selects between several input signals and forwards the selected input to a single output. +.. _Netlist: + **Netlist** Netlists describe the components and connectivity of an electronic circuit. @@ -185,6 +218,8 @@ Glossary Place and route routines involve complicated maths problems that require optimization. These routines are usually performed by software and produce a layout schema for a chip. +.. _Propogation delay: + **Propagation delay** The time required to change the output from one logic state to another logic state after input is changed. @@ -192,6 +227,8 @@ Glossary The maximum speed at which a synchronous logic circuit works can be determined by combining the longest path of propagation delay from input to output with the maximum combined propagation delay. Bear in mind that, alongside logic gates, wires also have propogation delay. +.. _Register: + **Register** A memory device that can store a specific number of data bits. @@ -244,6 +281,8 @@ Glossary Synthesis represents the hardware definition language as register transfer level that is automatically transfered into gates. +.. _Waveform: + **Waveform** A mathematical (logical) description of a signal. diff --git a/docs/intro.rst b/docs/intro.rst index 4598d9f6d..b4b410b0f 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -18,7 +18,7 @@ The Amaranth language The :doc:`Amaranth hardware description language ` is a Python library for modeling of synchronous logic. Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys_, or converted to human-readable Verilog code for use with industry-standard toolchains. -By relying on the flexibility, rich functionality and widespread adoption of the Python language, the Amaranth language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and finite state machines, and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs; Python libraries can be seamlessly used with Amaranth during design or verification; and Python development tools can process Amaranth code. +By relying on the flexibility, rich functionality and widespread adoption of the Python language, the :term:`Amaranth` language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and finite state machines, and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs; Python libraries can be seamlessly used with Amaranth during design or verification; and Python development tools can process Amaranth code. A core design principle of the Amaranth language is to be not only easy to use, but also hard to accidentally misuse. Some HDLs provide functionality that has unexpected and undesirable behavior in synthesis, often with expensive consequences, and require a significant effort in learning a "safe" coding style and adopting third-party linting tools. Amaranth lacks non-synthesizable constructs and avoids error-prone inference in favor of explicit instantiation. It has many diagnostics (and regularly adds new ones) highlighting potential design issues. Most importantly, all usability issues are considered `reportable bugs`_. From f4736dc87629a07aebc259798461234435d652eb Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 31 Aug 2023 12:40:12 +0100 Subject: [PATCH 30/45] change to clb --- docs/intro.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/intro.rst b/docs/intro.rst index b4b410b0f..4598d9f6d 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -18,7 +18,7 @@ The Amaranth language The :doc:`Amaranth hardware description language ` is a Python library for modeling of synchronous logic. Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys_, or converted to human-readable Verilog code for use with industry-standard toolchains. -By relying on the flexibility, rich functionality and widespread adoption of the Python language, the :term:`Amaranth` language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and finite state machines, and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs; Python libraries can be seamlessly used with Amaranth during design or verification; and Python development tools can process Amaranth code. +By relying on the flexibility, rich functionality and widespread adoption of the Python language, the Amaranth language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and finite state machines, and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs; Python libraries can be seamlessly used with Amaranth during design or verification; and Python development tools can process Amaranth code. A core design principle of the Amaranth language is to be not only easy to use, but also hard to accidentally misuse. Some HDLs provide functionality that has unexpected and undesirable behavior in synthesis, often with expensive consequences, and require a significant effort in learning a "safe" coding style and adopting third-party linting tools. Amaranth lacks non-synthesizable constructs and avoids error-prone inference in favor of explicit instantiation. It has many diagnostics (and regularly adds new ones) highlighting potential design issues. Most importantly, all usability issues are considered `reportable bugs`_. From 00a9d54452d0c97f551543bf227014687b1e0b34 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 31 Aug 2023 12:40:33 +0100 Subject: [PATCH 31/45] chagne to clb --- docs/glossary.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 6f71fd642..ab785d991 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -44,7 +44,7 @@ Glossary Be aware that different FPGA manufacturers use different names for this component. - Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. The three essential components of a logic block are flip-flops, LUTs, and multiplexers. + Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. The three essential components of a logic block are :ref:`flip-flop`s, :ref:`LUT`s, and :ref:`multiplexer`s. .. _Clock signal: From e63827f9cb49cd9bfef679df42eb71789fd3f6e3 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 31 Aug 2023 12:43:22 +0100 Subject: [PATCH 32/45] clb second time --- docs/glossary.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index ab785d991..3cfec2e1b 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -44,7 +44,7 @@ Glossary Be aware that different FPGA manufacturers use different names for this component. - Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. The three essential components of a logic block are :ref:`flip-flop`s, :ref:`LUT`s, and :ref:`multiplexer`s. + Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. The three essential components of a logic block are :ref:`flip-flop`s, :ref:`LUT`s, and :ref:`multiplexer`s. .. _Clock signal: From 33add18873bb1cb106a8e607ac242546d210d84b Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 31 Aug 2023 12:53:55 +0100 Subject: [PATCH 33/45] clb again --- docs/glossary.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 3cfec2e1b..eb757c4c0 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -44,7 +44,7 @@ Glossary Be aware that different FPGA manufacturers use different names for this component. - Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. The three essential components of a logic block are :ref:`flip-flop`s, :ref:`LUT`s, and :ref:`multiplexer`s. + Each FPGA contains many logic blocks that are surrounded by a system of programmable interconnects (I/O blocks), called a fabric, that routes signals between the CLBs. The three essential components of a logic block are :ref:`flip-flops`, :ref:`LUTs`, and :ref:`multiplexers`. .. _Clock signal: @@ -172,7 +172,7 @@ Glossary **MCU (Microcontroller unit)** An integrated circuit designed to govern a specific operation in an embedded system. - An MCU integrates a CPU, onboard memory (may be volatile, may be non-volatile), peripherals for communication, and, usually, clock functions. A complex MCU can be described as a system on chip :ref:`SoC(). + An MCU integrates a CPU, onboard memory (may be volatile, may be non-volatile), peripherals for communication, and, usually, clock functions. A complex MCU can be described as a system on chip :ref:`(SoC)`. .. _Memory-mapped peripheral: From d4a7f992e306c7e64b2b9e5a63b186ea17953cc4 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 31 Aug 2023 14:43:47 +0100 Subject: [PATCH 34/45] links and more links --- docs/glossary.rst | 50 +++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index eb757c4c0..4e30d15eb 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -58,7 +58,7 @@ Glossary **DRAM (Dynamic Random Access Memory)** DRAM is memory that is stored in capacitors and is constantly refreshed. - Rather than store data in flip-flops, as :ref:`SRAM` does, DRAM constantly reads data into capacitors, row-by-row, in sequence, even when no processing is taking place. Racing the decay of the refresh, the continual refreshing has a negative impact on speed and perforamance and the write process produces extra heat as it uses a strong charge. + Rather than store data in flip-flops, as :ref:`SRAM` does, DRAM constantly reads data into capacitors, row-by-row, in sequence, even when no processing is taking place. Racing the decay of the refresh has a negative impact on speed and perforamance and the write process produces extra heat as it uses a strong charge. DRAM has a higher storage capacity than other kinds of memory, is cheaper and smaller than SRAM, and memory can be deleted and refreshed while running a program. @@ -67,7 +67,7 @@ Glossary .. _DUT: **DUT (Device under test)** - A physical chip or logic circuit being tested at simulation. + A physical chip or logic circuit being tested at :ref:'simulation`. The results of the testing can result in a chip being given a grade to represent the extent to which it meets tolerance values. @@ -76,14 +76,14 @@ Glossary **Elaboration** Elaboration is the process of constructing a design hierarchy from pre-built modules. - Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the HDL code is analyzed to produce a netlist that itemizes the required logic elements and interconnects. + Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the :ref:`HDL` code is analyzed to produce a :ref:`netlist` that itemizes the required logic elements and interconnects. In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`place and route`, and :ref:`bitstream generation`. .. _FIFO: **FIFO (First In First Out)** - First in, first out is a method for organizing the processing of data, especially in a buffer, where the first (oldest) entry is processed first. + First in, first out is a method for organizing the processing of data, especially in a buffer, where the oldest entry is processed first. An elementary building block of integrated circuits, FIFOs are used when crossing clock domains, buffering data, or storing data for use at a later time. @@ -110,16 +110,16 @@ Glossary **FPGA (Field Programmable Gate Array)** A reconfigurable integrated circuit containing internal hardware blocks with user-programmable interconnects to create a customised application. - The device’s physical attributes are programmed using a hardware definition language. User-programmable I/O blocks interface between the FPGA and external devices. + The device’s physical attributes are programmed using a :ref:`hardware definition language`. User-programmable I/O blocks interface between the FPGA and external devices. FPGAs combine speed, programmability, and flexibility. In addition, they can process very large volumes of data by duplicating circuits and running them in parallel. .. _Hardware register: **Hardware register** - Circuits, typically composed of D flip-flops (DFF), that hold configuration and status information. + Circuits, typically composed of D :ref:`flip-flops` (DFF), that hold configuration and status information. - Written in low level HDL code, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. + Written in low level :ref:`HDL` code, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. .. _HDL: @@ -135,12 +135,12 @@ Glossary The circuit is a small wafer, usually made of semiconducting material, that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). These components can perform calculations and store data using either digital or analog technology. - Digital ICs use logic gates that work only with values of 1s and 0s. + Digital ICs use :ref:`logic gates` that work only with values of 1s and 0s. .. _JTAG: **JTAG** - JTAG (Joint Test Action Group) is an industry standard for verifying designs and testing devices like micro controllers and FPGAs after manufacture. + JTAG (Joint Test Action Group) is an industry standard for verifying designs and testing devices — micro controllers, FPGAs, etc. — after manufacture. JTAG is a hardware interface that provides a way to communicate directly with the microchips on a board. It enables the testing, via software, of all the different interconnects without having to physically probe the connections. @@ -154,16 +154,16 @@ Glossary .. _Logic synthesis: **Logic synthesis** - The process of translating a high-level logic definition to lower-level flip-flops and logic gates. + The process of translating a high-level logic definition to lower-level :ref:`flip-flops` and :ref:`logic gates`. - To achieve this, high-level language, written in a program like Python, is translated to lower-level register transfer level (:ref:`RTL`) to simulate the behaviour of the circuit for testing. + To achieve this, high-level code, written in a program like Python, is translated to register transfer level (:ref:`RTL`) to simulate the behaviour of the circuit for testing. .. _LUT: **LUT (Look up table)** An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. - A single input LUT is made up of two flip-flops and a multiplexer. This structure can be expanded into a tree to provide the required capacity. The larger the number of multiplexers, the longer the associated propagation delay. + A single input LUT is made up of two :ref:`flip-flops` and a :ref:`multiplexer`. This structure can be expanded into a tree to provide the required capacity. The larger the number of multiplexers, the longer the associated propagation delay. LUTs can be used to implement an arbitrary logic gate with the same or fewer inputs: a 4-LUT can implement 1, 2, 3, or 4 inputs. If five inputs are required, two 4-LUTS can be combined but at the expense of propogation delay. @@ -177,16 +177,16 @@ Glossary .. _Memory-mapped peripheral: **Memory-mapped peripheral** - Hardware devices, mapped to the memory address space of a microprocessor, are known as memory-mapped peripherals. + Hardware devices, mapped to the memory address space of a :ref:`microprocessor`, are known as memory-mapped peripherals. - The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. A memory-mapped peripheral behaves like physical memory but isn't physical memory. + The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. A memory-mapped peripheral behaves just like physical memory but isn't physical memory. .. _Microprocessor: **Microprocessor** A microprocessor is a miniature, programmable digital device — a tiny computer on a chip — that retrieves instructions from memory, decodes and executes them, and returns the output. - Microprocessors contain the arithmetic, logic, and control circuitry necessary to perform the functions of a digital computer’s central processing unit. + Microprocessors contain the arithmetic, logic, and control circuitry necessary to perform the functions of a computer’s central processing unit. .. _Multiplexer: @@ -214,18 +214,18 @@ Glossary .. _Place and route: **Place and route** - The process of deciding the placement of components on a chip and the related wiring between those components. + Place and route is the process of deciding the placement of components on a chip and the related wiring between those components. Place and route routines involve complicated maths problems that require optimization. These routines are usually performed by software and produce a layout schema for a chip. .. _Propogation delay: **Propagation delay** - The time required to change the output from one logic state to another logic state after input is changed. + Propogation delay is the time required to change the output from one logic state to another logic state after input is changed. In simplified terms, the time it takes for a signal to move from source to destination. - The maximum speed at which a synchronous logic circuit works can be determined by combining the longest path of propagation delay from input to output with the maximum combined propagation delay. Bear in mind that, alongside logic gates, wires also have propogation delay. + The maximum speed at which a synchronous logic circuit works can be determined by combining the longest path of propagation delay from input to output with the maximum combined propagation delay. Bear in mind that not only do logic gates have propogation delay, wires do too. .. _Register: @@ -239,16 +239,16 @@ Glossary .. _RTL: **Register transfer level (RTL)** - RTL, the lowest abstraction level for developing FPGAs, is used to create a representation of synchronous digital circuits between hardware registers. + RTL, the lowest abstraction level for developing :ref:`FPGAs`, is used to create a representation of synchronous digital circuits between :ref:`hardware registers`. - Hardware definition language is tranformed to RTL which then defines the circuit at gate level. The representation can be verified via simulation. + Hardware definition language is tranformed to RTL which then defines the circuit at gate level. The representation can be verified via :ref:`simulation`. .. _Simulation: **Simulation** A process in which a model of an electronic circuit is analysed by a computer program to validate its functionality. - Simulation models the behaviour of a circuit; it does not model the hardware components described by the HDL. Despite being written in HDL, the simulator treats the code as event-driven parallel programming language to run programs on a particular operating system or to port a system that doesn't have an FPGA. + Simulation models the behaviour of a circuit; it does not model the hardware components described by the :ref:`HDL`. Despite being written in HDL, the simulator treats the code as event-driven parallel programming language to run programs on a particular operating system or to port a system that doesn't have an :ref:`FPGA`. Simulation is an invaluable tool for ensuring a circuit works the way it was intended to and enables designers to rapidly iterate designs. @@ -259,7 +259,7 @@ Glossary In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces — into a single chip. - SoCs are typically built around a microprocessor, microcontroller, or specialised integrated circuit. This increases performance, reduces power consumption, and requires a smaller footprint on a printed circuit board. + SoCs are typically built around a :ref:`microprocessor`, :ref:`microcontroller`, or specialised :ref:`integrated circuit`. This increases performance, reduces power consumption, and requires a smaller footprint on a printed circuit board. SoCs are more complex than a microcontroller with a higher degree of integration and a greater variety of perhipherals. @@ -277,9 +277,9 @@ Glossary .. _Synthesis: **Synthesis** - Synthesis is the process of building a netlist from a circuit design model. + Synthesis is the process of building a :ref:``netlist` from a circuit design model. - Synthesis represents the hardware definition language as register transfer level that is automatically transfered into gates. + Synthesis represents the :ref:`hardware definition language`` as :ref:`register transfer level` that is automatically transfered into gates. .. _Waveform: @@ -288,4 +288,4 @@ Glossary Waveforms have three main characteristics: period, the length of time the waveform takes to repeat; frequency, the number of times the waveform repeats within a one second time period; and amplitude, the magnitude or intensity of the signal waveform measured in volts or amps. - The waveform of an electrical signal can be visualised using an oscilloscope. The square waveform is commonly used to represent digital information. A waveform dump, one of the outputs of simulation, can be used to measure the performance of devices a CPU. \ No newline at end of file + The waveform of an electrical signal can be visualised using an oscilloscope. The square waveform is commonly used to represent digital information. A waveform dump, one of the outputs of simulation, can be used to measure the performance of devices. \ No newline at end of file From 3468c4de2c9ace25e6b693fbbb295715f03412d9 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 31 Aug 2023 14:45:58 +0100 Subject: [PATCH 35/45] fixed errors --- docs/glossary.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 4e30d15eb..6dfe5e247 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -259,7 +259,7 @@ Glossary In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces — into a single chip. - SoCs are typically built around a :ref:`microprocessor`, :ref:`microcontroller`, or specialised :ref:`integrated circuit`. This increases performance, reduces power consumption, and requires a smaller footprint on a printed circuit board. + SoCs are typically built around a :ref:`microprocessor`, :ref:`microcontroller`, or specialised :ref:`integrated circuit`. This increases performance, reduces power consumption, and requires a smaller footprint on a printed circuit board. SoCs are more complex than a microcontroller with a higher degree of integration and a greater variety of perhipherals. @@ -279,7 +279,7 @@ Glossary **Synthesis** Synthesis is the process of building a :ref:``netlist` from a circuit design model. - Synthesis represents the :ref:`hardware definition language`` as :ref:`register transfer level` that is automatically transfered into gates. + Synthesis represents the :ref:`hardware definition language` as :ref:`register transfer level` that is automatically transfered into gates. .. _Waveform: From 91d248e6e3295dfe77e16642e716c4bf42b11ff3 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 31 Aug 2023 14:47:55 +0100 Subject: [PATCH 36/45] Last error --- docs/glossary.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 6dfe5e247..e6f2aadb1 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -259,7 +259,7 @@ Glossary In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces — into a single chip. - SoCs are typically built around a :ref:`microprocessor`, :ref:`microcontroller`, or specialised :ref:`integrated circuit`. This increases performance, reduces power consumption, and requires a smaller footprint on a printed circuit board. + SoCs are typically built around a :ref:`microprocessor`, :ref:`microcontroller`, or specialised :ref:`integrated circuit`. This increases performance, reduces power consumption, and requires a smaller footprint on a printed circuit board. SoCs are more complex than a microcontroller with a higher degree of integration and a greater variety of perhipherals. From 7114bc25beee182bf48b423e130eb4b3e5a72e12 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 31 Aug 2023 14:49:20 +0100 Subject: [PATCH 37/45] The last last change --- docs/glossary.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index e6f2aadb1..6e6ede446 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -277,7 +277,7 @@ Glossary .. _Synthesis: **Synthesis** - Synthesis is the process of building a :ref:``netlist` from a circuit design model. + Synthesis is the process of building a :ref:`netlist` from a circuit design model. Synthesis represents the :ref:`hardware definition language` as :ref:`register transfer level` that is automatically transfered into gates. From 8f63d131cab0774603aa385789b2e4da142f22e3 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 31 Aug 2023 15:40:59 +0100 Subject: [PATCH 38/45] Edits --- docs/glossary.rst | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index 6e6ede446..d973f4c21 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -17,23 +17,23 @@ Glossary The term *application* refers to the function the circuit will perform, not to a software application. - ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce so design and testing are critical to the success of ASIC development. + ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce. Design and testing are critical to the success of ASIC development. - Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via simulation. + Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via :ref:`simulation`. .. _Bitstream generation: **Bitstream generation** - The code that configures the flash memomory or external storage device to boot the FPGA at power on. + The code that configures the flash memomory or external storage device to boot an FPGA at power on. - The final step in translating requirements into circuits on a chip, the code in the bitstream operationalises requirements into logic blocks and interconnects on the FPGA chip. + The final step in translating requirements into circuits on a chip, the bitstream defines the logic blocks and interconnects on the FPGA chip. .. _BRAM: **Block RAM (BRAM)** - Block RAM is on-chip random access memory that stores large amounts of data and is distributed evenly across a chip. + Block RAM is on-chip random access memory, stored evenly across a chip, to store large amounts of data. - BRAM, sometimes called embedded RAM, doesn't need refreshing (as DRAM does) and, like SRAM, doesn't need a memory controller. Single-port BRAM can either read or write on the port; dual-port BRAM supports read and write for any two addresses and both ports can read *and* write. + BRAM, sometimes called embedded RAM, doesn't need refreshing (as DRAM does) and, like SRAM, doesn't need a memory controller. Single-port BRAM can either read or write on the single port; dual-port BRAM supports read and write for any two addresses and both ports can read *and* write. BRAM :ref:`FIFO` is used to cross clock domains or to buffer data between two interfaces. @@ -60,7 +60,7 @@ Glossary Rather than store data in flip-flops, as :ref:`SRAM` does, DRAM constantly reads data into capacitors, row-by-row, in sequence, even when no processing is taking place. Racing the decay of the refresh has a negative impact on speed and perforamance and the write process produces extra heat as it uses a strong charge. - DRAM has a higher storage capacity than other kinds of memory, is cheaper and smaller than SRAM, and memory can be deleted and refreshed while running a program. + DRAM has a higher storage capacity than other kinds of memory; is cheaper and smaller than SRAM; and memory can be deleted and refreshed while running a program. DRAM is incompatible with SRAM. To create a :ref:`SoC` with DRAM requires the design of capacitors; creating a SoC with SRAM requires the design of flip-flops. @@ -69,7 +69,7 @@ Glossary **DUT (Device under test)** A physical chip or logic circuit being tested at :ref:'simulation`. - The results of the testing can result in a chip being given a grade to represent the extent to which it meets tolerance values. + Testing can result in a chip being given a grade to represent the extent to which it met tolerance values. .. _Elaboration: @@ -126,7 +126,7 @@ Glossary **HDL (Hardware definition language)** A hardware definition language, such as :ref:`Amaranth`, describes the structure and timing of electronic circuits and digital logic circuits. - Modern HDLs include synthesizable code that characterises the synchronous logic (registers), combinational logic (logic gates), and behavioural code (used in testing) that describe a circuit. + Modern HDLs include synthesizable code that characterises the synchronous logic (:ref:`registers`), combinational logic (:ref:`logic gates`), and behavioural code (used in testing) that describe a circuit. .. _IC: @@ -179,7 +179,7 @@ Glossary **Memory-mapped peripheral** Hardware devices, mapped to the memory address space of a :ref:`microprocessor`, are known as memory-mapped peripherals. - The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. A memory-mapped peripheral behaves just like physical memory but isn't physical memory. + The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. .. _Microprocessor: @@ -207,7 +207,7 @@ Glossary **PLL (Phase-locked loop)** A phase-locked loop is an electronic circuit with a controllable oscillator that constantly adjusts in response to an input signal. - Its purpose is to generate a derived clock signal that can be faster or slower than the input signal. The derived clock signal can be the result of dividing an input frequency. PLLs can also increase frequency by a non-integer factor. + Its purpose is to generate a derived clock signal that can be faster or slower than the input signal. The derived clock signal can be the result of dividing an input frequency. PLLs can increase frequency by a non-integer factor. Where multiple clock domains are interacting synchronously, PLLs use a fixed phase relationship. @@ -232,7 +232,7 @@ Glossary **Register** A memory device that can store a specific number of data bits. - Made up of a series of flip-flops, a register can temporarily store data or a set of instructions for a processor. A register can enable both serial and parallel data transfers, allowing logic operations to be performed on the data stored in it. + Made up of a series of :ref:`flip-flops`, a register can temporarily store data or a set of instructions for a processor. A register can enable both serial and parallel data transfers, allowing logic operations to be performed on the data stored in it. A number of flip-flops can be combined to store binary words. The length of the stored binary word depends on the number of flip-flops that make up the register. From c76c8261a6b2fd6e38898bc353ffe587fbf4aee9 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Mon, 4 Sep 2023 10:33:56 +0100 Subject: [PATCH 39/45] Testing glossary links from other articles --- docs/intro.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/intro.rst b/docs/intro.rst index 4598d9f6d..667b24890 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -18,7 +18,7 @@ The Amaranth language The :doc:`Amaranth hardware description language ` is a Python library for modeling of synchronous logic. Ordinary Python code is used to construct a netlist of a digital circuit, which can be simulated, directly synthesized via Yosys_, or converted to human-readable Verilog code for use with industry-standard toolchains. -By relying on the flexibility, rich functionality and widespread adoption of the Python language, the Amaranth language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and finite state machines, and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs; Python libraries can be seamlessly used with Amaranth during design or verification; and Python development tools can process Amaranth code. +By relying on the flexibility, rich functionality and widespread adoption of the Python language, the Amaranth language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and :term:`finite state machines`, and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs; Python libraries can be seamlessly used with Amaranth during design or verification; and Python development tools can process Amaranth code. A core design principle of the Amaranth language is to be not only easy to use, but also hard to accidentally misuse. Some HDLs provide functionality that has unexpected and undesirable behavior in synthesis, often with expensive consequences, and require a significant effort in learning a "safe" coding style and adopting third-party linting tools. Amaranth lacks non-synthesizable constructs and avoids error-prone inference in favor of explicit instantiation. It has many diagnostics (and regularly adds new ones) highlighting potential design issues. Most importantly, all usability issues are considered `reportable bugs`_. From 0f12f9db915b41414e9fe146380e4589b03ca937 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Mon, 4 Sep 2023 11:08:14 +0100 Subject: [PATCH 40/45] Abbreviations --- docs/glossary.rst | 22 +++++++++++----------- docs/intro.rst | 2 +- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index d973f4c21..7a062add7 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -31,7 +31,7 @@ Glossary .. _BRAM: **Block RAM (BRAM)** - Block RAM is on-chip random access memory, stored evenly across a chip, to store large amounts of data. + On-chip random access memory, stored evenly across a chip, to store large amounts of data. BRAM, sometimes called embedded RAM, doesn't need refreshing (as DRAM does) and, like SRAM, doesn't need a memory controller. Single-port BRAM can either read or write on the single port; dual-port BRAM supports read and write for any two addresses and both ports can read *and* write. @@ -56,7 +56,7 @@ Glossary .. _DRAM: **DRAM (Dynamic Random Access Memory)** - DRAM is memory that is stored in capacitors and is constantly refreshed. + Memory that is stored in capacitors and is constantly refreshed. Rather than store data in flip-flops, as :ref:`SRAM` does, DRAM constantly reads data into capacitors, row-by-row, in sequence, even when no processing is taking place. Racing the decay of the refresh has a negative impact on speed and perforamance and the write process produces extra heat as it uses a strong charge. @@ -74,7 +74,7 @@ Glossary .. _Elaboration: **Elaboration** - Elaboration is the process of constructing a design hierarchy from pre-built modules. + The process of constructing a design hierarchy from pre-built modules. Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the :ref:`HDL` code is analyzed to produce a :ref:`netlist` that itemizes the required logic elements and interconnects. @@ -83,7 +83,7 @@ Glossary .. _FIFO: **FIFO (First In First Out)** - First in, first out is a method for organizing the processing of data, especially in a buffer, where the oldest entry is processed first. + A method for organizing the processing of data, especially in a buffer, where the oldest entry is processed first. An elementary building block of integrated circuits, FIFOs are used when crossing clock domains, buffering data, or storing data for use at a later time. @@ -140,7 +140,7 @@ Glossary .. _JTAG: **JTAG** - JTAG (Joint Test Action Group) is an industry standard for verifying designs and testing devices — micro controllers, FPGAs, etc. — after manufacture. + An industry standard for verifying designs and testing devices — micro controllers, FPGAs, etc. — after manufacture. JTAG is a hardware interface that provides a way to communicate directly with the microchips on a board. It enables the testing, via software, of all the different interconnects without having to physically probe the connections. @@ -184,7 +184,7 @@ Glossary .. _Microprocessor: **Microprocessor** - A microprocessor is a miniature, programmable digital device — a tiny computer on a chip — that retrieves instructions from memory, decodes and executes them, and returns the output. + A miniature, programmable digital device — a tiny computer on a chip — that retrieves instructions from memory, decodes and executes them, and returns the output. Microprocessors contain the arithmetic, logic, and control circuitry necessary to perform the functions of a computer’s central processing unit. @@ -205,7 +205,7 @@ Glossary .. _PLL: **PLL (Phase-locked loop)** - A phase-locked loop is an electronic circuit with a controllable oscillator that constantly adjusts in response to an input signal. + An electronic circuit with a controllable oscillator that constantly adjusts in response to an input signal. Its purpose is to generate a derived clock signal that can be faster or slower than the input signal. The derived clock signal can be the result of dividing an input frequency. PLLs can increase frequency by a non-integer factor. @@ -214,14 +214,14 @@ Glossary .. _Place and route: **Place and route** - Place and route is the process of deciding the placement of components on a chip and the related wiring between those components. + The process of deciding the placement of components on a chip and the related wiring between those components. Place and route routines involve complicated maths problems that require optimization. These routines are usually performed by software and produce a layout schema for a chip. .. _Propogation delay: **Propagation delay** - Propogation delay is the time required to change the output from one logic state to another logic state after input is changed. + The time required to change the output from one logic state to another logic state after input is changed. In simplified terms, the time it takes for a signal to move from source to destination. @@ -239,7 +239,7 @@ Glossary .. _RTL: **Register transfer level (RTL)** - RTL, the lowest abstraction level for developing :ref:`FPGAs`, is used to create a representation of synchronous digital circuits between :ref:`hardware registers`. + The lowest abstraction level for developing :ref:`FPGAs`, RTL creates a representation of synchronous digital circuits between :ref:`hardware registers`. Hardware definition language is tranformed to RTL which then defines the circuit at gate level. The representation can be verified via :ref:`simulation`. @@ -277,7 +277,7 @@ Glossary .. _Synthesis: **Synthesis** - Synthesis is the process of building a :ref:`netlist` from a circuit design model. + The process of building a :ref:`netlist` from a circuit design model. Synthesis represents the :ref:`hardware definition language` as :ref:`register transfer level` that is automatically transfered into gates. diff --git a/docs/intro.rst b/docs/intro.rst index 667b24890..5d7c24150 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -6,7 +6,7 @@ Introduction The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. -The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical FPGA development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. +The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical :abbr:`FPGA` development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. .. TODO: add links to connect_rpc docs once they exist From e9a7a68c8cb503c43aedbfb4dca413bafb21bd49 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Mon, 4 Sep 2023 11:12:46 +0100 Subject: [PATCH 41/45] abbr --- docs/intro.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/intro.rst b/docs/intro.rst index 5d7c24150..f66ae1995 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -6,7 +6,7 @@ Introduction The Amaranth project provides an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language. It aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components. -The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical :abbr:`FPGA` development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. +The Amaranth toolchain consists of the :ref:`Amaranth language `, the :ref:`standard library `, the :ref:`simulator `, and the :ref:`build system `, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. At the same time, it does not restrict the designer's choice of tools: existing industry-standard (System)Verilog or VHDL code can be integrated into an Amaranth-based design flow, or, conversely, Amaranth code can be integrated into an existing Verilog-based design flow. .. TODO: add links to connect_rpc docs once they exist From e5711a00a3a1a960cb344fde08cd26e732683d9c Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Mon, 4 Sep 2023 11:20:24 +0100 Subject: [PATCH 42/45] abbr 2 --- docs/intro.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/intro.rst b/docs/intro.rst index f66ae1995..2218678eb 100644 --- a/docs/intro.rst +++ b/docs/intro.rst @@ -20,7 +20,7 @@ The :doc:`Amaranth hardware description language ` is a Python library for By relying on the flexibility, rich functionality and widespread adoption of the Python language, the Amaranth language is focused on a single task: modeling digital logic well. It has first-class support for building blocks like clock domains and :term:`finite state machines`, and uses simple rules for arithmetic operations that closely match the Python semantics. Python classes, functions, loops and conditionals can be used to build organized and flexible designs; Python libraries can be seamlessly used with Amaranth during design or verification; and Python development tools can process Amaranth code. -A core design principle of the Amaranth language is to be not only easy to use, but also hard to accidentally misuse. Some HDLs provide functionality that has unexpected and undesirable behavior in synthesis, often with expensive consequences, and require a significant effort in learning a "safe" coding style and adopting third-party linting tools. Amaranth lacks non-synthesizable constructs and avoids error-prone inference in favor of explicit instantiation. It has many diagnostics (and regularly adds new ones) highlighting potential design issues. Most importantly, all usability issues are considered `reportable bugs`_. +A core design principle of the Amaranth language is to be not only easy to use, but also hard to accidentally misuse. Some :abbr:`HDLs(Hardware defintion language)` provide functionality that has unexpected and undesirable behavior in synthesis, often with expensive consequences, and require a significant effort in learning a "safe" coding style and adopting third-party linting tools. Amaranth lacks non-synthesizable constructs and avoids error-prone inference in favor of explicit instantiation. It has many diagnostics (and regularly adds new ones) highlighting potential design issues. Most importantly, all usability issues are considered `reportable bugs`_. .. _Yosys: https://yosyshq.net/yosys/ .. _reportable bugs: https://github.com/amaranth-lang/amaranth/issues @@ -31,11 +31,11 @@ A core design principle of the Amaranth language is to be not only easy to use, The Amaranth standard library ============================= -The Amaranth language comes with a standard library---a collection of essential digital design components and interfaces. It includes clock domain crossing primitives, synchronous and asynchronous FIFOs, a flexible I/O buffer interface, and more. By providing reliable building blocks out of the box, Amaranth allows the designer to focus on their application and avoids subtle differences in behavior between different designs. +The Amaranth language comes with a standard library---a collection of essential digital design components and interfaces. It includes clock domain crossing primitives, synchronous and asynchronous :abbr:`FIFOs(first in, first out)`, a flexible I/O buffer interface, and more. By providing reliable building blocks out of the box, Amaranth allows the designer to focus on their application and avoids subtle differences in behavior between different designs. .. TODO: link to stdlib here -Clock domain crossing often requires special treatment, such as using vendor-defined attributes or instantiating device-specific primitives. The CDC primitives in the Amaranth standard library can be overridden by the platform integration, and every platform integration included with Amaranth follows the vendor recommendations for CDC. +Clock domain crossing (CDC) often requires special treatment, such as using vendor-defined attributes or instantiating device-specific primitives. The CDC primitives in the Amaranth standard library can be overridden by the platform integration, and every platform integration included with Amaranth follows the vendor recommendations for CDC. High-speed designs usually require the use of registered (and sometimes, geared) I/O buffers. The Amaranth standard library provides a common interface to be used between I/O buffers and peripheral implementations. The Amaranth build system, if used, can instantiate I/O buffers for every platform integration included with Amaranth. @@ -78,7 +78,7 @@ FPGA toolchain integration Each FPGA family requires the use of synthesis and place & route tools specific for that device family. The Amaranth build system directly integrates with every major open-source and commercial FPGA toolchain, and can be easily extended to cover others. -Through this integration, Amaranth can specialize the CDC primitives and I/O buffers for a particular device and toolchain; generate I/O and clock constraints from board definition files; synchronize the power-on reset in single-clock designs; include (System)Verilog and VHDL files in the design (if supported by the toolchain); and finally, generate a script running synthesis, placement, routing, and timing analysis. The generated code can be customized to insert additional options, commands, constraints, and so on. +Through this integration, Amaranth can specialize the :abbr:`CDC(Clock domain crossing)` primitives and I/O buffers for a particular device and toolchain; generate I/O and clock constraints from board definition files; synchronize the power-on reset in single-clock designs; include (System)Verilog and VHDL files in the design (if supported by the toolchain); and finally, generate a script running synthesis, placement, routing, and timing analysis. The generated code can be customized to insert additional options, commands, constraints, and so on. The Amaranth build system produces self-contained, portable build trees that require only the toolchain to be present in the environment. This makes builds easier to reproduce, or to run on a remote machine. The generated build scripts are always provided for both \*nix and Windows. @@ -86,7 +86,7 @@ The Amaranth build system produces self-contained, portable build trees that req Development board definitions ----------------------------- -Getting started with a new FPGA development board often requires going through a laborous and error-prone process of deriving toolchain configuration and constraint files from the supplied documentation. The Amaranth project includes a community-maintained repository of definitions for many open-source and commercial FPGA development boards. +Getting started with a new FPGA development board often requires going through a laborious and error-prone process of deriving toolchain configuration and constraint files from the supplied documentation. The Amaranth project includes a community-maintained repository of definitions for many open-source and commercial FPGA development boards. These board definitions contain everything that is necessary to start using the board: FPGA family and model, clocks and resets, descriptions of on-board peripherals (including pin direction and attributes such as I/O standard), connector pinouts, and for boards with a built-in debug probe, the steps required to program the board. It takes a single Python invocation to generate, build, and download a test design that shows whether the board, toolchain, and programmer are working correctly. From 456970ac0668323d53e4ad70a312e8967b29579d Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Mon, 4 Sep 2023 16:18:14 +0100 Subject: [PATCH 43/45] looking for abbr --- docs/lang.rst | 12 ++++++------ docs/start.rst | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/lang.rst b/docs/lang.rst index 6a1c11086..4f2543791 100644 --- a/docs/lang.rst +++ b/docs/lang.rst @@ -81,7 +81,7 @@ All values have a ``.shape()`` method that computes their shape. The width of a Values ====== -The basic building block of the Amaranth language is a *value*, which is a term for a binary number that is computed or stored anywhere in the design. Each value has a *width*---the amount of bits used to represent the value---and a *signedness*---the interpretation of the value by arithmetic operations---collectively called its *shape*. Signed values always use `two's complement`_ representation. +The basic building block of the Amaranth language is a *value*, which is a term for a binary number that is computed or stored anywhere in the design. Each value has a *width*---the number of bits used to represent the value---and a *signedness*---the interpretation of the value by arithmetic operations---collectively called its *shape*. Signed values always use `two's complement`_ representation. .. _two's complement: https://en.wikipedia.org/wiki/Two's_complement @@ -98,7 +98,7 @@ The simplest Amaranth value is a *constant*, representing a fixed number, and in >>> ten = Const(10) >>> minus_two = C(-2) -The code above does not specify any shape for the constants. If the shape is omitted, Amaranth uses unsigned shape for positive numbers and signed shape for negative numbers, with the width inferred from the smallest amount of bits necessary to represent the number. As a special case, in order to get the same inferred shape for ``True`` and ``False``, ``0`` is considered to be 1-bit unsigned. +The code above does not specify any shape for the constants. If the shape is omitted, Amaranth uses unsigned shape for positive numbers and signed shape for negative numbers, with the width inferred from the smallest number of bits necessary to represent the number. As a special case, to get the same inferred shape for ``True`` and ``False``, ``0`` is considered to be 1-bit unsigned. .. doctest:: @@ -468,7 +468,7 @@ Although the syntax is similar, it is important to remember that Amaranth values ... TypeError: Attempted to convert Amaranth value to Python boolean -Because the value of ``a``, and therefore ``a == 0``, is not known at the time when the ``if`` statement is executed, there is no way to decide whether the body of the statement should be executed---in fact, if the design is synthesized, by the time ``a`` has any concrete value, the Python program has long finished! To solve this problem, Amaranth provides its own :ref:`control structures ` that, also, manipulate circuits. +Because the value of ``a``, and therefore ``a == 0``, is not known at the time the ``if`` statement is executed, there is no way to decide whether the body of the statement should be executed---in fact, if the design is synthesized, by the time ``a`` has any concrete value, the Python program has long finished! To solve this problem, Amaranth provides its own :ref:`control structures ` that, also, manipulate circuits. .. _lang-widthext: @@ -486,7 +486,7 @@ Arithmetic operators Most arithmetic operations on integers provided by Python can be used on Amaranth values, too. -Although Python integers have unlimited precision and Amaranth values are represented with a :ref:`finite amount of bits `, arithmetics on Amaranth values never overflows because the width of the arithmetic expression is always sufficient to represent all possible results. +Although Python integers have unlimited precision and Amaranth values are represented with a :ref:`finite number of bits `, arithmetic computations on Amaranth values never overflows because the width of the arithmetic expression is always sufficient to represent all possible results. .. doctest:: @@ -785,7 +785,7 @@ A *control domain* is a named group of :ref:`signals ` that change All designs have a single predefined *combinatorial domain*, containing all signals that change immediately when any value used to compute them changes. The name ``comb`` is reserved for the combinatorial domain. -A design can also have any amount of user-defined *synchronous domains*, also called *clock domains*, containing signals that change when a specific edge occurs on the domain's clock signal or, for domains with asynchronous reset, on the domain's reset signal. Most modules only use a single synchronous domain, conventionally called ``sync``, but the name ``sync`` does not have to be used, and lacks any special meaning beyond being the default. +A design can also have any number of user-defined *synchronous domains*, also called *clock domains*, containing signals that change when a specific edge occurs on the domain's clock signal or, for domains with asynchronous reset, on the domain's reset signal. Most modules only use a single synchronous domain, conventionally called ``sync``, but the name ``sync`` does not have to be used, and lacks any special meaning beyond being the default. The behavior of assignments differs for signals in :ref:`combinatorial ` and :ref:`synchronous ` domains. Collectively, signals in synchronous domains contain the state of a design, whereas signals in the combinatorial domain cannot form feedback loops or hold state. @@ -887,7 +887,7 @@ Every signal included in the target of an assignment becomes a part of the domai Assignment order ---------------- -Unlike with two different domains, adding multiple assignments to the same signal to the same domain is well-defined. +In contrast to working with two different domains, adding multiple assignments to the same signal to the same domain is well-defined. Assignments to different signal bits apply independently. For example, the following two snippets are equivalent: diff --git a/docs/start.rst b/docs/start.rst index 3d7772fbd..9314fa3d7 100644 --- a/docs/start.rst +++ b/docs/start.rst @@ -51,7 +51,7 @@ The test bench is implemented as a Python generator function that is co-simulate .. TODO: link to simulator reference -When run, the test bench finishes successfully, since all of the assertions hold, and produces a VCD file with waveforms recorded for every ``Signal`` as well as the clock of the ``sync`` domain: +When run, the test bench finishes successfully, since all of the assertions hold, and produces a VCD (Value Change Dump) file with waveforms recorded for every ``Signal`` as well as the clock of the ``sync`` domain: .. image:: _images/up_counter_gtkwave.png :alt: A screenshot of GTKWave displaying waveforms near the clock cycle where the counter overflows. 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The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. + Amaranth makes developing hardware definitions based on synchronous digital logic more intuitive by using the Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. .. _ASIC: - **ASIC (Application-specific integrated circuit)** - A non-standard integrated circuit chip made for a specific task or product. + **ASIC (Application-Specific Integrated Circuit)** + A non-standard application-specific integrated circuit chip made for a specific task or product. The term *application* refers to the function the circuit will perform, not to a software application. ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce. Design and testing are critical to the success of ASIC development. - Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from cell libraries. The resulting system can then be verified via :ref:`simulation`. + Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from :ref:`cell libraries`. The resulting system can then be verified via :ref:`simulation`. .. _Bitstream generation: **Bitstream generation** - The code that configures the flash memomory or external storage device to boot an FPGA at power on. - - The final step in translating requirements into circuits on a chip, the bitstream defines the logic blocks and interconnects on the FPGA chip. + The final step in translating requirements into circuits on a chip, the generated bitstream defines the logic blocks and interconnects on an FPGA chip as well as configuring the flash memory or external storage device to boot the FPGA at power on. .. _BRAM: - **Block RAM (BRAM)** - On-chip random access memory, stored evenly across a chip, to store large amounts of data. + **BRAM (Block RAM)** + On-chip random access memory, distributed evenly across a chip, to store large amounts of data. - BRAM, sometimes called embedded RAM, doesn't need refreshing (as DRAM does) and, like SRAM, doesn't need a memory controller. Single-port BRAM can either read or write on the single port; dual-port BRAM supports read and write for any two addresses and both ports can read *and* write. + BRAM, sometimes called embedded RAM, doesn't need refreshing (as :ref:`DRAM` does) and, like :ref:`SRAM`, doesn't need a memory controller. Single-port BRAM can either read or write on the single port; dual-port BRAM supports read and write for any two addresses and both ports can read *and* write. BRAM :ref:`FIFO` is used to cross clock domains or to buffer data between two interfaces. .. _CLB: - **CLB (Configurable logic block)** + **CLB Configurable Logic Block** The basic repeating logic block on an FPGA, the purpose of CLBs is to implement combinational and sequential logic on an FPGA. Be aware that different FPGA manufacturers use different names for this component. @@ -51,14 +49,35 @@ Glossary **Clock signal** An electronic logic signal that oscillates between a high and a low state at a constant frequency. - Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard, a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks can be made by dividing another clock signal or using a :ref:`PLL`. + Used to synchronise the actions of digital circuits, clock signals can be one of two types: primary or derived. Primary clocks are generated using a frequency standard: a stable oscillator that creates a signal with a high degree of accuracy and precision. Derived clocks can be made by dividing another clock signal or using a :ref:`PLL`. + +.. _Clock tree: + + **Clock tree** + A clock distribution network — clocking circuitry and devices — within a hardware design. + + The simplicity or complexity of the clock tree depends on the hardware design. In more complex systems, the clock tree is represented as a hierarchy where a single reference clock is cascaded and synthesized into a number of different output clocks. + +.. _Clock tree synthesis: + + **Clock tree synthesis** + A technique for distributing the clock signal equally among all sequential parts of a design. + + Clock tree synthesis occurs directly after :ref:`routing and before placement` in the :ref:`synthesis` process. It inserts buffers and/or inverters along the clock path to balance the clock delay to all inputs. The aim being to reduce latency and skew to ensure all inputs are synchronized. + +.. _Combinational logic: + + **Combinational logic** + A digital logic function, composed of :ref:`logic gates`, whose outputs are directly related to the current combination of values on its input — combinational logic has no memory or history. + + Combinational logic is also known as combinatorial logic. .. _DRAM: - **DRAM (Dynamic Random Access Memory)** + **DRAM (Dynamic Random Access Memmory)** Memory that is stored in capacitors and is constantly refreshed. - Rather than store data in flip-flops, as :ref:`SRAM` does, DRAM constantly reads data into capacitors, row-by-row, in sequence, even when no processing is taking place. Racing the decay of the refresh has a negative impact on speed and perforamance and the write process produces extra heat as it uses a strong charge. + Rather than store data in :ref:`flip-flop`s, as :ref:`SRAM` does, DRAM constantly reads data into capacitors, row-by-row, in sequence, even when no processing is taking place. Racing the decay of the refresh has a negative impact on speed and performance; and the write process produces extra heat because it uses a strong charge. DRAM has a higher storage capacity than other kinds of memory; is cheaper and smaller than SRAM; and memory can be deleted and refreshed while running a program. @@ -66,17 +85,17 @@ Glossary .. _DUT: - **DUT (Device under test)** - A physical chip or logic circuit being tested at :ref:'simulation`. + **DUT (Device Under Test)** + A physical chip or logic circuit being tested at :ref:`simulation`. Testing can result in a chip being given a grade to represent the extent to which it met tolerance values. .. _Elaboration: **Elaboration** - The process of constructing a design hierarchy from pre-built modules. - - Elaboration is the first step in translating requirements into circuits on a chip. In elaboration, the behaviour described in the :ref:`HDL` code is analyzed to produce a :ref:`netlist` that itemizes the required logic elements and interconnects. + The first step in the toolchain process, elaboration begins the translation of requirements into circuits on a chip. + + In elaboration, the behaviour described in the :ref:`HDL` code is analyzed to produce a technology independent :ref:`netlist` that itemizes the required logic elements and interconnects. In the toolchain, elaboration is followed by :ref:`synthesis`, :ref:`place and route`, and :ref:`bitstream generation`. @@ -92,9 +111,7 @@ Glossary **Finite state machine** A mathematical model describing a system with a limited number of conditional states of being. - A finite state machine reads a series of inputs. For each input, it will transition to a different state. Each state specifies which state to transition to next, for the given input. When the processing is complete, a ‘then’ action is taken. The abstract machine can process only one state at a time. - - This approach enables engineers to study and test each input and output scenario. + A finite state machine reads a series of inputs. For each input, it will transition to a different state. Each state specifies which state to transition to next, for the given input. When the processing is complete, a ‘then’ action is taken. The abstract machine can process only one state at a time. This approach enables engineers to study and test each input and output scenario. .. _Flip-flop: @@ -114,42 +131,47 @@ Glossary FPGAs combine speed, programmability, and flexibility. In addition, they can process very large volumes of data by duplicating circuits and running them in parallel. +.. _GDSII: + + **GDSII** + A binary file format consisting of geometric shapes, labels, and additional data that a foundry can use to manufacture a silicon chip. + + GDSII (or GDS2) is a standard for database interchange of ASIC artwork: all shapes in the design are assigned to a layer (or, sometimes, layers). Layers are combined to form a mask. Each mask is used in the photolithography process that produces the GDSII file the foundry will use when manufacturing the chip. + .. _Hardware register: **Hardware register** Circuits, typically composed of D :ref:`flip-flops` (DFF), that hold configuration and status information. - Written in low level :ref:`HDL` code, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. + Written in low-level :ref:`HDL` code, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. .. _HDL: - **HDL (Hardware definition language)** - A hardware definition language, such as :ref:`Amaranth`, describes the structure and timing of electronic circuits and digital logic circuits. + **HDL (Hardware Definition Language)** + An HDL, such as :ref:`Amaranth`, describes the structure and timing of electronic circuits and digital logic circuits. Modern HDLs include synthesizable code that characterises the synchronous logic (:ref:`registers`), combinational logic (:ref:`logic gates`), and behavioural code (used in testing) that describe a circuit. .. _IC: - **IC (Integrated circuit)** - An integrated circuit has many electronic components embedded on a single chip. + **IC (Integrated Circuit)** + Sometimes called a microchip or chip, an IC is a semiconductor-based electronic device consisting of transistors, resistors, capacitors, diodes, and inductors that perform the same functions as a larger circuit comprised of discrete components. - The circuit is a small wafer, usually made of semiconducting material, that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). These components can perform calculations and store data using either digital or analog technology. - - Digital ICs use :ref:`logic gates` that work only with values of 1s and 0s. + The circuit is a small wafer that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). These components can perform calculations and store data using either digital or analog technology. Digital ICs use :ref:`logic gates` that work only with values of 1s and 0s. .. _JTAG: **JTAG** An industry standard for verifying designs and testing devices — micro controllers, FPGAs, etc. — after manufacture. - JTAG is a hardware interface that provides a way to communicate directly with the microchips on a board. It enables the testing, via software, of all the different interconnects without having to physically probe the connections. + JTAG is a hardware interface that provides a way to communicate directly with the microchips on a board. It enables the testing, via software, of all the different interconnects on a chip without having to physically probe the connections. .. _Logic gate: **Logic gate** - An elementary building block of integrated circuits, logic gates perform logical operations on binary inputs and outputs. + An elementary building block of integrated circuits, logic gates are electronic devices that perform Boolean functions on one or more binary inputs to produce a single binary output. - Based on a Boolean function that computes TRUE or FALSE, each output is based on the input or combination of inputs supplied to it. + The relationship between the input and output is based on the logic gates in the circuit — AND, OR, NOT, XOR, etc. Logic gates can be combined to perform complex processes based on Boolean logic. .. _Logic synthesis: @@ -160,8 +182,8 @@ Glossary .. _LUT: - **LUT (Look up table)** - An elementary building block of integrated circuits, a LUT defines how combinatorial logic behaves: the output for every combination of inputs. + **LUT (Look Up Table)** + An elementary building block of integrated circuits, LUTs define how combinational logic behaves: the output for every combination of inputs. A single input LUT is made up of two :ref:`flip-flops` and a :ref:`multiplexer`. This structure can be expanded into a tree to provide the required capacity. The larger the number of multiplexers, the longer the associated propagation delay. @@ -169,7 +191,7 @@ Glossary .. _MCU: - **MCU (Microcontroller unit)** + **MCU (Microcontroller Unit)** An integrated circuit designed to govern a specific operation in an embedded system. An MCU integrates a CPU, onboard memory (may be volatile, may be non-volatile), peripherals for communication, and, usually, clock functions. A complex MCU can be described as a system on chip :ref:`(SoC)`. @@ -177,60 +199,60 @@ Glossary .. _Memory-mapped peripheral: **Memory-mapped peripheral** - Hardware devices, mapped to the memory address space of a :ref:`microprocessor`, are known as memory-mapped peripherals. + A hardware device that is treated as a memory location in a microcontroller or microprocessor. - The memory data bus moves information bi-directionally between the CPU and memory via store (write) and retrieve (read) signals. + A memory-mapped peripheral is identified by a unique 16-bit address and has a specific address in memory that it reads to and writes data from. .. _Microprocessor: **Microprocessor** A miniature, programmable digital device — a tiny computer on a chip — that retrieves instructions from memory, decodes and executes them, and returns the output. - Microprocessors contain the arithmetic, logic, and control circuitry necessary to perform the functions of a computer’s central processing unit. + Accepting binary data as input, microprocessors have memory, are clock-driven, and register-based. They contain the arithmetic, logic, and control circuitry necessary to perform the functions of a computer’s central processing unit. .. _Multiplexer: **Multiplexer** - A combinational logic circuit designed to switch one of several control signals to a single common output by the application of a control signal. + A combinational logic circuit designed to switch one of several control signals, often from different sources, to a single common output by the application of a control signal. - A multiplexer selects between several input signals and forwards the selected input to a single output. + Also known as a data selector or input selector, a multiplexer makes it possible for several input signals to share one device rather than having one device per input signal. .. _Netlist: **Netlist** - Netlists describe the components and connectivity of an electronic circuit. + A description of the components and connectivity of an electronic circuit. Netlists can be generated at different points in the toolchain process: after synthesis, where the placement information will not be available; and after place and route, when the placement information will be included. .. _PLL: - **PLL (Phase-locked loop)** - An electronic circuit with a controllable oscillator that constantly adjusts in response to an input signal. - - Its purpose is to generate a derived clock signal that can be faster or slower than the input signal. The derived clock signal can be the result of dividing an input frequency. PLLs can increase frequency by a non-integer factor. + **PLL (Phase-Locked Loop)** + A feedback circuit designed to allow one circuit board to synchronize the phase of its on-board clock with an external timing signal. + + PLL circuits compare the phase of an external signal to the phase of a clock signal produced by a voltage controlled crystal oscillator. The circuit then adjusts the phase of the oscillator’s clock signal to match the phase of the external signal to ensure the signals are precisely synchronised with each other. - Where multiple clock domains are interacting synchronously, PLLs use a fixed phase relationship. + The derived clock signal can be the result of dividing an input frequency. PLLs can increase frequency by a non-integer factor. Where multiple clock domains are interacting synchronously, PLLs use a fixed phase relationship. .. _Place and route: **Place and route** - The process of deciding the placement of components on a chip and the related wiring between those components. + A stage in the IC design process, place and route decides the placement of components on a chip and the wiring between those components. - Place and route routines involve complicated maths problems that require optimization. These routines are usually performed by software and produce a layout schema for a chip. + Placement defines the location of the electronic components, circuitry, and logic elements within the defined space. Routing defines the wiring required to connect the components. These routines are usually performed by the toolchain and produce the layout schema for a chip. .. _Propogation delay: **Propagation delay** The time required to change the output from one logic state to another logic state after input is changed. - In simplified terms, the time it takes for a signal to move from source to destination. + In simplified terms, the time it takes for a signal to move from source to destination. Propogation delay impacts :ref:`sequential logic` — logic driven by a clock. The further apart components in a circuit are, the longer the propogation delay will be. This will cause the clock to run more slowly and create timing errors. The maximum speed at which a synchronous logic circuit works can be determined by combining the longest path of propagation delay from input to output with the maximum combined propagation delay. Bear in mind that not only do logic gates have propogation delay, wires do too. .. _Register: **Register** - A memory device that can store a specific number of data bits. + A memory device, located at a known address, that can store a specific number of data bits. Made up of a series of :ref:`flip-flops`, a register can temporarily store data or a set of instructions for a processor. A register can enable both serial and parallel data transfers, allowing logic operations to be performed on the data stored in it. @@ -238,35 +260,40 @@ Glossary .. _RTL: - **Register transfer level (RTL)** + **RTL (Register Transfer Level)** The lowest abstraction level for developing :ref:`FPGAs`, RTL creates a representation of synchronous digital circuits between :ref:`hardware registers`. Hardware definition language is tranformed to RTL which then defines the circuit at gate level. The representation can be verified via :ref:`simulation`. +.. _Sequential logic: + + **Sequential logic** + A digital logic function whose outputs depend on both current and past inputs. + + Sequential logic has a memory function (unlike :ref:`combinational logic` which has none) and is used to construct :ref:`Finite state machines`. + + Sequential logic circuits can be either synchronous, the state of the device changes in response to a clock signal or asynchronous, the state of the device changes in response to changing inputs. + .. _Simulation: **Simulation** A process in which a model of an electronic circuit is analysed by a computer program to validate its functionality. - Simulation models the behaviour of a circuit; it does not model the hardware components described by the :ref:`HDL`. Despite being written in HDL, the simulator treats the code as event-driven parallel programming language to run programs on a particular operating system or to port a system that doesn't have an :ref:`FPGA`. - - Simulation is an invaluable tool for ensuring a circuit works the way it was intended to and enables designers to rapidly iterate designs. + Simulation models the behaviour of a circuit; it does not model the hardware components described by the :ref:`HDL`. Despite being written in HDL, the simulator treats the code as event-driven parallel programming language to run programs on a particular operating system or to port a system that doesn't have an :ref:`FPGA`. The output of the simulation is a value change dump (VCD). .. _SoC: **SoC (System on Chip)** An integrated circuit, containing almost all the circuitry and components an electronic system (smartphone, small embedded devices) requires. - In contrast to a computer system that is made up of many distinct components, an SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces — into a single chip. - - SoCs are typically built around a :ref:`microprocessor`, :ref:`microcontroller`, or specialised :ref:`integrated circuit`. This increases performance, reduces power consumption, and requires a smaller footprint on a printed circuit board. + In contrast to a computer system that is made up of many distinct components, a SoC integrates the required resources — CPU, memory interfaces, I/O devices, I/O interfaces — into a single chip. SoCs are more complex than a microcontroller with a higher degree of integration and a greater variety of perhipherals. - SoCs are more complex than a microcontroller with a higher degree of integration and a greater variety of perhipherals. + SoCs are typically built around a :ref:`microprocessor`, :ref:`microcontroller`, or specialised :ref:`integrated circuit`. This increases performance, reduces power consumption, and requires a smaller footprint on a printed circuit board. .. _SRAM: - **SRAM** - Static Random Access Memory (SRAM) is volatile memory that stores data whilst power is supplied (if the power is turned off, data is lost). + **SRAM (Static Random Access Memory)** + Volatile memory that stores data whilst power is supplied (if the power is turned off, data is lost). SRAM uses flip-flops to store bits and holds that value until the opposite value replaces it. SRAM is faster in operation than :ref:`DRAM` as it doesn't require a refresh process. @@ -274,18 +301,32 @@ Glossary SRAM is incompatible with DRAM. +.. _Standard cell library: + + **Standard cell library** + A collection of low-level logic functions, with fixed height and variable width cells that can be placed in rows, used to simplify automated digital circuit layout. + + The library will usually contain well-defined, pre-characterized logic functions — flip-flops, buffers, etc. — optimised for performance and physical size. Cell library characterization is a process of analyzing a circuit using both static and dynamic methods to generate models suitable for chip implementation flows. + + These functions enable a more modular approach to circuit design by abstracting some of the complexity of component layout and connectivity. Being well-defined, it's easier to estimate factors such as performance and timing and increase the likelihood of a successful design. + .. _Synthesis: **Synthesis** - The process of building a :ref:`netlist` from a circuit design model. + The process of coverting a high-level behavioural design to a lower-level physical implementation. + + The synthesis process represents the behaviour outlined in a :ref:`hardware definition language` as :ref:`register transfer level` that is then translated into logic gates: :ref:`LUTs` and :ref:`flip-flops`. A bitstream can then be generated to program an FPGA. + +.. _Tapeout: - Synthesis represents the :ref:`hardware definition language` as :ref:`register transfer level` that is automatically transfered into gates. + **Tapeout** + The final stage of the IC design process where photolithography is used to produce a graphic representation of the photomask of a circuit, in :ref:`GDSII` format, to be sent to the semiconductor foundry for manufacture. .. _Waveform: **Waveform** - A mathematical (logical) description of a signal. + A visual representation of changes in voltage or current in an electrical circuit over time. - Waveforms have three main characteristics: period, the length of time the waveform takes to repeat; frequency, the number of times the waveform repeats within a one second time period; and amplitude, the magnitude or intensity of the signal waveform measured in volts or amps. + Waveforms have different shapes and three main characteristics: period, the length of time the waveform takes to repeat; frequency, the number of times the waveform repeats within a time period; and amplitude, the magnitude or intensity of the signal waveform measured in volts or amps. The waveform of an electrical signal can be visualised using an oscilloscope. The square waveform is commonly used to represent digital information. A waveform dump, one of the outputs of simulation, can be used to measure the performance of devices. \ No newline at end of file From b997f0fd970cb81d2d60cb8e403ae62fa25d4fa4 Mon Sep 17 00:00:00 2001 From: Allyson Prolisko Date: Thu, 21 Sep 2023 12:48:21 +0100 Subject: [PATCH 45/45] Link checking --- docs/glossary.rst | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/docs/glossary.rst b/docs/glossary.rst index b4fbcb1fb..3d04e9005 100644 --- a/docs/glossary.rst +++ b/docs/glossary.rst @@ -6,9 +6,9 @@ Glossary .. _Amaranth: **Amaranth** - An open-source toolchain that uses the Python programming language to create. + An open-source toolchain that uses the Python programming language to create hardware definitions based on synchronous digital logic. - Amaranth makes developing hardware definitions based on synchronous digital logic more intuitive by using the Python programming language. The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. + The toolchain consists of the Amaranth language, the standard library, the simulator, and the build system, covering all steps of a typical :abbr:`FPGA(Field Programmable Gate Array)` development workflow. .. _ASIC: @@ -19,7 +19,7 @@ Glossary ASICs can be configured to be more power efficient and have better performance than an off-the-shelf general purpose integrated circuit. However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive to produce. Design and testing are critical to the success of ASIC development. - Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from :ref:`cell libraries`. The resulting system can then be verified via :ref:`simulation`. + Rather than designing and building them from the ground up, ASICs can be created by interconnecting functional components from :ref:`standard cell libraries`. The resulting system can then be verified via :ref:`simulation`. .. _Bitstream generation: @@ -37,7 +37,7 @@ Glossary .. _CLB: - **CLB Configurable Logic Block** + **CLB (Configurable Logic Block)** The basic repeating logic block on an FPGA, the purpose of CLBs is to implement combinational and sequential logic on an FPGA. Be aware that different FPGA manufacturers use different names for this component. @@ -63,7 +63,7 @@ Glossary **Clock tree synthesis** A technique for distributing the clock signal equally among all sequential parts of a design. - Clock tree synthesis occurs directly after :ref:`routing and before placement` in the :ref:`synthesis` process. It inserts buffers and/or inverters along the clock path to balance the clock delay to all inputs. The aim being to reduce latency and skew to ensure all inputs are synchronized. + Clock tree synthesis occurs directly after :ref:`placement and before routing` in the :ref:`synthesis` process. It inserts buffers and/or inverters along the clock path to balance the clock delay to all inputs. The aim being to reduce latency and skew to ensure all inputs are synchronized. .. _Combinational logic: @@ -77,7 +77,7 @@ Glossary **DRAM (Dynamic Random Access Memmory)** Memory that is stored in capacitors and is constantly refreshed. - Rather than store data in :ref:`flip-flop`s, as :ref:`SRAM` does, DRAM constantly reads data into capacitors, row-by-row, in sequence, even when no processing is taking place. Racing the decay of the refresh has a negative impact on speed and performance; and the write process produces extra heat because it uses a strong charge. + Rather than store data in :ref:`flip-flops`, as :ref:`SRAM` does, DRAM constantly reads data into capacitors, row-by-row, in sequence, even when no processing is taking place. Racing the decay of the refresh has a negative impact on speed and performance; and the write process produces extra heat because it uses a strong charge. DRAM has a higher storage capacity than other kinds of memory; is cheaper and smaller than SRAM; and memory can be deleted and refreshed while running a program. @@ -143,7 +143,7 @@ Glossary **Hardware register** Circuits, typically composed of D :ref:`flip-flops` (DFF), that hold configuration and status information. - Written in low-level :ref:`HDL` code, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making an SoC a function of a peripheral that is controlled by read and write signals to a memory location. + Written in low-level :ref:`HDL` code, a hardware register is a set of DFFs with a shared function. At a higher level, a hardware register can be a specific context for making a SoC a function of a peripheral that is controlled by read and write signals to a memory location. .. _HDL: @@ -157,7 +157,7 @@ Glossary **IC (Integrated Circuit)** Sometimes called a microchip or chip, an IC is a semiconductor-based electronic device consisting of transistors, resistors, capacitors, diodes, and inductors that perform the same functions as a larger circuit comprised of discrete components. - The circuit is a small wafer that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). These components can perform calculations and store data using either digital or analog technology. Digital ICs use :ref:`logic gates` that work only with values of 1s and 0s. + The circuit is a small wafer that can hold anywhere from hundreds to millions of transistors and resistors (with possibly a few capacitors). These components can perform calculations and store data using either digital or analog technology. ICs use :ref:`logic gates` that work only with values of 1s and 0s. .. _JTAG: @@ -222,7 +222,7 @@ Glossary **Netlist** A description of the components and connectivity of an electronic circuit. - Netlists can be generated at different points in the toolchain process: after synthesis, where the placement information will not be available; and after place and route, when the placement information will be included. + Netlists can be generated at different points in the toolchain process: during logical synthesis, where the placement information will not be available; and after place and route, when the placement information is available. .. _PLL: @@ -236,7 +236,7 @@ Glossary .. _Place and route: **Place and route** - A stage in the IC design process, place and route decides the placement of components on a chip and the wiring between those components. + A stage in the IC design process, place and route decides the placement of components on a chip and the wiring routes between those components. Placement defines the location of the electronic components, circuitry, and logic elements within the defined space. Routing defines the wiring required to connect the components. These routines are usually performed by the toolchain and produce the layout schema for a chip. @@ -272,7 +272,7 @@ Glossary Sequential logic has a memory function (unlike :ref:`combinational logic` which has none) and is used to construct :ref:`Finite state machines`. - Sequential logic circuits can be either synchronous, the state of the device changes in response to a clock signal or asynchronous, the state of the device changes in response to changing inputs. + Sequential logic circuits can be either synchronous (the state of the device changes in response to a clock signal) or asynchronous (the state of the device changes in response to changing inputs). .. _Simulation: @@ -297,7 +297,7 @@ Glossary SRAM uses flip-flops to store bits and holds that value until the opposite value replaces it. SRAM is faster in operation than :ref:`DRAM` as it doesn't require a refresh process. - In comparison with DRAM, SRAM has a lower power consumption, is more expensive to purchase, has lower storaage capacity, and is more complex in design. + In comparison with DRAM, SRAM has a lower power consumption, is more expensive to purchase, has lower storage capacity, and is more complex in design. SRAM is incompatible with DRAM. @@ -315,7 +315,7 @@ Glossary **Synthesis** The process of coverting a high-level behavioural design to a lower-level physical implementation. - The synthesis process represents the behaviour outlined in a :ref:`hardware definition language` as :ref:`register transfer level` that is then translated into logic gates: :ref:`LUTs` and :ref:`flip-flops`. A bitstream can then be generated to program an FPGA. + The synthesis process represents the behaviour outlined in a :ref:`hardware definition language` as :ref:`register transfer level` that is then translated into :ref:`logic gates` (:ref:`LUTs` and :ref:`flip-flops`). A bitstream can then be generated to program an FPGA. .. _Tapeout: