diff --git a/library/axi_ad7606x/Makefile b/library/axi_ad7606x/Makefile
index 324a9b946fc..444937477fa 100644
--- a/library/axi_ad7606x/Makefile
+++ b/library/axi_ad7606x/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
diff --git a/library/axi_ad7606x/axi_ad7606x.v b/library/axi_ad7606x/axi_ad7606x.v
index 05481711619..236f61aa386 100644
--- a/library/axi_ad7606x/axi_ad7606x.v
+++ b/library/axi_ad7606x/axi_ad7606x.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -41,7 +41,6 @@ module axi_ad7606x #(
   parameter       DEV_CONFIG = 0,
   parameter       ADC_TO_DMA_N_BITS = 16,
   parameter       ADC_N_BITS = 16,
-  parameter       ADC_READ_MODE = 0,
   parameter       EXTERNAL_CLK = 0
 ) (
 
diff --git a/library/axi_ad7606x/axi_ad7606x_16b_pif.v b/library/axi_ad7606x/axi_ad7606x_16b_pif.v
index 37c7f4e00dc..ce30918aed7 100644
--- a/library/axi_ad7606x/axi_ad7606x_16b_pif.v
+++ b/library/axi_ad7606x/axi_ad7606x_16b_pif.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
diff --git a/library/axi_ad7606x/axi_ad7606x_18b_pif.v b/library/axi_ad7606x/axi_ad7606x_18b_pif.v
index d98b65231e4..fd8bf2743d5 100644
--- a/library/axi_ad7606x/axi_ad7606x_18b_pif.v
+++ b/library/axi_ad7606x/axi_ad7606x_18b_pif.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
diff --git a/library/axi_ad7606x/axi_ad7606x_ip.tcl b/library/axi_ad7606x/axi_ad7606x_ip.tcl
index cd52d7e4ae4..fd6ad137c19 100644
--- a/library/axi_ad7606x/axi_ad7606x_ip.tcl
+++ b/library/axi_ad7606x/axi_ad7606x_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
diff --git a/projects/ad7606x_fmc/Readme.md b/projects/ad7606x_fmc/Readme.md
index 5267b3c6f68..e7b8c271955 100644
--- a/projects/ad7606x_fmc/Readme.md
+++ b/projects/ad7606x_fmc/Readme.md
@@ -20,8 +20,7 @@ hdl/projects/ad7606x_fmc/zed> make DEV_CONFIG=2 INTF=1 NUM_OF_SDI=4
 DEV_CONFIG  - Defines the device which will be used: 0 - AD7606B, 1 - AD7606C-16, 2 - AD7606C-18.
 INTF - Defines the operation interface: 0 - Parallel, 1 - Serial
 NUM_OF_SDI - Defines the number of SDI lines used: 1, 2, 4, 8
-SIMPLE_STATUS_CRC - Defines the ADC Read Mode option: 0 - Simple, 1 - STATUS, 2 - CRC, 3 - CRC_STATUS.
 EXT_CLK - Defines the external clock option for the ADC clock: 0 - No, 1 - Yes.
 
 For the serial interface, the following parameters will be used in make command: DEV_CONFIG, INTF, NUM_OF_SDI.
-For the parallel interface, the following parameters will be used in make command: DEV_CONFIG, INTF, SIMPLE_STATUS_CRC, EXT_CLK.
+For the parallel interface, the following parameters will be used in make command: DEV_CONFIG, INTF,EXT_CLK.
diff --git a/projects/ad7606x_fmc/common/ad7606x_bd.tcl b/projects/ad7606x_fmc/common/ad7606x_bd.tcl
index 429c238d230..4d041f22f81 100644
--- a/projects/ad7606x_fmc/common/ad7606x_bd.tcl
+++ b/projects/ad7606x_fmc/common/ad7606x_bd.tcl
@@ -9,14 +9,12 @@ set INTF $ad_project_params(INTF)
 set NUM_OF_SDI $ad_project_params(NUM_OF_SDI)
 set ADC_N_BITS [expr {$DEV_CONFIG == 2 ? 18 : 16}]
 set ADC_TO_DMA_N_BITS [expr {$ADC_N_BITS == 16 ? 16 : 32}]
-set SIMPLE_STATUS_CRC $ad_project_params(SIMPLE_STATUS_CRC)
 set EXT_CLK $ad_project_params(EXT_CLK)
 set TOTAL_N_BITS_DMA [expr {$ADC_TO_DMA_N_BITS*8}]
 
 puts "build parameters: DEV_CONFIG: $DEV_CONFIG"
 puts "build parameters: INTF: $INTF"
 puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI"
-puts "build parameters: SIMPLE_STATUS_CRC: $SIMPLE_STATUS_CRC"
 puts "build parameters: EXT_CLK: $EXT_CLK"
 
 # control lines
@@ -51,7 +49,6 @@ switch $INTF {
     ad_ip_parameter axi_ad7606x CONFIG.DEV_CONFIG $DEV_CONFIG
     ad_ip_parameter axi_ad7606x CONFIG.ADC_N_BITS $ADC_N_BITS
     ad_ip_parameter axi_ad7606x CONFIG.ADC_TO_DMA_N_BITS $ADC_TO_DMA_N_BITS
-    ad_ip_parameter axi_ad7606x CONFIG.ADC_READ_MODE $SIMPLE_STATUS_CRC
     ad_ip_parameter axi_ad7606x CONFIG.EXTERNAL_CLK $EXT_CLK
     
     # axi_pwm_gen
@@ -84,7 +81,7 @@ switch $INTF {
       ad_ip_parameter adc_clk_generator CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE 50.000
       ad_ip_parameter adc_clk_generator CONFIG.PRIM_SOURCE Global_buffer
       ad_ip_parameter adc_clk_generator CONFIG.CLKIN1_UI_JITTER 0
-      ad_ip_parameter adc_clk_generator CONFIG.PRIM_IN_FREQ 100.000 
+      ad_ip_parameter adc_clk_generator CONFIG.PRIM_IN_FREQ 100.000
     
       ad_connect  sys_cpu_clk adc_clk_generator/clk_in1
       ad_connect  sys_cpu_resetn adc_clk_generator/resetn
diff --git a/projects/ad7606x_fmc/zed/system_bd.tcl b/projects/ad7606x_fmc/zed/system_bd.tcl
index c9cb4b45f6a..3670fe8804d 100644
--- a/projects/ad7606x_fmc/zed/system_bd.tcl
+++ b/projects/ad7606x_fmc/zed/system_bd.tcl
@@ -15,13 +15,12 @@ source ../common/ad7606x_bd.tcl
 set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
 
 set DEV_CONFIG $ad_project_params(DEV_CONFIG)
-set SIMPLE_STATUS_CRC $ad_project_params(SIMPLE_STATUS_CRC)
 set EXT_CLK $ad_project_params(EXT_CLK)
 
 #system ID
 ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
 ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
-set sys_cstring "$DEV_CONFIG,$NUM_OF_SDI,$SIMPLE_STATUS_CRC,$EXT_CLK"
+set sys_cstring "$DEV_CONFIG,$NUM_OF_SDI,$EXT_CLK"
 
 sysid_gen_sys_init_file $sys_cstring
diff --git a/projects/ad7606x_fmc/zed/system_project.tcl b/projects/ad7606x_fmc/zed/system_project.tcl
index 9f14502ada9..db6f7203895 100644
--- a/projects/ad7606x_fmc/zed/system_project.tcl
+++ b/projects/ad7606x_fmc/zed/system_project.tcl
@@ -14,8 +14,6 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
 #  - Options : Parallel(0)/Serial(1)
 # NUM_OF_SDI - Number of SDI lines used
 #  - Options: 1, 2, 4, 8
-# SIMPLE_STATUS_CRC - ADC read mode options
-#  - Options : SIMPLE(0), STATUS(1), CRC(2) CRC_STATUS(3)
 # EXT_CLK - Use external clock as ADC clock
 #  - Options : No(0), Yes(1)
 
@@ -36,14 +34,12 @@ if {[info exists ::env(NUM_OF_SDI)]} {
   set env(NUM_OF_SDI) $NUM_OF_SDI
 }
 
-set SIMPLE_STATUS_CRC [get_env_param SIMPLE_STATUS_CRC 0]
 set EXT_CLK [get_env_param EXT_CLK 0]
 
 adi_project ad7606x_fmc_zed 0 [list \
   DEV_CONFIG $DEV_CONFIG \
   INTF $INTF \
   NUM_OF_SDI $NUM_OF_SDI \
-  SIMPLE_STATUS_CRC $SIMPLE_STATUS_CRC \
   EXT_CLK $EXT_CLK \
 ]