From c1e0698719db293be624b3ee900d0da56ddf6fba Mon Sep 17 00:00:00 2001 From: cristianmihaipopa <139123345+cristianmihaipopa@users.noreply.github.com> Date: Thu, 7 Dec 2023 15:18:59 +0200 Subject: [PATCH] AD9434: Zed porting and documentation (#1210) --- docs/index.rst | 3 +- .../ad9434_fmc/ad9434_fmc_block_diagram.svg | 1612 +++++++++++++++++ docs/projects/ad9434_fmc/index.rst | 216 +++ projects/ad9434_fmc/zed/Makefile | 26 + projects/ad9434_fmc/zed/system_bd.tcl | 17 + projects/ad9434_fmc/zed/system_constr.xdc | 45 + projects/ad9434_fmc/zed/system_project.tcl | 18 + projects/ad9434_fmc/zed/system_top.v | 226 +++ 8 files changed, 2162 insertions(+), 1 deletion(-) create mode 100644 docs/projects/ad9434_fmc/ad9434_fmc_block_diagram.svg create mode 100644 docs/projects/ad9434_fmc/index.rst create mode 100644 projects/ad9434_fmc/zed/Makefile create mode 100644 projects/ad9434_fmc/zed/system_bd.tcl create mode 100644 projects/ad9434_fmc/zed/system_constr.xdc create mode 100644 projects/ad9434_fmc/zed/system_project.tcl create mode 100644 projects/ad9434_fmc/zed/system_top.v diff --git a/docs/index.rst b/docs/index.rst index 3a9a74a567..27739f0b9d 100755 --- a/docs/index.rst +++ b/docs/index.rst @@ -24,6 +24,7 @@ HDL Reference Designs AD719X-ASDZ AD7616-SDZ AD9081-FMCA-EBZ/AD9082-FMCA-EBZ + AD9434-FMC AD9783-EBZ ADAQ7980-SDZ @@ -44,4 +45,4 @@ HDL Reference Designs HDL libraries and projects for various reference design and prototyping systems. This repository contains HDL code (Verilog or VHDL) and the required Tcl scripts to create and build a specific FPGA example design using Xilinx and/or Intel tool -chain. +chain. \ No newline at end of file diff --git a/docs/projects/ad9434_fmc/ad9434_fmc_block_diagram.svg b/docs/projects/ad9434_fmc/ad9434_fmc_block_diagram.svg new file mode 100644 index 0000000000..16687587a2 --- /dev/null +++ b/docs/projects/ad9434_fmc/ad9434_fmc_block_diagram.svg @@ -0,0 +1,1612 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + MEMORY INTERCONNECT + + + + ZC706/ZED + FMC CONNECTOR +   + +   +   +   + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Recive path + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + Zynq SoC + Timer + + + DAC core frame + + + + LVDS INTERFACE + + + + + + AD9434 CORE + + + + + DMA_Clk =100MHz + ADC_Clk =500MHz + + + + + AD9434_DMA + + CLK_IN_P + CLK_IN_N + + 64 + 64 + 64 + adc_data_p[11:0] + adc_data_n[11:0] + + ADC_Clk_in =500MHz +   +   +   +   + + + ADC CHANNEL + + + + + + + + + + + + + + + + + + IQ Corr + + + + + + PNMON + + + DC Filter + + diff --git a/docs/projects/ad9434_fmc/index.rst b/docs/projects/ad9434_fmc/index.rst new file mode 100644 index 0000000000..7cfb29236b --- /dev/null +++ b/docs/projects/ad9434_fmc/index.rst @@ -0,0 +1,216 @@ +.. _ad9434_fmc: + +AD9434-FMC HDL project +================================================================================ + +Overview +------------------------------------------------------------------------------- + +The :adi:`AD9434` is a 12-bit monolithic sampling analog-to-digital converter +(ADC) optimized for high performance, low power, and ease of use. The part +operates at up to a 500 MSPS conversion rate and is optimized for outstanding +dynamic performance in wideband carrier and broadband systems. All necessary +functions, including a sample-and-hold and voltage reference, are included on +the chip to provide a complete signal conversion solution. This reference +design includes a data capture interface and the external DDR-DRAM interface +for sample storage. It allows programming the device and monitoring its internal +status registers. The board also provides other options to drive the clock and +analog inputs of the ADC. + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`EVAL-AD9434` + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`AD9434` + +Supported carriers +------------------------------------------------------------------------------- + +.. list-table:: + :widths: 35 35 30 + :header-rows: 1 + + * - Evaluation board + - Carrier + - FMC slot + * - :adi:`EVAL-AD9434-FMC-500EBZ ` + - :xilinx:`ZC706` + - FMC LPC + * - + - :xilinx:`ZedBoard ` + - FMC LPC + +Block design +------------------------------------------------------------------------------- + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. image:: ad9434_fmc_block_diagram.svg + :width: 800 + :align: center + :alt: AD9434-FMC/ZC706/ZED block diagram + +Clock scheme +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +There are multiple ways to configure the clock source for :adi:`AD9434`. +In this section is presented a guide on how to rework the board to the desired +user clock circuitry. Below is a table on what components are needed to install +or uninstall on the evaluation board. + +==================== ======================================== ================ +Clock Configuration Install Uninstall +==================== ======================================== ================ +Ext. Signal Gen. as it is as it is +Oscillator R209, P1(shunt) --- +LVPECL R208, R307, R308, C300, C311, C304, C305 C209, C210 +LVDS R208, C306, C307 C209, C210, R311 +==================== ======================================== ================ + +For LVPECL and LVDS configurations, appropriate charge pump filter circuit +values are necessary to have an optimized clock buffer performance from +:adi:`AD9517-4`. + +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL(see more at :ref:`architecture`). + +==================== =============== +Instance Zynq/Microblaze +==================== =============== +axi_ad9434 0x44A0_0000 +axi_ad9434_dma 0x44A3_0000 +==================== =============== + +SPI connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - SPI type + - SPI manager instance + - SPI subordinate + - CS + * - PS + - SPI 0 + - AD9517 + - 1 + * - PS + - SPI 0 + - AD9434BCPZ + - 0 + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Below are the Programmable Logic interrupts used in this project. + +================ === ========== =========== +Instance name HDL Linux Zynq Actual Zynq +================ === ========== =========== +axi_ad9783_dma 13 57 89 +================ === ========== =========== + +These are the board-specific interrupts +(found in :git-hdl:`here `). + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI does not distribute the bit/elf files of these projects so they +must be built from the sources available :git-hdl:`here `. To get +the source you must +`clone `__ +the HDL repository. + +Then go to the project location (**projects/ad9434_fmc/carrier**) and run the +make command by typing in your command prompt (this example is for +:xilinx:`ZC706`): + +**Linux/Cygwin/WSL** + +.. code-block:: + + user@analog:~$ cd hdl/projects/ad9434_fmc/zc706 + user@analog:~/hdl/projects/ad9434_fmc/zc706$ make + +A more comprehensive build guide can be found in the :ref:`build_hdl` user +guide. + +Resources +------------------------------------------------------------------------------- + +Systems related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Here you can find the quick start guides available for these evaluation boards: + +.. list-table:: + :widths: 20 10 + :header-rows: 1 + + * - Evaluation board + - Zynq-7000 + * - AD9434-FMC + - :dokuwiki:`ZC706 ` + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheets: :adi:`AD9434` +- :dokuwiki:`EVAL-AD9434 user guide ` + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`AD9434-FMC HDL project source code ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_AD9434 + - :git-hdl:`library/axi_ad9434 ` + - --- + * - AXI_DMAC + - :git-hdl:`library/axi_dmac ` + - :ref:`here ` + * - AXI_CLKGEN + - :git-hdl:`library/axi_clkgen ` + - :dokuwiki:`[Wiki] ` + * - AXI_HDMI_TX + - :git-hdl:`library/axi_hdmi_tx ` + - :dokuwiki:`[Wiki] ` + * - AXI_SPDIF_TX + - :git-hdl:`library/axi_spdif_tx ` + - --- + * - AXI_SYSID + - :git-hdl:`library/axi_sysid ` + - :dokuwiki:`[Wiki] ` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom ` + - :dokuwiki:`[Wiki] ` + +Software related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-linux:`Linux device tree zynq-zc706-adv7511-ad9434-fmc-500ebz.dts ` +- :git-linux:`Linux driver ad9467.c ` + (used for AD9434-FMC as well) + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst \ No newline at end of file diff --git a/projects/ad9434_fmc/zed/Makefile b/projects/ad9434_fmc/zed/Makefile new file mode 100644 index 0000000000..c25ddb25f2 --- /dev/null +++ b/projects/ad9434_fmc/zed/Makefile @@ -0,0 +1,26 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9434_fmc_zed + +M_DEPS += ../common/ad9434_spi.v +M_DEPS += ../common/ad9434_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_ad9434 +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9434_fmc/zed/system_bd.tcl b/projects/ad9434_fmc/zed/system_bd.tcl new file mode 100644 index 0000000000..c156030bee --- /dev/null +++ b/projects/ad9434_fmc/zed/system_bd.tcl @@ -0,0 +1,17 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source ../common/ad9434_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file diff --git a/projects/ad9434_fmc/zed/system_constr.xdc b/projects/ad9434_fmc/zed/system_constr.xdc new file mode 100644 index 0000000000..47ecc160b3 --- /dev/null +++ b/projects/ad9434_fmc/zed/system_constr.xdc @@ -0,0 +1,45 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ad9434 + +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_p] ; ## G6 FMC_LA00_CC_P IO_L13P_T2_MRCC_34 +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_n] ; ## G7 FMC_LA00_CC_N IO_L13N_T2_MRCC_34 + +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[0]] ; ## D17 FMC_LA13_P IO_L4P_T0_34 +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[0]] ; ## D18 FMC_LA13_N IO_L4N_T0_34 +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[1]] ; ## H16 FMC_LA11_P IO_L5P_T0_34 +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[2]] ; ## G15 FMC_LA12_P IO_L18P_T2_34 +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[2]] ; ## G16 FMC_LA12_N IO_L18N_T2_34 +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[3]] ; ## D14 FMC_LA09_P IO_L17P_T2_34 +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[3]] ; ## D15 FMC_LA09_N IO_L17N_T2_34 +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[4]] ; ## C14 FMC_LA10_P IO_L22P_T3_34 +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[4]] ; ## C15 FMC_LA10_N IO_L22N_T3_34 +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[5]] ; ## H13 FMC_LA07_P IO_L21P_T3_DQS_34 +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[5]] ; ## H14 FMC_LA07_N IO_L21N_T3_DQS_34 +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[6]] ; ## G12 FMC_LA08_P IO_L8P_T1_34 +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[6]] ; ## G13 FMC_LA08_N IO_L8N_T1_34 +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[7]] ; ## D11 FMC_LA05_P IO_L7P_T1_34 +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[7]] ; ## D12 FMC_LA05_N IO_L7N_T1_34 +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[8]] ; ## C10 FMC_LA06_P IO_L10P_T1_34 +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[8]] ; ## C11 FMC_LA06_N IO_L10N_T1_34 +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[9]] ; ## H10 FMC_LA04_P IO_L15P_T2_DQS_34 +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[9]] ; ## H11 FMC_LA04_N IO_L15N_T2_DQS_34 +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[10]] ; ## G9 FMC_LA03_P IO_L16P_T2_34 +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[10]] ; ## G10 FMC_LA03_N IO_L16N_T2_34 +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[11]] ; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34 +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[11]] ; ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34 + +#adc + +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_p] ; ## H7 FMC_LA02_P IO_L20P_T3_34 +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_n] ; ## H8 FMC_LA02_N IO_L20N_T3_34 + +#spi + +set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## G36 FMC_LA33_P IO_L18P_T2_AD13P_35 +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## G37 FMC_LA33_N IO_L18N_T2_AD13N_35 +set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports spi_dio] ; ## H37 FMC_LA32_P IO_L15P_T2_DQS_AD12P_35 +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## H38 FMC_LA32_N IO_L15N_T2_DQS_AD12N_35 diff --git a/projects/ad9434_fmc/zed/system_project.tcl b/projects/ad9434_fmc/zed/system_project.tcl new file mode 100644 index 0000000000..80f6768389 --- /dev/null +++ b/projects/ad9434_fmc/zed/system_project.tcl @@ -0,0 +1,18 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project ad9434_fmc_zed +adi_project_files ad9434_fmc_zed [list \ + "../common/ad9434_spi.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +adi_project_run ad9434_fmc_zed diff --git a/projects/ad9434_fmc/zed/system_top.v b/projects/ad9434_fmc/zed/system_top.v new file mode 100644 index 0000000000..9b34e872f2 --- /dev/null +++ b/projects/ad9434_fmc/zed/system_top.v @@ -0,0 +1,226 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output spdif, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + input adc_clk_p, + input adc_clk_n, + input [11:0] adc_data_p, + input [11:0] adc_data_n, + input adc_or_p, + input adc_or_n, + + output spi_csn_clk, + output spi_csn_adc, + output spi_sclk, + inout spi_dio +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + wire spi_miso; + wire spi_mosi; + + assign gpio_i[63:32] = gpio_o[63:32]; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH (32) + ) i_iobuf ( + .dio_t (gpio_t[31:0]), + .dio_i (gpio_o[31:0]), + .dio_o (gpio_i[31:0]), + .dio_p (gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_scl ( + .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_sda ( + .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + ad9434_spi i_spi ( + .spi_csn({spi_csn_clk, spi_csn_adc}), + .spi_clk(spi_sclk), + .spi_mosi(spi_mosi), + .spi_miso(spi_miso), + .spi_sdio(spi_dio)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + + .spdif (spdif), + + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + + .otg_vbusoc (otg_vbusoc), + + .adc_clk_p(adc_clk_p), + .adc_clk_n(adc_clk_n), + .adc_data_p(adc_data_p), + .adc_data_n(adc_data_n), + .adc_or_p(adc_or_p), + .adc_or_n(adc_or_n), + + .spi0_clk_i (spi_sclk), + .spi0_clk_o (spi_sclk), + .spi0_csn_0_o (spi_csn_adc), + .spi0_csn_1_o (spi_csn_clk), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (spi_mosi), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); + +endmodule