From cc748dc7f3e9f7dd6948ed8a8c5197a9d0afcac4 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Wed, 22 Jan 2025 08:28:26 +0200 Subject: [PATCH] util_axis_fifo_asym: Updated after rebase Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/watchdog.sv | 2 +- library/utilities/test_harness_env.sv | 16 +- testbenches/ip/scoreboard/environment.sv | 2 +- .../ip/scoreboard/tests/test_program.sv | 2 +- testbenches/ip/util_axis_fifo_asym/Makefile | 30 +-- .../ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl | 26 ++- .../ip/util_axis_fifo_asym/environment.sv | 178 +++++------------- .../ip/util_axis_fifo_asym/system_bd.tcl | 69 ++++--- .../ip/util_axis_fifo_asym/system_project.tcl | 30 +-- .../ip/util_axis_fifo_asym/system_tb.sv | 14 +- .../util_axis_fifo_asym/tests/test_program.sv | 92 +++++---- 11 files changed, 201 insertions(+), 260 deletions(-) diff --git a/library/drivers/common/watchdog.sv b/library/drivers/common/watchdog.sv index ed09fda6..5d377358 100644 --- a/library/drivers/common/watchdog.sv +++ b/library/drivers/common/watchdog.sv @@ -82,7 +82,7 @@ package watchdog_pkg; fork begin #(this.timer*1ns); - this.error($sformatf("Watchdog timer timed out! %s", this.message)); + this.fatal($sformatf("Watchdog timer timed out! %s", this.message)); end @this.stop_event; join_any diff --git a/library/utilities/test_harness_env.sv b/library/utilities/test_harness_env.sv index 3f05d8b2..50c2566f 100644 --- a/library/utilities/test_harness_env.sv +++ b/library/utilities/test_harness_env.sv @@ -91,9 +91,9 @@ package test_harness_env_pkg; this.mng.agent.start_master(); this.ddr.agent.start_slave(); - this.sys_clk_vip_if.start_clock; - this.dma_clk_vip_if.start_clock; - this.ddr_clk_vip_if.start_clock; + this.sys_clk_vip_if.start_clock(); + this.dma_clk_vip_if.start_clock(); + this.ddr_clk_vip_if.start_clock(); endtask //============================================================================ @@ -103,9 +103,9 @@ package test_harness_env_pkg; this.mng.agent.stop_master(); this.ddr.agent.stop_slave(); - this.sys_clk_vip_if.stop_clock; - this.dma_clk_vip_if.stop_clock; - this.ddr_clk_vip_if.stop_clock; + this.sys_clk_vip_if.stop_clock(); + this.dma_clk_vip_if.stop_clock(); + this.ddr_clk_vip_if.stop_clock(); endtask //============================================================================ @@ -113,9 +113,9 @@ package test_harness_env_pkg; //============================================================================ task sys_reset(); //asserts all the resets for 100 ns - this.sys_rst_vip_if.assert_reset; + this.sys_rst_vip_if.assert_reset(); #200; - this.sys_rst_vip_if.deassert_reset; + this.sys_rst_vip_if.deassert_reset(); #800; endtask diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index 8efbe384..36a298c1 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -18,7 +18,7 @@ package environment_pkg; import scoreboard_pkg::*; - class scoreboard_environment #(`AXIS_VIP_PARAM_DECL(adc_src), `AXIS_VIP_PARAM_DECL(dac_dst), `AXIS_VIP_PARAM_DECL(adc_dst_pt), `AXIS_VIP_PARAM_DECL(dac_src_pt)) extends adi_environment; + class scoreboard_environment #(`AXIS_VIP_PARAM_DECL(adc_src), `AXIS_VIP_PARAM_DECL(dac_dst), `AXI_VIP_PARAM_DECL(adc_dst_pt), `AXI_VIP_PARAM_DECL(dac_src_pt)) extends adi_environment; // Agents adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(adc_src)) adc_src_axis_agent; diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index 962c573f..dc821f98 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -60,7 +60,7 @@ import `PKGIFY(test_harness, dac_src_axi_pt_1)::*; `define ADC_TRANSFER_LENGTH 32'h600 -program test_program; +program test_program(); // declare the class instances test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; diff --git a/testbenches/ip/util_axis_fifo_asym/Makefile b/testbenches/ip/util_axis_fifo_asym/Makefile index ec82fca6..72f90010 100644 --- a/testbenches/ip/util_axis_fifo_asym/Makefile +++ b/testbenches/ip/util_axis_fifo_asym/Makefile @@ -4,30 +4,14 @@ #################################################################################### #################################################################################### -# All test-bench dependencies except test programs -SV_DEPS += ../../../library/utilities/utils.svh -SV_DEPS += ../../../library/utilities/logger_pkg.sv -SV_DEPS += ../../../library/regmaps/reg_accessor.sv -SV_DEPS += ../../../library/vip/amd/m_axis_sequencer.sv -SV_DEPS += ../../../library/vip/amd/s_axis_sequencer.sv -SV_DEPS += ../../../library/vip/amd/m_axi_sequencer.sv -SV_DEPS += ../../../library/vip/amd/s_axi_sequencer.sv -SV_DEPS += ../../../library/utilities/test_harness_env.sv -SV_DEPS += ../../../library/regmaps/adi_peripheral_pkg.sv -SV_DEPS += ../../../library/regmaps/adi_regmap_pkg.sv -SV_DEPS += ../../../library/drivers/common/mailbox.sv -SV_DEPS += ../../../library/drivers/common/x_monitor.sv -SV_DEPS += ../../../library/drivers/common/scoreboard.sv -SV_DEPS += ../../../library/drivers/common/filter.sv -SV_DEPS += ../../../library/drivers/common/interfaces.svh -SV_DEPS += ../../../library/drivers/common/watchdog.sv -SV_DEPS += environment.sv -SV_DEPS += system_tb.sv +# Makeincludes +include ../../../scripts/make_tb_path.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_axis.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_scoreboard.mk -ENV_DEPS += system_project.tcl -ENV_DEPS += system_bd.tcl -ENV_DEPS += ../../../scripts/adi_sim.tcl -ENV_DEPS += ../../../scripts/run_sim.tcl +# Remaining test-bench dependencies except test programs +SV_DEPS += environment.sv LIB_DEPS := util_cdc LIB_DEPS += util_axis_fifo diff --git a/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl b/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl index 632414e6..9cfd760c 100644 --- a/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl +++ b/testbenches/ip/util_axis_fifo_asym/cfgs/cfg_rand.tcl @@ -1,5 +1,14 @@ global ad_project_params +set async_clk [expr int(rand()*2)] +set ad_project_params(ASYNC_CLK) $async_clk + +set tkeep_en [expr int(rand()*2)] +set ad_project_params(TKEEP_EN) $tkeep_en + +set tlast_en [expr int(rand()*2)] +set ad_project_params(TLAST_EN) $tlast_en + set random_width [expr int(8*pow(2, int(7.0*rand()+1)))] set INPUT_WIDTH $random_width set ad_project_params(INPUT_WIDTH) $INPUT_WIDTH @@ -8,10 +17,10 @@ set random_width [expr int(8*pow(2, int(7.0*rand()+1)))] set OUTPUT_WIDTH $random_width set ad_project_params(OUTPUT_WIDTH) $OUTPUT_WIDTH -set FIFO_LIMITED [expr int(rand()*2)] -set ad_project_params(FIFO_LIMITED) $FIFO_LIMITED +set fifo_limited [expr int(rand()*2)] +set ad_project_params(FIFO_LIMITED) $fifo_limited -if {$FIFO_LIMITED} { +if {$fifo_limited} { if {$INPUT_WIDTH > $OUTPUT_WIDTH} { set RATIO $INPUT_WIDTH/$OUTPUT_WIDTH } else { @@ -24,5 +33,12 @@ if {$FIFO_LIMITED} { set random_width [expr int(int(log($RATIO)/log(2))+4.0*rand()+1)] set ad_project_params(ADDRESS_WIDTH) $random_width -set ad_project_params(INPUT_CLK) [expr int(rand()*9000)+1000] -set ad_project_params(OUTPUT_CLK) [expr int(rand()*9000)+1000] +set input_clk [expr int(rand()*9)+1] +set ad_project_params(INPUT_CLK) $input_clk + +if {$async_clk} { + set output_clk [expr int(rand()*9)+1] + set ad_project_params(OUTPUT_CLK) $output_clk +} else { + set ad_project_params(OUTPUT_CLK) $input_clk +} diff --git a/testbenches/ip/util_axis_fifo_asym/environment.sv b/testbenches/ip/util_axis_fifo_asym/environment.sv index d31cfd8c..cff284f7 100644 --- a/testbenches/ip/util_axis_fifo_asym/environment.sv +++ b/testbenches/ip/util_axis_fifo_asym/environment.sv @@ -1,112 +1,72 @@ `include "utils.svh" +`include "axis_definitions.svh" package environment_pkg; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; - import m_axis_sequencer_pkg::*; - import s_axis_sequencer_pkg::*; import logger_pkg::*; - - import axi_vip_pkg::*; + import adi_common_pkg::*; import axi4stream_vip_pkg::*; - import test_harness_env_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import adi_axis_agent_pkg::*; import scoreboard_pkg::*; - import x_monitor_pkg::*; - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; + class util_axis_fifo_environment #(`AXIS_VIP_PARAM_DECL(input_axis), `AXIS_VIP_PARAM_DECL(output_axis), int INPUT_CLK, int OUTPUT_CLK) extends adi_environment; - import `PKGIFY(test_harness, input_axis)::*; - import `PKGIFY(test_harness, output_axis)::*; + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(INPUT_CLK)) input_clk_vip_if; + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(OUTPUT_CLK)) output_clk_vip_if; - class environment extends test_harness_env; + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(input_axis)) input_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(output_axis)) output_axis_agent; - virtual interface clk_if input_clk_if; - virtual interface clk_if output_clk_if; - - // agents and sequencers - `AGENT(test_harness, input_axis, mst_t) input_axis_agent; - `AGENT(test_harness, output_axis, slv_t) output_axis_agent; - - m_axis_sequencer #(`AGENT(test_harness, input_axis, mst_t), - `AXIS_VIP_PARAMS(test_harness, input_axis) - ) input_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, output_axis, slv_t)) output_axis_seq; - - x_axis_monitor #(`AGENT(test_harness, input_axis, mst_t)) input_axis_mon; - x_axis_monitor #(`AGENT(test_harness, output_axis, slv_t)) output_axis_mon; - - scoreboard scoreboard_inst; + scoreboard #(logic [7:0]) scoreboard_inst; //============================================================================ // Constructor //============================================================================ function new ( - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, + input string name, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(INPUT_CLK)) input_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(OUTPUT_CLK)) output_clk_vip_if, - virtual interface clk_if input_clk_if, - virtual interface clk_if output_clk_if, - - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, input_axis)) input_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, output_axis)) output_axis_vip_if - ); + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(input_axis)) input_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(output_axis)) output_axis_vip_if); // creating the agents - super.new(sys_clk_vip_if, - dma_clk_vip_if, - ddr_clk_vip_if, - sys_rst_vip_if, - mng_vip_if, - ddr_vip_if); - - this.input_clk_if = input_clk_if; - this.output_clk_if = output_clk_if; - - input_axis_agent = new("Input AXI Stream Agent", input_axis_vip_if); - output_axis_agent = new("Output AXI Stream Agent", output_axis_vip_if); + super.new(name); - input_axis_seq = new(input_axis_agent); - output_axis_seq = new(output_axis_agent); + this.input_clk_vip_if = input_clk_vip_if; + this.output_clk_vip_if = output_clk_vip_if; - input_axis_mon = new("Input AXIS Transaction Monitor", input_axis_agent); - output_axis_mon = new("Output AXIS Transaction Monitor", output_axis_agent); - - scoreboard_inst = new("Verification Environment Scoreboard"); + this.input_axis_agent = new("Input AXI Stream Agent", input_axis_vip_if, this); + this.output_axis_agent = new("Output AXI Stream Agent", output_axis_vip_if, this); + this.scoreboard_inst = new("Util AXIS FIFO Scoreboard", this); endfunction //============================================================================ // Configure environment //============================================================================ task configure(); - // configuration for input - this.input_axis_seq.set_stop_policy(STOP_POLICY_PACKET); - this.input_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - this.input_axis_seq.set_descriptor_gen_mode(1); - this.input_axis_seq.set_data_beat_delay(0); - this.input_axis_seq.set_descriptor_delay(0); - this.input_axis_seq.set_inactive_drive_output_0(); + this.input_axis_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET); + this.input_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + this.input_axis_agent.sequencer.set_descriptor_gen_mode(1); + this.input_axis_agent.sequencer.set_data_beat_delay(0); + this.input_axis_agent.sequencer.set_descriptor_delay(0); + this.input_axis_agent.sequencer.set_inactive_drive_output_0(); // configuration for output - this.output_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + this.output_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); - // this.output_axis_seq.set_use_variable_ranges(); - // this.output_axis_seq.set_high_time_range(1,1); - // this.output_axis_seq.set_low_time_range(0,0); - - // this.output_axis_seq.clr_use_variable_ranges(); - // this.output_axis_seq.set_high_time(1); - // this.output_axis_seq.set_low_time(1); + // this.output_axis_agent.sequencer.set_use_variable_ranges(); + // this.output_axis_agent.sequencer.set_high_time_range(1,1); + // this.output_axis_agent.sequencer.set_low_time_range(0,0); + // this.output_axis_agent.sequencer.clr_use_variable_ranges(); + // this.output_axis_agent.sequencer.set_high_time(1); + // this.output_axis_agent.sequencer.set_low_time(1); endtask //============================================================================ @@ -115,72 +75,38 @@ package environment_pkg; // - Start the agents //============================================================================ task start(); + this.input_clk_vip_if.start_clock(); + this.output_clk_vip_if.start_clock(); - super.start(); - - input_clk_if.start_clock(`INPUT_CLK); - output_clk_if.start_clock(`OUTPUT_CLK); - - input_axis_agent.start_master(); - output_axis_agent.start_slave(); - - scoreboard_inst.set_source_stream(input_axis_mon); - scoreboard_inst.set_sink_stream(output_axis_mon); + this.input_axis_agent.agent.start_master(); + this.output_axis_agent.agent.start_slave(); + this.input_axis_agent.monitor.publisher.subscribe(this.scoreboard_inst.subscriber_source); + this.output_axis_agent.monitor.publisher.subscribe(this.scoreboard_inst.subscriber_sink); endtask //============================================================================ - // Start the test - // - start the RX scoreboard and sequencer - // - start the TX scoreboard and sequencer - // - setup the RX DMA - // - setup the TX DMA + // Run subroutine //============================================================================ - task test(); - + task run(); fork - input_axis_seq.run(); - output_axis_seq.run(); + this.input_axis_agent.sequencer.run(); + this.output_axis_agent.sequencer.run(); - input_axis_mon.run(); - output_axis_mon.run(); + this.input_axis_agent.monitor.run(); + this.output_axis_agent.monitor.run(); - scoreboard_inst.run(); + this.scoreboard_inst.run(); join_none - - endtask - - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - // Evaluate the scoreboard's results - endtask - - //============================================================================ - // Run subroutine - //============================================================================ - task run; - - //pre_test(); - test(); - endtask //============================================================================ // Stop subroutine //============================================================================ - task stop; - - super.stop(); - - input_axis_seq.stop(); - input_axis_agent.stop_master(); - output_axis_agent.stop_slave(); - - post_test(); - + task stop(); + this.input_axis_agent.sequencer.stop(); + this.input_axis_agent.agent.stop_master(); + this.output_axis_agent.agent.stop_slave(); endtask endclass diff --git a/testbenches/ip/util_axis_fifo_asym/system_bd.tcl b/testbenches/ip/util_axis_fifo_asym/system_bd.tcl index 2e33dd51..66fd1740 100644 --- a/testbenches/ip/util_axis_fifo_asym/system_bd.tcl +++ b/testbenches/ip/util_axis_fifo_asym/system_bd.tcl @@ -33,67 +33,94 @@ # *************************************************************************** # *************************************************************************** -global ad_hdl_dir - -source ../../../../scripts/adi_env.tcl - -# system level parameters global ad_project_params +set ASYNC_CLK $ad_project_params(ASYNC_CLK) +set TKEEP_EN $ad_project_params(TKEEP_EN) +set TLAST_EN $ad_project_params(TLAST_EN) set INPUT_WIDTH $ad_project_params(INPUT_WIDTH) set OUTPUT_WIDTH $ad_project_params(OUTPUT_WIDTH) set FIFO_LIMITED $ad_project_params(FIFO_LIMITED) set ADDRESS_WIDTH $ad_project_params(ADDRESS_WIDTH) +set INPUT_CLK $ad_project_params(INPUT_CLK) +set OUTPUT_CLK $ad_project_params(OUTPUT_CLK) + +# Input clock +ad_ip_instance clk_vip input_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ [expr pow(10, 9)/$INPUT_CLK] \ +] +adi_sim_add_define "INPUT_CLK_VIP=input_clk_vip" + +ad_ip_instance clk_vip output_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ [expr pow(10, 9)/$OUTPUT_CLK] \ +] +adi_sim_add_define "OUTPUT_CLK_VIP=output_clk_vip" + +ad_connect input_clk input_clk_vip/clk_out +ad_connect output_clk output_clk_vip/clk_out + +ad_ip_instance proc_sys_reset input_rstgen +ad_ip_parameter input_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +ad_ip_instance proc_sys_reset output_rstgen +ad_ip_parameter output_rstgen CONFIG.C_EXT_RST_WIDTH 1 -# input clock and reset -create_bd_port -dir I input_clk +ad_connect sys_rst_vip/rst_out input_rstgen/ext_reset_in +ad_connect sys_rst_vip/rst_out output_rstgen/ext_reset_in -# output clock and reset -create_bd_port -dir I output_clk +ad_connect input_clk input_rstgen/slowest_sync_clk +ad_connect output_clk output_rstgen/slowest_sync_clk +ad_connect input_resetn input_rstgen/peripheral_aresetn +ad_connect output_resetn output_rstgen/peripheral_aresetn ad_ip_instance util_axis_fifo_asym util_axis_fifo_asym_DUT [list \ - ASYNC_CLK 1 \ + ASYNC_CLK $ASYNC_CLK \ S_DATA_WIDTH $INPUT_WIDTH \ ADDRESS_WIDTH $ADDRESS_WIDTH \ M_DATA_WIDTH $OUTPUT_WIDTH \ M_AXIS_REGISTERED 1 \ - ALMOST_EMPTY_THRESHOLD 16 \ - ALMOST_FULL_THRESHOLD 16 \ - TLAST_EN 1 \ - TKEEP_EN 1 \ + ALMOST_EMPTY_THRESHOLD 0 \ + ALMOST_FULL_THRESHOLD 0 \ + TLAST_EN $TLAST_EN \ + TKEEP_EN $TKEEP_EN \ FIFO_LIMITED $FIFO_LIMITED \ ADDRESS_WIDTH_PERSPECTIVE 0 \ ] ad_connect input_clk util_axis_fifo_asym_DUT/s_axis_aclk -ad_connect sys_cpu_resetn util_axis_fifo_asym_DUT/s_axis_aresetn +ad_connect input_resetn util_axis_fifo_asym_DUT/s_axis_aresetn ad_connect output_clk util_axis_fifo_asym_DUT/m_axis_aclk -ad_connect sys_cpu_resetn util_axis_fifo_asym_DUT/m_axis_aresetn +ad_connect output_resetn util_axis_fifo_asym_DUT/m_axis_aresetn ad_ip_instance axi4stream_vip input_axis [list \ INTERFACE_MODE {MASTER} \ HAS_TREADY {1} \ - HAS_TLAST {1} \ - HAS_TKEEP {1} \ + TDEST_WIDTH {0} \ + TID_WIDTH {0} \ + HAS_TLAST $TLAST_EN \ + HAS_TKEEP $TKEEP_EN \ TDATA_NUM_BYTES [expr {$INPUT_WIDTH/8}] \ ] adi_sim_add_define "INPUT_AXIS=input_axis" ad_connect input_clk input_axis/aclk -ad_connect sys_cpu_resetn input_axis/aresetn +ad_connect input_resetn input_axis/aresetn ad_connect util_axis_fifo_asym_DUT/s_axis input_axis/m_axis ad_ip_instance axi4stream_vip output_axis [list \ INTERFACE_MODE {SLAVE} \ + HAS_TLAST $TLAST_EN \ + HAS_TKEEP $TKEEP_EN \ TDATA_NUM_BYTES [expr {$OUTPUT_WIDTH/8}] \ - HAS_TLAST {1} \ ] adi_sim_add_define "OUTPUT_AXIS=output_axis" ad_connect output_clk output_axis/aclk -ad_connect sys_cpu_resetn output_axis/aresetn +ad_connect output_resetn output_axis/aresetn ad_connect util_axis_fifo_asym_DUT/m_axis output_axis/s_axis diff --git a/testbenches/ip/util_axis_fifo_asym/system_project.tcl b/testbenches/ip/util_axis_fifo_asym/system_project.tcl index 4245b0ec..86b8f596 100644 --- a/testbenches/ip/util_axis_fifo_asym/system_project.tcl +++ b/testbenches/ip/util_axis_fifo_asym/system_project.tcl @@ -1,6 +1,4 @@ source ../../../scripts/adi_sim.tcl -source ../../../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl if {$argc < 1} { puts "Expecting at least one argument that specifies the test configuration" @@ -12,36 +10,20 @@ if {$argc < 1} { # Read config file source "cfgs/${cfg_file}" -global ad_project_params - # Set the project name set project_name [file rootname $cfg_file] # Create the project adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" +source $ad_tb_dir/library/includes/sp_include_axis.tcl +source $ad_tb_dir/library/includes/sp_include_scoreboard.tcl + # Add test files to the project adi_sim_project_files [list \ - "../../../library/utilities/utils.svh" \ - "../../../library/utilities/logger_pkg.sv" \ - "../../../library/regmaps/reg_accessor.sv" \ - "../../../library/vip/amd/m_axis_sequencer.sv" \ - "../../../library/vip/amd/s_axis_sequencer.sv" \ - "../../../library/vip/amd/m_axi_sequencer.sv" \ - "../../../library/vip/amd/s_axi_sequencer.sv" \ - "../../../library/regmaps/adi_peripheral_pkg.sv" \ - "../../../library/regmaps/adi_regmap_pkg.sv" \ - "../../../library/utilities/test_harness_env.sv" \ - "../../../library/drivers/common/mailbox.sv" \ - "../../../library/drivers/common/x_monitor.sv" \ - "../../../library/drivers/common/scoreboard.sv" \ - "../../../library/drivers/common/filter.sv" \ - "../../../library/drivers/common/interfaces.svh" \ - "../../../library/drivers/common/watchdog.sv" \ - "environment.sv" \ - "tests/test_program.sv" \ - "system_tb.sv" \ - ] + "environment.sv" \ + "tests/test_program.sv" \ +] #set a default test program adi_sim_add_define "TEST_PROGRAM=test_program" diff --git a/testbenches/ip/util_axis_fifo_asym/system_tb.sv b/testbenches/ip/util_axis_fifo_asym/system_tb.sv index ea79f943..e92f32ea 100644 --- a/testbenches/ip/util_axis_fifo_asym/system_tb.sv +++ b/testbenches/ip/util_axis_fifo_asym/system_tb.sv @@ -36,21 +36,11 @@ `timescale 1ns/1ps `include "utils.svh" -`include "interfaces.svh" module system_tb(); - clk_if input_clk_if(); - clk_if output_clk_if(); + `TEST_PROGRAM test(); - `TEST_PROGRAM test( - .input_clk_if(input_clk_if), - .output_clk_if(output_clk_if) - ); - - test_harness `TH ( - .input_clk (input_clk_if.clk), - .output_clk (output_clk_if.clk) - ); + test_harness `TH (); endmodule diff --git a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv index 10814784..8608bb06 100644 --- a/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv +++ b/testbenches/ip/util_axis_fifo_asym/tests/test_program.sv @@ -36,79 +36,95 @@ // // `include "utils.svh" +`include "axis_definitions.svh" -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; +import test_harness_env_pkg::*; import environment_pkg::*; -import m_axis_sequencer_pkg::*; -import s_axis_sequencer_pkg::*; import watchdog_pkg::*; -program test_program ( - clk_if input_clk_if, - clk_if output_clk_if); +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, input_axis)::*; +import `PKGIFY(test_harness, output_axis)::*; + +program test_program (); // declare the class instances - environment env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + util_axis_fifo_environment #(`AXIS_VIP_PARAMS(test_harness, input_axis), `AXIS_VIP_PARAMS(test_harness, output_axis), `INPUT_CLK, `OUTPUT_CLK) uaf_env; watchdog send_data_wd; initial begin // create environment - env = new(`TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - - input_clk_if, - output_clk_if, - - `TH.`INPUT_AXIS.inst.IF, - `TH.`OUTPUT_AXIS.inst.IF - ); - - setLoggerVerbosity(5); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + uaf_env = new("Util AXIS FIFO Environment", + `TH.`INPUT_CLK_VIP.inst.IF, + `TH.`OUTPUT_CLK_VIP.inst.IF, + `TH.`INPUT_AXIS.inst.IF, + `TH.`OUTPUT_AXIS.inst.IF); + + setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + uaf_env.start(); + + base_env.sys_reset(); - env.configure(); + uaf_env.configure(); + uaf_env.input_axis_agent.sequencer.set_keep_some(); - env.run(); + uaf_env.run(); - send_data_wd = new(500000, "Send data"); + send_data_wd = new("Util AXIS FIFO Watchdog", 500000, "Send data"); send_data_wd.start(); - env.input_axis_seq.start(); + uaf_env.input_axis_agent.sequencer.start(); // stimulus - repeat($urandom_range(5,13)) begin + repeat($urandom_range(5,10)) begin send_data_wd.reset(); - repeat($urandom_range(1,5)) - env.input_axis_seq.add_xfer_descriptor($urandom_range(1,1000), 1, 0); + if ((!`TKEEP_EN || !`TLAST_EN) && `INPUT_WIDTH < `OUTPUT_WIDTH) begin + repeat($urandom_range(1,5)) begin + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor_packet_size($urandom_range(1,128)*`OUTPUT_WIDTH/`INPUT_WIDTH, `TLAST_EN, 0); + end + end else begin + repeat($urandom_range(1,5)) begin + uaf_env.input_axis_agent.sequencer.add_xfer_descriptor($urandom_range(1,1024), `TLAST_EN, 0); + end + end #($urandom_range(1,10)*1us); - env.input_axis_seq.clear_descriptor_queue(); + uaf_env.input_axis_agent.sequencer.clear_descriptor_queue(); #1us; - env.scoreboard_inst.wait_until_complete(); + uaf_env.scoreboard_inst.wait_until_complete(); - `INFOV(("Packet finished."), 5); + `INFO(("Packet finished."), ADI_VERBOSITY_LOW); end send_data_wd.stop(); - - env.stop(); + + #100ns; + + uaf_env.stop(); + base_env.stop(); - `INFO(("Test bench done!")); + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); end