diff --git a/library/drivers/common/filter.sv b/library/drivers/common/filter.sv new file mode 100644 index 00000000..7243e192 --- /dev/null +++ b/library/drivers/common/filter.sv @@ -0,0 +1,116 @@ +`include "utils.svh" + +package filter_pkg; + + import logger_pkg::*; + + class filter_class; + + protected bit [31:0] position; + protected logic [7:0] value; + protected bit equals; + + bit result; + + function new( + input bit [31:0] position, + input logic [7:0] value, + input bit equals = 1); + + this.position = position; + this.value = value; + this.equals = equals; + this.result = 0; + endfunction: new + + function void apply_filter(input logic [7:0] packet[]); + logic [7:0] value; + + value = packet[this.position]; + for (int i=0; i< $size(value); i++) + if (this.value[i] == 1'bx || this.value[i] == 1'bz) continue; + else if (this.value[i] != value[i]) begin + this.result = !equals; + return; + end + + this.result = equals; + return; + endfunction: apply_filter + + endclass: filter_class + + + class filter_tree_class; + + protected bit filter_type; // 0 - all leaf nodes/cells are evaluated with logical or + // 1 - all leaf nodes/cells are evaluated with logical and + + bit result; + + protected filter_class filter[]; + filter_tree_class ft[]; + + function new( + input bit filter_type, + input bit [31:0] nr_of_filters, + input bit [31:0] nr_of_filter_trees); + + this.filter_type = filter_type; + this.result = filter_type; + this.filter = new[nr_of_filters]; + this.ft = new[nr_of_filter_trees]; + endfunction: new + + function void add_filter( + input bit [31:0] filter_nr, + input bit [31:0] position, + input logic [7:0] value, + input bit equals = 1); + + this.filter[filter_nr] = new (position, value, equals); + endfunction: add_filter + + function void add_filter_tree( + input bit [31:0] filter_tree_nr, + input bit filter_type, + input bit [31:0] nr_of_filters, + input bit [31:0] nr_of_filter_trees); + + this.ft[filter_tree_nr] = new (filter_type, nr_of_filters, nr_of_filter_trees); + endfunction: add_filter_tree + + function void remove_filters(); + this.filter = new[0]; + this.ft = new[0]; + endfunction: remove_filters + + task apply_filter(input logic [7:0] packet[]); + if (this.filter != null) begin + for (int i=0; i>source_transaction_event; this.source_monitor.put_key(); + + if (this.filter_enabled) + this.filter_tree_source.apply_filter(packet); + + if (!this.filter_enabled || this.filter_tree_source.result) begin + for (int i=0; i>source_transaction_event; + end end endtask: get_source_transaction @@ -148,6 +215,7 @@ package scoreboard_pkg; task get_sink_transaction(); logic [7:0] sink_byte; + logic [7:0] packet []; forever begin fork begin @@ -162,15 +230,26 @@ package scoreboard_pkg; break; this.sink_monitor.get_key(); - for (int i=0; i>sink_transaction_event; this.sink_monitor.put_key(); + + if (this.filter_enabled) + this.filter_tree_sink.apply_filter(packet); + + if (!this.filter_enabled || this.filter_tree_sink.result) begin + for (int i=0; i>sink_transaction_event; + end end endtask: get_sink_transaction @@ -190,7 +269,7 @@ package scoreboard_pkg; (this.sink_byte_stream_size > 0)) begin byte_streams_empty_sig = 0; source_byte = this.source_byte_stream.pop_back(); - if (this.sink_type == CYCLIC) + if (this.transfer_type == CYCLIC) this.source_byte_stream.push_front(source_byte); else this.source_byte_stream_size--; @@ -201,10 +280,16 @@ package scoreboard_pkg; `ERROR(("Scoreboard failed at: exp %h - rcv %h", source_byte, sink_byte)); end end else begin - if ((this.source_byte_stream_size == 0) && - (this.sink_byte_stream_size == 0)) begin - byte_streams_empty_sig = 1; - ->>byte_streams_empty; + if (this.sink_byte_stream_size == 0) begin + if (this.transfer_type == CYCLIC) begin + byte_streams_empty_sig = 1; + ->>byte_streams_empty; + end else begin + if ((this.source_byte_stream_size == 0)) begin + byte_streams_empty_sig = 1; + ->>byte_streams_empty; + end + end end fork begin fork diff --git a/library/drivers/common/scoreboard_pack.sv b/library/drivers/common/scoreboard_pack.sv index fe2a5c6f..a058fbd4 100644 --- a/library/drivers/common/scoreboard_pack.sv +++ b/library/drivers/common/scoreboard_pack.sv @@ -66,7 +66,7 @@ package scoreboard_pack_pkg; for (int j=0; j>byte_streams_empty; + if (this.sink_byte_stream_size < this.channels*this.samples*this.width/8) begin + if (this.transfer_type == CYCLIC) begin + byte_streams_empty_sig = 1; + ->>byte_streams_empty; + end else begin + if ((this.source_byte_stream_size == 0)) begin + byte_streams_empty_sig = 1; + ->>byte_streams_empty; + end + end end fork begin fork diff --git a/library/drivers/common/watchdog.sv b/library/drivers/common/watchdog.sv index 3eb6fd84..e5c84228 100644 --- a/library/drivers/common/watchdog.sv +++ b/library/drivers/common/watchdog.sv @@ -63,12 +63,11 @@ package watchdog_pkg; task reset(); this.stop(); - #1step; this.start(); endtask: reset task stop(); - ->>this.stop_event; + ->this.stop_event; endtask: stop task start(); diff --git a/library/drivers/common/x_monitor.sv b/library/drivers/common/x_monitor.sv index f2f69994..e2849a5e 100644 --- a/library/drivers/common/x_monitor.sv +++ b/library/drivers/common/x_monitor.sv @@ -8,14 +8,17 @@ package x_monitor_pkg; import logger_pkg::*; import mailbox_pkg::*; + class x_monitor extends xil_component; mailbox_c #(logic [7:0]) mailbox; protected semaphore semaphore_key; protected event transaction_event; + protected event scoreboard_event; protected bit enabled; + // constructor function new(input string name); super.new(name); @@ -35,7 +38,7 @@ package x_monitor_pkg; // event functions task transaction_captured(); - ->>this.transaction_event; + ->this.transaction_event; endtask task wait_for_transaction_event(); @@ -44,42 +47,28 @@ package x_monitor_pkg; // run task task run(); - fork this.enabled = 1; get_transaction(); join_none + endtask - endtask /* run */ - - // virtual functions - virtual function void set_sink_type(input bit sink_type); - endfunction - - virtual function bit get_sink_type(); + virtual function bit get_packet_type(); endfunction virtual task get_transaction(); endtask - endclass + endclass: x_monitor - typedef enum bit { - READ_OP = 1'b0, - WRITE_OP = 1'b1 - } operation_type_t; - class x_axi_monitor #( type T, operation_type_t operation_type ) extends x_monitor; - // operation type: 1 - write - // 0 - read + class x_axi_monitor #( type T, xil_axi_cmd_t operation_type ) extends x_monitor; // analysis port from the monitor protected xil_analysis_port #(axi_monitor_transaction) axi_ap; protected T agent; - protected int axi_byte_stream_size; - // constructor function new(input string name, T agent); @@ -90,64 +79,73 @@ package x_monitor_pkg; this.agent = agent; this.axi_ap = this.agent.monitor.item_collected_port; - this.axi_byte_stream_size = 0; + endfunction: new - endfunction /* new */ + // check if monitor is sending an entire packet at once + virtual function bit get_packet_type(); + return 1; + endfunction: get_packet_type - // collect data from the DDR interface, all WRITE transaction are coming - // from the ADC and all READ transactions are going to the DAC + // collect data from an AXI4 interface + // to monitor both operations, use 2 monitors virtual task get_transaction(); axi_monitor_transaction transaction; xil_axi_data_beat data_beat; xil_axi_strb_beat strb_beat; + int transaction_length; int num_bytes; - logic [7:0] axi_byte; + int valid_bytes; + logic [7:0] axi_packet []; forever begin - this.get_key(); this.axi_ap.get(transaction); - if (bit'(transaction.get_cmd_type()) == operation_type) begin - this.put_key(); + if (transaction.get_cmd_type() == operation_type) begin num_bytes = transaction.get_data_width()/8; - for (int i=0; i<(transaction.get_len()+1); i++) begin + transaction_length = transaction.get_len()+1; + + for (int i=0; i> disable_ev; - #1step; endtask: stop task run(); diff --git a/library/vip/amd/s_axis_sequencer.sv b/library/vip/amd/s_axis_sequencer.sv index eede6bac..300bd581 100644 --- a/library/vip/amd/s_axis_sequencer.sv +++ b/library/vip/amd/s_axis_sequencer.sv @@ -59,7 +59,7 @@ package s_axis_sequencer_pkg; // new function new(); - this.mode = XIL_AXI4STREAM_READY_GEN_RANDOM; + this.mode = XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE; this.low_time = 0; this.high_time = 1; this.high_time_min = 1; diff --git a/testbenches/ip/axis_sequencers/tests/test_program.sv b/testbenches/ip/axis_sequencers/tests/test_program.sv index c44e2f35..80ddc65d 100644 --- a/testbenches/ip/axis_sequencers/tests/test_program.sv +++ b/testbenches/ip/axis_sequencers/tests/test_program.sv @@ -69,8 +69,6 @@ program test_program; `TH.`DST_AXIS.inst.IF ); - #1step; - setLoggerVerbosity(250); env.start(); @@ -123,8 +121,6 @@ program test_program; env.src_axis_seq.start(); - #1step; - case (`SRC_DESCRIPTORS) 1: //env.src_axis_seq.beat_sent(); env.src_axis_seq.packet_sent(); diff --git a/testbenches/ip/base/Makefile b/testbenches/ip/base/Makefile index 174b9836..e92a6d9b 100644 --- a/testbenches/ip/base/Makefile +++ b/testbenches/ip/base/Makefile @@ -18,6 +18,7 @@ SV_DEPS += ../../../library/regmaps/adi_regmap_pkg.sv SV_DEPS += ../../../library/drivers/common/mailbox.sv SV_DEPS += ../../../library/drivers/common/x_monitor.sv SV_DEPS += ../../../library/drivers/common/scoreboard.sv +SV_DEPS += ../../../library/drivers/common/filter.sv SV_DEPS += ../../../library/drivers/common/watchdog.sv SV_DEPS += environment.sv SV_DEPS += system_tb.sv diff --git a/testbenches/ip/base/system_project.tcl b/testbenches/ip/base/system_project.tcl index 54e1f340..c7735013 100644 --- a/testbenches/ip/base/system_project.tcl +++ b/testbenches/ip/base/system_project.tcl @@ -33,6 +33,7 @@ adi_sim_project_files [list \ "../../../library/drivers/common/mailbox.sv" \ "../../../library/drivers/common/x_monitor.sv" \ "../../../library/drivers/common/scoreboard.sv" \ + "../../../library/drivers/common/filter.sv" \ "../../../library/drivers/common/watchdog.sv" \ "environment.sv" \ "tests/test_program.sv" \ diff --git a/testbenches/ip/packet_filter/Makefile b/testbenches/ip/packet_filter/Makefile new file mode 100644 index 00000000..81afb3dd --- /dev/null +++ b/testbenches/ip/packet_filter/Makefile @@ -0,0 +1,54 @@ +#################################################################################### +#################################################################################### +## Copyright 2024(c) Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# All test-bench dependencies except test programs +SV_DEPS += ../common/sv/utils.svh +SV_DEPS += ../common/sv/logger_pkg.sv +SV_DEPS += ../common/sv/reg_accessor.sv +SV_DEPS += ../common/sv/m_axis_sequencer.sv +SV_DEPS += ../common/sv/s_axis_sequencer.sv +SV_DEPS += ../common/sv/m_axi_sequencer.sv +SV_DEPS += ../common/sv/s_axi_sequencer.sv +SV_DEPS += ../common/sv/test_harness_env.sv +SV_DEPS += ../common/sv/adi_peripheral_pkg.sv +SV_DEPS += ../common/sv/adi_regmap_pkg.sv +SV_DEPS += ../common/sv/mailbox.sv +SV_DEPS += ../common/sv/x_monitor.sv +SV_DEPS += ../common/sv/scoreboard.sv +SV_DEPS += ../common/sv/watchdog.sv +SV_DEPS += ../common/sv/filter.sv +SV_DEPS += environment.sv +SV_DEPS += system_tb.sv + +ENV_DEPS += system_project.tcl +ENV_DEPS += system_bd.tcl +ENV_DEPS +=../scripts/adi_sim.tcl +ENV_DEPS +=../scripts/run_sim.tcl + +# default test program +TP := test_program + +# config files should have the following format +# cfg__.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) +#$(warning $(CFG_FILES)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP))) + +include ../scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui +# +# run all test from a configuration +# make cfg1_mm2mm_default + +#################################################################################### +#################################################################################### diff --git a/testbenches/ip/packet_filter/README.md b/testbenches/ip/packet_filter/README.md new file mode 100644 index 00000000..7c6d0faa --- /dev/null +++ b/testbenches/ip/packet_filter/README.md @@ -0,0 +1,35 @@ +Base design to be copied when starting to work on a new testbench. + +By default includes: + + * all the files that are needed for any testbench + * scoreboard and auxiliary module imports, ready to be integrated + * new environment file ready to expand the base test harness environment + * test program that powers up and shuts down the system + * option to add manual seeding + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/testbenches/ip/packet_filter/cfgs/cfg1.tcl b/testbenches/ip/packet_filter/cfgs/cfg1.tcl new file mode 100644 index 00000000..d040d253 --- /dev/null +++ b/testbenches/ip/packet_filter/cfgs/cfg1.tcl @@ -0,0 +1 @@ +global ad_project_params diff --git a/testbenches/ip/packet_filter/environment.sv b/testbenches/ip/packet_filter/environment.sv new file mode 100644 index 00000000..970789c5 --- /dev/null +++ b/testbenches/ip/packet_filter/environment.sv @@ -0,0 +1,93 @@ +`include "utils.svh" + +package environment_pkg; + + import m_axi_sequencer_pkg::*; + import s_axi_sequencer_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import logger_pkg::*; + + import axi_vip_pkg::*; + import axi4stream_vip_pkg::*; + import test_harness_env_pkg::*; + import scoreboard_pkg::*; + import x_monitor_pkg::*; + + import `PKGIFY(test_harness, mng_axi_vip)::*; + import `PKGIFY(test_harness, ddr_axi_vip)::*; + + class environment extends test_harness_env; + + /* Add agents and sequencers */ + + //============================================================================ + // Constructor + //============================================================================ + function new ( + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, + virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, + + virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, + + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if + ); + + // Creating the agents + super.new(sys_clk_vip_if, + dma_clk_vip_if, + ddr_clk_vip_if, + sys_rst_vip_if, + mng_vip_if, + ddr_vip_if); + + endfunction + + //============================================================================ + // Start environment + //============================================================================ + task start(); + + super.start(); + + endtask + + //============================================================================ + // Start the test + //============================================================================ + task test(); + endtask + + + //============================================================================ + // Post test subroutine + //============================================================================ + task post_test(); + endtask + + //============================================================================ + // Run subroutine + //============================================================================ + task run; + + //pre_test(); + test(); + + endtask + + //============================================================================ + // Stop subroutine + //============================================================================ + task stop; + + super.stop(); + + post_test(); + + endtask + + endclass + +endpackage diff --git a/testbenches/ip/packet_filter/system_bd.tcl b/testbenches/ip/packet_filter/system_bd.tcl new file mode 100644 index 00000000..8f1707c4 --- /dev/null +++ b/testbenches/ip/packet_filter/system_bd.tcl @@ -0,0 +1,40 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_hdl_dir + +source ../../scripts/adi_env.tcl + +global ad_project_params diff --git a/testbenches/ip/packet_filter/system_project.tcl b/testbenches/ip/packet_filter/system_project.tcl new file mode 100644 index 00000000..5c947852 --- /dev/null +++ b/testbenches/ip/packet_filter/system_project.tcl @@ -0,0 +1,50 @@ +source ../scripts/adi_sim.tcl +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read config file +source "cfgs/${cfg_file}" + +# Set the project name +set project_name [file rootname $cfg_file] + +# Create the project +adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" + +# Add test files to the project +adi_sim_project_files [list \ + "../common/sv/utils.svh" \ + "../common/sv/logger_pkg.sv" \ + "../common/sv/reg_accessor.sv" \ + "../common/sv/m_axis_sequencer.sv" \ + "../common/sv/s_axis_sequencer.sv" \ + "../common/sv/m_axi_sequencer.sv" \ + "../common/sv/s_axi_sequencer.sv" \ + "../common/sv/adi_peripheral_pkg.sv" \ + "../common/sv/adi_regmap_pkg.sv" \ + "../common/sv/test_harness_env.sv" \ + "../common/sv/mailbox.sv" \ + "../common/sv/x_monitor.sv" \ + "../common/sv/scoreboard.sv" \ + "../common/sv/watchdog.sv" \ + "../common/sv/filter.sv" \ + "environment.sv" \ + "tests/test_program.sv" \ + "system_tb.sv" \ + ] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name + +# Use this only for debugging specific seeds that failed previously +#set_property -name {xsim.simulate.xsim.more_options} -value {-sv_seed 1695199824} -objects [get_filesets sim_1] + diff --git a/testbenches/ip/packet_filter/system_tb.sv b/testbenches/ip/packet_filter/system_tb.sv new file mode 100644 index 00000000..b2e0c285 --- /dev/null +++ b/testbenches/ip/packet_filter/system_tb.sv @@ -0,0 +1,45 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2024 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" + +module system_tb(); + + `TEST_PROGRAM test(); + test_harness `TH (); + +endmodule diff --git a/testbenches/ip/packet_filter/tests/test_program.sv b/testbenches/ip/packet_filter/tests/test_program.sv new file mode 100644 index 00000000..7431946a --- /dev/null +++ b/testbenches/ip/packet_filter/tests/test_program.sv @@ -0,0 +1,124 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; +import logger_pkg::*; +import environment_pkg::*; +import filter_pkg::*; + +program test_program; + + // Declare the class instances + environment env; + + // Process variables + process current_process; + string current_process_random_state; + + logic [7:0] packet_to_filter[8]; + filter_tree_class ft; + + + initial begin + + current_process = process::self(); + current_process_random_state = current_process.get_randstate(); + `INFO(("Randomization state: %s", current_process_random_state)); + + setLoggerVerbosity(250); + + // Create environment + env = new(`TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF + ); + + env.start(); + env.sys_reset(); + + /* Add other configurations if necessary before calling run */ + + env.run(); + + /* Add stimulus tasks */ + + packet_to_filter[0] = 8'h08; + packet_to_filter[1] = 8'h19; + packet_to_filter[2] = 8'h2A; + packet_to_filter[3] = 8'h3B; + packet_to_filter[4] = 8'h4C; + packet_to_filter[5] = 8'h5D; + packet_to_filter[6] = 8'h6E; + packet_to_filter[7] = 8'h7F; + + ft = new( + .filter_type(0), + .nr_of_filters(1), + .nr_of_filter_trees(1)); + ft.add_filter( + .filter_nr(0), + .position(0), + .value(8'hX8)); + ft.add_filter_tree( + .filter_tree_nr(0), + .filter_type(1), + .nr_of_filters(2), + .nr_of_filter_trees(0)); + ft.ft[0].add_filter( + .filter_nr(0), + .position(0), + .value(8'hX9)); + ft.ft[0].add_filter( + .filter_nr(1), + .position(7), + .value(8'b0111111X)); + + ft.apply_filter(packet_to_filter); + `INFO(("Filter result: %d", ft.result)); + + env.stop(); + + `INFO(("Test bench done!")); + $finish(); + + end + +endprogram diff --git a/testbenches/ip/packet_filter/waves/cfg1.wcfg b/testbenches/ip/packet_filter/waves/cfg1.wcfg new file mode 100644 index 00000000..2fe219f8 --- /dev/null +++ b/testbenches/ip/packet_filter/waves/cfg1.wcfg @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testbenches/ip/scoreboard/Makefile b/testbenches/ip/scoreboard/Makefile index 492afe87..58a1ac85 100644 --- a/testbenches/ip/scoreboard/Makefile +++ b/testbenches/ip/scoreboard/Makefile @@ -18,6 +18,7 @@ SV_DEPS += ../../../library/regmaps/adi_regmap_pkg.sv SV_DEPS += ../../../library/drivers/common/mailbox.sv SV_DEPS += ../../../library/drivers/common/x_monitor.sv SV_DEPS += ../../../library/drivers/common/scoreboard.sv +SV_DEPS += ../../../library/drivers/common/filter.sv SV_DEPS += ../../../library/drivers/dmac/dmac_api.sv SV_DEPS += ../../../library/drivers/dmac/dma_trans.sv SV_DEPS += ../../../library/regmaps/adi_regmap_dmac_pkg.sv diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index 57f88619..9db1a359 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -56,13 +56,13 @@ package environment_pkg; x_axis_monitor #(`AGENT(test_harness, adc_src_axis_0, mst_t)) adc_src_axis_0_mon; x_axis_monitor #(`AGENT(test_harness, dac_dst_axis_0, slv_t)) dac_dst_axis_0_mon; - x_axi_monitor #(`AGENT(test_harness, adc_dst_axi_pt_0, passthrough_mem_t), WRITE_OP) adc_dst_axi_pt_0_mon; - x_axi_monitor #(`AGENT(test_harness, dac_src_axi_pt_0, passthrough_mem_t), READ_OP) dac_src_axi_pt_0_mon; + x_axi_monitor #(`AGENT(test_harness, adc_dst_axi_pt_0, passthrough_mem_t), XIL_AXI_WRITE) adc_dst_axi_pt_0_mon; + x_axi_monitor #(`AGENT(test_harness, dac_src_axi_pt_0, passthrough_mem_t), XIL_AXI_READ) dac_src_axi_pt_0_mon; // x_axis_monitor #(`AGENT(test_harness, adc_src_axis_1, mst_t)) adc_src_axis_1_mon; // x_axis_monitor #(`AGENT(test_harness, dac_dst_axis_1, slv_t)) dac_dst_axis_1_mon; - // x_axi_monitor #(`AGENT(test_harness, adc_dst_axi_pt_1, passthrough_mem_t), WRITE_OP) adc_dst_axi_pt_1_mon; - // x_axi_monitor #(`AGENT(test_harness, dac_src_axi_pt_1, passthrough_mem_t), READ_OP) dac_src_axi_pt_1_mon; + // x_axi_monitor #(`AGENT(test_harness, adc_dst_axi_pt_1, passthrough_mem_t), XIL_AXI_WRITE) adc_dst_axi_pt_1_mon; + // x_axi_monitor #(`AGENT(test_harness, dac_src_axi_pt_1, passthrough_mem_t), XIL_AXI_READ) dac_src_axi_pt_1_mon; scoreboard scoreboard_tx0; scoreboard scoreboard_rx0; diff --git a/testbenches/ip/scoreboard/system_project.tcl b/testbenches/ip/scoreboard/system_project.tcl index 27649425..93689472 100644 --- a/testbenches/ip/scoreboard/system_project.tcl +++ b/testbenches/ip/scoreboard/system_project.tcl @@ -33,6 +33,7 @@ adi_sim_project_files [list \ "../../../library/drivers/common/mailbox.sv" \ "../../../library/drivers/common/x_monitor.sv" \ "../../../library/drivers/common/scoreboard.sv" \ + "../../../library/drivers/common/filter.sv" \ "../../../library/drivers/dmac/dmac_api.sv" \ "../../../library/drivers/dmac/dma_trans.sv" \ "../../../library/regmaps/adi_regmap_dmac_pkg.sv" \ diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index b75ea956..d4f83d0c 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -98,7 +98,7 @@ program test_program; //========================================================================= - setLoggerVerbosity(250); + setLoggerVerbosity(9); env.start(); env.sys_reset(); diff --git a/testbenches/ip/util_pack/Makefile b/testbenches/ip/util_pack/Makefile index 0e2bb8b9..2b148427 100644 --- a/testbenches/ip/util_pack/Makefile +++ b/testbenches/ip/util_pack/Makefile @@ -19,6 +19,7 @@ SV_DEPS += ../../../library/drivers/common/mailbox.sv SV_DEPS += ../../../library/drivers/common/x_monitor.sv SV_DEPS += ../../../library/drivers/common/scoreboard.sv SV_DEPS += ../../../library/drivers/common/scoreboard_pack.sv +SV_DEPS += ../../../library/drivers/common/filter.sv SV_DEPS += ../../../library/drivers/dmac/dmac_api.sv SV_DEPS += ../../../library/drivers/dmac/dma_trans.sv SV_DEPS += ../../../library/regmaps/adi_regmap_dmac_pkg.sv diff --git a/testbenches/ip/util_pack/environment.sv b/testbenches/ip/util_pack/environment.sv index 2a0601f0..ca2db83d 100644 --- a/testbenches/ip/util_pack/environment.sv +++ b/testbenches/ip/util_pack/environment.sv @@ -100,13 +100,13 @@ package environment_pkg; // TX stubs tx_src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - tx_src_axis_seq.add_xfer_descriptor(bytes_to_generate, 0, 0); + tx_src_axis_seq.add_xfer_descriptor(bytes_to_generate, 1, 0); tx_dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); // RX stub rx_src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - rx_src_axis_seq.add_xfer_descriptor(bytes_to_generate, 0, 0); + rx_src_axis_seq.add_xfer_descriptor(bytes_to_generate, 1, 0); rx_dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); diff --git a/testbenches/ip/util_pack/system_project.tcl b/testbenches/ip/util_pack/system_project.tcl index 6289033c..767694f7 100644 --- a/testbenches/ip/util_pack/system_project.tcl +++ b/testbenches/ip/util_pack/system_project.tcl @@ -34,6 +34,7 @@ adi_sim_project_files [list \ "../../../library/drivers/common/x_monitor.sv" \ "../../../library/drivers/common/scoreboard.sv" \ "../../../library/drivers/common/scoreboard_pack.sv" \ + "../../../library/drivers/common/filter.sv" \ "../../../library/drivers/dmac/dmac_api.sv" \ "../../../library/drivers/dmac/dma_trans.sv" \ "../../../library/regmaps/adi_regmap_dmac_pkg.sv" \