From a31763025231ecb972c50eebff11c4c9e3c116b8 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 16 Dec 2024 11:05:22 +0200 Subject: [PATCH 01/13] infrastructure refactorization Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/mailbox.sv | 67 ----- library/drivers/common/scoreboard.sv | 239 ++++++---------- library/drivers/common/watchdog.sv | 1 + library/drivers/common/x_monitor.sv | 182 ++++-------- library/includes/Makeinclude_axi.mk | 3 + library/includes/Makeinclude_axis.mk | 3 + library/includes/Makeinclude_common.mk | 1 + library/includes/Makeinclude_scoreboard.mk | 3 +- library/includes/sp_include_axi.tcl | 3 + library/includes/sp_include_axis.tcl | 3 + library/includes/sp_include_common.tcl | 1 + library/includes/sp_include_scoreboard.tcl | 3 +- library/regmaps/adi_peripheral_pkg.sv | 1 + library/regmaps/reg_accessor.sv | 2 +- library/utilities/adi_common_pkg.sv | 161 +++++++++++ library/utilities/logger_pkg.sv | 50 ---- library/utilities/test_harness_env.sv | 103 ++----- library/utilities/utils.svh | 223 +++++++-------- library/vip/adi/base/pub_sub_pkg.sv | 97 +++++++ library/vip/amd/adi_axi_agent.sv | 108 +++++++ library/vip/amd/adi_axis_agent.sv | 108 +++++++ library/vip/amd/m_axi_sequencer.sv | 9 +- library/vip/amd/m_axis_sequencer.sv | 26 +- library/vip/amd/s_axi_sequencer.sv | 16 +- library/vip/amd/s_axis_sequencer.sv | 35 +-- testbenches/ip/base/environment.sv | 91 ------ testbenches/ip/base/tests/test_program.sv | 15 +- testbenches/ip/scoreboard/environment.sv | 263 ++++-------------- testbenches/ip/scoreboard/system_bd.tcl | 2 +- .../ip/scoreboard/tests/test_program.sv | 142 ++++++---- 30 files changed, 942 insertions(+), 1019 deletions(-) delete mode 100644 library/drivers/common/mailbox.sv create mode 100644 library/utilities/adi_common_pkg.sv create mode 100644 library/vip/adi/base/pub_sub_pkg.sv create mode 100644 library/vip/amd/adi_axi_agent.sv create mode 100644 library/vip/amd/adi_axis_agent.sv delete mode 100644 testbenches/ip/base/environment.sv diff --git a/library/drivers/common/mailbox.sv b/library/drivers/common/mailbox.sv deleted file mode 100644 index 4f468bc2..00000000 --- a/library/drivers/common/mailbox.sv +++ /dev/null @@ -1,67 +0,0 @@ -`include "utils.svh" - -package mailbox_pkg; - - import logger_pkg::*; - - class mailbox_c #(type T) extends adi_component; - - T queue[$]; - - int size_max; - - event q_event; - - // constructor - function new( - input string name, - input int size_max = 0, - input adi_component parent = null); - - super.new(name, parent); - - this.size_max = size_max; - endfunction - - function int num(); - return this.queue.size(); - endfunction - - task get(ref T element); - if (this.num() == 0) - @this.q_event; - element = this.queue.pop_back(); - ->this.q_event; - endtask - - function int try_get(ref T element); - if (this.num() == 0) - return 0; - element = this.queue.pop_back(); - ->this.q_event; - return 1; - endfunction - - task put(input T element); - if (this.size_max == this.num() && this.size_max != 0) - @this.q_event; - this.queue.push_front(element); - ->this.q_event; - endtask - - function int try_put(input T element); - if (this.size_max == this.num() && this.size_max != 0) - return 0; - this.queue.push_front(element); - ->this.q_event; - return 1; - endfunction - - task flush(); - T element; - while(this.try_get(element)); - endtask - - endclass - -endpackage diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv index 640dabab..f5fe568a 100644 --- a/library/drivers/common/scoreboard.sv +++ b/library/drivers/common/scoreboard.sv @@ -6,23 +6,62 @@ package scoreboard_pkg; import axi4stream_vip_pkg::*; import axi_vip_pkg::*; import logger_pkg::*; - import x_monitor_pkg::*; - import mailbox_pkg::*; + import adi_common_pkg::*; + import pub_sub_pkg::*; class scoreboard extends adi_component; - typedef enum bit { CYCLIC=0, ONESHOT } sink_type_t; - protected sink_type_t sink_type; + class subscriber_class extends adi_subscriber #(logic [7:0]); + + protected scoreboard scoreboard_ref; + + protected logic [7:0] byte_stream [$]; + + function new( + input string name, + input scoreboard scoreboard_ref, + input adi_component parent = null); + + super.new(name, parent); + + this.scoreboard_ref = scoreboard_ref; + endfunction: new + + virtual function void update(input data_type data [$]); + this.info($sformatf("Data received: %d", data.size()), ADI_VERBOSITY_MEDIUM); + while (data.size()) begin + this.byte_stream.push_back(data.pop_front); + end + + if (this.scoreboard_ref.enabled) begin + this.scoreboard_ref.compare_transaction(); + end + endfunction: update + + function logic [7:0] get_data(); + return this.byte_stream.pop_front(); + endfunction: get_data + + function void put_data(logic [7:0] data); + this.byte_stream.push_back(data); + endfunction: put_data + + function int get_size(); + return this.byte_stream.size(); + endfunction: get_size - // List of analysis ports from the monitors - protected x_monitor source_monitor; - protected x_monitor sink_monitor; + function void clear_stream(); + this.byte_stream.delete(); + endfunction: clear_stream - protected logic [7:0] source_byte_stream [$]; - protected logic [7:0] sink_byte_stream [$]; + endclass: subscriber_class - protected int source_byte_stream_size; - protected int sink_byte_stream_size; + + subscriber_class subscriber_source; + subscriber_class subscriber_sink; + + typedef enum bit { CYCLIC=0, ONESHOT } sink_type_t; + protected sink_type_t sink_type; // counters and synchronizers protected bit enabled; @@ -31,8 +70,6 @@ package scoreboard_pkg; // protected event end_of_first_cycle; protected event byte_streams_empty; protected event stop_scoreboard; - protected event source_transaction_event; - protected event sink_transaction_event; // constructor function new( @@ -41,186 +78,82 @@ package scoreboard_pkg; super.new(name, parent); + this.subscriber_source = new("Subscriber Source", this); + this.subscriber_sink = new("Subscriber Sink", this); + this.enabled = 0; this.sink_type = ONESHOT; - this.source_byte_stream_size = 0; - this.sink_byte_stream_size = 0; this.byte_streams_empty_sig = 1; - endfunction: new - // connect the analysis ports of the monitor to the scoreboard - function void set_source_stream( - x_monitor source_monitor); - - this.source_monitor = source_monitor; - - endfunction: set_source_stream - - function void set_sink_stream( - x_monitor sink_monitor); - - this.sink_monitor = sink_monitor; - - endfunction: set_sink_stream - // run task task run(); - - fork - this.enabled = 1; - this.get_source_transaction(); - this.get_sink_transaction(); - this.compare_transaction(); - join_none - + this.enabled = 1; + + this.info($sformatf("Scoreboard enabled"), ADI_VERBOSITY_MEDIUM); endtask: run // stop scoreboard task stop(); this.enabled = 0; - ->>stop_scoreboard; this.clear_streams(); - #1step; + this.byte_streams_empty_sig = 1; endtask: stop // set sink type function void set_sink_type(input bit sink_type); - if (!this.enabled) begin this.sink_type = sink_type_t'(sink_type); end else begin this.error($sformatf("Can not configure sink_type while scoreboard is running.")); end - endfunction: set_sink_type - // clear source and sink byte streams - function void clear_streams(); - this.source_byte_stream.delete(); - this.sink_byte_stream.delete(); - - this.source_byte_stream_size = 0; - this.sink_byte_stream_size = 0; - endfunction: clear_streams - // get sink type function bit get_sink_type(); return this.sink_type; - endfunction + endfunction: get_sink_type + + // clear source and sink byte streams + protected function void clear_streams(); + this.subscriber_source.clear_stream(); + this.subscriber_source.clear_stream(); + endfunction: clear_streams // wait until source and sink byte streams are empty, full check task wait_until_complete(); if (this.byte_streams_empty_sig) return; - @byte_streams_empty; - endtask - - // get transaction data from source monitor - task get_source_transaction(); - - logic [7:0] source_byte; - - forever begin - fork begin - fork - this.source_monitor.wait_for_transaction_event(); - @stop_scoreboard; - join_any - disable fork; - end join - if (this.enabled == 0) - break; - - this.source_monitor.get_key(); - for (int i=0; i>source_transaction_event; - this.source_monitor.put_key(); - end - - endtask: get_source_transaction - - // get transaction data from sink monitor - task get_sink_transaction(); - - logic [7:0] sink_byte; - - forever begin - fork begin - fork - this.sink_monitor.wait_for_transaction_event(); - @stop_scoreboard; - join_any - disable fork; - end join - - if (this.enabled == 0) - break; - - this.sink_monitor.get_key(); - for (int i=0; i>sink_transaction_event; - this.sink_monitor.put_key(); - end - - endtask: get_sink_transaction + @this.byte_streams_empty; + endtask: wait_until_complete // compare the collected data - virtual task compare_transaction(); - + virtual function void compare_transaction(); logic [7:0] source_byte; logic [7:0] sink_byte; - this.info($sformatf("Started"), ADI_VERBOSITY_MEDIUM); - - forever begin : tx_path - if (this.enabled == 0) - break; - if ((this.source_byte_stream_size > 0) && - (this.sink_byte_stream_size > 0)) begin - byte_streams_empty_sig = 0; - source_byte = this.source_byte_stream.pop_back(); - if (this.sink_type == CYCLIC) - this.source_byte_stream.push_front(source_byte); - else - this.source_byte_stream_size--; - sink_byte = this.sink_byte_stream.pop_back(); - this.sink_byte_stream_size--; - this.info($sformatf("Source-sink data: exp %h - rcv %h", source_byte, sink_byte), ADI_VERBOSITY_MEDIUM); - if (source_byte != sink_byte) begin - this.error($sformatf("Failed at: exp %h - rcv %h", source_byte, sink_byte)); - end - end else begin - if ((this.source_byte_stream_size == 0) && - (this.sink_byte_stream_size == 0)) begin - byte_streams_empty_sig = 1; - ->>byte_streams_empty; - end - fork begin - fork - @source_transaction_event; - @sink_transaction_event; - @stop_scoreboard; - join_any - byte_streams_empty_sig = 0; - disable fork; - end join + if (this.enabled == 0) + return; + + while ((this.subscriber_source.get_size() > 0) && + (this.subscriber_sink.get_size() > 0)) begin + byte_streams_empty_sig = 0; + source_byte = this.subscriber_source.get_data(); + if (this.sink_type == CYCLIC) + this.subscriber_source.put_data(source_byte); + sink_byte = this.subscriber_sink.get_data(); + this.info($sformatf("Source-sink data: exp %h - rcv %h", source_byte, sink_byte), ADI_VERBOSITY_MEDIUM); + if (source_byte != sink_byte) begin + this.error($sformatf("Failed at: exp %h - rcv %h", source_byte, sink_byte)); end end - endtask /* compare_transaction */ + if ((this.subscriber_source.get_size() == 0) && + (this.subscriber_sink.get_size() == 0)) begin + this.byte_streams_empty_sig = 1; + ->this.byte_streams_empty; + end + endfunction: compare_transaction endclass diff --git a/library/drivers/common/watchdog.sv b/library/drivers/common/watchdog.sv index 917f3a32..ed09fda6 100644 --- a/library/drivers/common/watchdog.sv +++ b/library/drivers/common/watchdog.sv @@ -37,6 +37,7 @@ package watchdog_pkg; import logger_pkg::*; + import adi_common_pkg::*; class watchdog extends adi_component; diff --git a/library/drivers/common/x_monitor.sv b/library/drivers/common/x_monitor.sv index 2852b789..3eee77a0 100644 --- a/library/drivers/common/x_monitor.sv +++ b/library/drivers/common/x_monitor.sv @@ -6,202 +6,138 @@ package x_monitor_pkg; import axi4stream_vip_pkg::*; import axi_vip_pkg::*; import logger_pkg::*; - import mailbox_pkg::*; + import adi_common_pkg::*; + import pub_sub_pkg::*; - class x_monitor extends adi_component; - - mailbox_c #(logic [7:0]) mailbox; - protected semaphore semaphore_key; - protected event transaction_event; + class x_monitor extends adi_monitor; protected bit enabled; // constructor function new( input string name, - input adi_component parent = null); + input adi_agent parent = null); super.new(name, parent); - this.mailbox = new("Mailbox", 0, this); - this.semaphore_key = new(1); + this.enabled = 0; endfunction - // semaphore functions - task get_key(); - this.semaphore_key.get(); - endtask - - task put_key(); - this.semaphore_key.put(); - endtask - - // event functions - task transaction_captured(); - ->>this.transaction_event; - endtask - - task wait_for_transaction_event(); - @this.transaction_event; - endtask - - // run task task run(); + if (this.enabled) begin + this.error($sformatf("Monitor is already running!")); + return; + end fork - this.enabled = 1; - get_transaction(); + this.get_transaction(); join_none - endtask /* run */ + this.enabled = 1; + this.info($sformatf("Monitor enabled"), ADI_VERBOSITY_MEDIUM); + endtask: run // virtual functions - virtual function void set_sink_type(input bit sink_type); - endfunction - - virtual function bit get_sink_type(); - endfunction - virtual task get_transaction(); endtask endclass - typedef enum bit { - READ_OP = 1'b0, - WRITE_OP = 1'b1 - } operation_type_t; - class x_axi_monitor #( type T, operation_type_t operation_type ) extends x_monitor; - // operation type: 1 - write - // 0 - read + class x_axi_monitor #(int `AXI_VIP_PARAM_ORDER(axi)) extends x_monitor; // analysis port from the monitor + protected axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor; protected xil_analysis_port #(axi_monitor_transaction) axi_ap; - protected T agent; - - protected int axi_byte_stream_size; + adi_publisher #(logic [7:0]) publisher_tx; + adi_publisher #(logic [7:0]) publisher_rx; // constructor function new( input string name, - input T agent, - input adi_component parent = null); + input axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor, + input adi_agent parent = null); super.new(name, parent); - this.enabled = 0; - - this.agent = agent; - this.axi_ap = this.agent.monitor.item_collected_port; - - this.axi_byte_stream_size = 0; + this.monitor = monitor; + this.axi_ap = monitor.item_collected_port; - endfunction /* new */ + this.publisher_tx = new("Publisher TX", this); + this.publisher_rx = new("Publisher RX", this); + endfunction // collect data from the DDR interface, all WRITE transaction are coming // from the ADC and all READ transactions are going to the DAC virtual task get_transaction(); - axi_monitor_transaction transaction; xil_axi_data_beat data_beat; xil_axi_strb_beat strb_beat; int num_bytes; logic [7:0] axi_byte; + logic [7:0] data_queue [$]; forever begin - this.get_key(); this.axi_ap.get(transaction); - if (bit'(transaction.get_cmd_type()) == operation_type) begin - this.put_key(); - num_bytes = transaction.get_data_width()/8; - for (int i=0; i<(transaction.get_len()+1); i++) begin - data_beat = transaction.get_data_beat(i); - strb_beat = transaction.get_strb_beat(i); - for (int j=0; j +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package adi_common_pkg; + + import logger_pkg::*; + + class adi_reporter; + string name; + adi_reporter parent; + + function new( + input string name, + input adi_reporter parent = null); + + this.name = name; + this.parent = parent; + endfunction + + function string get_path(); + if (this.parent == null) + return this.name; + else + return $sformatf("%s.%s", this.parent.get_path(), this.name); + endfunction: get_path + + function void info( + input string message, + input adi_verbosity_t verbosity); + + `INFO(("[%s] %s", this.get_path(), message), verbosity); + endfunction: info + + function void warning(input string message); + `WARNING(("[%s] %s", this.get_path(), message)); + endfunction: warning + + function void error(input string message); + `ERROR(("[%s] %s", this.get_path(), message)); + endfunction: error + + function void fatal(input string message); + `FATAL(("[%s] %s", this.get_path(), message)); + endfunction: fatal + endclass: adi_reporter + + + class adi_component extends adi_reporter; + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_component + + + class adi_environment extends adi_component; + function new( + input string name, + input adi_environment parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_environment + + + class adi_api extends adi_component; + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_api + + + class adi_regmap extends adi_component; + function new( + input string name, + input adi_api parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_regmap + + + class adi_agent extends adi_component; + function new( + input string name, + input adi_environment parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_agent + + + class adi_driver extends adi_component; + function new( + input string name, + input adi_agent parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_driver + + + class adi_sequencer extends adi_component; + function new( + input string name, + input adi_agent parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_sequencer + + + class adi_monitor extends adi_component; + function new( + input string name, + input adi_agent parent = null); + + super.new(name, parent); + endfunction: new + endclass: adi_monitor + +endpackage diff --git a/library/utilities/logger_pkg.sv b/library/utilities/logger_pkg.sv index 0b2b64d2..6db5d3cb 100644 --- a/library/utilities/logger_pkg.sv +++ b/library/utilities/logger_pkg.sv @@ -71,54 +71,4 @@ package logger_pkg; verbosity = value; endfunction: setLoggerVerbosity - - class adi_reporter; - string name; - adi_reporter parent; - - function new( - input string name, - input adi_reporter parent = null); - - this.name = name; - this.parent = parent; - endfunction - - function string get_path(); - if (this.parent == null) - return this.name; - else - return $sformatf("%s.%s", this.parent.get_path(), this.name); - endfunction: get_path - - function void info( - input string message, - input adi_verbosity_t verbosity); - - PrintInfo($sformatf("[%s] %s", this.get_path(), message), verbosity); - endfunction: info - - function void warning(input string message); - PrintWarning($sformatf("[%s] %s", this.get_path(), message)); - endfunction: warning - - function void error(input string message); - PrintError($sformatf("[%s] %s", this.get_path(), message)); - endfunction: error - - function void fatal(input string message); - PrintFatal($sformatf("[%s] %s", this.get_path(), message)); - endfunction: fatal - endclass: adi_reporter - - - class adi_component extends adi_reporter; - function new( - input string name, - input adi_component parent = null); - - super.new(name, parent); - endfunction: new - endclass: adi_component - endpackage diff --git a/library/utilities/test_harness_env.sv b/library/utilities/test_harness_env.sv index 2850c1b0..042070ea 100644 --- a/library/utilities/test_harness_env.sv +++ b/library/utilities/test_harness_env.sv @@ -38,25 +38,18 @@ package test_harness_env_pkg; import logger_pkg::*; + import adi_common_pkg::*; import axi_vip_pkg::*; - import axi4stream_vip_pkg::*; import m_axi_sequencer_pkg::*; import s_axi_sequencer_pkg::*; - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; + import adi_axi_agent_pkg::*; - class test_harness_env extends adi_component; - // Agents - `AGENT(test_harness, mng_axi_vip, mst_t) mng_agent; - `AGENT(test_harness, ddr_axi_vip, slv_mem_t) ddr_axi_agent; - - // Sequencers - m_axi_sequencer #(`AGENT(test_harness, mng_axi_vip, mst_t)) mng; - s_axi_sequencer #(`AGENT(test_harness, ddr_axi_vip, slv_mem_t)) ddr_axi_seq; + class test_harness_env #(int `AXI_VIP_PARAM_ORDER(mng), int `AXI_VIP_PARAM_ORDER(ddr)) extends adi_environment; - // Register accessors - bit done = 0; + // Agents + adi_axi_master_agent #(`AXI_VIP_PARAM_ORDER(mng)) mng; + adi_axi_slave_mem_agent #(`AXI_VIP_PARAM_ORDER(ddr)) ddr; virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if; virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if; @@ -76,9 +69,8 @@ package test_harness_env_pkg; virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if - ); + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(mng)) mng_vip_if, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(ddr)) ddr_vip_if); super.new(name); @@ -88,13 +80,8 @@ package test_harness_env_pkg; this.sys_rst_vip_if = sys_rst_vip_if; // Creating the agents - mng_agent = new("AXI Manager agent", mng_vip_if); - ddr_axi_agent = new("AXI DDR stub agent", ddr_vip_if); - - // Creating the sequencers - mng = new("AXI Manager sequencer", mng_agent, this); - ddr_axi_seq = new("AXI DDR stub sequencer", ddr_axi_agent, this); - + this.mng = new("AXI Manager agent", mng_vip_if, this); + this.ddr = new("AXI DDR stub agent", ddr_vip_if, this); endfunction //============================================================================ @@ -103,76 +90,34 @@ package test_harness_env_pkg; // - Start the agents //============================================================================ task start(); - mng_agent.start_master(); - ddr_axi_agent.start_slave(); - - sys_clk_vip_if.start_clock; - dma_clk_vip_if.start_clock; - ddr_clk_vip_if.start_clock; - endtask - - //============================================================================ - // Start the test - // - start the scoreboard - // - start the sequencers - //============================================================================ - task test(); - fork - - join_none - endtask - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - // wait until done - wait_done(); - endtask + this.mng.agent.start_master(); + this.ddr.agent.start_slave(); - //============================================================================ - // Run subroutine - //============================================================================ - task run; - test(); - post_test(); + this.sys_clk_vip_if.start_clock; + this.dma_clk_vip_if.start_clock; + this.ddr_clk_vip_if.start_clock; endtask //============================================================================ // Stop subroutine //============================================================================ - task stop; - mng_agent.stop_master(); - ddr_axi_agent.stop_slave(); - - sys_clk_vip_if.stop_clock; - dma_clk_vip_if.stop_clock; - ddr_clk_vip_if.stop_clock; - endtask + task stop(); + this.mng.agent.stop_master(); + this.ddr.agent.stop_slave(); - //============================================================================ - // Wait until all component are done - //============================================================================ - task wait_done; - wait (done == 1); - //`INFO(("Shutting down")); - endtask - - //============================================================================ - // Test controller routine - //============================================================================ - task test_c_run(); - done = 1; + this.sys_clk_vip_if.stop_clock; + this.dma_clk_vip_if.stop_clock; + this.ddr_clk_vip_if.stop_clock; endtask //============================================================================ // System reset routine //============================================================================ - task sys_reset; + task sys_reset(); //asserts all the resets for 100 ns - sys_rst_vip_if.assert_reset; + this.sys_rst_vip_if.assert_reset; #200; - sys_rst_vip_if.deassert_reset; + this.sys_rst_vip_if.deassert_reset; #800; endtask diff --git a/library/utilities/utils.svh b/library/utilities/utils.svh index a14e3493..d021994c 100644 --- a/library/utilities/utils.svh +++ b/library/utilities/utils.svh @@ -48,126 +48,103 @@ // Help build VIP parameter name e.g. test_harness_dst_axis_vip_0_VIP_DATA_WIDTH `define GETPARAM(th,vip,param) th``_``vip``_0_``param -`define DMAC_PARAMS(th,vip) th``_``vip``_0_ID, \ - th``_``vip``_0_DMA_DATA_WIDTH_SRC, \ - th``_``vip``_0_DMA_DATA_WIDTH_DEST, \ - th``_``vip``_0_DMA_LENGTH_WIDTH, \ - th``_``vip``_0_DMA_2D_TRANSFER, \ - th``_``vip``_0_DMA_2D_TLAST_MODE, \ - th``_``vip``_0_ASYNC_CLK_REQ_SRC, \ - th``_``vip``_0_ASYNC_CLK_SRC_DEST, \ - th``_``vip``_0_ASYNC_CLK_DEST_REQ, \ - th``_``vip``_0_AXI_SLICE_DEST, \ - th``_``vip``_0_AXI_SLICE_SRC, \ - th``_``vip``_0_SYNC_TRANSFER_START, \ - th``_``vip``_0_CYCLIC, \ - th``_``vip``_0_DMA_AXI_PROTOCOL_DEST, \ - th``_``vip``_0_DMA_AXI_PROTOCOL_SRC, \ - th``_``vip``_0_DMA_TYPE_DEST, \ - th``_``vip``_0_DMA_TYPE_SRC, \ - th``_``vip``_0_DMA_AXI_ADDR_WIDTH, \ - th``_``vip``_0_MAX_BYTES_PER_BURST, \ - th``_``vip``_0_FIFO_SIZE, \ - th``_``vip``_0_AXI_ID_WIDTH_SRC, \ - th``_``vip``_0_AXI_ID_WIDTH_DEST, \ - th``_``vip``_0_DISABLE_DEBUG_REGISTERS, \ - th``_``vip``_0_ENABLE_DIAGNOSTICS_IF, \ - th``_``vip``_0_ENABLE_FRAME_LOCK, \ - th``_``vip``_0_MAX_NUM_FRAMES_WIDTH, \ - th``_``vip``_0_USE_EXT_SYNC, \ - th``_``vip``_0_HAS_AUTORUN - // Help build VIP Interface parameters name -`define AXI_VIP_IF_PARAMS(th,vip) th``_``vip``_0_VIP_PROTOCOL,\ - th``_``vip``_0_VIP_ADDR_WIDTH,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_AWUSER_WIDTH,\ - th``_``vip``_0_VIP_WUSER_WIDTH,\ - th``_``vip``_0_VIP_BUSER_WIDTH,\ - th``_``vip``_0_VIP_ARUSER_WIDTH,\ - th``_``vip``_0_VIP_RUSER_WIDTH,\ - th``_``vip``_0_VIP_SUPPORTS_NARROW,\ - th``_``vip``_0_VIP_HAS_BURST,\ - th``_``vip``_0_VIP_HAS_LOCK,\ - th``_``vip``_0_VIP_HAS_CACHE,\ - th``_``vip``_0_VIP_HAS_REGION,\ - th``_``vip``_0_VIP_HAS_PROT,\ - th``_``vip``_0_VIP_HAS_QOS,\ - th``_``vip``_0_VIP_HAS_WSTRB,\ - th``_``vip``_0_VIP_HAS_BRESP,\ - th``_``vip``_0_VIP_HAS_RRESP,\ - th``_``vip``_0_VIP_HAS_ARESETN - -`define AXIS_VIP_IF_PARAMS(th,vip) th``_``vip``_0_VIP_SIGNAL_SET,\ - th``_``vip``_0_VIP_DEST_WIDTH,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_USER_WIDTH,\ - th``_``vip``_0_VIP_USER_BITS_PER_BYTE,\ - th``_``vip``_0_VIP_HAS_ARESETN - -`define AXI_VIP_PARAM_DECL int AXI_VIP_PROTOCOL=0,\ - AXI_VIP_ADDR_WIDTH=32,\ - AXI_VIP_WDATA_WIDTH=32,\ - AXI_VIP_RDATA_WIDTH=32,\ - AXI_VIP_WID_WIDTH = 0,\ - AXI_VIP_RID_WIDTH = 0,\ - AXI_VIP_AWUSER_WIDTH=0,\ - AXI_VIP_WUSER_WIDTH=0,\ - AXI_VIP_BUSER_WIDTH=0,\ - AXI_VIP_ARUSER_WIDTH=0,\ - AXI_VIP_RUSER_WIDTH=0,\ - AXI_VIP_SUPPORTS_NARROW = 1,\ - AXI_VIP_HAS_BURST = 1,\ - AXI_VIP_HAS_LOCK = 1,\ - AXI_VIP_HAS_CACHE= 1,\ - AXI_VIP_HAS_REGION = 1,\ - AXI_VIP_HAS_PROT= 1,\ - AXI_VIP_HAS_QOS= 1,\ - AXI_VIP_HAS_WSTRB= 1,\ - AXI_VIP_HAS_BRESP= 1,\ - AXI_VIP_HAS_RRESP= 1,\ - AXI_VIP_HAS_ARESETN = 1 - -`define AXI_VIP_PARAM_ORDER AXI_VIP_PROTOCOL,\ - AXI_VIP_ADDR_WIDTH,\ - AXI_VIP_WDATA_WIDTH,\ - AXI_VIP_RDATA_WIDTH,\ - AXI_VIP_WID_WIDTH,\ - AXI_VIP_RID_WIDTH,\ - AXI_VIP_AWUSER_WIDTH,\ - AXI_VIP_WUSER_WIDTH,\ - AXI_VIP_BUSER_WIDTH,\ - AXI_VIP_ARUSER_WIDTH,\ - AXI_VIP_RUSER_WIDTH,\ - AXI_VIP_SUPPORTS_NARROW,\ - AXI_VIP_HAS_BURST,\ - AXI_VIP_HAS_LOCK,\ - AXI_VIP_HAS_CACHE,\ - AXI_VIP_HAS_REGION,\ - AXI_VIP_HAS_PROT,\ - AXI_VIP_HAS_QOS,\ - AXI_VIP_HAS_WSTRB,\ - AXI_VIP_HAS_BRESP,\ - AXI_VIP_HAS_RRESP,\ - AXI_VIP_HAS_ARESETN - -`define AXIS_VIP_PARAM_DECL int AXIS_VIP_INTERFACE_MODE = 2,\ - AXIS_VIP_SIGNAL_SET = 8'b00000011,\ - AXIS_VIP_DATA_WIDTH = 8,\ - AXIS_VIP_ID_WIDTH = 0,\ - AXIS_VIP_DEST_WIDTH = 0,\ - AXIS_VIP_USER_WIDTH = 0,\ - AXIS_VIP_USER_BITS_PER_BYTE = 0,\ - AXIS_VIP_HAS_TREADY = 1,\ - AXIS_VIP_HAS_TSTRB = 0,\ - AXIS_VIP_HAS_TKEEP = 0,\ - AXIS_VIP_HAS_TLAST = 0,\ - AXIS_VIP_HAS_ACLKEN = 0,\ - AXIS_VIP_HAS_ARESETN = 1 +`define AXI_VIP_IF_PARAMS(n) n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN + +`define AXI_VIP_PARAM_ORDER(n) n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN + +`define AXI_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_PROTOCOL,\ + th``_``vip``_0_VIP_ADDR_WIDTH,\ + th``_``vip``_0_VIP_DATA_WIDTH,\ + th``_``vip``_0_VIP_DATA_WIDTH,\ + th``_``vip``_0_VIP_ID_WIDTH,\ + th``_``vip``_0_VIP_ID_WIDTH,\ + th``_``vip``_0_VIP_AWUSER_WIDTH,\ + th``_``vip``_0_VIP_WUSER_WIDTH,\ + th``_``vip``_0_VIP_BUSER_WIDTH,\ + th``_``vip``_0_VIP_ARUSER_WIDTH,\ + th``_``vip``_0_VIP_RUSER_WIDTH,\ + th``_``vip``_0_VIP_SUPPORTS_NARROW,\ + th``_``vip``_0_VIP_HAS_BURST,\ + th``_``vip``_0_VIP_HAS_LOCK,\ + th``_``vip``_0_VIP_HAS_CACHE,\ + th``_``vip``_0_VIP_HAS_REGION,\ + th``_``vip``_0_VIP_HAS_PROT,\ + th``_``vip``_0_VIP_HAS_QOS,\ + th``_``vip``_0_VIP_HAS_WSTRB,\ + th``_``vip``_0_VIP_HAS_BRESP,\ + th``_``vip``_0_VIP_HAS_RRESP,\ + th``_``vip``_0_VIP_HAS_ARESETN + +`define AXIS_VIP_PARAM_DECL AXIS_VIP_INTERFACE_MODE = 2,\ + AXIS_VIP_SIGNAL_SET = 8'b00000011,\ + AXIS_VIP_DATA_WIDTH = 8,\ + AXIS_VIP_ID_WIDTH = 0,\ + AXIS_VIP_DEST_WIDTH = 0,\ + AXIS_VIP_USER_WIDTH = 0,\ + AXIS_VIP_USER_BITS_PER_BYTE = 0,\ + AXIS_VIP_HAS_TREADY = 1,\ + AXIS_VIP_HAS_TSTRB = 0,\ + AXIS_VIP_HAS_TKEEP = 0,\ + AXIS_VIP_HAS_TLAST = 0,\ + AXIS_VIP_HAS_ACLKEN = 0,\ + AXIS_VIP_HAS_ARESETN = 1 + +`define AXIS_VIP_PARAM_ORDER(n) n``_VIP_INTERFACE_MODE,\ + n``_VIP_SIGNAL_SET,\ + n``_VIP_DATA_WIDTH,\ + n``_VIP_ID_WIDTH,\ + n``_VIP_DEST_WIDTH,\ + n``_VIP_USER_WIDTH,\ + n``_VIP_USER_BITS_PER_BYTE,\ + n``_VIP_HAS_TREADY,\ + n``_VIP_HAS_TSTRB,\ + n``_VIP_HAS_TKEEP,\ + n``_VIP_HAS_TLAST,\ + n``_VIP_HAS_ACLKEN,\ + n``_VIP_HAS_ARESETN `define AXIS_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_INTERFACE_MODE,\ th``_``vip``_0_VIP_SIGNAL_SET,\ @@ -183,6 +160,14 @@ th``_``vip``_0_VIP_HAS_ACLKEN,\ th``_``vip``_0_VIP_HAS_ARESETN +`define AXIS_VIP_IF_PARAMS(n) n``_VIP_SIGNAL_SET,\ + n``_VIP_DEST_WIDTH,\ + n``_VIP_DATA_WIDTH,\ + n``_VIP_ID_WIDTH,\ + n``_VIP_USER_WIDTH,\ + n``_VIP_USER_BITS_PER_BYTE,\ + n``_VIP_HAS_ARESETN + `define AXI 0 `define AXIS 1 `define FIFO 2 diff --git a/library/vip/adi/base/pub_sub_pkg.sv b/library/vip/adi/base/pub_sub_pkg.sv new file mode 100644 index 00000000..570395a6 --- /dev/null +++ b/library/vip/adi/base/pub_sub_pkg.sv @@ -0,0 +1,97 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package pub_sub_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + + class adi_subscriber #(type data_type = int) extends adi_component; + + protected static bit [15:0] last_id = 'd0; + bit [15:0] id; + + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + + this.last_id++; + this.id = this.last_id; + endfunction: new + + virtual function void update(input data_type data [$]); + this.fatal($sformatf("This function is not implemented!")); + endfunction: update + + endclass: adi_subscriber + + + class adi_publisher #(type data_type = int) extends adi_component; + + protected adi_subscriber #(data_type) subscriber_list[bit[15:0]]; + + function new( + input string name, + input adi_component parent = null); + + super.new(name, parent); + endfunction: new + + function void subscribe(input adi_subscriber #(data_type) subscriber); + if (this.subscriber_list.exists(subscriber.id)) + this.error($sformatf("Subscriber already on the list!")); + else + this.subscriber_list[subscriber.id] = subscriber; + endfunction: subscribe + + function void unsubscribe(input adi_subscriber #(data_type) subscriber); + if (!this.subscriber_list.exists(subscriber.id)) + this.error($sformatf("Subscriber does not exist on list!")); + else + this.subscriber_list.delete(subscriber.id); + endfunction: unsubscribe + + function void notify(input data_type data [$]); + foreach (this.subscriber_list[i]) + this.subscriber_list[i].update(data); + endfunction: notify + + endclass: adi_publisher + +endpackage diff --git a/library/vip/amd/adi_axi_agent.sv b/library/vip/amd/adi_axi_agent.sv new file mode 100644 index 00000000..db83d451 --- /dev/null +++ b/library/vip/amd/adi_axi_agent.sv @@ -0,0 +1,108 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package adi_axi_agent_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + import axi_vip_pkg::*; + import m_axi_sequencer_pkg::*; + import s_axi_sequencer_pkg::*; + import x_monitor_pkg::*; + + + class adi_axi_master_agent #(int `AXI_VIP_PARAM_ORDER(master)) extends adi_agent; + + axi_mst_agent #(`AXI_VIP_PARAM_ORDER(master)) agent; + m_axi_sequencer #(`AXI_VIP_PARAM_ORDER(master)) sequencer; + x_axi_monitor #(`AXI_VIP_PARAM_ORDER(master)) monitor; + + function new( + input string name, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(master)) master_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", master_vip_if); + this.sequencer = new("Sequencer", this.agent, this); + this.monitor = new("Monitor TX", this.agent.monitor, this); + endfunction: new + + endclass: adi_axi_master_agent + + + class adi_axi_slave_mem_agent #(int `AXI_VIP_PARAM_ORDER(slave)) extends adi_agent; + + axi_slv_mem_agent #(`AXI_VIP_PARAM_ORDER(slave)) agent; + s_axi_sequencer #(`AXI_VIP_PARAM_ORDER(slave)) sequencer; + x_axi_monitor #(`AXI_VIP_PARAM_ORDER(slave)) monitor; + + function new( + input string name, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(slave)) slave_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", slave_vip_if); + this.sequencer = new("Sequencer", this.agent.mem_model, this); + this.monitor = new("Monitor TX", this.agent.monitor, this); + endfunction: new + + endclass: adi_axi_slave_mem_agent + + + class adi_axi_passthrough_mem_agent #(int `AXI_VIP_PARAM_ORDER(passthrough)) extends adi_agent; + + axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(passthrough)) agent; + x_axi_monitor #(`AXI_VIP_PARAM_ORDER(passthrough)) monitor; + + function new( + input string name, + virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(passthrough)) passthrough_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", passthrough_vip_if); + this.monitor = new("Monitor TX", this.agent.monitor, this); + endfunction: new + + endclass: adi_axi_passthrough_mem_agent + +endpackage diff --git a/library/vip/amd/adi_axis_agent.sv b/library/vip/amd/adi_axis_agent.sv new file mode 100644 index 00000000..65801c1a --- /dev/null +++ b/library/vip/amd/adi_axis_agent.sv @@ -0,0 +1,108 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package adi_axis_agent_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + import axi4stream_vip_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import x_monitor_pkg::*; + + + class adi_axis_master_agent #(int `AXIS_VIP_PARAM_ORDER(master)) extends adi_agent; + + axi4stream_mst_agent #(`AXIS_VIP_IF_PARAMS(master)) agent; + m_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(master)) sequencer; + x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(master)) monitor; + + function new( + input string name, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(master)) master_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", master_vip_if); + this.sequencer = new("Sequencer", this.agent.driver, this); + this.monitor = new("Monitor", this.agent.monitor, this); + endfunction: new + + endclass: adi_axis_master_agent + + + class adi_axis_slave_agent #(int `AXIS_VIP_PARAM_ORDER(slave)) extends adi_agent; + + axi4stream_slv_agent #(`AXIS_VIP_IF_PARAMS(slave)) agent; + s_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(slave)) sequencer; + x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(slave)) monitor; + + function new( + input string name, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(slave)) slave_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", slave_vip_if); + this.sequencer = new("Sequencer", this.agent.driver, this); + this.monitor = new("Monitor", this.agent.monitor, this); + endfunction: new + + endclass: adi_axis_slave_agent + + + class adi_axis_passthrough_mem_agent #(int `AXIS_VIP_PARAM_ORDER(passthrough)) extends adi_agent; + + axi4stream_passthrough_agent #(`AXIS_VIP_IF_PARAMS(passthrough)) agent; + x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(passthrough)) monitor; + + function new( + input string name, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(passthrough)) passthrough_vip_if, + input adi_environment parent = null); + + super.new(name, parent); + + this.agent = new("Agent", passthrough_vip_if); + this.monitor = new("Monitor", this.agent.monitor, this); + endfunction: new + + endclass: adi_axis_passthrough_mem_agent + +endpackage diff --git a/library/vip/amd/m_axi_sequencer.sv b/library/vip/amd/m_axi_sequencer.sv index eb25855d..7e917b0a 100644 --- a/library/vip/amd/m_axi_sequencer.sv +++ b/library/vip/amd/m_axi_sequencer.sv @@ -39,19 +39,20 @@ package m_axi_sequencer_pkg; import axi_vip_pkg::*; import logger_pkg::*; + import adi_common_pkg::*; import reg_accessor_pkg::*; - class m_axi_sequencer #( type T ) extends reg_accessor; + class m_axi_sequencer #(int `AXI_VIP_PARAM_ORDER(m)) extends reg_accessor; - T agent; + axi_mst_agent #(`AXI_VIP_PARAM_ORDER(m)) agent; semaphore reader_s; semaphore writer_s; function new( input string name, - input T agent, - input adi_component parent = null); + input axi_mst_agent #(`AXI_VIP_PARAM_ORDER(m)) agent, + input adi_agent parent = null); super.new(name, parent); diff --git a/library/vip/amd/m_axis_sequencer.sv b/library/vip/amd/m_axis_sequencer.sv index 91fc876e..6a319870 100644 --- a/library/vip/amd/m_axis_sequencer.sv +++ b/library/vip/amd/m_axis_sequencer.sv @@ -38,6 +38,7 @@ package m_axis_sequencer_pkg; import axi4stream_vip_pkg::*; + import adi_common_pkg::*; import logger_pkg::*; typedef enum { @@ -97,7 +98,7 @@ package m_axis_sequencer_pkg; // new function new( input string name, - input adi_component parent = null); + input adi_agent parent = null); super.new(name, parent); @@ -310,20 +311,21 @@ package m_axis_sequencer_pkg; endclass: m_axis_sequencer_base - class m_axis_sequencer #( type T, `AXIS_VIP_PARAM_DECL) extends m_axis_sequencer_base; + class m_axis_sequencer #(int `AXIS_VIP_PARAM_ORDER(AXIS)) extends m_axis_sequencer_base; - protected T agent; + protected axi4stream_mst_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver; function new( input string name, - input T agent, - input adi_component parent = null); + input axi4stream_mst_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver, + input adi_agent parent = null); super.new(name, parent); - this.agent = agent; - this.agent.vif_proxy.set_no_insert_x_when_keep_low(1); + this.driver = driver; + + this.driver.vif_proxy.set_no_insert_x_when_keep_low(1); endfunction: new @@ -338,19 +340,19 @@ package m_axis_sequencer_pkg; // set vif proxy to drive outputs with 0 when inactive virtual task set_inactive_drive_output_0(); - agent.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); + this.driver.vif_proxy.set_dummy_drive_type(XIL_AXI4STREAM_VIF_DRIVE_NONE); this.wait_clk_count(2); endtask: set_inactive_drive_output_0 // check if ready is asserted virtual function bit check_ready_asserted(); - return agent.vif_proxy.is_ready_asserted(); + return this.driver.vif_proxy.is_ready_asserted(); endfunction: check_ready_asserted // wait for set amount of clock cycles virtual task wait_clk_count(input int wait_clocks); - agent.vif_proxy.wait_aclks(wait_clocks); + this.driver.vif_proxy.wait_aclks(wait_clocks); endtask: wait_clk_count // pack the byte stream into transfers(beats) then in packets by setting the tlast @@ -421,7 +423,7 @@ package m_axis_sequencer_pkg; end this.info($sformatf("generating axis transaction"), ADI_VERBOSITY_HIGH); - trans = agent.driver.create_transaction(); + trans = this.driver.create_transaction(); trans.set_data(data); trans.set_id('h0); trans.set_dest('h0); @@ -465,7 +467,7 @@ package m_axis_sequencer_pkg; forever begin @data_av_ev; this.info($sformatf("sending axis transaction"), ADI_VERBOSITY_HIGH); - agent.driver.send(trans); + this.driver.send(trans); ->> beat_done; end join_any diff --git a/library/vip/amd/s_axi_sequencer.sv b/library/vip/amd/s_axi_sequencer.sv index a097ece3..b03b2f40 100644 --- a/library/vip/amd/s_axi_sequencer.sv +++ b/library/vip/amd/s_axi_sequencer.sv @@ -37,28 +37,28 @@ package s_axi_sequencer_pkg; - import xil_common_vip_pkg::*; import axi_vip_pkg::*; + import adi_common_pkg::*; import logger_pkg::*; - class s_axi_sequencer #( type T ) extends adi_component; + class s_axi_sequencer #(int `AXI_VIP_PARAM_ORDER(s)) extends adi_component; - T agent; + xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(s)) mem_model; function new( input string name, - input T agent, - input adi_component parent = null); + input xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(s)) mem_model, + input adi_agent parent = null); super.new(name, parent); - this.agent = agent; + this.mem_model = mem_model; endfunction task get_byte_from_mem(input xil_axi_ulong addr, output bit [7:0] data); bit [31:0] four_bytes; - four_bytes = agent.mem_model.backdoor_memory_read_4byte(addr); + four_bytes = this.mem_model.backdoor_memory_read_4byte(addr); case (addr[1:0]) 2'b00: data = four_bytes[0+:8]; 2'b01: data = four_bytes[8+:8]; @@ -76,7 +76,7 @@ package s_axi_sequencer_pkg; 2'b10: strb = 'b0100; 2'b11: strb = 'b1000; endcase - agent.mem_model.backdoor_memory_write_4byte(.addr(addr), + this.mem_model.backdoor_memory_write_4byte(.addr(addr), .payload({4{data}}), .strb(strb)); endtask diff --git a/library/vip/amd/s_axis_sequencer.sv b/library/vip/amd/s_axis_sequencer.sv index 35418e6c..dc09e5ba 100644 --- a/library/vip/amd/s_axis_sequencer.sv +++ b/library/vip/amd/s_axis_sequencer.sv @@ -38,6 +38,7 @@ package s_axis_sequencer_pkg; import axi4stream_vip_pkg::*; + import adi_common_pkg::*; import logger_pkg::*; class s_axis_sequencer_base extends adi_component; @@ -60,7 +61,7 @@ package s_axis_sequencer_pkg; // new function new( input string name, - input adi_component parent = null); + input adi_agent parent = null); super.new(name, parent); @@ -156,26 +157,26 @@ package s_axis_sequencer_pkg; endclass: s_axis_sequencer_base - class s_axis_sequencer #( type T ) extends s_axis_sequencer_base; + class s_axis_sequencer #(int `AXIS_VIP_PARAM_ORDER(AXIS)) extends s_axis_sequencer_base; - protected T agent; + protected axi4stream_slv_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver; function new( input string name, - input T agent, - input adi_component parent = null); + input axi4stream_slv_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver, + input adi_agent parent = null); super.new(name, parent); - this.agent = agent; + this.driver = driver; endfunction virtual task user_gen_tready(); axi4stream_ready_gen tready_gen; - tready_gen = agent.driver.create_ready("TREADY"); + tready_gen = this.driver.create_ready("TREADY"); tready_gen.set_ready_policy(this.mode); @@ -191,27 +192,9 @@ package s_axis_sequencer_pkg; tready_gen.set_low_time_range(this.low_time_min, this.low_time_max); tready_gen.set_high_time_range(this.high_time_min, this.high_time_max); end - agent.driver.send_tready(tready_gen); + this.driver.send_tready(tready_gen); endtask - // Get transfer from the monitor and serialize data into a byte stream - // Assumption: all bytes from beat are valid (no position or null bytes) - virtual task get_transfer(); - - axi4stream_monitor_transaction mytrans; - xil_axi4stream_data_beat data_beat; - - agent.monitor.item_collected_port.get(mytrans); - - //$display(mytrans.convert2string); - - data_beat = mytrans.get_data_beat(); - - for (int i=0; i Date: Mon, 16 Dec 2024 11:19:54 +0200 Subject: [PATCH 02/13] infrastructure refactorization: Fixes Signed-off-by: Istvan-Zsolt Szekely --- library/vip/adi/io_vip/io_vip_ip.tcl | 2 +- library/vip/adi/spi_vip/adi_spi_vip_ip.tcl | 2 +- testbenches/ip/base/Makefile | 1 - testbenches/ip/base/system_project.tcl | 1 - 4 files changed, 2 insertions(+), 4 deletions(-) diff --git a/library/vip/adi/io_vip/io_vip_ip.tcl b/library/vip/adi/io_vip/io_vip_ip.tcl index 46f5fcad..a99e8474 100644 --- a/library/vip/adi/io_vip/io_vip_ip.tcl +++ b/library/vip/adi/io_vip/io_vip_ip.tcl @@ -3,7 +3,7 @@ ### SPDX short identifier: ADIBSD ############################################################################### -source ../../../../../scripts/adi_env.tcl +source ../../../../scripts/adi_tb_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create io_vip diff --git a/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl b/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl index d6748352..1e745e88 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl +++ b/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl @@ -3,7 +3,7 @@ ### SPDX short identifier: ADIBSD ############################################################################### -source ../../../../../scripts/adi_env.tcl +source ../../../../scripts/adi_tb_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create adi_spi_vip diff --git a/testbenches/ip/base/Makefile b/testbenches/ip/base/Makefile index 6c2e0bea..845120e2 100644 --- a/testbenches/ip/base/Makefile +++ b/testbenches/ip/base/Makefile @@ -9,7 +9,6 @@ include ../../../scripts/make_tb_path.mk include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk # Remaining test-bench dependencies except test programs -SV_DEPS += environment.sv # default test program TP := test_program diff --git a/testbenches/ip/base/system_project.tcl b/testbenches/ip/base/system_project.tcl index d86009f2..cc9ad709 100644 --- a/testbenches/ip/base/system_project.tcl +++ b/testbenches/ip/base/system_project.tcl @@ -18,7 +18,6 @@ adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e" # Add test files to the project adi_sim_project_files [list \ - "environment.sv" \ "tests/test_program.sv" \ ] From 4757bf4b6705df8e61253b2a33e31406d4d18c64 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 16 Dec 2024 14:18:13 +0200 Subject: [PATCH 03/13] infrastructure refactorization: Refactoring Signed-off-by: Istvan-Zsolt Szekely --- library/includes/Makeinclude_axi.mk | 11 +- library/includes/Makeinclude_axis.mk | 11 +- library/includes/Makeinclude_scoreboard.mk | 2 +- library/includes/sp_include_axi.tcl | 11 +- library/includes/sp_include_axis.tcl | 11 +- library/includes/sp_include_scoreboard.tcl | 2 +- .../adi/base => utilities}/pub_sub_pkg.sv | 0 library/utilities/test_harness_env.sv | 4 +- library/utilities/utils.svh | 124 ------------------ library/vip/amd/{ => axi}/adi_axi_agent.sv | 9 +- .../amd/axi/adi_axi_monitor.sv} | 107 +++------------ library/vip/amd/axi/axi_definitions.svh | 112 ++++++++++++++++ library/vip/amd/{ => axi}/m_axi_sequencer.sv | 1 + library/vip/amd/{ => axi}/s_axi_sequencer.sv | 1 + library/vip/amd/{ => axis}/adi_axis_agent.sv | 9 +- library/vip/amd/axis/adi_axis_monitor.sv | 77 +++++++++++ library/vip/amd/axis/axis_definitions.svh | 93 +++++++++++++ .../vip/amd/{ => axis}/m_axis_sequencer.sv | 1 + .../vip/amd/{ => axis}/s_axis_sequencer.sv | 1 + testbenches/ip/base/tests/test_program.sv | 1 + testbenches/ip/scoreboard/environment.sv | 2 + .../ip/scoreboard/tests/test_program.sv | 4 +- 22 files changed, 345 insertions(+), 249 deletions(-) rename library/{vip/adi/base => utilities}/pub_sub_pkg.sv (100%) rename library/vip/amd/{ => axi}/adi_axi_agent.sv (93%) rename library/{drivers/common/x_monitor.sv => vip/amd/axi/adi_axi_monitor.sv} (50%) create mode 100644 library/vip/amd/axi/axi_definitions.svh rename library/vip/amd/{ => axi}/m_axi_sequencer.sv (99%) rename library/vip/amd/{ => axi}/s_axi_sequencer.sv (99%) rename library/vip/amd/{ => axis}/adi_axis_agent.sv (93%) create mode 100644 library/vip/amd/axis/adi_axis_monitor.sv create mode 100644 library/vip/amd/axis/axis_definitions.svh rename library/vip/amd/{ => axis}/m_axis_sequencer.sv (99%) rename library/vip/amd/{ => axis}/s_axis_sequencer.sv (99%) diff --git a/library/includes/Makeinclude_axi.mk b/library/includes/Makeinclude_axi.mk index 6df5de65..8a1b27c8 100644 --- a/library/includes/Makeinclude_axi.mk +++ b/library/includes/Makeinclude_axi.mk @@ -3,9 +3,10 @@ #################################################################################### # All test-bench dependencies except test programs -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/adi_axi_agent.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/m_axi_sequencer.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/s_axi_sequencer.sv -SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/x_monitor.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/base/pub_sub_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/adi_axi_agent.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/m_axi_sequencer.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/s_axi_sequencer.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/adi_axi_monitor.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/axi_definitions.svh +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/reg_accessor.sv diff --git a/library/includes/Makeinclude_axis.mk b/library/includes/Makeinclude_axis.mk index d663d17c..5810ebd7 100644 --- a/library/includes/Makeinclude_axis.mk +++ b/library/includes/Makeinclude_axis.mk @@ -3,8 +3,9 @@ #################################################################################### # All test-bench dependencies except test programs -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/adi_axis_agent.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/m_axis_sequencer.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/s_axis_sequencer.sv -SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/base/pub_sub_pkg.sv -SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/x_monitor.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/adi_axis_agent.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/m_axis_sequencer.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/s_axis_sequencer.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/adi_axis_monitor.sv +SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axis/axis_definitions.svh +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv diff --git a/library/includes/Makeinclude_scoreboard.mk b/library/includes/Makeinclude_scoreboard.mk index 46c408f1..3fd4e67a 100644 --- a/library/includes/Makeinclude_scoreboard.mk +++ b/library/includes/Makeinclude_scoreboard.mk @@ -3,6 +3,6 @@ #################################################################################### # All test-bench dependencies except test programs -SV_DEPS += $(TB_LIBRARY_PATH)/vip/adi/base/pub_sub_pkg.sv +SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/scoreboard.sv SV_DEPS += $(TB_LIBRARY_PATH)/drivers/common/scoreboard_pack.sv diff --git a/library/includes/sp_include_axi.tcl b/library/includes/sp_include_axi.tcl index 35a46f99..89aaa064 100644 --- a/library/includes/sp_include_axi.tcl +++ b/library/includes/sp_include_axi.tcl @@ -35,10 +35,11 @@ # Add test files to the project adi_sim_project_files [list \ - "$ad_tb_dir/library/vip/amd/adi_axi_agent.sv" \ - "$ad_tb_dir/library/vip/amd/m_axi_sequencer.sv" \ - "$ad_tb_dir/library/vip/amd/s_axi_sequencer.sv" \ - "$ad_tb_dir/library/drivers/common/x_monitor.sv" \ - "$ad_tb_dir/library/vip/adi/base/pub_sub_pkg.sv" \ + "$ad_tb_dir/library/vip/amd/axi/adi_axi_agent.sv" \ + "$ad_tb_dir/library/vip/amd/axi/m_axi_sequencer.sv" \ + "$ad_tb_dir/library/vip/amd/axi/s_axi_sequencer.sv" \ + "$ad_tb_dir/library/vip/amd/axi/adi_axi_monitor.sv" \ + "$ad_tb_dir/library/vip/amd/axi/axi_definitions.svh" \ + "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ "$ad_tb_dir/library/regmaps/reg_accessor.sv" \ ] diff --git a/library/includes/sp_include_axis.tcl b/library/includes/sp_include_axis.tcl index dc284e77..50532616 100644 --- a/library/includes/sp_include_axis.tcl +++ b/library/includes/sp_include_axis.tcl @@ -35,9 +35,10 @@ # Add test files to the project adi_sim_project_files [list \ - "$ad_tb_dir/library/vip/amd/adi_axis_agent.sv" \ - "$ad_tb_dir/library/vip/amd/m_axis_sequencer.sv" \ - "$ad_tb_dir/library/vip/amd/s_axis_sequencer.sv" \ - "$ad_tb_dir/library/drivers/common/x_monitor.sv" \ - "$ad_tb_dir/library/vip/adi/base/pub_sub_pkg.sv" \ + "$ad_tb_dir/library/vip/amd/axis/adi_axis_agent.sv" \ + "$ad_tb_dir/library/vip/amd/axis/m_axis_sequencer.sv" \ + "$ad_tb_dir/library/vip/amd/axis/s_axis_sequencer.sv" \ + "$ad_tb_dir/library/vip/amd/axis/adi_axis_monitor.sv" \ + "$ad_tb_dir/library/vip/amd/axis/axis_definitions.svh" \ + "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ ] diff --git a/library/includes/sp_include_scoreboard.tcl b/library/includes/sp_include_scoreboard.tcl index cd47bdd7..03ac1a8b 100644 --- a/library/includes/sp_include_scoreboard.tcl +++ b/library/includes/sp_include_scoreboard.tcl @@ -35,7 +35,7 @@ # Add test files to the project adi_sim_project_files [list \ - "$ad_tb_dir/library/vip/adi/base/pub_sub_pkg.sv" \ + "$ad_tb_dir/library/utilities/pub_sub_pkg.sv" \ "$ad_tb_dir/library/drivers/common/scoreboard.sv" \ "$ad_tb_dir/library/drivers/common/scoreboard_pack.sv" \ ] diff --git a/library/vip/adi/base/pub_sub_pkg.sv b/library/utilities/pub_sub_pkg.sv similarity index 100% rename from library/vip/adi/base/pub_sub_pkg.sv rename to library/utilities/pub_sub_pkg.sv diff --git a/library/utilities/test_harness_env.sv b/library/utilities/test_harness_env.sv index 042070ea..3f05d8b2 100644 --- a/library/utilities/test_harness_env.sv +++ b/library/utilities/test_harness_env.sv @@ -34,14 +34,12 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" package test_harness_env_pkg; import logger_pkg::*; import adi_common_pkg::*; - import axi_vip_pkg::*; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; import adi_axi_agent_pkg::*; diff --git a/library/utilities/utils.svh b/library/utilities/utils.svh index d021994c..03a240df 100644 --- a/library/utilities/utils.svh +++ b/library/utilities/utils.svh @@ -48,130 +48,6 @@ // Help build VIP parameter name e.g. test_harness_dst_axis_vip_0_VIP_DATA_WIDTH `define GETPARAM(th,vip,param) th``_``vip``_0_``param -// Help build VIP Interface parameters name -`define AXI_VIP_IF_PARAMS(n) n``_VIP_PROTOCOL,\ - n``_VIP_ADDR_WIDTH,\ - n``_VIP_WDATA_WIDTH,\ - n``_VIP_RDATA_WIDTH,\ - n``_VIP_WID_WIDTH,\ - n``_VIP_RID_WIDTH,\ - n``_VIP_AWUSER_WIDTH,\ - n``_VIP_WUSER_WIDTH,\ - n``_VIP_BUSER_WIDTH,\ - n``_VIP_ARUSER_WIDTH,\ - n``_VIP_RUSER_WIDTH,\ - n``_VIP_SUPPORTS_NARROW,\ - n``_VIP_HAS_BURST,\ - n``_VIP_HAS_LOCK,\ - n``_VIP_HAS_CACHE,\ - n``_VIP_HAS_REGION,\ - n``_VIP_HAS_PROT,\ - n``_VIP_HAS_QOS,\ - n``_VIP_HAS_WSTRB,\ - n``_VIP_HAS_BRESP,\ - n``_VIP_HAS_RRESP,\ - n``_VIP_HAS_ARESETN - -`define AXI_VIP_PARAM_ORDER(n) n``_VIP_PROTOCOL,\ - n``_VIP_ADDR_WIDTH,\ - n``_VIP_WDATA_WIDTH,\ - n``_VIP_RDATA_WIDTH,\ - n``_VIP_WID_WIDTH,\ - n``_VIP_RID_WIDTH,\ - n``_VIP_AWUSER_WIDTH,\ - n``_VIP_WUSER_WIDTH,\ - n``_VIP_BUSER_WIDTH,\ - n``_VIP_ARUSER_WIDTH,\ - n``_VIP_RUSER_WIDTH,\ - n``_VIP_SUPPORTS_NARROW,\ - n``_VIP_HAS_BURST,\ - n``_VIP_HAS_LOCK,\ - n``_VIP_HAS_CACHE,\ - n``_VIP_HAS_REGION,\ - n``_VIP_HAS_PROT,\ - n``_VIP_HAS_QOS,\ - n``_VIP_HAS_WSTRB,\ - n``_VIP_HAS_BRESP,\ - n``_VIP_HAS_RRESP,\ - n``_VIP_HAS_ARESETN - -`define AXI_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_PROTOCOL,\ - th``_``vip``_0_VIP_ADDR_WIDTH,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_AWUSER_WIDTH,\ - th``_``vip``_0_VIP_WUSER_WIDTH,\ - th``_``vip``_0_VIP_BUSER_WIDTH,\ - th``_``vip``_0_VIP_ARUSER_WIDTH,\ - th``_``vip``_0_VIP_RUSER_WIDTH,\ - th``_``vip``_0_VIP_SUPPORTS_NARROW,\ - th``_``vip``_0_VIP_HAS_BURST,\ - th``_``vip``_0_VIP_HAS_LOCK,\ - th``_``vip``_0_VIP_HAS_CACHE,\ - th``_``vip``_0_VIP_HAS_REGION,\ - th``_``vip``_0_VIP_HAS_PROT,\ - th``_``vip``_0_VIP_HAS_QOS,\ - th``_``vip``_0_VIP_HAS_WSTRB,\ - th``_``vip``_0_VIP_HAS_BRESP,\ - th``_``vip``_0_VIP_HAS_RRESP,\ - th``_``vip``_0_VIP_HAS_ARESETN - -`define AXIS_VIP_PARAM_DECL AXIS_VIP_INTERFACE_MODE = 2,\ - AXIS_VIP_SIGNAL_SET = 8'b00000011,\ - AXIS_VIP_DATA_WIDTH = 8,\ - AXIS_VIP_ID_WIDTH = 0,\ - AXIS_VIP_DEST_WIDTH = 0,\ - AXIS_VIP_USER_WIDTH = 0,\ - AXIS_VIP_USER_BITS_PER_BYTE = 0,\ - AXIS_VIP_HAS_TREADY = 1,\ - AXIS_VIP_HAS_TSTRB = 0,\ - AXIS_VIP_HAS_TKEEP = 0,\ - AXIS_VIP_HAS_TLAST = 0,\ - AXIS_VIP_HAS_ACLKEN = 0,\ - AXIS_VIP_HAS_ARESETN = 1 - -`define AXIS_VIP_PARAM_ORDER(n) n``_VIP_INTERFACE_MODE,\ - n``_VIP_SIGNAL_SET,\ - n``_VIP_DATA_WIDTH,\ - n``_VIP_ID_WIDTH,\ - n``_VIP_DEST_WIDTH,\ - n``_VIP_USER_WIDTH,\ - n``_VIP_USER_BITS_PER_BYTE,\ - n``_VIP_HAS_TREADY,\ - n``_VIP_HAS_TSTRB,\ - n``_VIP_HAS_TKEEP,\ - n``_VIP_HAS_TLAST,\ - n``_VIP_HAS_ACLKEN,\ - n``_VIP_HAS_ARESETN - -`define AXIS_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_INTERFACE_MODE,\ - th``_``vip``_0_VIP_SIGNAL_SET,\ - th``_``vip``_0_VIP_DATA_WIDTH,\ - th``_``vip``_0_VIP_ID_WIDTH,\ - th``_``vip``_0_VIP_DEST_WIDTH,\ - th``_``vip``_0_VIP_USER_WIDTH,\ - th``_``vip``_0_VIP_USER_BITS_PER_BYTE,\ - th``_``vip``_0_VIP_HAS_TREADY,\ - th``_``vip``_0_VIP_HAS_TSTRB,\ - th``_``vip``_0_VIP_HAS_TKEEP,\ - th``_``vip``_0_VIP_HAS_TLAST,\ - th``_``vip``_0_VIP_HAS_ACLKEN,\ - th``_``vip``_0_VIP_HAS_ARESETN - -`define AXIS_VIP_IF_PARAMS(n) n``_VIP_SIGNAL_SET,\ - n``_VIP_DEST_WIDTH,\ - n``_VIP_DATA_WIDTH,\ - n``_VIP_ID_WIDTH,\ - n``_VIP_USER_WIDTH,\ - n``_VIP_USER_BITS_PER_BYTE,\ - n``_VIP_HAS_ARESETN - -`define AXI 0 -`define AXIS 1 -`define FIFO 2 - // Macros used in Simulation files during simulation `define INFO(m,v) \ PrintInfo($sformatf("%s", \ diff --git a/library/vip/amd/adi_axi_agent.sv b/library/vip/amd/axi/adi_axi_agent.sv similarity index 93% rename from library/vip/amd/adi_axi_agent.sv rename to library/vip/amd/axi/adi_axi_agent.sv index db83d451..bb6c42d2 100644 --- a/library/vip/amd/adi_axi_agent.sv +++ b/library/vip/amd/axi/adi_axi_agent.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" package adi_axi_agent_pkg; @@ -42,14 +43,14 @@ package adi_axi_agent_pkg; import axi_vip_pkg::*; import m_axi_sequencer_pkg::*; import s_axi_sequencer_pkg::*; - import x_monitor_pkg::*; + import adi_axi_monitor_pkg::*; class adi_axi_master_agent #(int `AXI_VIP_PARAM_ORDER(master)) extends adi_agent; axi_mst_agent #(`AXI_VIP_PARAM_ORDER(master)) agent; m_axi_sequencer #(`AXI_VIP_PARAM_ORDER(master)) sequencer; - x_axi_monitor #(`AXI_VIP_PARAM_ORDER(master)) monitor; + adi_axi_monitor #(`AXI_VIP_PARAM_ORDER(master)) monitor; function new( input string name, @@ -70,7 +71,7 @@ package adi_axi_agent_pkg; axi_slv_mem_agent #(`AXI_VIP_PARAM_ORDER(slave)) agent; s_axi_sequencer #(`AXI_VIP_PARAM_ORDER(slave)) sequencer; - x_axi_monitor #(`AXI_VIP_PARAM_ORDER(slave)) monitor; + adi_axi_monitor #(`AXI_VIP_PARAM_ORDER(slave)) monitor; function new( input string name, @@ -90,7 +91,7 @@ package adi_axi_agent_pkg; class adi_axi_passthrough_mem_agent #(int `AXI_VIP_PARAM_ORDER(passthrough)) extends adi_agent; axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(passthrough)) agent; - x_axi_monitor #(`AXI_VIP_PARAM_ORDER(passthrough)) monitor; + adi_axi_monitor #(`AXI_VIP_PARAM_ORDER(passthrough)) monitor; function new( input string name, diff --git a/library/drivers/common/x_monitor.sv b/library/vip/amd/axi/adi_axi_monitor.sv similarity index 50% rename from library/drivers/common/x_monitor.sv rename to library/vip/amd/axi/adi_axi_monitor.sv index 3eee77a0..3b227d2f 100644 --- a/library/drivers/common/x_monitor.sv +++ b/library/vip/amd/axi/adi_axi_monitor.sv @@ -1,25 +1,35 @@ `include "utils.svh" -package x_monitor_pkg; +package adi_axi_monitor_pkg; - import xil_common_vip_pkg::*; - import axi4stream_vip_pkg::*; import axi_vip_pkg::*; import logger_pkg::*; import adi_common_pkg::*; import pub_sub_pkg::*; - class x_monitor extends adi_monitor; + class adi_axi_monitor #(int `AXI_VIP_PARAM_ORDER(axi)) extends adi_monitor; + + // analysis port from the monitor + protected axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor; + + adi_publisher #(logic [7:0]) publisher_tx; + adi_publisher #(logic [7:0]) publisher_rx; protected bit enabled; // constructor function new( input string name, + input axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor, input adi_agent parent = null); - + super.new(name, parent); + this.monitor = monitor; + + this.publisher_tx = new("Publisher TX", this); + this.publisher_rx = new("Publisher RX", this); + this.enabled = 0; endfunction @@ -37,40 +47,9 @@ package x_monitor_pkg; this.info($sformatf("Monitor enabled"), ADI_VERBOSITY_MEDIUM); endtask: run - // virtual functions - virtual task get_transaction(); - endtask - - endclass - - - class x_axi_monitor #(int `AXI_VIP_PARAM_ORDER(axi)) extends x_monitor; - - // analysis port from the monitor - protected axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor; - protected xil_analysis_port #(axi_monitor_transaction) axi_ap; - - adi_publisher #(logic [7:0]) publisher_tx; - adi_publisher #(logic [7:0]) publisher_rx; - - // constructor - function new( - input string name, - input axi_monitor #(`AXI_VIP_PARAM_ORDER(axi)) monitor, - input adi_agent parent = null); - - super.new(name, parent); - - this.monitor = monitor; - this.axi_ap = monitor.item_collected_port; - - this.publisher_tx = new("Publisher TX", this); - this.publisher_rx = new("Publisher RX", this); - endfunction - // collect data from the DDR interface, all WRITE transaction are coming // from the ADC and all READ transactions are going to the DAC - virtual task get_transaction(); + task get_transaction(); axi_monitor_transaction transaction; xil_axi_data_beat data_beat; xil_axi_strb_beat strb_beat; @@ -79,7 +58,7 @@ package x_monitor_pkg; logic [7:0] data_queue [$]; forever begin - this.axi_ap.get(transaction); + this.monitor.item_collected_port.get(transaction); num_bytes = transaction.get_data_width()/8; for (int i=0; i<(transaction.get_len()+1); i++) begin data_beat = transaction.get_data_beat(i); @@ -106,56 +85,4 @@ package x_monitor_pkg; endclass - - class x_axis_monitor #(int `AXIS_VIP_PARAM_ORDER(axis)) extends x_monitor; - - // analysis port from the monitor - protected axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor; - protected xil_analysis_port #(axi4stream_monitor_transaction) axis_ap; - - adi_publisher #(logic [7:0]) publisher; - - // constructor - function new( - input string name, - input axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor, - input adi_agent parent = null); - - super.new(name, parent); - - this.monitor = monitor; - this.axis_ap = monitor.item_collected_port; - - this.publisher = new("Publisher", this); - endfunction - - // collect data from the AXI4Strean interface of the stub, this task - // handles both ONESHOT and CYCLIC scenarios - virtual task get_transaction(); - axi4stream_transaction transaction; - xil_axi4stream_data_beat data_beat; - xil_axi4stream_strb_beat keep_beat; - int num_bytes; - logic [7:0] axi_byte; - logic [7:0] data_queue [$]; - - forever begin - this.axis_ap.get(transaction); - // all bytes from a beat are valid - num_bytes = transaction.get_data_width()/8; - data_beat = transaction.get_data_beat(); - keep_beat = transaction.get_keep_beat(); - for (int j=0; j +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + + +`timescale 1ns/1ps + +`ifndef _AXI_DEFINITIONS_SVH_ +`define _AXI_DEFINITIONS_SVH_ + +// Help build VIP Interface parameters name +`define AXI_VIP_IF_PARAMS(n) n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN + +`define AXI_VIP_PARAM_ORDER(n) n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN + +`define AXI_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_PROTOCOL,\ + th``_``vip``_0_VIP_ADDR_WIDTH,\ + th``_``vip``_0_VIP_DATA_WIDTH,\ + th``_``vip``_0_VIP_DATA_WIDTH,\ + th``_``vip``_0_VIP_ID_WIDTH,\ + th``_``vip``_0_VIP_ID_WIDTH,\ + th``_``vip``_0_VIP_AWUSER_WIDTH,\ + th``_``vip``_0_VIP_WUSER_WIDTH,\ + th``_``vip``_0_VIP_BUSER_WIDTH,\ + th``_``vip``_0_VIP_ARUSER_WIDTH,\ + th``_``vip``_0_VIP_RUSER_WIDTH,\ + th``_``vip``_0_VIP_SUPPORTS_NARROW,\ + th``_``vip``_0_VIP_HAS_BURST,\ + th``_``vip``_0_VIP_HAS_LOCK,\ + th``_``vip``_0_VIP_HAS_CACHE,\ + th``_``vip``_0_VIP_HAS_REGION,\ + th``_``vip``_0_VIP_HAS_PROT,\ + th``_``vip``_0_VIP_HAS_QOS,\ + th``_``vip``_0_VIP_HAS_WSTRB,\ + th``_``vip``_0_VIP_HAS_BRESP,\ + th``_``vip``_0_VIP_HAS_RRESP,\ + th``_``vip``_0_VIP_HAS_ARESETN + +`endif diff --git a/library/vip/amd/m_axi_sequencer.sv b/library/vip/amd/axi/m_axi_sequencer.sv similarity index 99% rename from library/vip/amd/m_axi_sequencer.sv rename to library/vip/amd/axi/m_axi_sequencer.sv index 7e917b0a..c786d5ee 100644 --- a/library/vip/amd/m_axi_sequencer.sv +++ b/library/vip/amd/axi/m_axi_sequencer.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" package m_axi_sequencer_pkg; diff --git a/library/vip/amd/s_axi_sequencer.sv b/library/vip/amd/axi/s_axi_sequencer.sv similarity index 99% rename from library/vip/amd/s_axi_sequencer.sv rename to library/vip/amd/axi/s_axi_sequencer.sv index b03b2f40..c09f2f5d 100644 --- a/library/vip/amd/s_axi_sequencer.sv +++ b/library/vip/amd/axi/s_axi_sequencer.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" package s_axi_sequencer_pkg; diff --git a/library/vip/amd/adi_axis_agent.sv b/library/vip/amd/axis/adi_axis_agent.sv similarity index 93% rename from library/vip/amd/adi_axis_agent.sv rename to library/vip/amd/axis/adi_axis_agent.sv index 65801c1a..392b79e5 100644 --- a/library/vip/amd/adi_axis_agent.sv +++ b/library/vip/amd/axis/adi_axis_agent.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axis_definitions.svh" package adi_axis_agent_pkg; @@ -42,14 +43,14 @@ package adi_axis_agent_pkg; import axi4stream_vip_pkg::*; import m_axis_sequencer_pkg::*; import s_axis_sequencer_pkg::*; - import x_monitor_pkg::*; + import adi_axis_monitor_pkg::*; class adi_axis_master_agent #(int `AXIS_VIP_PARAM_ORDER(master)) extends adi_agent; axi4stream_mst_agent #(`AXIS_VIP_IF_PARAMS(master)) agent; m_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(master)) sequencer; - x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(master)) monitor; + adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(master)) monitor; function new( input string name, @@ -70,7 +71,7 @@ package adi_axis_agent_pkg; axi4stream_slv_agent #(`AXIS_VIP_IF_PARAMS(slave)) agent; s_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(slave)) sequencer; - x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(slave)) monitor; + adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(slave)) monitor; function new( input string name, @@ -90,7 +91,7 @@ package adi_axis_agent_pkg; class adi_axis_passthrough_mem_agent #(int `AXIS_VIP_PARAM_ORDER(passthrough)) extends adi_agent; axi4stream_passthrough_agent #(`AXIS_VIP_IF_PARAMS(passthrough)) agent; - x_axis_monitor #(`AXIS_VIP_PARAM_ORDER(passthrough)) monitor; + adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(passthrough)) monitor; function new( input string name, diff --git a/library/vip/amd/axis/adi_axis_monitor.sv b/library/vip/amd/axis/adi_axis_monitor.sv new file mode 100644 index 00000000..b13849cb --- /dev/null +++ b/library/vip/amd/axis/adi_axis_monitor.sv @@ -0,0 +1,77 @@ +`include "utils.svh" + +package adi_axis_monitor_pkg; + + import axi4stream_vip_pkg::*; + import logger_pkg::*; + import adi_common_pkg::*; + import pub_sub_pkg::*; + + class adi_axis_monitor #(int `AXIS_VIP_PARAM_ORDER(axis)) extends adi_monitor; + + // analysis port from the monitor + protected axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor; + + adi_publisher #(logic [7:0]) publisher; + + protected bit enabled; + + // constructor + function new( + input string name, + input axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor, + input adi_agent parent = null); + + super.new(name, parent); + + this.monitor = monitor; + + this.publisher = new("Publisher", this); + + this.enabled = 0; + endfunction + + task run(); + if (this.enabled) begin + this.error($sformatf("Monitor is already running!")); + return; + end + + fork + this.get_transaction(); + join_none + + this.enabled = 1; + this.info($sformatf("Monitor enabled"), ADI_VERBOSITY_MEDIUM); + endtask: run + + // collect data from the AXI4Strean interface of the stub, this task + // handles both ONESHOT and CYCLIC scenarios + task get_transaction(); + axi4stream_transaction transaction; + xil_axi4stream_data_beat data_beat; + xil_axi4stream_strb_beat keep_beat; + int num_bytes; + logic [7:0] axi_byte; + logic [7:0] data_queue [$]; + + forever begin + this.monitor.item_collected_port.get(transaction); + // all bytes from a beat are valid + num_bytes = transaction.get_data_width()/8; + data_beat = transaction.get_data_beat(); + keep_beat = transaction.get_keep_beat(); + for (int j=0; j +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + + +`timescale 1ns/1ps + +`ifndef _AXIS_DEFINITIONS_SVH_ +`define _AXIS_DEFINITIONS_SVH_ + +// Help build VIP Interface parameters name +`define AXIS_VIP_PARAM_DECL AXIS_VIP_INTERFACE_MODE = 2,\ + AXIS_VIP_SIGNAL_SET = 8'b00000011,\ + AXIS_VIP_DATA_WIDTH = 8,\ + AXIS_VIP_ID_WIDTH = 0,\ + AXIS_VIP_DEST_WIDTH = 0,\ + AXIS_VIP_USER_WIDTH = 0,\ + AXIS_VIP_USER_BITS_PER_BYTE = 0,\ + AXIS_VIP_HAS_TREADY = 1,\ + AXIS_VIP_HAS_TSTRB = 0,\ + AXIS_VIP_HAS_TKEEP = 0,\ + AXIS_VIP_HAS_TLAST = 0,\ + AXIS_VIP_HAS_ACLKEN = 0,\ + AXIS_VIP_HAS_ARESETN = 1 + +`define AXIS_VIP_PARAM_ORDER(n) n``_VIP_INTERFACE_MODE,\ + n``_VIP_SIGNAL_SET,\ + n``_VIP_DATA_WIDTH,\ + n``_VIP_ID_WIDTH,\ + n``_VIP_DEST_WIDTH,\ + n``_VIP_USER_WIDTH,\ + n``_VIP_USER_BITS_PER_BYTE,\ + n``_VIP_HAS_TREADY,\ + n``_VIP_HAS_TSTRB,\ + n``_VIP_HAS_TKEEP,\ + n``_VIP_HAS_TLAST,\ + n``_VIP_HAS_ACLKEN,\ + n``_VIP_HAS_ARESETN + +`define AXIS_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_INTERFACE_MODE,\ + th``_``vip``_0_VIP_SIGNAL_SET,\ + th``_``vip``_0_VIP_DATA_WIDTH,\ + th``_``vip``_0_VIP_ID_WIDTH,\ + th``_``vip``_0_VIP_DEST_WIDTH,\ + th``_``vip``_0_VIP_USER_WIDTH,\ + th``_``vip``_0_VIP_USER_BITS_PER_BYTE,\ + th``_``vip``_0_VIP_HAS_TREADY,\ + th``_``vip``_0_VIP_HAS_TSTRB,\ + th``_``vip``_0_VIP_HAS_TKEEP,\ + th``_``vip``_0_VIP_HAS_TLAST,\ + th``_``vip``_0_VIP_HAS_ACLKEN,\ + th``_``vip``_0_VIP_HAS_ARESETN + +`define AXIS_VIP_IF_PARAMS(n) n``_VIP_SIGNAL_SET,\ + n``_VIP_DEST_WIDTH,\ + n``_VIP_DATA_WIDTH,\ + n``_VIP_ID_WIDTH,\ + n``_VIP_USER_WIDTH,\ + n``_VIP_USER_BITS_PER_BYTE,\ + n``_VIP_HAS_ARESETN + +`endif diff --git a/library/vip/amd/m_axis_sequencer.sv b/library/vip/amd/axis/m_axis_sequencer.sv similarity index 99% rename from library/vip/amd/m_axis_sequencer.sv rename to library/vip/amd/axis/m_axis_sequencer.sv index 6a319870..8bf3c429 100644 --- a/library/vip/amd/m_axis_sequencer.sv +++ b/library/vip/amd/axis/m_axis_sequencer.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axis_definitions.svh" package m_axis_sequencer_pkg; diff --git a/library/vip/amd/s_axis_sequencer.sv b/library/vip/amd/axis/s_axis_sequencer.sv similarity index 99% rename from library/vip/amd/s_axis_sequencer.sv rename to library/vip/amd/axis/s_axis_sequencer.sv index dc09e5ba..26e229b7 100644 --- a/library/vip/amd/s_axis_sequencer.sv +++ b/library/vip/amd/axis/s_axis_sequencer.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axis_definitions.svh" package s_axis_sequencer_pkg; diff --git a/testbenches/ip/base/tests/test_program.sv b/testbenches/ip/base/tests/test_program.sv index 6c5c21b5..d002e04a 100644 --- a/testbenches/ip/base/tests/test_program.sv +++ b/testbenches/ip/base/tests/test_program.sv @@ -34,6 +34,7 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" import logger_pkg::*; import test_harness_env_pkg::*; diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index 48261fdb..a849e39d 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -1,4 +1,6 @@ `include "utils.svh" +`include "axi_definitions.svh" +`include "axis_definitions.svh" package environment_pkg; diff --git a/testbenches/ip/scoreboard/tests/test_program.sv b/testbenches/ip/scoreboard/tests/test_program.sv index 029698a4..3ae86f18 100644 --- a/testbenches/ip/scoreboard/tests/test_program.sv +++ b/testbenches/ip/scoreboard/tests/test_program.sv @@ -36,9 +36,9 @@ // // `include "utils.svh" +`include "axi_definitions.svh" +`include "axis_definitions.svh" -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; import environment_pkg::*; import test_harness_env_pkg::*; From 5dd8e70743ccbbcccf9e146eb6436f6ae29bd4fc Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 16 Dec 2024 14:58:15 +0200 Subject: [PATCH 04/13] infrastructure refactorization: Generalized scoreboard Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/scoreboard.sv | 26 ++++++++++++++---------- testbenches/ip/scoreboard/environment.sv | 4 ++-- 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv index f5fe568a..765182f4 100644 --- a/library/drivers/common/scoreboard.sv +++ b/library/drivers/common/scoreboard.sv @@ -9,17 +9,17 @@ package scoreboard_pkg; import adi_common_pkg::*; import pub_sub_pkg::*; - class scoreboard extends adi_component; + class scoreboard #(type data_type = int) extends adi_component; - class subscriber_class extends adi_subscriber #(logic [7:0]); + class subscriber_class extends adi_subscriber #(data_type); - protected scoreboard scoreboard_ref; + protected scoreboard #(data_type) scoreboard_ref; - protected logic [7:0] byte_stream [$]; + protected data_type byte_stream [$]; function new( input string name, - input scoreboard scoreboard_ref, + input scoreboard #(data_type) scoreboard_ref, input adi_component parent = null); super.new(name, parent); @@ -30,19 +30,19 @@ package scoreboard_pkg; virtual function void update(input data_type data [$]); this.info($sformatf("Data received: %d", data.size()), ADI_VERBOSITY_MEDIUM); while (data.size()) begin - this.byte_stream.push_back(data.pop_front); + this.byte_stream.push_back(data.pop_front()); end - if (this.scoreboard_ref.enabled) begin + if (this.scoreboard_ref.get_enabled()) begin this.scoreboard_ref.compare_transaction(); end endfunction: update - function logic [7:0] get_data(); + function data_type get_data(); return this.byte_stream.pop_front(); endfunction: get_data - function void put_data(logic [7:0] data); + function void put_data(data_type data); this.byte_stream.push_back(data); endfunction: put_data @@ -100,6 +100,10 @@ package scoreboard_pkg; this.byte_streams_empty_sig = 1; endtask: stop + function bit get_enabled(); + return this.enabled; + endfunction: get_enabled + // set sink type function void set_sink_type(input bit sink_type); if (!this.enabled) begin @@ -129,8 +133,8 @@ package scoreboard_pkg; // compare the collected data virtual function void compare_transaction(); - logic [7:0] source_byte; - logic [7:0] sink_byte; + data_type source_byte; + data_type sink_byte; if (this.enabled == 0) return; diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index a849e39d..515d5b1d 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -26,8 +26,8 @@ package environment_pkg; adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(adc_dst_pt)) adc_dst_axi_pt_agent; adi_axi_passthrough_mem_agent #(`AXI_VIP_PARAM_ORDER(dac_src_pt)) dac_src_axi_pt_agent; - scoreboard scoreboard_tx; - scoreboard scoreboard_rx; + scoreboard #(logic [7:0]) scoreboard_tx; + scoreboard #(logic [7:0]) scoreboard_rx; //============================================================================ // Constructor From 3bc97eaaf62293aa292b2780397fe0e239ffb7de Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 16 Dec 2024 15:14:53 +0200 Subject: [PATCH 05/13] infrastructure refactorization: Updated DMA loopback project Signed-off-by: Istvan-Zsolt Szekely --- .../ip/dma_loopback/tests/test_program.sv | 45 +++++++++---------- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index 0e609f33..62ff95ec 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -36,19 +36,22 @@ // // `include "utils.svh" +`include "axi_definitions.svh" import test_harness_env_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; import dma_trans_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + program test_program; - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + // Register accessors dmac_api m_dmac_api; dmac_api s_dmac_api; @@ -56,7 +59,7 @@ program test_program; initial begin //creating environment - env = new("DMA Loopback Environment", + base_env = new("DMA Loopback Environment", `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, @@ -64,29 +67,25 @@ program test_program; `TH.`MNG_AXI.inst.IF, `TH.`DDR_AXI.inst.IF); - #2ps; - setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + + base_env.start(); + start_clocks(); + base_env.sys_reset(); - m_dmac_api = new("TX_DMA", env.mng, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", base_env.mng.sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", base_env.mng.sequencer, `RX_DMA_BA); s_dmac_api.probe(); - start_clocks(); - sys_reset(); - - #1us; - // ------------------------------------------------------- // Test TX DMA and RX DMA in loopback // ------------------------------------------------------- // Init test data for (int i=0;i<2048*2 ;i=i+2) begin - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,'hF); end do_transfer( @@ -103,6 +102,11 @@ program test_program; .length('h1000) ); + base_env.stop(); + + `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); + $finish(); + end task do_transfer(bit [31:0] src_addr, @@ -147,8 +151,8 @@ program test_program; for (int i=0;i Date: Mon, 16 Dec 2024 16:06:58 +0200 Subject: [PATCH 06/13] infrastructure refactorization: Fixed address value in DMA loopback for DDR Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/dma_loopback/tests/test_program.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index 62ff95ec..02320217 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -44,6 +44,7 @@ import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; import dma_trans_pkg::*; +import axi_vip_pkg::*; import `PKGIFY(test_harness, mng_axi_vip)::*; import `PKGIFY(test_harness, ddr_axi_vip)::*; @@ -85,7 +86,7 @@ program test_program; // Init test data for (int i=0;i<2048*2 ;i=i+2) begin - base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF); end do_transfer( From 71c126b6da05a57855c8bd850b84ee0b6333fdbb Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Fri, 17 Jan 2025 16:00:40 +0200 Subject: [PATCH 07/13] infrastructure refactorization: Updated IP level testbenches Signed-off-by: Istvan-Zsolt Szekely --- library/drivers/common/scoreboard.sv | 3 - library/drivers/common/scoreboard_pack.sv | 124 ++++++----- library/vip/adi/spi_vip/adi_spi_vip_ip.tcl | 4 +- library/vip/adi/spi_vip/adi_spi_vip_pkg.sv | 1 + library/vip/adi/spi_vip/s_spi_sequencer.sv | 1 + testbenches/ip/axi_tdd/tests/test_program.sv | 168 +++++++-------- testbenches/ip/axis_sequencers/environment.sv | 110 +++------- .../ip/axis_sequencers/tests/test_program.sv | 96 +++++---- testbenches/ip/dma_flock/environment.sv | 92 +++----- testbenches/ip/dma_flock/scoreboard.sv | 3 +- .../ip/dma_flock/tests/test_program.sv | 82 +++++--- .../tests/test_program_frame_delay.sv | 87 ++++---- .../ip/dma_sg/tests/test_program_1d.sv | 151 ++++++------- .../ip/dma_sg/tests/test_program_2d.sv | 129 ++++++------ .../ip/dma_sg/tests/test_program_tr_queue.sv | 171 +++++++-------- testbenches/ip/i3c_controller/Makefile | 6 +- .../ip/i3c_controller/system_project.tcl | 2 + .../ip/i3c_controller/tests/test_program.sv | 35 +-- .../ip/jesd_loopback/tests/test_program.sv | 144 ++++++------- .../jesd_loopback_64b/tests/test_program.sv | 88 ++++---- .../ip/scoreboard/tests/test_program.sv | 2 +- testbenches/ip/spi_engine/spi_environment.sv | 43 +--- .../ip/spi_engine/tests/test_program.sv | 86 ++++---- .../ip/spi_engine/tests/test_sleep_delay.sv | 86 ++++---- testbenches/ip/util_pack/environment.sv | 199 +++++------------- .../ip/util_pack/tests/test_program.sv | 73 ++++--- 26 files changed, 938 insertions(+), 1048 deletions(-) diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv index 765182f4..7c1ccc0d 100644 --- a/library/drivers/common/scoreboard.sv +++ b/library/drivers/common/scoreboard.sv @@ -2,9 +2,6 @@ package scoreboard_pkg; - import xil_common_vip_pkg::*; - import axi4stream_vip_pkg::*; - import axi_vip_pkg::*; import logger_pkg::*; import adi_common_pkg::*; import pub_sub_pkg::*; diff --git a/library/drivers/common/scoreboard_pack.sv b/library/drivers/common/scoreboard_pack.sv index 7a7b151d..cd6020b1 100644 --- a/library/drivers/common/scoreboard_pack.sv +++ b/library/drivers/common/scoreboard_pack.sv @@ -2,12 +2,8 @@ package scoreboard_pack_pkg; - import xil_common_vip_pkg::*; - import axi4stream_vip_pkg::*; - import axi_vip_pkg::*; import logger_pkg::*; - import x_monitor_pkg::*; - import mailbox_pkg::*; + import adi_common_pkg::*; import scoreboard_pkg::*; typedef enum { @@ -15,7 +11,7 @@ package scoreboard_pack_pkg; UPACK } pack_type; - class scoreboard_pack extends scoreboard; + class scoreboard_pack #(type data_type = int) extends scoreboard#(.data_type(data_type)); protected int channels; protected int samples; @@ -42,62 +38,90 @@ package scoreboard_pack_pkg; endfunction: new // compare the collected data - virtual task compare_transaction(); + virtual function void compare_transaction(); logic [7:0] source_byte; logic [7:0] sink_byte; - logic [7:0] sink_byte_stream_block [int]; + data_type sink_byte_stream_block [int]; int outer_loop = (this.mode == CPACK) ? this.channels : this.samples; int inner_loop = (this.mode == CPACK) ? this.samples : this.channels; - this.info($sformatf("Scoreboard started"), 100); - - forever begin : tx_path - if (this.enabled == 0) - break; - if ((this.source_byte_stream_size > 0) && - (this.sink_byte_stream_size >= this.channels*this.samples*this.width/8)) begin - byte_streams_empty_sig = 0; - for (int i=0; i 0) && + // (this.sink_byte_stream_size >= this.channels*this.samples*this.width/8)) begin + // byte_streams_empty_sig = 0; + // for (int i=0; i>byte_streams_empty; + // end + // fork begin + // fork + // @source_transaction_event; + // @sink_transaction_event; + // @stop_scoreboard; + // join_any + // byte_streams_empty_sig = 0; + // disable fork; + // end join + // end + // end + + while ((this.subscriber_source.get_size() > 0) && + (this.subscriber_sink.get_size() >= this.channels*this.samples*this.width/8)) begin + byte_streams_empty_sig = 0; + for (int i=0; i>byte_streams_empty; - end - fork begin - fork - @source_transaction_event; - @sink_transaction_event; - @stop_scoreboard; - join_any - byte_streams_empty_sig = 0; - disable fork; - end join end - end + end - endtask /* compare_transaction */ + if ((this.subscriber_source.get_size() == 0) && + (this.subscriber_sink.get_size() == 0)) begin + this.byte_streams_empty_sig = 1; + ->this.byte_streams_empty; + end + endfunction: compare_transaction endclass diff --git a/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl b/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl index 1e745e88..ec3e200a 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl +++ b/library/vip/adi/spi_vip/adi_spi_vip_ip.tcl @@ -12,8 +12,8 @@ adi_ip_files adi_spi_vip [list \ "adi_spi_vip.sv" \ "spi_vip_if.sv" \ "adi_spi_vip_pkg.ttcl" \ - "$ad_hdl_dir/testbenches/library/utilities/utils.svh" \ - "$ad_hdl_dir/testbenches/library/utilities/logger_pkg.sv" \ + "$ad_tb_dir/library/utilities/utils.svh" \ + "$ad_tb_dir/library/utilities/logger_pkg.sv" \ ] adi_ip_properties_lite adi_spi_vip diff --git a/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv b/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv index b403a0ba..4d66c3c6 100644 --- a/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv +++ b/library/vip/adi/spi_vip/adi_spi_vip_pkg.sv @@ -38,6 +38,7 @@ package adi_spi_vip_pkg; import logger_pkg::*; + import adi_common_pkg::*; `define SPI_VIP_PARAM_ORDER SPI_VIP_MODE ,\ SPI_VIP_CPOL ,\ diff --git a/library/vip/adi/spi_vip/s_spi_sequencer.sv b/library/vip/adi/spi_vip/s_spi_sequencer.sv index 82995926..79112770 100644 --- a/library/vip/adi/spi_vip/s_spi_sequencer.sv +++ b/library/vip/adi/spi_vip/s_spi_sequencer.sv @@ -38,6 +38,7 @@ package s_spi_sequencer_pkg; import logger_pkg::*; + import adi_common_pkg::*; import adi_spi_vip_pkg::*; class s_spi_sequencer #(`SPI_VIP_PARAM_ORDER) extends adi_component; diff --git a/testbenches/ip/axi_tdd/tests/test_program.sv b/testbenches/ip/axi_tdd/tests/test_program.sv index 05324c7b..0819bacd 100644 --- a/testbenches/ip/axi_tdd/tests/test_program.sv +++ b/testbenches/ip/axi_tdd/tests/test_program.sv @@ -37,17 +37,18 @@ // `include "utils.svh" -import test_harness_env_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; +import test_harness_env_pkg::*; import adi_regmap_pkg::*; import adi_regmap_tdd_gen_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + program test_program; //instantiate the environment - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; //written variables int unsigned ch_on [32]; @@ -88,23 +89,19 @@ program test_program; initial begin //creating environment - env = new("Axi TDD Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + base_env.start(); start_clocks(); - sys_reset(); - - #1us; + base_env.sys_reset(); // ------------------------------------------------------- // Test start @@ -112,7 +109,7 @@ program test_program; // Init test data // Read the interface description - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_INTERFACE_DESCRIPTION), val); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_INTERFACE_DESCRIPTION), val); channel_count = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_CHANNEL_COUNT_EXTRA(val); reg_count_width = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_REGISTER_WIDTH(val); burst_count_width = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_BURST_COUNT_WIDTH(val); @@ -122,41 +119,41 @@ program test_program; sync_ext_cdc = `GET_TDDN_CNTRL_INTERFACE_DESCRIPTION_SYNC_EXTERNAL_CDC(val); // Register configuration - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(32'hFFFFFFFF)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'h00000000)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), `SET_TDDN_CNTRL_BURST_COUNT_BURST_COUNT(channel_count+1)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), `SET_TDDN_CNTRL_STARTUP_DELAY_STARTUP_DELAY(32'h0000007F)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), `SET_TDDN_CNTRL_FRAME_LENGTH_FRAME_LENGTH(32'h0000007F)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), `SET_TDDN_CNTRL_SYNC_COUNTER_LOW_SYNC_COUNTER_LOW(32'h000001FF)); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), `SET_TDDN_CNTRL_SYNC_COUNTER_HIGH_SYNC_COUNTER_HIGH(32'h00000000)); // Reading back the actual register values (the values may change depending on the synthesis configuration) - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), frame_length); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_FRAME_LENGTH), frame_length); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), sync_count_low); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_LOW), sync_count_low); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), sync_count_high); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_SYNC_COUNTER_HIGH), sync_count_high); // ------------------------------------------------------- @@ -172,17 +169,17 @@ program test_program; end for (int i=0; i<32; i++) begin - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, `SET_TDDN_CNTRL_CH0_ON_CH0_ON(ch_on[i])); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, `SET_TDDN_CNTRL_CH0_OFF_CH0_OFF(ch_off[i])); end // Read back the values; unimplemented channels should not store these values for (int i=0; i<32; i++) begin - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); if (i <= channel_count) begin expected_val = ch_on[i]; @@ -196,7 +193,7 @@ program test_program; success_count++; end - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); if (i <= channel_count) begin expected_val = ch_off[i]; @@ -212,7 +209,7 @@ program test_program; end // Read the status register to validate the current state - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b00) begin `FATAL(("Idle state: Expected 2'b00 found 2'b%b", current_state)); @@ -222,7 +219,7 @@ program test_program; // Enable the module; use internal sync for transfer triggering - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(1)| @@ -238,7 +235,7 @@ program test_program; // Read the status register to validate the current state repeat (8) @(posedge `TH.dut_tdd.inst.up_clk); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b10) begin `FATAL(("Waiting state: Expected 2'b10 found 2'b%b", current_state)); @@ -264,7 +261,7 @@ program test_program; // Read the status register to validate the current state issuing a parallel thread repeat (8) @(posedge `TH.dut_tdd.inst.up_clk); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b11) begin `FATAL(("Running state: Expected 2'b11 found 2'b%b", current_state)); @@ -281,7 +278,7 @@ program test_program; //*******// // Read the status register to validate the current state repeat (8) @(posedge `TH.dut_tdd.inst.up_clk); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STATUS), current_state); if (current_state !== 2'b01) begin `FATAL(("Armed state: Expected 2'b01 found 2'b%b", current_state)); @@ -290,17 +287,17 @@ program test_program; end // Disable the module to change the polarity - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to inverted polarity - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'hFFFFFFFF)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // Re-enable the module - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(1)| @@ -321,14 +318,14 @@ program test_program; // ARMED // //*******// // Disable the module - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to direct polarity - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'h00000000)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // ------------------------------------------------------- @@ -344,16 +341,16 @@ program test_program; end for (int i=0; i<32; i++) begin - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, `SET_TDDN_CNTRL_CH0_ON_CH0_ON(ch_on[i])); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, `SET_TDDN_CNTRL_CH0_OFF_CH0_OFF(ch_off[i])); end // Read back the values; unimplemented channels should not store these values for (int i=0; i<32; i++) begin - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_ON)+i*8, val); if (i <= channel_count) begin expected_val = ch_on[i]; @@ -367,7 +364,7 @@ program test_program; success_count++; end - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CH0_OFF)+i*8, val); if (i <= channel_count) begin expected_val = ch_off[i]; @@ -384,7 +381,7 @@ program test_program; // Enable the module; use external sync for transfer triggering - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -408,17 +405,17 @@ program test_program; // ARMED // //*******// // Disable the module - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to inverted polarity - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'hFFFFFFFF)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // Keep the module enabled; issue a software sync - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -439,14 +436,14 @@ program test_program; // ARMED // //*******// // Disable the module - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); // Switch to direct polarity - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), `SET_TDDN_CNTRL_CHANNEL_POLARITY_CHANNEL_POLARITY(32'h00000000)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_POLARITY), ch_pol); // ------------------------------------------------------- @@ -454,11 +451,11 @@ program test_program; // ------------------------------------------------------- // Increase the burst count value by 1 - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), `SET_TDDN_CNTRL_BURST_COUNT_BURST_COUNT(channel_count+2)); // Keep the module enabled; issue a software sync; enable external sync and reset on sync - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -487,7 +484,7 @@ program test_program; end // Disable the module before the end of the burst - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); @(posedge `TH.dut_tdd.inst.tdd_endof_frame); @@ -495,24 +492,24 @@ program test_program; // Check the pulse length using a loop on all available channels check_pulse_length(); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(0)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), ch_en); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), `SET_TDDN_CNTRL_BURST_COUNT_BURST_COUNT(0)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_BURST_COUNT), burst_count); - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), `SET_TDDN_CNTRL_STARTUP_DELAY_STARTUP_DELAY(0)); - env.mng.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); + base_env.mng.sequencer.RegRead32(`TDD_BA+GetAddrs(TDDN_CNTRL_STARTUP_DELAY), startup_delay); // Enable the module with external synchronization actived - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_SYNC_SOFT(0)| `SET_TDDN_CNTRL_CONTROL_SYNC_EXT(1)| `SET_TDDN_CNTRL_CONTROL_SYNC_INT(0)| @@ -535,7 +532,7 @@ program test_program; success_count++; end - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(ch_en)); ch_en = (ch_en << 1) | 32'b1; @@ -553,7 +550,7 @@ program test_program; success_count++; end - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CHANNEL_ENABLE), `SET_TDDN_CNTRL_CHANNEL_ENABLE_CHANNEL_ENABLE(ch_en)); ch_en = (ch_en >> 1); @@ -561,13 +558,14 @@ program test_program; end // Disable the module - env.mng.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), + base_env.mng.sequencer.RegWrite32(`TDD_BA+GetAddrs(TDDN_CNTRL_CONTROL), `SET_TDDN_CNTRL_CONTROL_ENABLE(0)); + base_env.stop(); stop_clocks(); `INFO(("Testbench finished!"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -582,14 +580,6 @@ program test_program; endtask - task sys_reset(); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - endtask - - task trigger_ext_event(); #20ns; `TB.sync_in =1'b1; @@ -607,11 +597,15 @@ program test_program; time t1=0, t2=0, expected_pulse_lengh; fork - channel_probe(i, t1, t2); - join_none - @(posedge `TH.dut_tdd.inst.tdd_endof_frame); - repeat (3) @(posedge `TH.dut_tdd.inst.clk); - disable fork; + begin + fork + channel_probe(i, t1, t2); + join_none + @(posedge `TH.dut_tdd.inst.tdd_endof_frame); + repeat (3) @(posedge `TH.dut_tdd.inst.clk); + disable fork; + end + join if (ch_on[i] == ch_off[i]) begin expected_pulse_lengh = 0; diff --git a/testbenches/ip/axis_sequencers/environment.sv b/testbenches/ip/axis_sequencers/environment.sv index ba3fe31c..423e8b63 100644 --- a/testbenches/ip/axis_sequencers/environment.sv +++ b/testbenches/ip/axis_sequencers/environment.sv @@ -1,32 +1,21 @@ `include "utils.svh" +`include "axis_definitions.svh" package environment_pkg; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; - import m_axis_sequencer_pkg::*; - import s_axis_sequencer_pkg::*; import logger_pkg::*; - import axi_vip_pkg::*; - import axi4stream_vip_pkg::*; - import test_harness_env_pkg::*; - - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; - - import `PKGIFY(test_harness, src_axis)::*; - import `PKGIFY(test_harness, dst_axis)::*; + import adi_common_pkg::*; - class environment extends test_harness_env; + import axi4stream_vip_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import adi_axis_agent_pkg::*; - // agents and sequencers - `AGENT(test_harness, src_axis, mst_t) src_axis_agent; - `AGENT(test_harness, dst_axis, slv_t) dst_axis_agent; + class axis_sequencer_environment #(int `AXIS_VIP_PARAM_ORDER(src_axis), int `AXIS_VIP_PARAM_ORDER(dst_axis)) extends adi_environment; - m_axis_sequencer #(`AGENT(test_harness, src_axis, mst_t), - `AXIS_VIP_PARAMS(test_harness, src_axis) - ) src_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, dst_axis, slv_t)) dst_axis_seq; + // Agents + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(src_axis)) src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(dst_axis)) dst_axis_agent; //============================================================================ // Constructor @@ -34,34 +23,14 @@ package environment_pkg; function new ( input string name, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, - - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, src_axis)) src_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, dst_axis)) dst_axis_vip_if - ); + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(src_axis)) src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(dst_axis)) dst_axis_vip_if); // creating the agents - super.new(name, - sys_clk_vip_if, - dma_clk_vip_if, - ddr_clk_vip_if, - sys_rst_vip_if, - mng_vip_if, - ddr_vip_if); - - src_axis_agent = new("Source AXI Stream Agent", src_axis_vip_if); - dst_axis_agent = new("Destination AXI Stream Agent", dst_axis_vip_if); - - src_axis_seq = new("Source AXI Stream Agent", src_axis_agent, this); - dst_axis_seq = new("Destination AXI Stream Agent", dst_axis_agent, this); + super.new(name); + this.src_axis_agent = new("Source AXI Stream Agent", src_axis_vip_if, this); + this.dst_axis_agent = new("Destination AXI Stream Agent", dst_axis_vip_if, this); endfunction //============================================================================ @@ -69,68 +38,41 @@ package environment_pkg; // - Configure the sequencer VIPs with an initial configuration before starting them //============================================================================ task configure(); - xil_axi4stream_ready_gen_policy_t dac_mode; // source stub - src_axis_seq.set_stop_policy(STOP_POLICY_PACKET); + this.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET); // destination stub dac_mode = XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE; - dst_axis_seq.set_mode(dac_mode); - + this.dst_axis_agent.sequencer.set_mode(dac_mode); endtask //============================================================================ // Start environment //============================================================================ task start(); - - super.start(); - - src_axis_agent.start_master(); - dst_axis_agent.start_slave(); - - endtask - - //============================================================================ - // Start the test - //============================================================================ - task test(); - fork - src_axis_seq.run(); - dst_axis_seq.run(); - join_none - endtask - - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); + this.src_axis_agent.agent.start_master(); + this.dst_axis_agent.agent.start_slave(); endtask //============================================================================ // Run subroutine //============================================================================ task run; - - //pre_test(); - test(); - + fork + this.src_axis_agent.sequencer.run(); + this.dst_axis_agent.sequencer.run(); + join_none endtask //============================================================================ // Stop subroutine //============================================================================ task stop; - - super.stop(); - src_axis_seq.stop(); - src_axis_agent.stop_master(); - dst_axis_agent.stop_slave(); - post_test(); - + this.src_axis_agent.sequencer.stop(); + this.src_axis_agent.agent.stop_master(); + this.dst_axis_agent.agent.stop_slave(); endtask endclass diff --git a/testbenches/ip/axis_sequencers/tests/test_program.sv b/testbenches/ip/axis_sequencers/tests/test_program.sv index ac02bb73..1e513528 100644 --- a/testbenches/ip/axis_sequencers/tests/test_program.sv +++ b/testbenches/ip/axis_sequencers/tests/test_program.sv @@ -37,80 +37,86 @@ // `include "utils.svh" -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; -import m_axis_sequencer_pkg::*; -import s_axis_sequencer_pkg::*; import logger_pkg::*; +import test_harness_env_pkg::*; import environment_pkg::*; import watchdog_pkg::*; +import axi4stream_vip_pkg::*; +import m_axis_sequencer_pkg::*; +import s_axis_sequencer_pkg::*; -//============================================================================= -// Register Maps -//============================================================================= +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, src_axis)::*; +import `PKGIFY(test_harness, dst_axis)::*; program test_program; // declare the class instances - environment env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + axis_sequencer_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis), `AXIS_VIP_PARAMS(test_harness, dst_axis)) axis_seq_env; watchdog send_data_wd; initial begin // create environment - env = new("Axis Sequencers Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SRC_AXIS.inst.IF, - `TH.`DST_AXIS.inst.IF - ); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + axis_seq_env = new("Axis Sequencers Environment", + `TH.`SRC_AXIS.inst.IF, + `TH.`DST_AXIS.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + axis_seq_env.start(); + + base_env.sys_reset(); - env.configure(); + axis_seq_env.configure(); - env.run(); + axis_seq_env.run(); - env.src_axis_seq.set_data_beat_delay(`SRC_BEAT_DELAY); - env.src_axis_seq.set_descriptor_delay(`SRC_DESCRIPTOR_DELAY); + axis_seq_env.src_axis_agent.sequencer.set_data_beat_delay(`SRC_BEAT_DELAY); + axis_seq_env.src_axis_agent.sequencer.set_descriptor_delay(`SRC_DESCRIPTOR_DELAY); - env.dst_axis_seq.set_high_time(`DEST_BEAT_DELAY_HIGH); - env.dst_axis_seq.set_low_time(`DEST_BEAT_DELAY_LOW); + axis_seq_env.dst_axis_agent.sequencer.set_high_time(`DEST_BEAT_DELAY_HIGH); + axis_seq_env.dst_axis_agent.sequencer.set_low_time(`DEST_BEAT_DELAY_LOW); case (`DEST_BACKPRESSURE) - 1: env.dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_SINGLE); - 2: env.dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + 1: axis_seq_env.dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_SINGLE); + 2: axis_seq_env.dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); default: `FATAL(("Destination backpressure mode parameter incorrect!")); endcase case (`SRC_DESCRIPTORS) 1: begin - env.src_axis_seq.set_descriptor_gen_mode(0); - env.src_axis_seq.set_stop_policy(STOP_POLICY_DATA_BEAT); - // env.src_axis_seq.add_xfer_descriptor(32'h600, 1, 0); - env.src_axis_seq.add_xfer_descriptor_packet_size(32'd10, 1, 0); + axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(0); + axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_DATA_BEAT); + // axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); + axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor_packet_size(32'd10, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 1000, "Send data"); end 2: begin - env.src_axis_seq.set_descriptor_gen_mode(0); - env.src_axis_seq.set_stop_policy(STOP_POLICY_DESCRIPTOR_QUEUE); - repeat (10) env.src_axis_seq.add_xfer_descriptor(32'h600, 1, 0); + axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(0); + axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_DESCRIPTOR_QUEUE); + repeat (10) axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 30000, "Send data"); end 3: begin - env.src_axis_seq.set_descriptor_gen_mode(1); - env.src_axis_seq.set_stop_policy(STOP_POLICY_PACKET); - env.src_axis_seq.add_xfer_descriptor(32'h600, 1, 0); + axis_seq_env.src_axis_agent.sequencer.set_descriptor_gen_mode(1); + axis_seq_env.src_axis_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET); + axis_seq_env.src_axis_agent.sequencer.add_xfer_descriptor(32'h600, 1, 0); send_data_wd = new("Axis Sequencer Watchdog", 20000, "Send data"); end @@ -119,27 +125,27 @@ program test_program; send_data_wd.start(); - env.src_axis_seq.start(); + axis_seq_env.src_axis_agent.sequencer.start(); #1step; case (`SRC_DESCRIPTORS) - 1: //env.src_axis_seq.beat_sent(); - env.src_axis_seq.packet_sent(); - 2: env.src_axis_seq.wait_empty_descriptor_queue(); + 1: //axis_seq_env.src_axis_agent.sequencer.beat_sent(); + axis_seq_env.src_axis_agent.sequencer.packet_sent(); + 2: axis_seq_env.src_axis_agent.sequencer.wait_empty_descriptor_queue(); 3: begin #10us; - env.src_axis_seq.stop(); + axis_seq_env.src_axis_agent.sequencer.stop(); - env.src_axis_seq.packet_sent(); + axis_seq_env.src_axis_agent.sequencer.packet_sent(); end default: ; endcase send_data_wd.stop(); - env.stop(); + base_env.stop(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); diff --git a/testbenches/ip/dma_flock/environment.sv b/testbenches/ip/dma_flock/environment.sv index cdf0ff9d..a0f6d155 100644 --- a/testbenches/ip/dma_flock/environment.sv +++ b/testbenches/ip/dma_flock/environment.sv @@ -34,37 +34,24 @@ // *************************************************************************** `include "utils.svh" +`include "axis_definitions.svh" package environment_pkg; - import axi_vip_pkg::*; + import logger_pkg::*; + import adi_common_pkg::*; + import scoreboard_pkg::*; import axi4stream_vip_pkg::*; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; import m_axis_sequencer_pkg::*; import s_axis_sequencer_pkg::*; - import test_harness_env_pkg::*; - import dma_trans_pkg::*; - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; - import `PKGIFY(test_harness, src_axis_vip)::*; - import `PKGIFY(test_harness, dst_axis_vip)::*; + import adi_axis_agent_pkg::*; - class environment extends test_harness_env; + class dma_flock_environment #(int `AXIS_VIP_PARAM_ORDER(src_axis), int `AXIS_VIP_PARAM_ORDER(dst_axis)) extends adi_environment; // Agents - `AGENT(test_harness, src_axis_vip, mst_t) src_axis_agent; - `AGENT(test_harness, dst_axis_vip, slv_t) dst_axis_agent; - - // Sequencers - m_axis_sequencer #(`AGENT(test_harness, src_axis_vip, mst_t), - `AXIS_VIP_PARAMS(test_harness, src_axis_vip) - ) src_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, dst_axis_vip, slv_t)) dst_axis_seq; - // Register accessors - - dma_transfer_group trans_q[$]; + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(src_axis)) src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(dst_axis)) dst_axis_agent; scoreboard scrb; @@ -74,34 +61,16 @@ package environment_pkg; function new( input string name, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, src_axis_vip)) src_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, dst_axis_vip)) dst_axis_vip_if - ); - super.new(name, - sys_clk_vip_if, - dma_clk_vip_if, - ddr_clk_vip_if, - sys_rst_vip_if, - mng_vip_if, - ddr_vip_if); + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(src_axis)) src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(dst_axis)) dst_axis_vip_if); - // Creating the agents - src_axis_agent = new("Src AXI stream agent", src_axis_vip_if); - dst_axis_agent = new("Dest AXI stream agent", dst_axis_vip_if); + super.new(name); - // Creating the sequencers - src_axis_seq = new("Src AXI stream sequencer", src_axis_agent, this); - dst_axis_seq = new("Dest AXI stream sequencer", dst_axis_agent, this); + // Creating the agents + this.src_axis_agent = new("Src AXI stream agent", src_axis_vip_if, this); + this.dst_axis_agent = new("Dest AXI stream agent", dst_axis_vip_if, this); - scrb = new("Scoreboard", this); + this.scrb = new(); endfunction @@ -111,15 +80,12 @@ package environment_pkg; // - Start the agents //============================================================================ task start(); - super.start(); - scrb.connect( - src_axis_agent.monitor.item_collected_port, - dst_axis_agent.monitor.item_collected_port - ); - - src_axis_agent.start_master(); - dst_axis_agent.start_slave(); + this.scrb.connect( + this.src_axis_agent.agent.monitor.item_collected_port, + this.dst_axis_agent.agent.monitor.item_collected_port); + this.src_axis_agent.agent.start_master(); + this.dst_axis_agent.agent.start_slave(); endtask //============================================================================ @@ -128,27 +94,24 @@ package environment_pkg; // - start the sequencers //============================================================================ task test(); - super.test(); - src_axis_seq.run(); + this.src_axis_agent.sequencer.run(); // DEST AXIS does not have to run, scoreboard connects and // gathers packets from the agent - scrb.run(); - test_c_run(); + this.scrb.run(); endtask //============================================================================ // Post test subroutine //============================================================================ task post_test(); - super.post_test(); // wait until done - scrb.shutdown(); + this.scrb.shutdown(); endtask //============================================================================ // Run subroutine //============================================================================ - task run; + task run(); test(); post_test(); endtask @@ -156,10 +119,9 @@ package environment_pkg; //============================================================================ // Stop subroutine //============================================================================ - task stop; - super.stop(); - src_axis_agent.stop_master(); - dst_axis_agent.stop_slave(); + task stop(); + this.src_axis_agent.agent.stop_master(); + this.dst_axis_agent.agent.stop_slave(); endtask endclass diff --git a/testbenches/ip/dma_flock/scoreboard.sv b/testbenches/ip/dma_flock/scoreboard.sv index e728d0d0..37c3c689 100644 --- a/testbenches/ip/dma_flock/scoreboard.sv +++ b/testbenches/ip/dma_flock/scoreboard.sv @@ -120,7 +120,8 @@ package scoreboard_pkg; end end endtask : run_dst - task shutdown; + + task shutdown(); -> shutdown_event; endtask: shutdown diff --git a/testbenches/ip/dma_flock/tests/test_program.sv b/testbenches/ip/dma_flock/tests/test_program.sv index 18347e63..9d34f74e 100644 --- a/testbenches/ip/dma_flock/tests/test_program.sv +++ b/testbenches/ip/dma_flock/tests/test_program.sv @@ -35,18 +35,28 @@ `include "utils.svh" +import logger_pkg::*; import environment_pkg::*; +import test_harness_env_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; -import logger_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; import dma_trans_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, src_axis_vip)::*; +import `PKGIFY(test_harness, dst_axis_vip)::*; + program test_program; - environment env; + // declare the class instances + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + dma_flock_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis_vip), `AXIS_VIP_PARAMS(test_harness, dst_axis_vip)) dma_flock_env; + // Register accessors dmac_api m_dmac_api; dmac_api s_dmac_api; @@ -58,32 +68,36 @@ program test_program; initial begin //creating environment - env = new("DMA Flock environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SRC_AXIS.inst.IF, - `TH.`DST_AXIS.inst.IF - ); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + dma_flock_env = new("DMA Flock Environment", + `TH.`SRC_AXIS.inst.IF, + `TH.`DST_AXIS.inst.IF); has_sfsync = `M_DMA_CFG_USE_EXT_SYNC; has_dfsync = `S_DMA_CFG_USE_EXT_SYNC; setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + + base_env.start(); + dma_flock_env.start(); + start_clocks(); - env.sys_reset(); - env.run(); - m_dmac_api = new("TX_DMA_BA", env.mng, `TX_DMA_BA); + base_env.sys_reset(); + + dma_flock_env.run(); + + m_dmac_api = new("TX_DMA_BA", base_env.mng.sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA_BA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA_BA", base_env.mng.sequencer, `RX_DMA_BA); s_dmac_api.probe(); sanity_test; @@ -115,8 +129,8 @@ program test_program; .dst_clk( 50000000) ); + base_env.stop(); stop_clocks(); - env.stop(); `INFO(("Testbench done!"), ADI_VERBOSITY_NONE); $finish(); @@ -138,13 +152,13 @@ program test_program; axi_ready_gen wready_gen; // Set no backpressure from AXIS destination - env.dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); - env.dst_axis_seq.user_gen_tready(); + dma_flock_env.dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + dma_flock_env.dst_axis_agent.sequencer.user_gen_tready(); // Set no backpressure from DDR - wready_gen = env.ddr_axi_agent.wr_driver.create_ready("wready"); + wready_gen = base_env.ddr.agent.wr_driver.create_ready("wready"); wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); - env.ddr_axi_agent.wr_driver.send_wready(wready_gen); + base_env.ddr.agent.wr_driver.send_wready(wready_gen); m_seg = new(m_dmac_api.p); rand_succ = m_seg.randomize() with { dst_addr == 0; @@ -160,9 +174,9 @@ program test_program; s_seg = m_seg.toSlaveSeg(); - env.src_axis_seq.set_stop_policy(m_axis_sequencer_pkg::STOP_POLICY_DESCRIPTOR_QUEUE); - env.src_axis_seq.set_data_gen_mode(m_axis_sequencer_pkg::DATA_GEN_MODE_TEST_DATA); - env.src_axis_seq.start(); + dma_flock_env.src_axis_agent.sequencer.set_stop_policy(m_axis_sequencer_pkg::STOP_POLICY_DESCRIPTOR_QUEUE); + dma_flock_env.src_axis_agent.sequencer.set_data_gen_mode(m_axis_sequencer_pkg::DATA_GEN_MODE_TEST_DATA); + dma_flock_env.src_axis_agent.sequencer.start(); m_dmac_api.set_control('b1001); m_dmac_api.set_flags('b111); @@ -191,7 +205,7 @@ program test_program; begin for (int l = 0; l < m_seg.ylength; l++) begin // update the AXIS generator command - env.src_axis_seq.add_xfer_descriptor(.bytes_to_generate(m_seg.length), + dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor(.bytes_to_generate(m_seg.length), .gen_last(1), .gen_sync(l==0)); end @@ -199,7 +213,7 @@ program test_program; // update the AXIS generator data for (int j = 0; j < m_seg.get_bytes_in_transfer; j++) begin // ADI DMA frames start from offset 0x00 - env.src_axis_seq.push_byte_for_stream(frame_count); + dma_flock_env.src_axis_agent.sequencer.push_byte_for_stream(frame_count); end end join @@ -220,7 +234,7 @@ program test_program; sync_gen_en = 0; // Stop triggers wait stop policy - env.src_axis_seq.stop(); + dma_flock_env.src_axis_agent.sequencer.stop(); // Shutdown DMACs m_dmac_api.disable_dma(); @@ -235,16 +249,16 @@ program test_program; bit [63:0] mtestWData; // Write Data bit [31:0] rdData; - env.mng.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); mtestWData = 0; repeat (10) begin - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); - env.mng.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); mtestWData += 4; end - env.mng.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); endtask diff --git a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv index f91b0498..e0508432 100644 --- a/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv +++ b/testbenches/ip/dma_flock/tests/test_program_frame_delay.sv @@ -35,18 +35,28 @@ `include "utils.svh" -import environment_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; +import environment_pkg::*; +import test_harness_env_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; import dma_trans_pkg::*; +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, src_axis_vip)::*; +import `PKGIFY(test_harness, dst_axis_vip)::*; program test_program_frame_delay; - environment env; + // declare the class instances + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + dma_flock_environment #(`AXIS_VIP_PARAMS(test_harness, src_axis_vip), `AXIS_VIP_PARAMS(test_harness, dst_axis_vip)) dma_flock_env; + // Register accessors dmac_api m_dmac_api; dmac_api s_dmac_api; @@ -59,19 +69,19 @@ program test_program_frame_delay; int sync_gen_en; initial begin + //creating environment - env = new("DMA Flock environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SRC_AXIS.inst.IF, - `TH.`DST_AXIS.inst.IF - ); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + dma_flock_env = new("DMA Flock Environment", + `TH.`SRC_AXIS.inst.IF, + `TH.`DST_AXIS.inst.IF); has_sfsync = `M_DMA_CFG_USE_EXT_SYNC; has_dfsync = `S_DMA_CFG_USE_EXT_SYNC; @@ -79,15 +89,20 @@ program test_program_frame_delay; has_s_autorun = `S_DMA_CFG_AUTORUN; setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + + base_env.start(); + dma_flock_env.start(); + start_clocks(); - env.sys_reset(); - env.run(); - m_dmac_api = new("TX_DMA_BA", env.mng, `TX_DMA_BA); + base_env.sys_reset(); + + dma_flock_env.run(); + + m_dmac_api = new("TX_DMA_BA", base_env.mng.sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA_BA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA_BA", base_env.mng.sequencer, `RX_DMA_BA); s_dmac_api.probe(); @@ -145,7 +160,7 @@ program test_program_frame_delay; end stop_clocks(); - env.stop(); + base_env.stop(); `INFO(("Testbench done!"), ADI_VERBOSITY_NONE); $finish(); @@ -169,13 +184,13 @@ program test_program_frame_delay; axi_ready_gen wready_gen; // Set no backpressure from AXIS destination - env.dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); - env.dst_axis_seq.user_gen_tready(); + dma_flock_env.dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + dma_flock_env.dst_axis_agent.sequencer.user_gen_tready(); // Set no backpressure from DDR - wready_gen = env.ddr_axi_agent.wr_driver.create_ready("wready"); + wready_gen = base_env.ddr.agent.wr_driver.create_ready("wready"); wready_gen.set_ready_policy(XIL_AXI_READY_GEN_NO_BACKPRESSURE); - env.ddr_axi_agent.wr_driver.send_wready(wready_gen); + base_env.ddr.agent.wr_driver.send_wready(wready_gen); m_seg = new(m_dmac_api.p); @@ -202,9 +217,9 @@ program test_program_frame_delay; s_seg = m_seg.toSlaveSeg(); - env.src_axis_seq.set_stop_policy(m_axis_sequencer_pkg::STOP_POLICY_DESCRIPTOR_QUEUE); - env.src_axis_seq.set_data_gen_mode(m_axis_sequencer_pkg::DATA_GEN_MODE_TEST_DATA); - env.src_axis_seq.start(); + dma_flock_env.src_axis_agent.sequencer.set_stop_policy(m_axis_sequencer_pkg::STOP_POLICY_DESCRIPTOR_QUEUE); + dma_flock_env.src_axis_agent.sequencer.set_data_gen_mode(m_axis_sequencer_pkg::DATA_GEN_MODE_TEST_DATA); + dma_flock_env.src_axis_agent.sequencer.start(); if (has_autorun == 0) begin m_dmac_api.set_control('b1001); @@ -238,7 +253,7 @@ program test_program_frame_delay; begin for (int l = 0; l < m_seg.ylength; l++) begin // update the AXIS generator command - env.src_axis_seq.add_xfer_descriptor(.bytes_to_generate(m_seg.length), + dma_flock_env.src_axis_agent.sequencer.add_xfer_descriptor(.bytes_to_generate(m_seg.length), .gen_last(1), .gen_sync(l==0)); end @@ -246,7 +261,7 @@ program test_program_frame_delay; // update the AXIS generator data for (int j = 0; j < m_seg.get_bytes_in_transfer; j++) begin // ADI DMA frames start from offset 0x00 - env.src_axis_seq.push_byte_for_stream(frame_count); + dma_flock_env.src_axis_agent.sequencer.push_byte_for_stream(frame_count); end end join @@ -269,7 +284,7 @@ program test_program_frame_delay; sync_gen_en = 0; // Stop triggers wait stop policy - env.src_axis_seq.stop(); + dma_flock_env.src_axis_agent.sequencer.stop(); // Shutdown DMACs if (!has_m_autorun) begin @@ -288,16 +303,16 @@ program test_program_frame_delay; bit [63:0] mtestWData; // Write Data bit [31:0] rdData; - env.mng.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); mtestWData = 0; repeat (10) begin - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); - env.mng.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); + base_env.mng.sequencer.RegReadVerify32(`TX_DMA_BA + GetAddrs(DMAC_SCRATCH), mtestWData); mtestWData += 4; end - env.mng.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); + base_env.mng.sequencer.RegReadVerify32(`RX_DMA_BA + GetAddrs(DMAC_IDENTIFICATION), 'h44_4D_41_43); endtask diff --git a/testbenches/ip/dma_sg/tests/test_program_1d.sv b/testbenches/ip/dma_sg/tests/test_program_1d.sv index 12921e48..e8ef4624 100644 --- a/testbenches/ip/dma_sg/tests/test_program_1d.sv +++ b/testbenches/ip/dma_sg/tests/test_program_1d.sv @@ -37,18 +37,21 @@ // `include "utils.svh" -import test_harness_env_pkg::*; -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; +import test_harness_env_pkg::*; import adi_regmap_pkg::*; import adi_regmap_dmac_pkg::*; import dmac_api_pkg::*; import dma_trans_pkg::*; +import axi_vip_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; program test_program_1d; - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + // Register accessors dmac_api m_dmac_api; dmac_api s_dmac_api; @@ -56,26 +59,24 @@ program test_program_1d; initial begin // Creating environment - env = new("DMA SG Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); + base_env.start(); `TH.`DEVICE_CLK.inst.IF.start_clock(); - env.sys_reset(); + base_env.sys_reset(); - m_dmac_api = new("TX_DMA", env.mng, `TX_DMA_BA); + m_dmac_api = new("TX_DMA", base_env.mng.sequencer, `TX_DMA_BA); m_dmac_api.probe(); - s_dmac_api = new("RX_DMA", env.mng, `RX_DMA_BA); + s_dmac_api = new("RX_DMA", base_env.mng.sequencer, `RX_DMA_BA); s_dmac_api.probe(); #1us; @@ -86,69 +87,69 @@ program test_program_1d; // Init test data with incrementing 16-bit value from 0 up to address 'h8000 for (int i=0;i<'h4000;i=i+2) begin - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(xil_axi_uint'(`DDR_BA+i*2),(((i+1)) << 16) | i ,'hF); end // TX BLOCK // 1st Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0000), .flags(2'b00), .id ('h0123), .src_addr (`DDR_BA+'h0000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_0060), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0000)), .flags(2'b00), .id ('h0123), .src_addr (xil_axi_uint'(`DDR_BA+'h0000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0060)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 2nd Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0030), .flags(2'b00), .id ('h4567), .src_addr (`DDR_BA+'h1000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_0090), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0030)), .flags(2'b00), .id ('h4567), .src_addr (xil_axi_uint'(`DDR_BA+'h1000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0090)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 3rd Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0060), .flags(2'b00), .id ('h89AB), .src_addr (`DDR_BA+'h2000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_0030), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0060)), .flags(2'b00), .id ('h89AB), .src_addr (xil_axi_uint'(`DDR_BA+'h2000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0030)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 4th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0090), .flags(2'b00), .id ('hCDEF), .src_addr (`DDR_BA+'h3000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_00C0), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0090)), .flags(2'b00), .id ('hCDEF), .src_addr (xil_axi_uint'(`DDR_BA+'h3000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_00C0)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 5th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_00C0), .flags(2'b00), .id ('hAABB), .src_addr (`DDR_BA+'h4000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_00F0), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_00C0)), .flags(2'b00), .id ('hAABB), .src_addr (xil_axi_uint'(`DDR_BA+'h4000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_00F0)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 6th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_00F0), .flags(2'b00), .id ('hCCDD), .src_addr (`DDR_BA+'h5000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_0120), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_00F0)), .flags(2'b00), .id ('hCCDD), .src_addr (xil_axi_uint'(`DDR_BA+'h5000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0120)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 7th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0120), .flags(2'b00), .id ('hEEFF), .src_addr (`DDR_BA+'h6000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_0150), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0120)), .flags(2'b00), .id ('hEEFF), .src_addr (xil_axi_uint'(`DDR_BA+'h6000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0150)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 8th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_0150), .flags(2'b11), .id ('h1234), .src_addr (`DDR_BA+'h7000), .dest_addr (0), - .next_desc_addr(`DDR_BA+'h1_FFFF), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_0150)), .flags(2'b11), .id ('h1234), .src_addr (xil_axi_uint'(`DDR_BA+'h7000)), .dest_addr (0), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_FFFF)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // RX BLOCK // 1st Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_1000), .flags(2'b00), .id ('h3210), .src_addr (0), .dest_addr(`DDR_BA+'h8000), - .next_desc_addr(`DDR_BA+'h1_1060), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_1000)), .flags(2'b00), .id ('h3210), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'h8000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_1060)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 2nd Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_1030), .flags(2'b00), .id ('h7654), .src_addr (0), .dest_addr(`DDR_BA+'h9000), - .next_desc_addr(`DDR_BA+'h1_1090), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_1030)), .flags(2'b00), .id ('h7654), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'h9000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_1090)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 3rd Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_1060), .flags(2'b00), .id ('hBA98), .src_addr (0), .dest_addr(`DDR_BA+'hA000), - .next_desc_addr(`DDR_BA+'h1_1030), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_1060)), .flags(2'b00), .id ('hBA98), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'hA000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_1030)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 4th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_1090), .flags(2'b11), .id ('hFEDC), .src_addr (0), .dest_addr(`DDR_BA+'hB000), - .next_desc_addr(`DDR_BA+'h1_FFFF), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_1090)), .flags(2'b11), .id ('hFEDC), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'hB000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_FFFF)), .y_len(0), .x_len('h0FFF), .src_stride(0), .dst_stride(0)); // 5th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_10C0), .flags(2'b00), .id ('hDCDC), .src_addr (0), .dest_addr(`DDR_BA+'hC000), - .next_desc_addr(`DDR_BA+'h1_10F0), .y_len(0), .x_len('h1FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_10C0)), .flags(2'b00), .id ('hDCDC), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'hC000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_10F0)), .y_len(0), .x_len('h1FFF), .src_stride(0), .dst_stride(0)); // 6th Descriptor - write_descriptor(.desc_addr (`DDR_BA+'h1_10F0), .flags(2'b11), .id ('hFEFE), .src_addr (0), .dest_addr(`DDR_BA+'hE000), - .next_desc_addr(`DDR_BA+'h1_FFFF), .y_len(0), .x_len('h1FFF), .src_stride(0), .dst_stride(0)); + write_descriptor(.desc_addr (xil_axi_uint'(`DDR_BA+'h1_10F0)), .flags(2'b11), .id ('hFEFE), .src_addr (0), .dest_addr(xil_axi_uint'(`DDR_BA+'hE000)), + .next_desc_addr(xil_axi_uint'(`DDR_BA+'h1_FFFF)), .y_len(0), .x_len('h1FFF), .src_stride(0), .dst_stride(0)); do_sg_transfer( - .tx_desc_addr(`DDR_BA+'h1_0000), - .rx_desc_addr(`DDR_BA+'h1_1000) + .tx_desc_addr(xil_axi_uint'(`DDR_BA+'h1_0000)), + .rx_desc_addr(xil_axi_uint'(`DDR_BA+'h1_1000)) ); #1us; check_data( - .src_addr(`DDR_BA+'h0000), - .dest_addr(`DDR_BA+'h8000), + .src_addr(xil_axi_uint'(`DDR_BA+'h0000)), + .dest_addr(xil_axi_uint'(`DDR_BA+'h8000)), .length('h8000) ); - env.stop(); + base_env.stop(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); @@ -166,18 +167,18 @@ program test_program_1d; bit [31:0] src_stride, bit [31:0] dst_stride); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h00, flags, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h04, id, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h08, dest_addr, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h0C, 0, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h10, src_addr, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h14, 0, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h18, next_desc_addr, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h1C, 0, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h20, y_len, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h24, x_len, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h28, src_stride, 'hF); - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h2C, dst_stride, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h00, flags, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h04, id, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h08, dest_addr, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h0C, 0, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h10, src_addr, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h14, 0, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h18, next_desc_addr, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h1C, 0, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h20, y_len, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h24, x_len, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h28, src_stride, 'hF); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(desc_addr+'h2C, dst_stride, 'hF); endtask : write_descriptor @@ -187,25 +188,25 @@ program test_program_1d; dma_segment m_seg, s_seg; int m_tid, s_tid; - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), tx_desc_addr); //TX descriptor first address + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC `SET_DMAC_CONTROL_HWDESC(1) | `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr); //RX descriptor first address + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_CONTROL), //Enable DMA and set HWDESC `SET_DMAC_CONTROL_HWDESC(1) | `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_FLAGS), 0); //Disable all flags - env.mng.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'hC0); //RX descriptor first address - env.mng.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_SG_ADDRESS), rx_desc_addr+'hC0); //RX descriptor first address + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); m_dmac_api.transfer_id_get(m_tid); @@ -229,8 +230,8 @@ program test_program_1d; for (int i=0;i> 8*i; - env.sdo_src_seq.push_byte_for_stream(data[i]); + spi_env.sdo_src_seq.push_byte_for_stream(data[i]); end - env.sdo_src_seq.add_xfer_descriptor((`DATA_WIDTH/8),0,0); + spi_env.sdo_src_seq.add_xfer_descriptor((`DATA_WIDTH/8),0,0); `endif endtask @@ -279,14 +291,14 @@ bit [`DATA_DLENGTH-1:0] one_shot_sdo_data [sdo_mem_num-1 :0] = '{default:'0}; task offload_spi_test(); //Configure DMA - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure the Offload module axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); @@ -338,7 +350,7 @@ task offload_spi_test(); end for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin - sdi_read_data[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + sdi_read_data[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); if (sdi_read_data[i] != sdi_read_data_store[i]) begin `INFO(("sdi_read_data[%d]: %x; sdi_read_data_store[%d]: %x", i, sdi_read_data[i], i, sdi_read_data_store[i]), ADI_VERBOSITY_LOW); `ERROR(("Offload Read Test FAILED")); diff --git a/testbenches/ip/spi_engine/tests/test_sleep_delay.sv b/testbenches/ip/spi_engine/tests/test_sleep_delay.sv index 1206ffc2..3dee7d3e 100644 --- a/testbenches/ip/spi_engine/tests/test_sleep_delay.sv +++ b/testbenches/ip/spi_engine/tests/test_sleep_delay.sv @@ -34,18 +34,23 @@ // *************************************************************************** `include "utils.svh" +`include "axi_definitions.svh" -import axi_vip_pkg::*; +import logger_pkg::*; +import test_harness_env_pkg::*; +import spi_environment_pkg::*; import axi4stream_vip_pkg::*; import adi_regmap_pkg::*; import adi_regmap_clkgen_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; import adi_regmap_spi_engine_pkg::*; -import logger_pkg::*; -import spi_environment_pkg::*; import spi_engine_instr_pkg::*; import adi_spi_vip_pkg::*; +import axi_vip_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; //--------------------------------------------------------------------------- // SPI Engine configuration parameters @@ -64,7 +69,9 @@ program test_sleep_delay ( timeunit 1ns; timeprecision 100ps; -spi_environment env; +// declare the class instances +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +spi_environment spi_env; // -------------------------- // Wrapper function for AXI read verify @@ -72,13 +79,13 @@ spi_environment env; task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -87,7 +94,7 @@ endtask task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -95,7 +102,7 @@ endtask // -------------------------- task spi_receive( output [`DATA_DLENGTH:0] data); - env.spi_seq.receive_data(data); + spi_env.spi_seq.receive_data(data); endtask // -------------------------- @@ -103,14 +110,14 @@ endtask // -------------------------- task spi_send( input [`DATA_DLENGTH:0] data); - env.spi_seq.send_data(data); + spi_env.spi_seq.send_data(data); endtask // -------------------------- // Wrapper function for waiting for all SPI // -------------------------- task spi_wait_send(); - env.spi_seq.flush_send(); + spi_env.spi_seq.flush_send(); endtask // -------------------------- @@ -119,32 +126,36 @@ endtask initial begin //creating environment - env = new("SPI Engine Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `ifdef DEF_SDO_STREAMING - `TH.`SDO_SRC.inst.IF, - `endif - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SPI_S.inst.IF - ); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + spi_env = new("SPI Engine Environment", + `ifdef DEF_SDO_STREAMING + `TH.`SDO_SRC.inst.IF, + `endif + `TH.`SPI_S.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.configure(); - env.sys_reset(); + base_env.start(); + spi_env.start(); + + base_env.sys_reset(); + + spi_env.configure(); - env.run(); + spi_env.run(); - env.spi_seq.set_default_miso_data('h2AA55); + spi_env.spi_seq.set_default_miso_data('h2AA55); // start sdo source (will wait for data enqueued) `ifdef DEF_SDO_STREAMING - env.sdo_src_seq.start(); + spi_env.sdo_src_seq.start(); `endif sanity_test(); @@ -155,7 +166,8 @@ initial begin cs_delay_test(3,3); - env.stop(); + spi_env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); @@ -373,14 +385,14 @@ task cs_delay_test( `INFO(("axi_pwm_gen started."), ADI_VERBOSITY_LOW); //Configure DMA - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Enable SPI Engine axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); @@ -429,7 +441,7 @@ task cs_delay_test( #2000ns for (int i=0; i<=(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS); i=i+1) begin - offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); end if (irq_pending == 'h0) begin @@ -455,7 +467,7 @@ task cs_delay_test( `INFO(("CS Delay Test PASSED"), ADI_VERBOSITY_LOW); #2000ns - env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(1)); axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(0)); @@ -489,7 +501,7 @@ task cs_delay_test( #2000ns for (int i=0; i<=((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1); i=i+1) begin - offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i][`DATA_DLENGTH-1:0] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); end if (irq_pending == 'h0) begin diff --git a/testbenches/ip/util_pack/environment.sv b/testbenches/ip/util_pack/environment.sv index 5543cd5f..49686ad5 100644 --- a/testbenches/ip/util_pack/environment.sv +++ b/testbenches/ip/util_pack/environment.sv @@ -2,48 +2,25 @@ package environment_pkg; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; - import m_axis_sequencer_pkg::*; - import s_axis_sequencer_pkg::*; import logger_pkg::*; + import adi_common_pkg::*; - import axi_vip_pkg::*; import axi4stream_vip_pkg::*; - import test_harness_env_pkg::*; + import m_axis_sequencer_pkg::*; + import s_axis_sequencer_pkg::*; + import adi_axis_agent_pkg::*; import scoreboard_pack_pkg::*; - import x_monitor_pkg::*; - - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; - import `PKGIFY(test_harness, tx_src_axis)::*; - import `PKGIFY(test_harness, tx_dst_axis)::*; - import `PKGIFY(test_harness, rx_src_axis)::*; - import `PKGIFY(test_harness, rx_dst_axis)::*; - - class environment extends test_harness_env; + class util_pack_environment #(int `AXIS_VIP_PARAM_ORDER(tx_src_axis), int `AXIS_VIP_PARAM_ORDER(tx_dst_axis), int `AXIS_VIP_PARAM_ORDER(rx_src_axis), int `AXIS_VIP_PARAM_ORDER(rx_dst_axis)) extends adi_environment; // agents and sequencers - `AGENT(test_harness, tx_src_axis, mst_t) tx_src_axis_agent; - `AGENT(test_harness, tx_dst_axis, slv_t) tx_dst_axis_agent; - `AGENT(test_harness, rx_src_axis, mst_t) rx_src_axis_agent; - `AGENT(test_harness, rx_dst_axis, slv_t) rx_dst_axis_agent; + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(tx_src_axis)) tx_src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(tx_dst_axis)) tx_dst_axis_agent; + adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(rx_src_axis)) rx_src_axis_agent; + adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(rx_dst_axis)) rx_dst_axis_agent; - m_axis_sequencer #(`AGENT(test_harness, tx_src_axis, mst_t), - `AXIS_VIP_PARAMS(test_harness, tx_src_axis)) tx_src_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, tx_dst_axis, slv_t)) tx_dst_axis_seq; - m_axis_sequencer #(`AGENT(test_harness, rx_src_axis, mst_t), - `AXIS_VIP_PARAMS(test_harness, rx_src_axis)) rx_src_axis_seq; - s_axis_sequencer #(`AGENT(test_harness, rx_dst_axis, slv_t)) rx_dst_axis_seq; - - x_axis_monitor #(`AGENT(test_harness, tx_src_axis, mst_t)) tx_src_axis_mon; - x_axis_monitor #(`AGENT(test_harness, tx_dst_axis, slv_t)) tx_dst_axis_mon; - x_axis_monitor #(`AGENT(test_harness, rx_src_axis, mst_t)) rx_src_axis_mon; - x_axis_monitor #(`AGENT(test_harness, rx_dst_axis, slv_t)) rx_dst_axis_mon; - - scoreboard_pack scoreboard_tx; - scoreboard_pack scoreboard_rx; + scoreboard_pack #(logic [7:0]) scoreboard_tx; + scoreboard_pack #(logic [7:0]) scoreboard_rx; //============================================================================ // Constructor @@ -51,48 +28,21 @@ package environment_pkg; function new ( input string name, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, - - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, tx_src_axis)) tx_src_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, tx_dst_axis)) tx_dst_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, rx_src_axis)) rx_src_axis_vip_if, - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, rx_dst_axis)) rx_dst_axis_vip_if - ); + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(tx_src_axis)) tx_src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(tx_dst_axis)) tx_dst_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(rx_src_axis)) rx_src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(rx_dst_axis)) rx_dst_axis_vip_if); // creating the agents - super.new(name, - sys_clk_vip_if, - dma_clk_vip_if, - ddr_clk_vip_if, - sys_rst_vip_if, - mng_vip_if, - ddr_vip_if); - - tx_src_axis_agent = new("TX Source AXI Stream Agent", tx_src_axis_vip_if); - tx_dst_axis_agent = new("TX Destination AXI Stream Agent", tx_dst_axis_vip_if); - rx_src_axis_agent = new("RX Source AXI Stream Agent", rx_src_axis_vip_if); - rx_dst_axis_agent = new("RX Destination AXI Stream Agent", rx_dst_axis_vip_if); - - tx_src_axis_seq = new("TX Source AXI Stream Agent", tx_src_axis_agent, this); - tx_dst_axis_seq = new("TX Destination AXI Stream Agent", tx_dst_axis_agent, this); - rx_src_axis_seq = new("RX Source AXI Stream Agent", rx_src_axis_agent, this); - rx_dst_axis_seq = new("RX Destination AXI Stream Agent", rx_dst_axis_agent, this); - - tx_src_axis_mon = new("TX Source AXIS Transaction Monitor", tx_src_axis_agent, this); - tx_dst_axis_mon = new("TX Destination AXIS Transaction Monitor", tx_dst_axis_agent, this); - rx_src_axis_mon = new("RX Source AXIS Transaction Monitor", rx_src_axis_agent, this); - rx_dst_axis_mon = new("RX Destination AXIS Transaction Monitor", rx_dst_axis_agent, this); - - scoreboard_tx = new("TX Scoreboard", `CHANNELS, `SAMPLES, `WIDTH, CPACK, this); - scoreboard_rx = new("RX Scoreboard", `CHANNELS, `SAMPLES, `WIDTH, UPACK, this); + super.new(name); + + this.tx_src_axis_agent = new("TX Source AXI Stream Agent", tx_src_axis_vip_if, this); + this.tx_dst_axis_agent = new("TX Destination AXI Stream Agent", tx_dst_axis_vip_if, this); + this.rx_src_axis_agent = new("RX Source AXI Stream Agent", rx_src_axis_vip_if, this); + this.rx_dst_axis_agent = new("RX Destination AXI Stream Agent", rx_dst_axis_vip_if, this); + this.scoreboard_tx = new("TX Scoreboard", `CHANNELS, `SAMPLES, `WIDTH, CPACK, this); + this.scoreboard_rx = new("RX Scoreboard", `CHANNELS, `SAMPLES, `WIDTH, UPACK, this); endfunction //============================================================================ @@ -100,19 +50,17 @@ package environment_pkg; // - Configure the sequencer VIPs with an initial configuration before starting them //============================================================================ task configure(int bytes_to_generate); - // TX stubs - tx_src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - tx_src_axis_seq.add_xfer_descriptor(bytes_to_generate, 0, 0); + this.tx_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + this.tx_src_axis_agent.sequencer.add_xfer_descriptor(bytes_to_generate, 0, 0); - tx_dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + this.tx_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); // RX stub - rx_src_axis_seq.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); - rx_src_axis_seq.add_xfer_descriptor(bytes_to_generate, 0, 0); - - rx_dst_axis_seq.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); + this.rx_src_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR); + this.rx_src_axis_agent.sequencer.add_xfer_descriptor(bytes_to_generate, 0, 0); + this.rx_dst_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE); endtask //============================================================================ @@ -121,83 +69,44 @@ package environment_pkg; // - Start the agents //============================================================================ task start(); + this.tx_src_axis_agent.agent.start_master(); + this.tx_dst_axis_agent.agent.start_slave(); + this.rx_src_axis_agent.agent.start_master(); + this.rx_dst_axis_agent.agent.start_slave(); - super.start(); - - tx_src_axis_agent.start_master(); - tx_dst_axis_agent.start_slave(); - rx_src_axis_agent.start_master(); - rx_dst_axis_agent.start_slave(); - - scoreboard_tx.set_source_stream(tx_src_axis_mon); - scoreboard_tx.set_sink_stream(tx_dst_axis_mon); - - scoreboard_rx.set_source_stream(rx_src_axis_mon); - scoreboard_rx.set_sink_stream(rx_dst_axis_mon); - - endtask - - //============================================================================ - // Start the test - // - start the RX scoreboard and sequencer - // - start the TX scoreboard and sequencer - // - setup the RX DMA - // - setup the TX DMA - //============================================================================ - task test(); - - fork - tx_src_axis_seq.run(); - tx_dst_axis_seq.run(); - rx_src_axis_seq.run(); - rx_dst_axis_seq.run(); - - tx_src_axis_mon.run(); - tx_dst_axis_mon.run(); - rx_src_axis_mon.run(); - rx_dst_axis_mon.run(); - - scoreboard_tx.run(); - scoreboard_rx.run(); - join_none + this.tx_src_axis_agent.monitor.publisher.subscribe(this.scoreboard_tx.subscriber_source); + this.tx_dst_axis_agent.monitor.publisher.subscribe(this.scoreboard_tx.subscriber_sink); - endtask - - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - // Evaluate the scoreboard's results + this.rx_src_axis_agent.monitor.publisher.subscribe(this.scoreboard_rx.subscriber_source); + this.rx_dst_axis_agent.monitor.publisher.subscribe(this.scoreboard_rx.subscriber_sink); endtask //============================================================================ // Run subroutine //============================================================================ - task run; - - //pre_test(); - test(); + task run(); + fork + this.tx_src_axis_agent.sequencer.run(); + this.tx_dst_axis_agent.sequencer.run(); + this.rx_src_axis_agent.sequencer.run(); + this.rx_dst_axis_agent.sequencer.run(); + this.scoreboard_tx.run(); + this.scoreboard_rx.run(); + join_none endtask //============================================================================ // Stop subroutine //============================================================================ - task stop; - - super.stop(); - - tx_src_axis_seq.stop(); - rx_src_axis_seq.stop(); - - tx_src_axis_agent.stop_master(); - tx_dst_axis_agent.stop_slave(); - rx_src_axis_agent.stop_master(); - rx_dst_axis_agent.stop_slave(); - - post_test(); - + task stop(); + this.tx_src_axis_agent.sequencer.stop(); + this.rx_src_axis_agent.sequencer.stop(); + + this.tx_src_axis_agent.agent.stop_master(); + this.tx_dst_axis_agent.agent.stop_slave(); + this.rx_src_axis_agent.agent.stop_master(); + this.rx_dst_axis_agent.agent.stop_slave(); endtask endclass diff --git a/testbenches/ip/util_pack/tests/test_program.sv b/testbenches/ip/util_pack/tests/test_program.sv index 8562e7e9..9e2ae2af 100644 --- a/testbenches/ip/util_pack/tests/test_program.sv +++ b/testbenches/ip/util_pack/tests/test_program.sv @@ -36,18 +36,28 @@ // // `include "utils.svh" +`include "axi_definitions.svh" +`include "axis_definitions.svh" -import axi_vip_pkg::*; -import axi4stream_vip_pkg::*; import logger_pkg::*; +import test_harness_env_pkg::*; import environment_pkg::*; import dmac_api_pkg::*; import watchdog_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +import `PKGIFY(test_harness, tx_src_axis)::*; +import `PKGIFY(test_harness, tx_dst_axis)::*; +import `PKGIFY(test_harness, rx_src_axis)::*; +import `PKGIFY(test_harness, rx_dst_axis)::*; + program test_program; // declare the class instances - environment env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + util_pack_environment #(`AXIS_VIP_PARAMS(test_harness, tx_src_axis), `AXIS_VIP_PARAMS(test_harness, tx_dst_axis), `AXIS_VIP_PARAMS(test_harness, rx_src_axis), `AXIS_VIP_PARAMS(test_harness, rx_dst_axis)) pack_env; watchdog packer_scoreboard_wd; @@ -61,35 +71,37 @@ program test_program; setLoggerVerbosity(ADI_VERBOSITY_NONE); // create environment - env = new("Util Pack Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - - `TH.`TX_SRC_AXIS.inst.IF, - `TH.`TX_DST_AXIS.inst.IF, - `TH.`RX_SRC_AXIS.inst.IF, - `TH.`RX_DST_AXIS.inst.IF - ); - - dmac_tx = new("DMAC TX 0", env.mng, `TX_DMA_BA); - dmac_rx = new("DMAC RX 0", env.mng, `RX_DMA_BA); - - env.start(); - env.sys_reset(); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + pack_env = new("Util Pack Environment", + `TH.`TX_SRC_AXIS.inst.IF, + `TH.`TX_DST_AXIS.inst.IF, + `TH.`RX_SRC_AXIS.inst.IF, + `TH.`RX_DST_AXIS.inst.IF); + + dmac_tx = new("DMAC TX 0", base_env.mng.sequencer, `TX_DMA_BA); + dmac_rx = new("DMAC RX 0", base_env.mng.sequencer, `RX_DMA_BA); + + base_env.start(); + pack_env.start(); + + base_env.sys_reset(); // configure environment sequencers - env.configure(data_length); + pack_env.configure(data_length); `INFO(("Bring up IPs from reset."), ADI_VERBOSITY_LOW); systemBringUp(); // Start the ADC/DAC stubs `INFO(("Call the run() ..."), ADI_VERBOSITY_LOW); - env.run(); + pack_env.run(); // Generate DMA transfers `INFO(("Start DMAs"), ADI_VERBOSITY_LOW); @@ -97,8 +109,8 @@ program test_program; tx_dma_transfer(data_length); // start generating data - env.tx_src_axis_seq.start(); - env.rx_src_axis_seq.start(); + pack_env.tx_src_axis_agent.sequencer.start(); + pack_env.rx_src_axis_agent.sequencer.start(); // prepare watchdog with 20 us of wait time packer_scoreboard_wd = new("Packer watchdog", 20000, "Packers Scoreboard"); @@ -108,13 +120,14 @@ program test_program; // wait for scoreboards to finish fork - env.scoreboard_rx.wait_until_complete(); - env.scoreboard_tx.wait_until_complete(); + pack_env.scoreboard_rx.wait_until_complete(); + pack_env.scoreboard_tx.wait_until_complete(); join packer_scoreboard_wd.stop(); - env.stop(); + pack_env.stop(); + base_env.stop(); `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); $finish(); @@ -122,12 +135,10 @@ program test_program; end task systemBringUp(); - `INFO(("Bring up RX DMAC 0"), ADI_VERBOSITY_LOW); dmac_rx.enable_dma(); `INFO(("Bring up TX DMAC 0"), ADI_VERBOSITY_LOW); dmac_tx.enable_dma(); - endtask // RX DMA transfer generator From 39147159fc9c28eaa5085c8db8b6e9f5ebcb40aa Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 20 Jan 2025 09:36:17 +0200 Subject: [PATCH 08/13] infrastructure refactorization: IP level updates - Fixed SPI engine environment - Updated environment creation and macros Signed-off-by: Istvan-Zsolt Szekely --- library/vip/amd/axi/axi_definitions.svh | 67 +++++++++++++------ library/vip/amd/axi/m_axi_sequencer.sv | 6 +- library/vip/amd/axi/s_axi_sequencer.sv | 6 +- library/vip/amd/axis/adi_axis_agent.sv | 6 +- library/vip/amd/axis/adi_axis_monitor.sv | 6 +- library/vip/amd/axis/axis_definitions.svh | 42 ++++++------ library/vip/amd/axis/m_axis_sequencer.sv | 2 +- library/vip/amd/axis/s_axis_sequencer.sv | 2 +- testbenches/ip/axis_sequencers/environment.sv | 2 +- testbenches/ip/dma_flock/environment.sv | 2 +- testbenches/ip/scoreboard/environment.sv | 2 +- testbenches/ip/spi_engine/spi_environment.sv | 30 ++++----- testbenches/ip/util_pack/environment.sv | 2 +- 13 files changed, 98 insertions(+), 77 deletions(-) diff --git a/library/vip/amd/axi/axi_definitions.svh b/library/vip/amd/axi/axi_definitions.svh index 98576d16..93f026e5 100644 --- a/library/vip/amd/axi/axi_definitions.svh +++ b/library/vip/amd/axi/axi_definitions.svh @@ -40,28 +40,28 @@ `define _AXI_DEFINITIONS_SVH_ // Help build VIP Interface parameters name -`define AXI_VIP_IF_PARAMS(n) n``_VIP_PROTOCOL,\ - n``_VIP_ADDR_WIDTH,\ - n``_VIP_WDATA_WIDTH,\ - n``_VIP_RDATA_WIDTH,\ - n``_VIP_WID_WIDTH,\ - n``_VIP_RID_WIDTH,\ - n``_VIP_AWUSER_WIDTH,\ - n``_VIP_WUSER_WIDTH,\ - n``_VIP_BUSER_WIDTH,\ - n``_VIP_ARUSER_WIDTH,\ - n``_VIP_RUSER_WIDTH,\ - n``_VIP_SUPPORTS_NARROW,\ - n``_VIP_HAS_BURST,\ - n``_VIP_HAS_LOCK,\ - n``_VIP_HAS_CACHE,\ - n``_VIP_HAS_REGION,\ - n``_VIP_HAS_PROT,\ - n``_VIP_HAS_QOS,\ - n``_VIP_HAS_WSTRB,\ - n``_VIP_HAS_BRESP,\ - n``_VIP_HAS_RRESP,\ - n``_VIP_HAS_ARESETN +`define AXI_VIP_PARAM_DECL(n) int n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN `define AXI_VIP_PARAM_ORDER(n) n``_VIP_PROTOCOL,\ n``_VIP_ADDR_WIDTH,\ @@ -85,6 +85,29 @@ n``_VIP_HAS_BRESP,\ n``_VIP_HAS_RRESP,\ n``_VIP_HAS_ARESETN + +`define AXI_VIP_IF_PARAMS(n) n``_VIP_PROTOCOL,\ + n``_VIP_ADDR_WIDTH,\ + n``_VIP_WDATA_WIDTH,\ + n``_VIP_RDATA_WIDTH,\ + n``_VIP_WID_WIDTH,\ + n``_VIP_RID_WIDTH,\ + n``_VIP_AWUSER_WIDTH,\ + n``_VIP_WUSER_WIDTH,\ + n``_VIP_BUSER_WIDTH,\ + n``_VIP_ARUSER_WIDTH,\ + n``_VIP_RUSER_WIDTH,\ + n``_VIP_SUPPORTS_NARROW,\ + n``_VIP_HAS_BURST,\ + n``_VIP_HAS_LOCK,\ + n``_VIP_HAS_CACHE,\ + n``_VIP_HAS_REGION,\ + n``_VIP_HAS_PROT,\ + n``_VIP_HAS_QOS,\ + n``_VIP_HAS_WSTRB,\ + n``_VIP_HAS_BRESP,\ + n``_VIP_HAS_RRESP,\ + n``_VIP_HAS_ARESETN `define AXI_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_PROTOCOL,\ th``_``vip``_0_VIP_ADDR_WIDTH,\ diff --git a/library/vip/amd/axi/m_axi_sequencer.sv b/library/vip/amd/axi/m_axi_sequencer.sv index c786d5ee..f6db767e 100644 --- a/library/vip/amd/axi/m_axi_sequencer.sv +++ b/library/vip/amd/axi/m_axi_sequencer.sv @@ -43,16 +43,16 @@ package m_axi_sequencer_pkg; import adi_common_pkg::*; import reg_accessor_pkg::*; - class m_axi_sequencer #(int `AXI_VIP_PARAM_ORDER(m)) extends reg_accessor; + class m_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends reg_accessor; - axi_mst_agent #(`AXI_VIP_PARAM_ORDER(m)) agent; + axi_mst_agent #(`AXI_VIP_PARAM_ORDER(AXI)) agent; semaphore reader_s; semaphore writer_s; function new( input string name, - input axi_mst_agent #(`AXI_VIP_PARAM_ORDER(m)) agent, + input axi_mst_agent #(`AXI_VIP_PARAM_ORDER(AXI)) agent, input adi_agent parent = null); super.new(name, parent); diff --git a/library/vip/amd/axi/s_axi_sequencer.sv b/library/vip/amd/axi/s_axi_sequencer.sv index c09f2f5d..1e1ab9e3 100644 --- a/library/vip/amd/axi/s_axi_sequencer.sv +++ b/library/vip/amd/axi/s_axi_sequencer.sv @@ -42,13 +42,13 @@ package s_axi_sequencer_pkg; import adi_common_pkg::*; import logger_pkg::*; - class s_axi_sequencer #(int `AXI_VIP_PARAM_ORDER(s)) extends adi_component; + class s_axi_sequencer #(`AXI_VIP_PARAM_DECL(AXI)) extends adi_component; - xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(s)) mem_model; + xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(AXI)) mem_model; function new( input string name, - input xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(s)) mem_model, + input xil_axi_slv_mem_model #(`AXI_VIP_PARAM_ORDER(AXI)) mem_model, input adi_agent parent = null); super.new(name, parent); diff --git a/library/vip/amd/axis/adi_axis_agent.sv b/library/vip/amd/axis/adi_axis_agent.sv index 392b79e5..621ff43f 100644 --- a/library/vip/amd/axis/adi_axis_agent.sv +++ b/library/vip/amd/axis/adi_axis_agent.sv @@ -46,7 +46,7 @@ package adi_axis_agent_pkg; import adi_axis_monitor_pkg::*; - class adi_axis_master_agent #(int `AXIS_VIP_PARAM_ORDER(master)) extends adi_agent; + class adi_axis_master_agent #(`AXIS_VIP_PARAM_DECL(master)) extends adi_agent; axi4stream_mst_agent #(`AXIS_VIP_IF_PARAMS(master)) agent; m_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(master)) sequencer; @@ -67,7 +67,7 @@ package adi_axis_agent_pkg; endclass: adi_axis_master_agent - class adi_axis_slave_agent #(int `AXIS_VIP_PARAM_ORDER(slave)) extends adi_agent; + class adi_axis_slave_agent #(`AXIS_VIP_PARAM_DECL(slave)) extends adi_agent; axi4stream_slv_agent #(`AXIS_VIP_IF_PARAMS(slave)) agent; s_axis_sequencer #(`AXIS_VIP_PARAM_ORDER(slave)) sequencer; @@ -88,7 +88,7 @@ package adi_axis_agent_pkg; endclass: adi_axis_slave_agent - class adi_axis_passthrough_mem_agent #(int `AXIS_VIP_PARAM_ORDER(passthrough)) extends adi_agent; + class adi_axis_passthrough_mem_agent #(`AXIS_VIP_PARAM_DECL(passthrough)) extends adi_agent; axi4stream_passthrough_agent #(`AXIS_VIP_IF_PARAMS(passthrough)) agent; adi_axis_monitor #(`AXIS_VIP_PARAM_ORDER(passthrough)) monitor; diff --git a/library/vip/amd/axis/adi_axis_monitor.sv b/library/vip/amd/axis/adi_axis_monitor.sv index b13849cb..e2a4ba55 100644 --- a/library/vip/amd/axis/adi_axis_monitor.sv +++ b/library/vip/amd/axis/adi_axis_monitor.sv @@ -7,10 +7,10 @@ package adi_axis_monitor_pkg; import adi_common_pkg::*; import pub_sub_pkg::*; - class adi_axis_monitor #(int `AXIS_VIP_PARAM_ORDER(axis)) extends adi_monitor; + class adi_axis_monitor #(`AXIS_VIP_PARAM_DECL(AXIS)) extends adi_monitor; // analysis port from the monitor - protected axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor; + protected axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(AXIS)) monitor; adi_publisher #(logic [7:0]) publisher; @@ -19,7 +19,7 @@ package adi_axis_monitor_pkg; // constructor function new( input string name, - input axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(axis)) monitor, + input axi4stream_monitor #(`AXIS_VIP_IF_PARAMS(AXIS)) monitor, input adi_agent parent = null); super.new(name, parent); diff --git a/library/vip/amd/axis/axis_definitions.svh b/library/vip/amd/axis/axis_definitions.svh index 1db18ff1..ed98435c 100644 --- a/library/vip/amd/axis/axis_definitions.svh +++ b/library/vip/amd/axis/axis_definitions.svh @@ -40,19 +40,19 @@ `define _AXIS_DEFINITIONS_SVH_ // Help build VIP Interface parameters name -`define AXIS_VIP_PARAM_DECL AXIS_VIP_INTERFACE_MODE = 2,\ - AXIS_VIP_SIGNAL_SET = 8'b00000011,\ - AXIS_VIP_DATA_WIDTH = 8,\ - AXIS_VIP_ID_WIDTH = 0,\ - AXIS_VIP_DEST_WIDTH = 0,\ - AXIS_VIP_USER_WIDTH = 0,\ - AXIS_VIP_USER_BITS_PER_BYTE = 0,\ - AXIS_VIP_HAS_TREADY = 1,\ - AXIS_VIP_HAS_TSTRB = 0,\ - AXIS_VIP_HAS_TKEEP = 0,\ - AXIS_VIP_HAS_TLAST = 0,\ - AXIS_VIP_HAS_ACLKEN = 0,\ - AXIS_VIP_HAS_ARESETN = 1 +`define AXIS_VIP_PARAM_DECL(n) int n``_VIP_INTERFACE_MODE, \ + n``_VIP_SIGNAL_SET, \ + n``_VIP_DATA_WIDTH, \ + n``_VIP_ID_WIDTH, \ + n``_VIP_DEST_WIDTH, \ + n``_VIP_USER_WIDTH, \ + n``_VIP_USER_BITS_PER_BYTE, \ + n``_VIP_HAS_TREADY, \ + n``_VIP_HAS_TSTRB, \ + n``_VIP_HAS_TKEEP, \ + n``_VIP_HAS_TLAST, \ + n``_VIP_HAS_ACLKEN, \ + n``_VIP_HAS_ARESETN `define AXIS_VIP_PARAM_ORDER(n) n``_VIP_INTERFACE_MODE,\ n``_VIP_SIGNAL_SET,\ @@ -68,6 +68,14 @@ n``_VIP_HAS_ACLKEN,\ n``_VIP_HAS_ARESETN +`define AXIS_VIP_IF_PARAMS(n) n``_VIP_SIGNAL_SET,\ + n``_VIP_DEST_WIDTH,\ + n``_VIP_DATA_WIDTH,\ + n``_VIP_ID_WIDTH,\ + n``_VIP_USER_WIDTH,\ + n``_VIP_USER_BITS_PER_BYTE,\ + n``_VIP_HAS_ARESETN + `define AXIS_VIP_PARAMS(th,vip) th``_``vip``_0_VIP_INTERFACE_MODE,\ th``_``vip``_0_VIP_SIGNAL_SET,\ th``_``vip``_0_VIP_DATA_WIDTH,\ @@ -82,12 +90,4 @@ th``_``vip``_0_VIP_HAS_ACLKEN,\ th``_``vip``_0_VIP_HAS_ARESETN -`define AXIS_VIP_IF_PARAMS(n) n``_VIP_SIGNAL_SET,\ - n``_VIP_DEST_WIDTH,\ - n``_VIP_DATA_WIDTH,\ - n``_VIP_ID_WIDTH,\ - n``_VIP_USER_WIDTH,\ - n``_VIP_USER_BITS_PER_BYTE,\ - n``_VIP_HAS_ARESETN - `endif diff --git a/library/vip/amd/axis/m_axis_sequencer.sv b/library/vip/amd/axis/m_axis_sequencer.sv index 8bf3c429..8a3155ef 100644 --- a/library/vip/amd/axis/m_axis_sequencer.sv +++ b/library/vip/amd/axis/m_axis_sequencer.sv @@ -312,7 +312,7 @@ package m_axis_sequencer_pkg; endclass: m_axis_sequencer_base - class m_axis_sequencer #(int `AXIS_VIP_PARAM_ORDER(AXIS)) extends m_axis_sequencer_base; + class m_axis_sequencer #(`AXIS_VIP_PARAM_DECL(AXIS)) extends m_axis_sequencer_base; protected axi4stream_mst_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver; diff --git a/library/vip/amd/axis/s_axis_sequencer.sv b/library/vip/amd/axis/s_axis_sequencer.sv index 26e229b7..6f566641 100644 --- a/library/vip/amd/axis/s_axis_sequencer.sv +++ b/library/vip/amd/axis/s_axis_sequencer.sv @@ -158,7 +158,7 @@ package s_axis_sequencer_pkg; endclass: s_axis_sequencer_base - class s_axis_sequencer #(int `AXIS_VIP_PARAM_ORDER(AXIS)) extends s_axis_sequencer_base; + class s_axis_sequencer #(`AXIS_VIP_PARAM_DECL(AXIS)) extends s_axis_sequencer_base; protected axi4stream_slv_driver #(`AXIS_VIP_IF_PARAMS(AXIS)) driver; diff --git a/testbenches/ip/axis_sequencers/environment.sv b/testbenches/ip/axis_sequencers/environment.sv index 423e8b63..4007dcc4 100644 --- a/testbenches/ip/axis_sequencers/environment.sv +++ b/testbenches/ip/axis_sequencers/environment.sv @@ -11,7 +11,7 @@ package environment_pkg; import s_axis_sequencer_pkg::*; import adi_axis_agent_pkg::*; - class axis_sequencer_environment #(int `AXIS_VIP_PARAM_ORDER(src_axis), int `AXIS_VIP_PARAM_ORDER(dst_axis)) extends adi_environment; + class axis_sequencer_environment #(`AXIS_VIP_PARAM_DECL(src_axis), `AXIS_VIP_PARAM_DECL(dst_axis)) extends adi_environment; // Agents adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(src_axis)) src_axis_agent; diff --git a/testbenches/ip/dma_flock/environment.sv b/testbenches/ip/dma_flock/environment.sv index a0f6d155..cac44346 100644 --- a/testbenches/ip/dma_flock/environment.sv +++ b/testbenches/ip/dma_flock/environment.sv @@ -47,7 +47,7 @@ package environment_pkg; import s_axis_sequencer_pkg::*; import adi_axis_agent_pkg::*; - class dma_flock_environment #(int `AXIS_VIP_PARAM_ORDER(src_axis), int `AXIS_VIP_PARAM_ORDER(dst_axis)) extends adi_environment; + class dma_flock_environment #(`AXIS_VIP_PARAM_DECL(src_axis), `AXIS_VIP_PARAM_DECL(dst_axis)) extends adi_environment; // Agents adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(src_axis)) src_axis_agent; diff --git a/testbenches/ip/scoreboard/environment.sv b/testbenches/ip/scoreboard/environment.sv index 515d5b1d..8efbe384 100644 --- a/testbenches/ip/scoreboard/environment.sv +++ b/testbenches/ip/scoreboard/environment.sv @@ -18,7 +18,7 @@ package environment_pkg; import scoreboard_pkg::*; - class scoreboard_environment #(int `AXIS_VIP_PARAM_ORDER(adc_src), int `AXIS_VIP_PARAM_ORDER(dac_dst), int `AXI_VIP_PARAM_ORDER(adc_dst_pt), int `AXI_VIP_PARAM_ORDER(dac_src_pt)) extends adi_environment; + class scoreboard_environment #(`AXIS_VIP_PARAM_DECL(adc_src), `AXIS_VIP_PARAM_DECL(dac_dst), `AXIS_VIP_PARAM_DECL(adc_dst_pt), `AXIS_VIP_PARAM_DECL(dac_src_pt)) extends adi_environment; // Agents adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(adc_src)) adc_src_axis_agent; diff --git a/testbenches/ip/spi_engine/spi_environment.sv b/testbenches/ip/spi_engine/spi_environment.sv index e93a3c99..76f17bd3 100644 --- a/testbenches/ip/spi_engine/spi_environment.sv +++ b/testbenches/ip/spi_engine/spi_environment.sv @@ -62,9 +62,7 @@ package spi_environment_pkg; // Sequencers s_spi_sequencer #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_seq; `ifdef DEF_SDO_STREAMING - m_axis_sequencer #(`AGENT(test_harness, sdo_src, mst_t), - `AXIS_VIP_PARAMS(test_harness, sdo_src) - ) sdo_src_seq; + m_axis_sequencer #(`AXIS_VIP_PARAMS(test_harness, sdo_src)) sdo_src_seq; `endif //============================================================================ @@ -74,22 +72,22 @@ package spi_environment_pkg; input string name, `ifdef DEF_SDO_STREAMING - virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness, sdo_src)) sdo_src_axis_vip_if, + virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(test_harness_sdo_src_0)) sdo_src_axis_vip_if, `endif virtual interface spi_vip_if #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_s_vip_if); super.new(name); // Creating the agents - spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); + this.spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); `ifdef DEF_SDO_STREAMING - sdo_src_agent = new("SDO Source AXI Stream Agent", sdo_src_axis_vip_if); + this.sdo_src_agent = new("SDO Source AXI Stream Agent", sdo_src_axis_vip_if); `endif // Creating the sequencers - spi_seq = new("SPI VIP Agent", spi_agent, this); + this.spi_seq = new("SPI VIP Agent", this.spi_agent, this); `ifdef DEF_SDO_STREAMING - sdo_src_seq = new("SPI VIP Agent", sdo_src_agent, this); + this.sdo_src_seq = new("SDO Source AXI Stream Sequencer", this.sdo_src_agent.driver); `endif // downgrade reset check: we are currently using a clock generator for the SPI clock, @@ -106,8 +104,8 @@ package spi_environment_pkg; //============================================================================ task configure(); `ifdef DEF_SDO_STREAMING - sdo_src_seq.set_stop_policy(STOP_POLICY_PACKET); - sdo_src_seq.set_data_gen_mode(DATA_GEN_MODE_TEST_DATA); + this.sdo_src_seq.set_stop_policy(STOP_POLICY_PACKET); + this.sdo_src_seq.set_data_gen_mode(DATA_GEN_MODE_TEST_DATA); `endif endtask @@ -117,9 +115,9 @@ package spi_environment_pkg; // - Start the agents //============================================================================ task start(); - spi_agent.start(); + this.spi_agent.start(); `ifdef DEF_SDO_STREAMING - sdo_src_agent.start_master(); + this.sdo_src_agent.start_master(); `endif endtask @@ -131,7 +129,7 @@ package spi_environment_pkg; task test(); fork `ifdef DEF_SDO_STREAMING - sdo_src_seq.run(); + this.sdo_src_seq.run(); `endif join_none endtask @@ -153,10 +151,10 @@ package spi_environment_pkg; // Stop subroutine //============================================================================ task stop(); - spi_agent.stop(); + this.spi_agent.stop(); `ifdef DEF_SDO_STREAMING - sdo_src_seq.stop(); - sdo_src_agent.stop_master(); + this.sdo_src_seq.stop(); + this.sdo_src_agent.stop_master(); `endif endtask diff --git a/testbenches/ip/util_pack/environment.sv b/testbenches/ip/util_pack/environment.sv index 49686ad5..41cdd55e 100644 --- a/testbenches/ip/util_pack/environment.sv +++ b/testbenches/ip/util_pack/environment.sv @@ -11,7 +11,7 @@ package environment_pkg; import adi_axis_agent_pkg::*; import scoreboard_pack_pkg::*; - class util_pack_environment #(int `AXIS_VIP_PARAM_ORDER(tx_src_axis), int `AXIS_VIP_PARAM_ORDER(tx_dst_axis), int `AXIS_VIP_PARAM_ORDER(rx_src_axis), int `AXIS_VIP_PARAM_ORDER(rx_dst_axis)) extends adi_environment; + class util_pack_environment #(`AXIS_VIP_PARAM_DECL(tx_src_axis), `AXIS_VIP_PARAM_DECL(tx_dst_axis), `AXIS_VIP_PARAM_DECL(rx_src_axis), `AXIS_VIP_PARAM_DECL(rx_dst_axis)) extends adi_environment; // agents and sequencers adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(tx_src_axis)) tx_src_axis_agent; From f5bd5f75946b094126c7c735ecd22e96b091950c Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 20 Jan 2025 10:54:41 +0200 Subject: [PATCH 09/13] infrastructure refactorization: Updated Project level testbenches Signed-off-by: Istvan-Zsolt Szekely --- .../project/ad463x/tests/test_program.sv | 49 +++-- .../project/ad57xx/ad57xx_environment.sv | 66 +------ .../project/ad57xx/tests/test_program.sv | 66 ++++--- .../project/ad738x/tests/test_program.sv | 49 +++-- .../project/ad7606x/tests/test_program_4ch.sv | 37 ++-- .../project/ad7606x/tests/test_program_6ch.sv | 35 ++-- .../project/ad7606x/tests/test_program_8ch.sv | 35 ++-- .../project/ad7606x/tests/test_program_si.sv | 45 ++--- .../project/ad7616/tests/test_program_pi.sv | 49 +++-- .../project/ad7616/tests/test_program_si.sv | 49 +++-- .../project/ad9083/tests/test_program.sv | 178 +++++++++--------- .../ad_quadmxfe1_ebz/tests/test_dma.sv | 110 +++++------ .../ad_quadmxfe1_ebz/tests/test_program.sv | 138 +++++++------- .../tests/test_program_64b66b.sv | 166 ++++++++-------- .../project/adrv9001/tests/test_program.sv | 101 +++++----- .../project/adrv9009/tests/test_program.sv | 138 +++++++------- .../project/fmcomms2/tests/test_program.sv | 42 ++--- .../project/mxfe/tests/test_program.sv | 172 ++++++++--------- .../project/pluto/tests/test_program.sv | 42 +++-- .../pulsar_adc_pmdz/tests/test_program.sv | 49 +++-- 20 files changed, 798 insertions(+), 818 deletions(-) diff --git a/testbenches/project/ad463x/tests/test_program.sv b/testbenches/project/ad463x/tests/test_program.sv index ab354508..5582ae6a 100644 --- a/testbenches/project/ad463x/tests/test_program.sv +++ b/testbenches/project/ad463x/tests/test_program.sv @@ -47,6 +47,9 @@ import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + //--------------------------------------------------------------------------- // SPI Engine configuration parameters //--------------------------------------------------------------------------- @@ -98,7 +101,7 @@ program test_program ( input ad463x_spi_clk, input [(`NUM_OF_SDI - 1):0] ad463x_spi_sdi); -test_harness_env env; +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verify @@ -107,14 +110,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -124,7 +127,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -133,7 +136,7 @@ endtask initial begin //creating environment - env = new("AD463X Environment", + base_env = new("AD463X Environment", `TH.`SYS_CLK.inst.IF, `TH.`DMA_CLK.inst.IF, `TH.`DDR_CLK.inst.IF, @@ -142,13 +145,9 @@ initial begin `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -160,10 +159,10 @@ initial begin offload_spi_test(); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -254,7 +253,7 @@ bit [31:0] sdi_preg[$]; bit [31:0] sdi_nreg[$]; initial begin - while(1) begin + forever begin @(posedge ad463x_spi_clk); m_spi_csn_int_d <= m_spi_csn_int_s; end @@ -272,7 +271,7 @@ assign end_of_word = (CPOL ^ CPHA) ? (spi_sclk_neg_counter == DATA_DLENGTH); initial begin - while(1) begin + forever begin @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); if (m_spi_csn_negedge_s) begin spi_sclk_pos_counter <= 8'b0; @@ -283,7 +282,7 @@ initial begin end initial begin - while(1) begin + forever begin @(negedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); if (m_spi_csn_negedge_s) begin spi_sclk_neg_counter <= 8'b0; @@ -295,7 +294,7 @@ end // SDI shift register initial begin - while(1) begin + forever begin // synchronization if (CPHA ^ CPOL) @(posedge spi_sclk_bfm or posedge m_spi_csn_negedge_s); @@ -347,7 +346,7 @@ bit [31:0] sdi_shiftreg_old; assign sdi_shiftreg2 = {1'b0, sdi_shiftreg[31:1]}; initial begin - while(1) begin + forever begin @(posedge ad463x_echo_sclk); sdi_data_store <= {sdi_shiftreg[27:0], 4'b0}; if (sdi_data_store == 'h0 && shiftreg_sampled == 'h1 && sdi_shiftreg != 'h0) begin @@ -430,7 +429,7 @@ end bit [31:0] offload_transfer_cnt; initial begin - while(1) begin + forever begin @(posedge shiftreg_sampled && offload_status); offload_transfer_cnt <= offload_transfer_cnt + 'h1; end @@ -446,14 +445,14 @@ bit [31:0] offload_captured_word_arr [(2 * NUM_OF_TRANSFERS) -1 :0]; task offload_spi_test(); //Configure DMA - env.mng.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 - env.mng.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - env.mng.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 + base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.sequencer.RegWrite32(`AD469X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module @@ -486,7 +485,7 @@ task offload_spi_test(); for (int i=0; i<=((2 * NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - offload_captured_word_arr[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i] = base_env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); end if (irq_pending == 'h0) begin diff --git a/testbenches/project/ad57xx/ad57xx_environment.sv b/testbenches/project/ad57xx/ad57xx_environment.sv index b30a885e..51e4c0cb 100644 --- a/testbenches/project/ad57xx/ad57xx_environment.sv +++ b/testbenches/project/ad57xx/ad57xx_environment.sv @@ -37,18 +37,15 @@ package ad57xx_environment_pkg; - import axi_vip_pkg::*; - import axi4stream_vip_pkg::*; - import m_axi_sequencer_pkg::*; - import s_axi_sequencer_pkg::*; + import logger_pkg::*; + import adi_common_pkg::*; + import s_spi_sequencer_pkg::*; import adi_spi_vip_pkg::*; - import test_harness_env_pkg::*; - import `PKGIFY(test_harness, mng_axi_vip)::*; - import `PKGIFY(test_harness, ddr_axi_vip)::*; + import `PKGIFY(test_harness, spi_s_vip)::*; - class ad57xx_environment extends test_harness_env; + class ad57xx_environment extends adi_environment; // Agents adi_spi_agent #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_agent; @@ -62,30 +59,14 @@ package ad57xx_environment_pkg; function new( input string name, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(10)) sys_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(5)) dma_clk_vip_if, - virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(2.5)) ddr_clk_vip_if, - - virtual interface rst_vip_if #(.C_ASYNCHRONOUS(1), .C_RST_POLARITY(1)) sys_rst_vip_if, - - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, mng_axi_vip)) mng_vip_if, - virtual interface axi_vip_if #(`AXI_VIP_IF_PARAMS(test_harness, ddr_axi_vip)) ddr_vip_if, virtual interface spi_vip_if #(`SPI_VIP_PARAMS(test_harness, spi_s_vip)) spi_s_vip_if ); - super.new(name, - sys_clk_vip_if, - dma_clk_vip_if, - ddr_clk_vip_if, - sys_rst_vip_if, - mng_vip_if, - ddr_vip_if); - // Creating the agents - spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); + this.spi_agent = new("SPI VIP Agent", spi_s_vip_if, this); // Creating the sequencers - spi_seq = new("SPI VIP Sequencer", spi_agent, this); + this.spi_seq = new("SPI VIP Sequencer", this.spi_agent, this); endfunction @@ -95,43 +76,14 @@ package ad57xx_environment_pkg; // - Start the agents //============================================================================ task start(); - super.start(); - spi_agent.start(); - endtask - - //============================================================================ - // Start the test - // - start the scoreboard - // - start the sequencers - //============================================================================ - task test(); - super.test(); - fork - - join_none - endtask - - //============================================================================ - // Post test subroutine - //============================================================================ - task post_test(); - super.post_test(); - endtask - - //============================================================================ - // Run subroutine - //============================================================================ - task run; - test(); - post_test(); + this.spi_agent.start(); endtask //============================================================================ // Stop subroutine //============================================================================ task stop; - spi_agent.stop(); - super.stop(); + this.spi_agent.stop(); endtask endclass diff --git a/testbenches/project/ad57xx/tests/test_program.sv b/testbenches/project/ad57xx/tests/test_program.sv index e1bdb3e1..b9128388 100644 --- a/testbenches/project/ad57xx/tests/test_program.sv +++ b/testbenches/project/ad57xx/tests/test_program.sv @@ -35,6 +35,9 @@ `include "utils.svh" +import logger_pkg::*; +import test_harness_env_pkg::*; +import ad57xx_environment_pkg::*; import axi_vip_pkg::*; import axi4stream_vip_pkg::*; import adi_regmap_pkg::*; @@ -42,11 +45,12 @@ import adi_regmap_clkgen_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; import adi_regmap_spi_engine_pkg::*; -import logger_pkg::*; -import ad57xx_environment_pkg::*; import spi_engine_instr_pkg::*; import adi_spi_vip_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + //--------------------------------------------------------------------------- // SPI Engine configuration parameters //--------------------------------------------------------------------------- @@ -60,7 +64,8 @@ timeprecision 100ps; typedef enum {DATA_MODE_RANDOM, DATA_MODE_RAMP, DATA_MODE_PATTERN} offload_test_t; -ad57xx_environment env; +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; +ad57xx_environment spi_env; // -------------------------- // Wrapper function for AXI read verify @@ -68,13 +73,13 @@ ad57xx_environment env; task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -83,7 +88,7 @@ endtask task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -91,7 +96,7 @@ endtask // -------------------------- task spi_receive( output [`DATA_DLENGTH:0] data); - env.spi_seq.receive_data(data); + spi_env.spi_seq.receive_data(data); endtask // -------------------------- @@ -99,14 +104,14 @@ endtask // -------------------------- task spi_send( input [`DATA_DLENGTH:0] data); - env.spi_seq.send_data(data); + spi_env.spi_seq.send_data(data); endtask // -------------------------- // Wrapper function for waiting for all SPI // -------------------------- task spi_wait_send(); - env.spi_seq.flush_send(); + spi_env.spi_seq.flush_send(); endtask @@ -117,21 +122,25 @@ endtask initial begin //creating environment - env = new("Axis Sequencers Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF, - `TH.`SPI_S.inst.IF); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + + spi_env = new("SPI Environment", + `TH.`SPI_S.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.spi_seq.set_default_miso_data('h0); + base_env.start(); + spi_env.start(); + + spi_env.spi_seq.set_default_miso_data('h0); - env.sys_reset(); + base_env.sys_reset(); sanity_test(); @@ -143,10 +152,11 @@ initial begin offload_spi_test(`TEST_DATA_MODE); - env.stop(); + spi_env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -268,21 +278,21 @@ task offload_spi_test( temp_data = {4'b0001,dac_word,2'b00}; sdo_write_data_store [i] = temp_data; - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(.addr(`DDR_BA + 4*i), + base_env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(.addr(`DDR_BA + 4*i), .payload(temp_data), .strb('1)); spi_send('0); end //Configure TX DMA - env.mng.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); - env.mng.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); - env.mng.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); - env.mng.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)*4)-1)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); + base_env.mng.sequencer.RegWrite32(`SPI_ENGINE_TX_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Configure the Offload module axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG); diff --git a/testbenches/project/ad738x/tests/test_program.sv b/testbenches/project/ad738x/tests/test_program.sv index 49ce5017..5c1c80cc 100644 --- a/testbenches/project/ad738x/tests/test_program.sv +++ b/testbenches/project/ad738x/tests/test_program.sv @@ -47,6 +47,9 @@ import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + //--------------------------------------------------------------------------- // SPI Engine configuration parameters //--------------------------------------------------------------------------- @@ -98,7 +101,7 @@ program test_program ( input ad738x_spi_cs); -test_harness_env env; +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -107,14 +110,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -124,7 +127,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -133,22 +136,18 @@ endtask initial begin //creating environment - env = new("AD738X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -160,10 +159,10 @@ initial begin offload_spi_test(); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -420,14 +419,14 @@ task offload_spi_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); //Configure DMA - env.mng.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 - env.mng.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - env.mng.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*2)-1)); // X_LENGHTH = 1024-1 + base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.sequencer.RegWrite32(`AD738x_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD738x_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); @@ -455,7 +454,7 @@ task offload_spi_test(); for (int i=0; i<=((2* NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - offload_captured_word_arr[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); end if (offload_captured_word_arr [(2 * NUM_OF_TRANSFERS) - 1:2] != offload_sdi_data_store_arr [(2 * NUM_OF_TRANSFERS) - 1:2]) begin diff --git a/testbenches/project/ad7606x/tests/test_program_4ch.sv b/testbenches/project/ad7606x/tests/test_program_4ch.sv index 0bcedcfb..e33a02d2 100755 --- a/testbenches/project/ad7606x/tests/test_program_4ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_4ch.sv @@ -47,7 +47,10 @@ import adi_regmap_common_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; -localparam SIMPLE_STATUS_CRC = 0; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +parameter SIMPLE_STATUS_CRC = 0; localparam CH0 = 8'h00 * 4; localparam CH1 = 8'h10 * 4; @@ -69,7 +72,7 @@ program test_program_4ch ( output rx_busy, output logic [2:0] adc_config_mode); - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -78,14 +81,14 @@ program test_program_4ch ( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -95,7 +98,7 @@ program test_program_4ch ( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -103,19 +106,19 @@ program test_program_4ch ( // -------------------------- initial begin - //creating environment - env = new("AD7606X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -133,10 +136,10 @@ program test_program_4ch ( #100 db_transmission_test(); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end diff --git a/testbenches/project/ad7606x/tests/test_program_6ch.sv b/testbenches/project/ad7606x/tests/test_program_6ch.sv index 2613b3bc..f9fe57e9 100755 --- a/testbenches/project/ad7606x/tests/test_program_6ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_6ch.sv @@ -47,7 +47,10 @@ import adi_regmap_common_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; -localparam SIMPLE_STATUS_CRC = 0; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +parameter SIMPLE_STATUS_CRC = 0; localparam CH0 = 8'h00 * 4; localparam CH1 = 8'h10 * 4; @@ -71,7 +74,7 @@ program test_program_6ch ( output rx_busy, output logic [2:0] adc_config_mode); - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -80,14 +83,14 @@ program test_program_6ch ( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -97,7 +100,7 @@ program test_program_6ch ( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -105,19 +108,19 @@ program test_program_6ch ( // -------------------------- initial begin - //creating environment - env = new("AD7606X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -136,7 +139,7 @@ program test_program_6ch ( #100 db_transmission_test(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end diff --git a/testbenches/project/ad7606x/tests/test_program_8ch.sv b/testbenches/project/ad7606x/tests/test_program_8ch.sv index df553d99..38cd7d80 100755 --- a/testbenches/project/ad7606x/tests/test_program_8ch.sv +++ b/testbenches/project/ad7606x/tests/test_program_8ch.sv @@ -47,7 +47,10 @@ import adi_regmap_common_pkg::*; import adi_regmap_dmac_pkg::*; import adi_regmap_pwm_gen_pkg::*; -localparam SIMPLE_STATUS_CRC = 0; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +parameter SIMPLE_STATUS_CRC = 0; localparam CH0 = 8'h00 * 4; localparam CH1 = 8'h10 * 4; @@ -73,7 +76,7 @@ program test_program_8ch ( output rx_busy, output logic [2:0] adc_config_mode); - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -82,14 +85,14 @@ program test_program_8ch ( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -99,7 +102,7 @@ program test_program_8ch ( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -107,19 +110,19 @@ program test_program_8ch ( // -------------------------- initial begin - //creating environment - env = new("AD7606X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -138,7 +141,7 @@ program test_program_8ch ( #100 db_transmission_test(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end diff --git a/testbenches/project/ad7606x/tests/test_program_si.sv b/testbenches/project/ad7606x/tests/test_program_si.sv index fed5120c..4f55c963 100755 --- a/testbenches/project/ad7606x/tests/test_program_si.sv +++ b/testbenches/project/ad7606x/tests/test_program_si.sv @@ -47,6 +47,9 @@ import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + //--------------------------------------------------------------------------- // SPI Engine configuration parameters //--------------------------------------------------------------------------- @@ -100,7 +103,7 @@ program test_program_si ( input rx_busy, output rx_cnvst_n); - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verify @@ -109,14 +112,14 @@ program test_program_si ( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -126,7 +129,7 @@ program test_program_si ( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -134,19 +137,19 @@ program test_program_si ( // -------------------------- initial begin - //creating environment - env = new("AD7606X Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - env.sys_reset(); + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -159,7 +162,7 @@ program test_program_si ( offload_spi_test(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -430,14 +433,14 @@ program test_program_si ( task offload_spi_test(); //Configure DMA - env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*`NUM_OF_SDI)-1)); // X_LENGHTH - env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - env.mng.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4*`NUM_OF_SDI)-1)); // X_LENGHTH + base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.sequencer.RegWrite32(`AD7606X_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD7606_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); @@ -466,7 +469,7 @@ program test_program_si ( for (int i=0; i<=((`NUM_OF_SDI * NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - offload_captured_word_arr[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); end if (offload_captured_word_arr != offload_sdi_data_store_arr) begin `ERROR(("Offload Test FAILED")); diff --git a/testbenches/project/ad7616/tests/test_program_pi.sv b/testbenches/project/ad7616/tests/test_program_pi.sv index 3fa69e9c..14a1bef6 100755 --- a/testbenches/project/ad7616/tests/test_program_pi.sv +++ b/testbenches/project/ad7616/tests/test_program_pi.sv @@ -47,6 +47,9 @@ import adi_regmap_pwm_gen_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + localparam AD7616_CTRL_RESETN = 1; localparam AD7616_CTRL_CNVST_EN = 2; localparam NUM_OF_TRANSFERS = 10; @@ -61,7 +64,7 @@ program test_program_pi ( input sys_clk, input rx_busy); -test_harness_env env; +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -70,14 +73,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -87,7 +90,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -96,22 +99,18 @@ endtask initial begin //creating environment - env = new("AD7616 Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -119,10 +118,10 @@ initial begin data_acquisition_test(); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -210,13 +209,13 @@ task data_acquisition_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); // Configure DMA - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS // Configure AXI_AD7616 axi_write (`AXI_AD7616_BA + GetAddrs(AXI_AD7616_REG_UP_CNTRL), @@ -233,7 +232,7 @@ task data_acquisition_test(); transfer_status = 1; - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA wait(transfer_cnt == 2 * NUM_OF_TRANSFERS ); @@ -254,7 +253,7 @@ task data_acquisition_test(); for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - captured_word_arr[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); end if (captured_word_arr != dma_data_store_arr) begin diff --git a/testbenches/project/ad7616/tests/test_program_si.sv b/testbenches/project/ad7616/tests/test_program_si.sv index 4f8cf554..bf8f4497 100755 --- a/testbenches/project/ad7616/tests/test_program_si.sv +++ b/testbenches/project/ad7616/tests/test_program_si.sv @@ -47,6 +47,9 @@ import adi_regmap_spi_engine_pkg::*; import logger_pkg::*; import test_harness_env_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + //--------------------------------------------------------------------------- // SPI Engine configuration parameters //--------------------------------------------------------------------------- @@ -101,7 +104,7 @@ program test_program_si ( output rx_busy); -test_harness_env env; +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; // -------------------------- // Wrapper function for AXI read verif @@ -110,14 +113,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - env.mng.RegRead32(raddr,data); + base_env.mng.RegRead32(raddr,data); endtask // -------------------------- @@ -127,7 +130,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - env.mng.RegWrite32(waddr,wdata); + base_env.mng.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -136,22 +139,18 @@ endtask initial begin //creating environment - env = new("AD7616 Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - #100 + base_env.start(); + base_env.sys_reset(); sanity_test(); @@ -163,10 +162,10 @@ initial begin offload_spi_test(); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -420,14 +419,14 @@ task offload_spi_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); //Configure DMA - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 + base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD7616_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); @@ -456,7 +455,7 @@ task offload_spi_test(); for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - offload_captured_word_arr[i] = env.ddr_axi_agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); end if (offload_captured_word_arr [(NUM_OF_TRANSFERS) - 1:2] != offload_sdi_data_store_arr [(NUM_OF_TRANSFERS) - 1:2]) begin diff --git a/testbenches/project/ad9083/tests/test_program.sv b/testbenches/project/ad9083/tests/test_program.sv index 4b089441..71b71461 100644 --- a/testbenches/project/ad9083/tests/test_program.sv +++ b/testbenches/project/ad9083/tests/test_program.sv @@ -52,11 +52,16 @@ import adi_regmap_xcvr_pkg::*; import adi_jesd204_pkg::*; import adi_xcvr_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + parameter RX_OUT_BYTES = 8; parameter TX_OUT_BYTES = 8; + program test_program; - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + bit [31:0] val; int link_clk_freq; int device_clk_freq; @@ -70,22 +75,17 @@ program test_program; initial begin //creating environment - env = new("AD9083 Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - - `TH.`SYS_CLK.inst.IF.start_clock; - `TH.`DMA_CLK.inst.IF.start_clock; - `TH.`DDR_CLK.inst.IF.start_clock; + + base_env.start(); link_clk_freq = lane_rate/40; data_path_width = 4; @@ -102,13 +102,7 @@ program test_program; `TH.`DEVICE_CLK.inst.IF.start_clock; `TH.`SYSREF_CLK.inst.IF.start_clock; - //asserts all the resets for 100 ns - `TH.`SYS_RST.inst.IF.assert_reset; - - #100 - `TH.`SYS_RST.inst.IF.deassert_reset; - - #1us; + base_env.sys_reset(); // ------------------------------------------------------- // Test DDS path @@ -118,29 +112,29 @@ program test_program; // // Enable Rx channel - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); // Select DDS as source - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(0)); // Configure tone amplitude and frequency - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_1), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_1_DDS_SCALE_1(32'h00000fff)); - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_2), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INIT_1(16'h0000)| `SET_DAC_CHANNEL_REG_CHAN_CNTRL_2_DDS_INCR_1(16'h0100)); // Pull out TPL cores from reset - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // Sync DDS cores - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_CNTRL_1), `SET_DAC_COMMON_REG_CNTRL_1_SYNC(1)); // @@ -148,25 +142,25 @@ program test_program; // //LINK DISABLE - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); //SYSREFCONF - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_CONF), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_CONF), `SET_JESD_TX_SYSREF_CONF_SYSREF_DISABLE(0)); // Enable SYSREF handling //CONF0 - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF0), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF0), `SET_JESD_TX_LINK_CONF0_OCTETS_PER_FRAME(`TX_JESD_F-1)| `SET_JESD_TX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`TX_JESD_F*`TX_JESD_K-1)); - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF4), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF4), `SET_JESD_TX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`TX_JESD_F*`TX_JESD_K)/TX_OUT_BYTES-1)); //CONF1 - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF1), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_CONF1), `SET_JESD_TX_LINK_CONF1_SCRAMBLER_DISABLE(0)); // Scrambler enable //LINK ENABLE - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); // @@ -174,39 +168,39 @@ program test_program; // //LINK DISABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); //SYSREFCONF - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_CONF), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_CONF), `SET_JESD_RX_SYSREF_CONF_SYSREF_DISABLE(0)); // Enable SYSREF handling //CONF0 - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF0), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF0), `SET_JESD_RX_LINK_CONF0_OCTETS_PER_FRAME(`RX_JESD_F-1)| `SET_JESD_RX_LINK_CONF0_OCTETS_PER_MULTIFRAME(`RX_JESD_F*`RX_JESD_K-1)); - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF4), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF4), `SET_JESD_RX_LINK_CONF4_TPL_BEATS_PER_MULTIFRAME((`RX_JESD_F*`RX_JESD_K)/RX_OUT_BYTES-1)); // Beats per multiframe //CONF1 - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF1), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_CONF1), `SET_JESD_RX_LINK_CONF1_DESCRAMBLER_DISABLE(0)); // Scrambler enable //LINK ENABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); //XCVR INIT //REG CTRL - env.mng.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_CONTROL), + base_env.mng.sequencer.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_CONTROL), `SET_XCVR_CONTROL_LPM_DFE_N(1)| `SET_XCVR_CONTROL_OUTCLK_SEL(4)); // RXOUTCLK uses DIV2 - env.mng.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_CONTROL), + base_env.mng.sequencer.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_CONTROL), `SET_XCVR_CONTROL_LPM_DFE_N(1)| `SET_XCVR_CONTROL_OUTCLK_SEL(4)); // TXOUTCLK uses DIV2 - env.mng.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_RESETN), + base_env.mng.sequencer.RegWrite32(`RX_XCVR_BA + GetAddrs(XCVR_RESETN), `SET_XCVR_RESETN_RESETN(1)); - env.mng.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_RESETN), + base_env.mng.sequencer.RegWrite32(`TX_XCVR_BA + GetAddrs(XCVR_RESETN), `SET_XCVR_RESETN_RESETN(1)); // Give time the PLLs to lock @@ -214,22 +208,22 @@ program test_program; //Read status back // Check SYSREF_STATUS - env.mng.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - env.mng.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); // Check if in DATA state and SYNC is 1 - env.mng.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - env.mng.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), `SET_JESD_TX_LINK_STATUS_STATUS_SYNC(1)| `SET_JESD_TX_LINK_STATUS_STATUS_STATE(3)); //LINK DISABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); // ------------------------------------------------------- @@ -240,85 +234,85 @@ program test_program; // .step (1), // .max_sample(2048) for (int i=0;i<2048*2 ;i=i+2) begin - env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,15); + base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(`DDR_BA+i*2,(((i+1)) << 16) | i ,15); end #5us; // Reset TPL cores - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_DAC_COMMON_REG_RSTN_RSTN(0)); - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_ADC_COMMON_REG_RSTN_RSTN(0)); // Pull out TPL cores from reset - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_COMMON_REG_RSTN), `SET_DAC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_DAC_COMMON_REG_RSTN_RSTN(1)); - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_COMMON_REG_RSTN), `SET_ADC_COMMON_REG_RSTN_MMCM_RSTN(1)| `SET_ADC_COMMON_REG_RSTN_RSTN(1)); // Configure Transport Layer for DMA - env.mng.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), + base_env.mng.sequencer.RegWrite32(`DAC_TPL_BA + GetAddrs(DAC_CHANNEL_REG_CHAN_CNTRL_7), `SET_DAC_CHANNEL_REG_CHAN_CNTRL_7_DAC_DDS_SEL(2)); #1us; // Configure TX DMA - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); // SRC_ADDRESS - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer // Configure RX DMA - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00001000)); // DEST_ADDRESS - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer //LINK ENABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); #25us; //Read status back // Check SYSREF_STATUS - env.mng.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_SYSREF_STATUS), `SET_JESD_RX_SYSREF_STATUS_SYSREF_DETECTED(1)); - env.mng.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_SYSREF_STATUS), `SET_JESD_TX_SYSREF_STATUS_SYSREF_DETECTED(1)); #1us; // Check if in DATA state and SYNC is 1 - env.mng.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_STATUS), `SET_JESD_RX_LINK_STATUS_STATUS_STATE(3)); - env.mng.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), + base_env.mng.sequencer.RegReadVerify32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_STATUS), `SET_JESD_TX_LINK_STATUS_STATUS_SYNC(1)| `SET_JESD_TX_LINK_STATUS_STATUS_STATE(3)); #5us; - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(0)); #5us; @@ -331,45 +325,45 @@ program test_program; //LINK DISABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(1)); - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(1)); - env.mng.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), + base_env.mng.sequencer.RegWrite32(`ADC_TPL_BA + GetAddrs(ADC_CHANNEL_REG_CHAN_CNTRL), `SET_ADC_CHANNEL_REG_CHAN_CNTRL_ENABLE(1)); #5us; // Configure TX DMA - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_SRC_ADDRESS), `SET_DMAC_SRC_ADDRESS_SRC_ADDRESS(`DDR_BA)); // SRC_ADDRESS - env.mng.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`TX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer // Configure RX DMA - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_CYCLIC(0)| `SET_DMAC_FLAGS_TLAST(1)); // use TLAST, disable CYCLIC - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH(32'h000003DF)); // X_LENGTH = 992-1 - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA+32'h00002000)); // DEST_ADDRESS - env.mng.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), + base_env.mng.sequencer.RegWrite32(`RX_DMA_BA+GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA //LINK ENABLE - env.mng.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_RX_BA + GetAddrs(JESD_RX_LINK_DISABLE), `SET_JESD_RX_LINK_DISABLE_LINK_DISABLE(0)); - env.mng.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), + base_env.mng.sequencer.RegWrite32(`AXI_JESD_TX_BA + GetAddrs(JESD_TX_LINK_DISABLE), `SET_JESD_TX_LINK_DISABLE_LINK_DISABLE(0)); #10us; @@ -381,10 +375,10 @@ program test_program; .max_sample(496) ); - env.stop(); + base_env.stop(); `INFO(("Test Done"), ADI_VERBOSITY_NONE); - $finish; + $finish(); end @@ -403,7 +397,7 @@ program test_program; for (int i=0;i Date: Mon, 20 Jan 2025 15:22:50 +0200 Subject: [PATCH 10/13] infrastructure refactorization: Updates and fixes Signed-off-by: Istvan-Zsolt Szekely --- .../ip/dma_loopback/tests/test_program.sv | 14 ++--- testbenches/ip/hbm/tests/test_program.sv | 57 ++++++++++--------- .../project/ad463x/tests/test_program.sv | 2 +- .../project/ad57xx/tests/test_program.sv | 2 +- .../project/ad738x/tests/test_program.sv | 2 +- .../project/ad7606x/tests/test_program_si.sv | 2 +- .../project/ad9083/tests/test_program.sv | 2 +- .../ad_quadmxfe1_ebz/tests/test_program.sv | 2 +- .../project/adrv9001/tests/test_program.sv | 12 ++-- .../project/adrv9009/tests/test_program.sv | 2 +- .../project/fmcomms2/tests/test_program.sv | 2 +- .../project/mxfe/tests/test_program.sv | 8 +-- .../project/pluto/tests/test_program.sv | 4 +- .../pulsar_adc_pmdz/tests/test_program.sv | 2 +- 14 files changed, 57 insertions(+), 56 deletions(-) diff --git a/testbenches/ip/dma_loopback/tests/test_program.sv b/testbenches/ip/dma_loopback/tests/test_program.sv index 02320217..0c1c93b3 100644 --- a/testbenches/ip/dma_loopback/tests/test_program.sv +++ b/testbenches/ip/dma_loopback/tests/test_program.sv @@ -60,13 +60,13 @@ program test_program; initial begin //creating environment - base_env = new("DMA Loopback Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); diff --git a/testbenches/ip/hbm/tests/test_program.sv b/testbenches/ip/hbm/tests/test_program.sv index a8480581..69abbfe0 100644 --- a/testbenches/ip/hbm/tests/test_program.sv +++ b/testbenches/ip/hbm/tests/test_program.sv @@ -44,37 +44,38 @@ import axi4stream_vip_pkg::*; import logger_pkg::*; import adi_regmap_dmac_pkg::*; +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + `define RX_DMA 32'h7c42_0000 `define TX_DMA 32'h7c43_0000 `define DDR_BASE 32'h8000_0000 program test_program; - test_harness_env env; + test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + bit [31:0] val; bit [31:0] src_addr; initial begin //creating environment - env = new("HBM Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); - - #2ps; + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); setLoggerVerbosity(ADI_VERBOSITY_NONE); - env.start(); - `TH.`HBM_CLK.inst.IF.start_clock; + base_env.start(); - env.sys_reset(); + `TH.`HBM_CLK.inst.IF.start_clock; - #1us; + base_env.sys_reset(); // // ------------------------------------------------------- // // Test TX DMA and RX DMA in loopback @@ -82,7 +83,7 @@ program test_program; // // // Init test data // for (int i=0;i<2048*2 ;i=i+2) begin -// env.ddr_axi_agent.mem_model.backdoor_memory_write_4byte(`DDR_BASE+src_addr+i*2,(((i+1)) << 16) | i ,'hF); +// base_env.ddr.agent.mem_model.backdoor_memory_write_4byte(`DDR_BASE+src_addr+i*2,(((i+1)) << 16) | i ,'hF); // end // // do_transfer( @@ -99,7 +100,7 @@ program test_program; // .length('h1000) // ); // -// env.stop(); +// base_env.stop(); // // `INFO(("Test bench done!"), ADI_VERBOSITY_NONE); // $finish(); @@ -111,27 +112,27 @@ program test_program; // bit [31:0] length); // // // Configure TX DMA -// env.mng.RegWrite32(`TX_DMA+GetAddrs(dmac_CONTROL), +// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_CONTROL), // `SET_dmac_CONTROL_ENABLE(1)); -// env.mng.RegWrite32(`TX_DMA+GetAddrs(dmac_FLAGS), +// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_FLAGS), // `SET_dmac_FLAGS_TLAST(32'h00000006)); -// env.mng.RegWrite32(`TX_DMA+GetAddrs(dmac_X_LENGTH), +// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_X_LENGTH), // `SET_dmac_X_LENGTH_X_LENGTH(length-1)); -// env.mng.RegWrite32(`TX_DMA+GetAddrs(dmac_SRC_ADDRESS), +// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_SRC_ADDRESS), // `SET_dmac_SRC_ADDRESS_SRC_ADDRESS(src_addr)); -// env.mng.RegWrite32(`TX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), +// base_env.mng.sequencer.RegWrite32(`TX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), // `SET_dmac_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // // // Configure RX DMA -// env.mng.RegWrite32(`RX_DMA+GetAddrs(dmac_CONTROL), +// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_CONTROL), // `SET_dmac_CONTROL_ENABLE(1)); -// env.mng.RegWrite32(`RX_DMA+GetAddrs(dmac_FLAGS), +// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_FLAGS), // `SET_dmac_FLAGS_TLAST(32'h00000006)); -// env.mng.RegWrite32(`RX_DMA+GetAddrs(dmac_X_LENGTH), +// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_X_LENGTH), // `SET_dmac_X_LENGTH_X_LENGTH(length-1)); -// env.mng.RegWrite32(`RX_DMA+GetAddrs(dmac_DEST_ADDRESS), +// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_DEST_ADDRESS), // `SET_dmac_DEST_ADDRESS_DEST_ADDRESS(dest_addr)); -// env.mng.RegWrite32(`RX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), +// base_env.mng.sequencer.RegWrite32(`RX_DMA+GetAddrs(dmac_TRANSFER_SUBMIT), // `SET_dmac_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // endtask // @@ -149,8 +150,8 @@ program test_program; // for (int i=0;i Date: Mon, 20 Jan 2025 16:26:59 +0200 Subject: [PATCH 11/13] ad7616: Fixes - Fixed the serial test - Parallel data acquisition test still failing Signed-off-by: Istvan-Zsolt Szekely --- library/regmaps/adi_regmap_axi_ad7616_pkg.sv | 16 ++++++------- testbenches/project/ad7616/cfgs/cfg_pi.tcl | 2 +- testbenches/project/ad7616/cfgs/cfg_si.tcl | 2 +- testbenches/project/ad7616/system_bd.tcl | 10 ++------ testbenches/project/ad7616/system_project.tcl | 6 ++--- testbenches/project/ad7616/system_tb.sv | 2 +- .../project/ad7616/tests/test_program_pi.sv | 12 ++++------ .../project/ad7616/tests/test_program_si.sv | 24 +++++++------------ 8 files changed, 29 insertions(+), 45 deletions(-) diff --git a/library/regmaps/adi_regmap_axi_ad7616_pkg.sv b/library/regmaps/adi_regmap_axi_ad7616_pkg.sv index 8630ec2f..45b3c0a4 100644 --- a/library/regmaps/adi_regmap_axi_ad7616_pkg.sv +++ b/library/regmaps/adi_regmap_axi_ad7616_pkg.sv @@ -41,22 +41,22 @@ package adi_regmap_axi_ad7616_pkg; /* AXI AD7616 (axi_ad7616) */ - const reg_t AXI_AD7616_REG_VERSION = '{ 'h0400, "REG_VERSION" , '{ + const reg_t AXI_AD7616_REG_VERSION = '{ 'h0000, "REG_VERSION" , '{ "VERSION": '{ 31, 0, RO, 'h00001002 }}}; `define SET_AXI_AD7616_REG_VERSION_VERSION(x) SetField(AXI_AD7616_REG_VERSION,"VERSION",x) `define GET_AXI_AD7616_REG_VERSION_VERSION(x) GetField(AXI_AD7616_REG_VERSION,"VERSION",x) - const reg_t AXI_AD7616_REG_ID = '{ 'h0404, "REG_ID" , '{ + const reg_t AXI_AD7616_REG_ID = '{ 'h0004, "REG_ID" , '{ "ID": '{ 31, 0, RO, 'h00000000 }}}; `define SET_AXI_AD7616_REG_ID_ID(x) SetField(AXI_AD7616_REG_ID,"ID",x) `define GET_AXI_AD7616_REG_ID_ID(x) GetField(AXI_AD7616_REG_ID,"ID",x) - const reg_t AXI_AD7616_REG_SCRATCH = '{ 'h0408, "REG_SCRATCH" , '{ + const reg_t AXI_AD7616_REG_SCRATCH = '{ 'h0008, "REG_SCRATCH" , '{ "SCRATCH": '{ 31, 0, RW, 'h00000000 }}}; `define SET_AXI_AD7616_REG_SCRATCH_SCRATCH(x) SetField(AXI_AD7616_REG_SCRATCH,"SCRATCH",x) `define GET_AXI_AD7616_REG_SCRATCH_SCRATCH(x) GetField(AXI_AD7616_REG_SCRATCH,"SCRATCH",x) - const reg_t AXI_AD7616_REG_UP_CNTRL = '{ 'h0440, "REG_UP_CNTRL" , '{ + const reg_t AXI_AD7616_REG_UP_CNTRL = '{ 'h0040, "REG_UP_CNTRL" , '{ "CNVST_EN": '{ 1, 1, RW, 'h0 }, "RESETN": '{ 0, 0, RW, 'h0 }}}; `define SET_AXI_AD7616_REG_UP_CNTRL_CNVST_EN(x) SetField(AXI_AD7616_REG_UP_CNTRL,"CNVST_EN",x) @@ -64,22 +64,22 @@ package adi_regmap_axi_ad7616_pkg; `define SET_AXI_AD7616_REG_UP_CNTRL_RESETN(x) SetField(AXI_AD7616_REG_UP_CNTRL,"RESETN",x) `define GET_AXI_AD7616_REG_UP_CNTRL_RESETN(x) GetField(AXI_AD7616_REG_UP_CNTRL,"RESETN",x) - const reg_t AXI_AD7616_REG_UP_CONV_RATE = '{ 'h0444, "REG_UP_CONV_RATE" , '{ + const reg_t AXI_AD7616_REG_UP_CONV_RATE = '{ 'h0044, "REG_UP_CONV_RATE" , '{ "UP_CONV_RATE": '{ 31, 0, RW, 'h00000000 }}}; `define SET_AXI_AD7616_REG_UP_CONV_RATE_UP_CONV_RATE(x) SetField(AXI_AD7616_REG_UP_CONV_RATE,"UP_CONV_RATE",x) `define GET_AXI_AD7616_REG_UP_CONV_RATE_UP_CONV_RATE(x) GetField(AXI_AD7616_REG_UP_CONV_RATE,"UP_CONV_RATE",x) - const reg_t AXI_AD7616_REG_UP_BURST_LENGTH = '{ 'h0448, "REG_UP_BURST_LENGTH" , '{ + const reg_t AXI_AD7616_REG_UP_BURST_LENGTH = '{ 'h0048, "REG_UP_BURST_LENGTH" , '{ "UP_BURST_LENGTH": '{ 4, 0, RW, 'h000 }}}; `define SET_AXI_AD7616_REG_UP_BURST_LENGTH_UP_BURST_LENGTH(x) SetField(AXI_AD7616_REG_UP_BURST_LENGTH,"UP_BURST_LENGTH",x) `define GET_AXI_AD7616_REG_UP_BURST_LENGTH_UP_BURST_LENGTH(x) GetField(AXI_AD7616_REG_UP_BURST_LENGTH,"UP_BURST_LENGTH",x) - const reg_t AXI_AD7616_REG_UP_READ_DATA = '{ 'h044c, "REG_UP_READ_DATA" , '{ + const reg_t AXI_AD7616_REG_UP_READ_DATA = '{ 'h004c, "REG_UP_READ_DATA" , '{ "UP_READ_DATA": '{ 31, 0, RO, 'h00000000 }}}; `define SET_AXI_AD7616_REG_UP_READ_DATA_UP_READ_DATA(x) SetField(AXI_AD7616_REG_UP_READ_DATA,"UP_READ_DATA",x) `define GET_AXI_AD7616_REG_UP_READ_DATA_UP_READ_DATA(x) GetField(AXI_AD7616_REG_UP_READ_DATA,"UP_READ_DATA",x) - const reg_t AXI_AD7616_REG_UP_WRITE_DATA = '{ 'h0450, "REG_UP_WRITE_DATA" , '{ + const reg_t AXI_AD7616_REG_UP_WRITE_DATA = '{ 'h0050, "REG_UP_WRITE_DATA" , '{ "UP_WRITE_DATA": '{ 31, 0, WO, 'h00000000 }}}; `define SET_AXI_AD7616_REG_UP_WRITE_DATA_UP_WRITE_DATA(x) SetField(AXI_AD7616_REG_UP_WRITE_DATA,"UP_WRITE_DATA",x) `define GET_AXI_AD7616_REG_UP_WRITE_DATA_UP_WRITE_DATA(x) GetField(AXI_AD7616_REG_UP_WRITE_DATA,"UP_WRITE_DATA",x) diff --git a/testbenches/project/ad7616/cfgs/cfg_pi.tcl b/testbenches/project/ad7616/cfgs/cfg_pi.tcl index 49b70d8e..e447cce9 100755 --- a/testbenches/project/ad7616/cfgs/cfg_pi.tcl +++ b/testbenches/project/ad7616/cfgs/cfg_pi.tcl @@ -1,3 +1,3 @@ global ad_project_params -set ad_project_params(SER_PAR_N) 0 +set ad_project_params(INTF) 0 diff --git a/testbenches/project/ad7616/cfgs/cfg_si.tcl b/testbenches/project/ad7616/cfgs/cfg_si.tcl index ce97f85c..b1f2479c 100755 --- a/testbenches/project/ad7616/cfgs/cfg_si.tcl +++ b/testbenches/project/ad7616/cfgs/cfg_si.tcl @@ -1,3 +1,3 @@ global ad_project_params -set ad_project_params(SER_PAR_N) 1 +set ad_project_params(INTF) 1 diff --git a/testbenches/project/ad7616/system_bd.tcl b/testbenches/project/ad7616/system_bd.tcl index 5d5c5336..7fd76333 100755 --- a/testbenches/project/ad7616/system_bd.tcl +++ b/testbenches/project/ad7616/system_bd.tcl @@ -36,7 +36,7 @@ global ad_project_params # system level parameters -set SER_PAR_N $ad_project_params(SER_PAR_N) +set INTF $ad_project_params(INTF) adi_project_files [list \ "$ad_hdl_dir/library/common/ad_edge_detect.v" \ @@ -48,7 +48,7 @@ adi_project_files [list \ source $ad_hdl_dir/projects/ad7616_sdz/common/ad7616_bd.tcl -if {$SER_PAR_N == 1} { +if {$INTF == 1} { create_bd_port -dir O spi_clk create_bd_port -dir O ad7616_irq @@ -63,8 +63,6 @@ if {$SER_PAR_N == 1} { } else { create_bd_port -dir O sys_clk - ad_disconnect spi_clk ad7616_pwm_gen/ext_clk - ad_connect sys_cpu_clk ad7616_pwm_gen/ext_clk ad_connect sys_clk sys_cpu_clk set BA_AD7616 0x44A80000 @@ -80,7 +78,3 @@ adi_sim_add_define "AD7616_DMA_BA=[format "%d" ${BA_DMA}]" set BA_PWM 0x44B00000 set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_ad7616_pwm_gen}] adi_sim_add_define "AD7616_PWM_GEN_BA=[format "%d" ${BA_PWM}]" - -set BA_CLKGEN 0x44A70000 -set_property offset $BA_CLKGEN [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_spi_clkgen}] -adi_sim_add_define "AD7616_AXI_CLKGEN_BA=[format "%d" ${BA_CLKGEN}]" diff --git a/testbenches/project/ad7616/system_project.tcl b/testbenches/project/ad7616/system_project.tcl index 931ccbf7..378c3ba9 100755 --- a/testbenches/project/ad7616/system_project.tcl +++ b/testbenches/project/ad7616/system_project.tcl @@ -16,12 +16,12 @@ set project_name [file rootname $cfg_file] # Set project params global ad_project_params -set SER_PAR_N $ad_project_params(SER_PAR_N) +set INTF $ad_project_params(INTF) #set a default test program -if {$SER_PAR_N == 1} { +if {$INTF == 1} { adi_sim_add_define "TEST_PROGRAM=test_program_si" -} elseif {$SER_PAR_N == 0} { +} elseif {$INTF == 0} { adi_sim_add_define "TEST_PROGRAM=test_program_pi" } else { adi_sim_add_define "TEST_PROGRAM=test_program_si" diff --git a/testbenches/project/ad7616/system_tb.sv b/testbenches/project/ad7616/system_tb.sv index 8d4d43c6..73480c91 100755 --- a/testbenches/project/ad7616/system_tb.sv +++ b/testbenches/project/ad7616/system_tb.sv @@ -39,7 +39,7 @@ module system_tb(); generate - if (`SER_PAR_N == 1) begin //serial interface + if (`INTF == 1) begin //serial interface wire ad7616_spi_sclk; wire ad7616_spi_sdo; wire [1:0] ad7616_spi_sdi; diff --git a/testbenches/project/ad7616/tests/test_program_pi.sv b/testbenches/project/ad7616/tests/test_program_pi.sv index 14a1bef6..6f302f47 100755 --- a/testbenches/project/ad7616/tests/test_program_pi.sv +++ b/testbenches/project/ad7616/tests/test_program_pi.sv @@ -196,12 +196,6 @@ bit [31:0] captured_word_arr [(NUM_OF_TRANSFERS) -1 :0]; task data_acquisition_test(); - // Start spi clk generator - axi_write (`AD7616_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), - `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | - `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) - ); - // Configure pwm gen axi_write (`AD7616_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_RSTN), `SET_AXI_PWM_GEN_REG_RSTN_RESET(1)); // PWM_GEN reset in regmap (ACTIVE HIGH) axi_write (`AD7616_PWM_GEN_BA + GetAddrs(AXI_PWM_GEN_REG_PULSE_X_PERIOD), `SET_AXI_PWM_GEN_REG_PULSE_X_PERIOD_PULSE_X_PERIOD('h64)); // set PWM period @@ -253,10 +247,12 @@ task data_acquisition_test(); for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); end - if (captured_word_arr != dma_data_store_arr) begin + `INFO(("captured_word_arr: %x; dma_data_store_arr %x", captured_word_arr, dma_data_store_arr), ADI_VERBOSITY_LOW); + + if (captured_word_arr != dma_data_store_arr) begin `ERROR(("Data Acquisition Test FAILED")); end else begin `INFO(("Data Acquisition Test PASSED"), ADI_VERBOSITY_LOW); diff --git a/testbenches/project/ad7616/tests/test_program_si.sv b/testbenches/project/ad7616/tests/test_program_si.sv index bf8f4497..54407e77 100755 --- a/testbenches/project/ad7616/tests/test_program_si.sv +++ b/testbenches/project/ad7616/tests/test_program_si.sv @@ -113,14 +113,14 @@ task axi_read_v( input [31:0] raddr, input [31:0] vdata); - base_env.mng.RegReadVerify32(raddr,vdata); + base_env.mng.sequencer.RegReadVerify32(raddr,vdata); endtask task axi_read( input [31:0] raddr, output [31:0] data); - base_env.mng.RegRead32(raddr,data); + base_env.mng.sequencer.RegRead32(raddr,data); endtask // -------------------------- @@ -130,7 +130,7 @@ task axi_write( input [31:0] waddr, input [31:0] wdata); - base_env.mng.RegWrite32(waddr,wdata); + base_env.mng.sequencer.RegWrite32(waddr,wdata); endtask // -------------------------- @@ -419,14 +419,14 @@ task offload_spi_test(); `INFO(("Axi_pwm_gen started"), ADI_VERBOSITY_LOW); //Configure DMA - base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA - base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_CONTROL), `SET_DMAC_CONTROL_ENABLE(1)); // Enable DMA + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_FLAGS), `SET_DMAC_FLAGS_TLAST(1) | `SET_DMAC_FLAGS_PARTIAL_REPORTING_EN(1) ); // Use TLAST - base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 - base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS - base_env.mng.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_X_LENGTH), `SET_DMAC_X_LENGTH_X_LENGTH((NUM_OF_TRANSFERS*4)-1)); // X_LENGHTH = 1024-1 + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA)); // DEST_ADDRESS + base_env.mng.sequencer.RegWrite32(`AD7616_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1)); // Submit transfer DMA // Configure the Offload module axi_write (`SPI_AD7616_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), INST_CFG); @@ -455,7 +455,7 @@ task offload_spi_test(); for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin #1 - offload_captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(`DDR_BA + 4*i); + offload_captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); end if (offload_captured_word_arr [(NUM_OF_TRANSFERS) - 1:2] != offload_sdi_data_store_arr [(NUM_OF_TRANSFERS) - 1:2]) begin @@ -472,12 +472,6 @@ endtask bit [31:0] sdi_fifo_data = 0; task fifo_spi_test(); - // Start spi clk generator - axi_write (`AD7616_AXI_CLKGEN_BA + GetAddrs(AXI_CLKGEN_REG_RSTN), - `SET_AXI_CLKGEN_REG_RSTN_MMCM_RSTN(1) | - `SET_AXI_CLKGEN_REG_RSTN_RSTN(1) - ); - // Enable SPI Engine axi_write (`SPI_AD7616_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_ENABLE), `SET_AXI_SPI_ENGINE_ENABLE_ENABLE(0)); From c8a87373390e2cbf9c91b0c70c32879adb6e6569 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Mon, 20 Jan 2025 17:17:41 +0200 Subject: [PATCH 12/13] dma_flock: Fixed testbench after rebase Signed-off-by: Istvan-Zsolt Szekely --- testbenches/ip/dma_flock/environment.sv | 2 +- testbenches/ip/dma_flock/scoreboard.sv | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/testbenches/ip/dma_flock/environment.sv b/testbenches/ip/dma_flock/environment.sv index cac44346..6305c7c4 100644 --- a/testbenches/ip/dma_flock/environment.sv +++ b/testbenches/ip/dma_flock/environment.sv @@ -70,7 +70,7 @@ package environment_pkg; this.src_axis_agent = new("Src AXI stream agent", src_axis_vip_if, this); this.dst_axis_agent = new("Dest AXI stream agent", dst_axis_vip_if, this); - this.scrb = new(); + this.scrb = new("Scoreboard", this); endfunction diff --git a/testbenches/ip/dma_flock/scoreboard.sv b/testbenches/ip/dma_flock/scoreboard.sv index 37c3c689..7d532bd2 100644 --- a/testbenches/ip/dma_flock/scoreboard.sv +++ b/testbenches/ip/dma_flock/scoreboard.sv @@ -37,6 +37,7 @@ package scoreboard_pkg; + import adi_common_pkg::*; import xil_common_vip_pkg::*; import axi4stream_vip_pkg::*; import axi_vip_pkg::*; From 43d53fbd5766970a7d6c30a54884e3a6d7161c73 Mon Sep 17 00:00:00 2001 From: Istvan-Zsolt Szekely Date: Tue, 21 Jan 2025 09:04:57 +0200 Subject: [PATCH 13/13] adi_datatypes: Added FIFO and LIFO class implementation Signed-off-by: Istvan-Zsolt Szekely --- library/utilities/adi_datatypes.sv | 160 +++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 library/utilities/adi_datatypes.sv diff --git a/library/utilities/adi_datatypes.sv b/library/utilities/adi_datatypes.sv new file mode 100644 index 00000000..45219c0a --- /dev/null +++ b/library/utilities/adi_datatypes.sv @@ -0,0 +1,160 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2024 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +package adi_datatypes_pkg; + + import logger_pkg::*; + import adi_common_pkg::*; + + class adi_fifo #(type data_type = int) extends adi_component; + + local data_type adi_fifo [$]; + local int depth; + + function new( + input string name, + input int depth, + input adi_component parent = null); + + super.new(name, parent); + + this.depth = depth; + endfunction: new + + function bit push(input data_type data); + if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + return 1'b0; + end else begin + this.adi_fifo.push_back(data); + return 1'b1; + end + endfunction: push + + function data_type pop(); + if (this.adi_fifo.size() == 0) begin + return null; + end else begin + return this.adi_fifo.pop_front(); + end + endfunction: pop + + function int room(); + return depth-this.adi_fifo.size(); + endfunction: room + + function int size(); + return this.adi_fifo.size(); + endfunction: room + + function void clear(); + this.adi_fifo.delete(); + endfunction: clear + + function bit insert( + input int index, + input data_type data); + + if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + return 1'b0; + end else begin + this.adi_fifo.insert(index, data); + return 1'b1; + end + endfunction: clear + + endclass: adi_fifo + + + class adi_lifo #(type data_type = int) extends adi_component; + + local data_type adi_fifo [$]; + local int depth; + + function new( + input string name, + input int depth, + input adi_component parent = null); + + super.new(name, parent); + + this.depth = depth; + endfunction: new + + function bit push(input data_type data); + if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + return 1'b0; + end else begin + this.adi_fifo.push_front(data); + return 1'b1; + end + endfunction: push + + function data_type pop(); + if (this.adi_fifo.size() == 0) begin + return null; + end else begin + return this.adi_fifo.pop_front(); + end + endfunction: pop + + function int room(); + return depth-this.adi_fifo.size(); + endfunction: room + + function int size(); + return this.adi_fifo.size(); + endfunction: room + + function void clear(); + this.adi_fifo.delete(); + endfunction: clear + + function bit insert( + input int index, + input data_type data); + + if (this.adi_fifo.size() == this.depth && this.depth != 0) begin + return 1'b0; + end else begin + this.adi_fifo.insert(index, data); + return 1'b1; + end + endfunction: clear + + endclass: adi_lifo + +endpackage: adi_datatypes_pkg