Unimplemented SEQGEN

[mjc0608]

Hi,

I'm using sv2v to translate this project to verilog. I'm using design compiler version T-2022.03-SP3.

It looks like DC generates some SEQGEN cells that contains both synchronous data and asynchronous data, which triggers some assertions in sv2v.

Is there a way to avoid these cells during synthesis? Also, if we want to implement the missing support, what should we do (i.e., which document should we read)?

Best,
Jiacheng

[taylor-bsg]

My guess is that you are synthesizing code that has asynchronous resets. Our code base has very few of these, so you may need to lightly extend the tool to support those SEQGENs. Feel free to make a pull request! M

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On Mon, Jan 30, 2023 at 6:43 PM Jiacheng Ma ***@***.***> wrote: Hi, I'm using sv2v to translate this project <https://github.com/openhwgroup/cvfpu> to verilog. I'm using design compiler version T-2022.03-SP3. It looks like DC generates some SEQGEN cells that contains both synchronous data and asynchronous data, which triggers some assertions in sv2v. Is there a way to avoid these cells during synthesis? Also, if we want to implement the missing support, what should we do (i.e., which document should we read)? Best, Jiacheng — Reply to this email directly, view it on GitHub <#23>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AEFG5AHVW32EPBBI6XNWGW3WVB33JANCNFSM6AAAAAAUL4H264> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>