From 6b3852bbf829934fed0d01c1dda52569ed7cb05b Mon Sep 17 00:00:00 2001 From: "Andrey Butok (B00423)" Date: Mon, 19 Mar 2018 15:29:19 +0100 Subject: [PATCH] FNET 4.1.1 --- .../boards/frdmk64f/bench/iar/bench.ewd | 11050 -------------- .../boards/frdmk64f/bench/iar/bench.ewp | 2766 ---- .../boards/frdmk64f/bench/iar/bench.eww | 33 - .../boards/frdmk64f/bench/kds/.cproject | 344 - fnet_demos/boards/frdmk64f/bench/kds/.project | 1380 -- .../bench_frdmk64f debug cmsisdap.launch | 62 - .../bench_frdmk64f debug jlink.launch | 80 - .../Settings/bench_frdmk64f debug pne.launch | 200 - .../bench_frdmk64f release cmsisdap.launch | 62 - .../bench_frdmk64f release jlink.launch | 80 - .../bench_frdmk64f release pne.launch | 200 - .../frdmk64f/bench/kds/bench_frdmk64f.wsd | 9 - fnet_demos/boards/frdmk64f/boot/iar/boot.ewd | 11050 -------------- fnet_demos/boards/frdmk64f/boot/iar/boot.ewp | 2766 ---- fnet_demos/boards/frdmk64f/boot/iar/boot.eww | 33 - fnet_demos/boards/frdmk64f/boot/kds/.cproject | 344 - fnet_demos/boards/frdmk64f/boot/kds/.project | 1380 -- .../boot_frdmk64f debug cmsisdap.launch | 62 - .../Settings/boot_frdmk64f debug jlink.launch | 80 - .../Settings/boot_frdmk64f debug pne.launch | 200 - .../boot_frdmk64f release cmsisdap.launch | 62 - .../boot_frdmk64f release jlink.launch | 80 - .../Settings/boot_frdmk64f release pne.launch | 200 - .../frdmk64f/boot/kds/boot_frdmk64f.wsd | 9 - .../boards/frdmk64f/shell/iar/shell.ewd | 11050 -------------- .../boards/frdmk64f/shell/iar/shell.ewp | 2766 ---- .../boards/frdmk64f/shell/iar/shell.eww | 33 - .../boards/frdmk64f/shell/kds/.cproject | 344 - fnet_demos/boards/frdmk64f/shell/kds/.project | 1380 -- .../shell_frdmk64f debug cmsisdap.launch | 62 - .../shell_frdmk64f debug jlink.launch | 80 - .../Settings/shell_frdmk64f debug pne.launch | 200 - .../shell_frdmk64f release cmsisdap.launch | 62 - .../shell_frdmk64f release jlink.launch | 80 - .../shell_frdmk64f release pne.launch | 200 - .../frdmk64f/shell/kds/shell_frdmk64f.wsd | 9 - .../frdmk64f/shell_boot/iar/shell_boot.ewd | 11050 -------------- .../frdmk64f/shell_boot/iar/shell_boot.ewp | 2766 ---- .../frdmk64f/shell_boot/iar/shell_boot.eww | 33 - .../boards/frdmk64f/shell_boot/kds/.cproject | 344 - .../boards/frdmk64f/shell_boot/kds/.project | 2425 --- .../shell_boot_frdmk64f debug cmsisdap.launch | 62 - .../shell_boot_frdmk64f debug jlink.launch | 80 - .../shell_boot_frdmk64f debug pne.launch | 200 - ...hell_boot_frdmk64f release cmsisdap.launch | 62 - .../shell_boot_frdmk64f release jlink.launch | 80 - .../shell_boot_frdmk64f release pne.launch | 200 - .../shell_boot/kds/shell_boot_frdmk64f.wsd | 9 - .../shell_freertos/iar/shell_freertos.ewd | 11050 -------------- .../shell_freertos/iar/shell_freertos.ewp | 2863 ---- .../shell_freertos/iar/shell_freertos.eww | 33 - .../frdmk64f/shell_freertos/kds/.cproject | 352 - .../frdmk64f/shell_freertos/kds/.project | 2685 ---- ...ll_freertos_frdmk64f debug cmsisdap.launch | 62 - ...shell_freertos_frdmk64f debug jlink.launch | 80 - .../shell_freertos_frdmk64f debug pne.launch | 200 - ..._freertos_frdmk64f release cmsisdap.launch | 62 - ...ell_freertos_frdmk64f release jlink.launch | 80 - ...shell_freertos_frdmk64f release pne.launch | 200 - .../kds/shell_freertos_frdmk64f.wsd | 9 - .../iar/shell_freertos_wifi_qca.ewd | 11050 -------------- .../iar/shell_freertos_wifi_qca.ewp | 3347 ----- .../iar/shell_freertos_wifi_qca.eww | 33 - .../shell_freertos_wifi_qca/kds/.cproject | 392 - .../shell_freertos_wifi_qca/kds/.project | 2260 --- ...os_wifi_qca_frdmk64f debug cmsisdap.launch | 62 - ...ertos_wifi_qca_frdmk64f debug jlink.launch | 80 - ...reertos_wifi_qca_frdmk64f debug pne.launch | 200 - ..._wifi_qca_frdmk64f release cmsisdap.launch | 62 - ...tos_wifi_qca_frdmk64f release jlink.launch | 80 - ...ertos_wifi_qca_frdmk64f release pne.launch | 200 - .../kds/shell_freertos_wifi_qca_frdmk64f.wsd | 9 - .../shell_mbedtls/iar/shell_mbedtls.ewd | 11050 -------------- .../shell_mbedtls/iar/shell_mbedtls.ewp | 3198 ---- .../shell_mbedtls/iar/shell_mbedtls.eww | 33 - .../frdmk64f/shell_mbedtls/kds/.cproject | 348 - .../frdmk64f/shell_mbedtls/kds/.project | 2085 --- ...ell_mbedtls_frdmk64f debug cmsisdap.launch | 62 - .../shell_mbedtls_frdmk64f debug jlink.launch | 80 - .../shell_mbedtls_frdmk64f debug pne.launch | 200 - ...l_mbedtls_frdmk64f release cmsisdap.launch | 62 - ...hell_mbedtls_frdmk64f release jlink.launch | 80 - .../shell_mbedtls_frdmk64f release pne.launch | 200 - .../kds/shell_mbedtls_frdmk64f.wsd | 9 - .../boards/frdmk66f/bench/iar/bench.ewd | 11050 -------------- .../boards/frdmk66f/bench/iar/bench.ewp | 2764 ---- .../boards/frdmk66f/bench/iar/bench.eww | 33 - .../boards/frdmk66f/bench/kds/.cproject | 342 - fnet_demos/boards/frdmk66f/bench/kds/.project | 2425 --- .../bench_frdmk66f debug jlink.launch | 80 - .../Settings/bench_frdmk66f debug pne.launch | 200 - .../bench_frdmk66f release jlink.launch | 80 - .../bench_frdmk66f release pne.launch | 200 - .../frdmk66f/bench/kds/bench_frdmk66f.wsd | 9 - fnet_demos/boards/frdmk66f/boot/iar/boot.ewd | 11050 -------------- fnet_demos/boards/frdmk66f/boot/iar/boot.ewp | 2764 ---- fnet_demos/boards/frdmk66f/boot/iar/boot.eww | 33 - fnet_demos/boards/frdmk66f/boot/kds/.cproject | 342 - fnet_demos/boards/frdmk66f/boot/kds/.project | 2425 --- .../Settings/boot_frdmk66f debug jlink.launch | 80 - .../Settings/boot_frdmk66f debug pne.launch | 200 - .../boot_frdmk66f release jlink.launch | 80 - .../Settings/boot_frdmk66f release pne.launch | 200 - .../frdmk66f/boot/kds/boot_frdmk66f.wsd | 9 - .../boards/frdmk66f/shell/iar/shell.ewd | 11050 -------------- .../boards/frdmk66f/shell/iar/shell.ewp | 2764 ---- .../boards/frdmk66f/shell/iar/shell.eww | 33 - .../boards/frdmk66f/shell/kds/.cproject | 342 - fnet_demos/boards/frdmk66f/shell/kds/.project | 2425 --- .../shell_frdmk66f debug jlink.launch | 80 - .../Settings/shell_frdmk66f debug pne.launch | 200 - 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.../shell_freertos_frdmk66f debug pne.launch | 200 - ...ell_freertos_frdmk66f release jlink.launch | 80 - ...shell_freertos_frdmk66f release pne.launch | 200 - .../kds/shell_freertos_frdmk66f.wsd | 9 - .../shell_mbedtls/iar/shell_mbedtls.ewd | 11050 -------------- .../shell_mbedtls/iar/shell_mbedtls.ewp | 3196 ---- .../shell_mbedtls/iar/shell_mbedtls.eww | 33 - .../frdmk66f/shell_mbedtls/kds/.cproject | 346 - .../frdmk66f/shell_mbedtls/kds/.project | 3815 ----- .../shell_mbedtls_frdmk66f debug jlink.launch | 80 - .../shell_mbedtls_frdmk66f debug pne.launch | 200 - ...hell_mbedtls_frdmk66f release jlink.launch | 80 - .../shell_mbedtls_frdmk66f release pne.launch | 200 - .../kds/shell_mbedtls_frdmk66f.wsd | 9 - .../boards/twrk60d100m/bench/iar/bench.ewd | 11050 -------------- .../boards/twrk60d100m/bench/iar/bench.ewp | 2756 ---- .../boards/twrk60d100m/bench/iar/bench.eww | 33 - .../boards/twrk60d100m/bench/kds/.cproject | 342 - .../boards/twrk60d100m/bench/kds/.project | 2425 --- .../bench_twrk60d100m debug jlink.launch | 80 - .../bench_twrk60d100m debug pne.launch | 199 - .../bench_twrk60d100m release jlink.launch | 80 - .../bench_twrk60d100m release pne.launch | 199 - .../bench/kds/bench_twrk60d100m.wsd | 9 - .../boards/twrk60d100m/boot/iar/boot.ewd | 11050 -------------- .../boards/twrk60d100m/boot/iar/boot.ewp | 2756 ---- .../boards/twrk60d100m/boot/iar/boot.eww | 33 - .../boards/twrk60d100m/boot/kds/.cproject | 342 - .../boards/twrk60d100m/boot/kds/.project | 2425 --- .../boot_twrk60d100m debug jlink.launch | 80 - .../boot_twrk60d100m debug pne.launch | 199 - .../boot_twrk60d100m release jlink.launch | 80 - .../boot_twrk60d100m release pne.launch | 199 - .../twrk60d100m/boot/kds/boot_twrk60d100m.wsd | 9 - .../boards/twrk60d100m/shell/iar/shell.ewd | 11050 -------------- .../boards/twrk60d100m/shell/iar/shell.ewp | 2756 ---- .../boards/twrk60d100m/shell/iar/shell.eww | 33 - .../boards/twrk60d100m/shell/kds/.cproject | 342 - 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fnet_demos/build/frdmk64f/bench/kds/.cproject | 179 + fnet_demos/build/frdmk64f/bench/kds/.project | 26 + ...h_frdmk64f int flash debug cmsisdap.launch | 61 + ...ench_frdmk64f int flash debug jlink.launch | 72 + .../bench_frdmk64f int flash debug pne.launch | 200 + ...frdmk64f int flash release cmsisdap.launch | 61 + ...ch_frdmk64f int flash release jlink.launch | 72 + ...ench_frdmk64f int flash release pne.launch | 200 + .../frdmk64f/bench/kds/bench_frdmk64f.wsd | 9 + .../build/frdmk64f/bench/kds/makedir.bat | 4 + .../build/frdmk64f/boot/iar/boot-frdmk64f.ewd | 2834 ++++ .../build/frdmk64f/boot/iar/boot-frdmk64f.ewp | 2032 +++ .../build/frdmk64f/boot/iar/boot-frdmk64f.eww | 3 + fnet_demos/build/frdmk64f/boot/kds/.cproject | 179 + fnet_demos/build/frdmk64f/boot/kds/.project | 26 + ...t_frdmk64f int flash debug cmsisdap.launch | 61 + ...boot_frdmk64f int flash debug jlink.launch | 72 + .../boot_frdmk64f int flash debug pne.launch | 200 + ...frdmk64f int flash release cmsisdap.launch | 61 + ...ot_frdmk64f int flash release jlink.launch | 72 + ...boot_frdmk64f int flash release pne.launch | 200 + .../build/frdmk64f/boot/kds/boot_frdmk64f.wsd | 9 + .../build/frdmk64f/boot/kds/makedir.bat | 4 + .../frdmk64f/shell/iar/shell-frdmk64f.ewd | 2834 ++++ .../frdmk64f/shell/iar/shell-frdmk64f.ewp | 2032 +++ .../frdmk64f/shell/iar/shell-frdmk64f.eww | 3 + fnet_demos/build/frdmk64f/shell/kds/.cproject | 179 + fnet_demos/build/frdmk64f/shell/kds/.project | 26 + .../build/frdmk64f/shell/kds/makedir.bat | 4 + ...l_frdmk64f int flash debug cmsisdap.launch | 61 + ...hell_frdmk64f int flash debug jlink.launch | 72 + .../shell_frdmk64f int flash debug pne.launch | 200 + ...frdmk64f int flash release cmsisdap.launch | 61 + ...ll_frdmk64f int flash release jlink.launch | 72 + ...hell_frdmk64f int flash release pne.launch | 200 + .../frdmk64f/shell/kds/shell_frdmk64f.wsd | 9 + .../shell_boot/iar/shell_boot-frdmk64f.ewd | 2834 ++++ .../shell_boot/iar/shell_boot-frdmk64f.ewp | 2032 +++ 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pne.launch | 200 + ...frdmk64f int flash release cmsisdap.launch | 61 + ...os_frdmk64f int flash release jlink.launch | 72 + ...rtos_frdmk64f int flash release pne.launch | 200 + .../kds/shell_freertos_frdmk64f.wsd | 9 + .../iar/shell_freertos_wifi_qca-frdmk64f.ewd | 2834 ++++ .../iar/shell_freertos_wifi_qca-frdmk64f.ewp | 2032 +++ .../iar/shell_freertos_wifi_qca-frdmk64f.eww | 3 + .../shell_freertos_wifi_qca/kds/.cproject | 179 + .../shell_freertos_wifi_qca/kds/.project | 26 + .../shell_freertos_wifi_qca/kds/makedir.bat | 4 + ...a_frdmk64f int flash debug cmsisdap.launch | 61 + ..._qca_frdmk64f int flash debug jlink.launch | 72 + ...fi_qca_frdmk64f int flash debug pne.launch | 200 + ...frdmk64f int flash release cmsisdap.launch | 61 + ...ca_frdmk64f int flash release jlink.launch | 72 + ..._qca_frdmk64f int flash release pne.launch | 200 + .../kds/shell_freertos_wifi_qca_frdmk64f.wsd | 9 + .../iar/shell_mbedtls-frdmk64f.ewd | 2834 ++++ .../iar/shell_mbedtls-frdmk64f.ewp | 2032 +++ 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release cmsisdap.launch | 61 + ...ch_frdmk66f int flash release jlink.launch | 72 + ...ench_frdmk66f int flash release pne.launch | 200 + .../frdmk66f/bench/kds/bench_frdmk66f.wsd | 9 + .../build/frdmk66f/bench/kds/makedir.bat | 4 + .../build/frdmk66f/boot/iar/boot-frdmk66f.ewd | 2834 ++++ .../build/frdmk66f/boot/iar/boot-frdmk66f.ewp | 2032 +++ .../build/frdmk66f/boot/iar/boot-frdmk66f.eww | 3 + fnet_demos/build/frdmk66f/boot/kds/.cproject | 179 + fnet_demos/build/frdmk66f/boot/kds/.project | 26 + ...t_frdmk66f int flash debug cmsisdap.launch | 61 + ...boot_frdmk66f int flash debug jlink.launch | 72 + .../boot_frdmk66f int flash debug pne.launch | 200 + ...frdmk66f int flash release cmsisdap.launch | 61 + ...ot_frdmk66f int flash release jlink.launch | 72 + ...boot_frdmk66f int flash release pne.launch | 200 + .../build/frdmk66f/boot/kds/boot_frdmk66f.wsd | 9 + .../build/frdmk66f/boot/kds/makedir.bat | 4 + .../frdmk66f/shell/iar/shell-frdmk66f.ewd | 2834 ++++ .../frdmk66f/shell/iar/shell-frdmk66f.ewp | 2032 +++ .../frdmk66f/shell/iar/shell-frdmk66f.eww | 3 + fnet_demos/build/frdmk66f/shell/kds/.cproject | 179 + fnet_demos/build/frdmk66f/shell/kds/.project | 26 + .../build/frdmk66f/shell/kds/makedir.bat | 4 + ...l_frdmk66f int flash debug cmsisdap.launch | 61 + ...hell_frdmk66f int flash debug jlink.launch | 72 + .../shell_frdmk66f int flash debug pne.launch | 200 + ...frdmk66f int flash release cmsisdap.launch | 61 + ...ll_frdmk66f int flash release jlink.launch | 72 + ...hell_frdmk66f int flash release pne.launch | 200 + .../frdmk66f/shell/kds/shell_frdmk66f.wsd | 9 + .../shell_boot/iar/shell_boot-frdmk66f.ewd | 2834 ++++ .../shell_boot/iar/shell_boot-frdmk66f.ewp | 2032 +++ .../shell_boot/iar/shell_boot-frdmk66f.eww | 3 + .../build/frdmk66f/shell_boot/kds/.cproject | 179 + .../build/frdmk66f/shell_boot/kds/.project | 26 + .../build/frdmk66f/shell_boot/kds/makedir.bat | 4 + ...t_frdmk66f int flash debug cmsisdap.launch | 61 + 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.../common/startup/LPC54628/fsl_flexcomm.h | 75 + fnet_demos/common/startup/LPC54628/fsl_gpio.c | 77 + fnet_demos/common/startup/LPC54628/fsl_gpio.h | 351 + .../common/startup/LPC54628/fsl_inputmux.c | 66 + .../common/startup/LPC54628/fsl_inputmux.h | 104 + .../LPC54628/fsl_inputmux_connections.h | 216 + .../common/startup/LPC54628/fsl_iocon.h | 178 + fnet_demos/common/startup/LPC54628/fsl_pint.c | 467 + fnet_demos/common/startup/LPC54628/fsl_pint.h | 568 + .../common/startup/LPC54628/fsl_power.c | 38 + .../common/startup/LPC54628/fsl_power.h | 251 + .../common/startup/LPC54628/fsl_reset.c | 126 + .../common/startup/LPC54628/fsl_reset.h | 297 + fnet_demos/common/startup/LPC54628/fsl_spi.c | 854 ++ fnet_demos/common/startup/LPC54628/fsl_spi.h | 736 + .../common/startup/LPC54628/fsl_spi_dma.c | 525 + .../common/startup/LPC54628/fsl_spi_dma.h | 224 + .../common/startup/LPC54628/fsl_usart.c | 708 + .../common/startup/LPC54628/fsl_usart.h | 663 + .../LPC54628/iar/LPC54628J512_flash_fnet.icf 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a/fnet_demos/boards/frdmk64f/shell_boot/iar/shell_boot.eww +++ /dev/null @@ -1,33 +0,0 @@ - - - - - all - - shell_boot - Release - - - shell_boot - Debug - - - - Release - - shell_boot - Release - - - - Debug - - shell_boot - Debug - - - - - $WS_DIR$/shell_boot.ewp - - diff --git a/fnet_demos/boards/frdmk64f/shell_boot/kds/.cproject b/fnet_demos/boards/frdmk64f/shell_boot/kds/.cproject deleted file mode 100644 index a1b074bd..00000000 --- a/fnet_demos/boards/frdmk64f/shell_boot/kds/.cproject +++ /dev/null @@ -1,344 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fnet_demos/boards/frdmk64f/shell_boot/kds/.project b/fnet_demos/boards/frdmk64f/shell_boot/kds/.project deleted file mode 100644 index 1cd6cc88..00000000 --- a/fnet_demos/boards/frdmk64f/shell_boot/kds/.project +++ /dev/null @@ -1,2425 +0,0 @@ - - - shell_boot_frdmk64f - - - - - - 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b2be9c3f..00000000 --- a/fnet_demos/boards/frdmk66f/shell_boot/kds/.cproject +++ /dev/null @@ -1,342 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fnet_demos/boards/frdmk66f/shell_boot/kds/.project b/fnet_demos/boards/frdmk66f/shell_boot/kds/.project deleted file mode 100644 index be4218c0..00000000 --- a/fnet_demos/boards/frdmk66f/shell_boot/kds/.project +++ /dev/null @@ -1,2425 +0,0 @@ - - - shell_boot_frdmk66f - - - - - - com.freescale.processorexpert.core.expertprojectbuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - com.freescale.processorexpert.core.expertprojectnature - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - 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a/fnet_demos/boards/frdmk66f/shell_mbedtls/kds/Settings/shell_mbedtls_frdmk66f debug pne.launch b/fnet_demos/boards/frdmk66f/shell_mbedtls/kds/Settings/shell_mbedtls_frdmk66f debug pne.launch deleted file mode 100644 index 3e03e07e..00000000 --- a/fnet_demos/boards/frdmk66f/shell_mbedtls/kds/Settings/shell_mbedtls_frdmk66f debug pne.launch +++ /dev/null @@ -1,200 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fnet_demos/boards/frdmk66f/shell_mbedtls/kds/Settings/shell_mbedtls_frdmk66f release jlink.launch b/fnet_demos/boards/frdmk66f/shell_mbedtls/kds/Settings/shell_mbedtls_frdmk66f release jlink.launch deleted file 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a/fnet_demos/boards/twrk60d100m/boot/kds/.cproject +++ /dev/null @@ -1,342 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fnet_demos/boards/twrk60d100m/boot/kds/.project b/fnet_demos/boards/twrk60d100m/boot/kds/.project deleted file mode 100644 index c7f782be..00000000 --- a/fnet_demos/boards/twrk60d100m/boot/kds/.project +++ /dev/null @@ -1,2425 +0,0 @@ - - - boot_twrk60d100m - - - - - - com.freescale.processorexpert.core.expertprojectbuilder - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - com.freescale.processorexpert.core.expertprojectnature - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - 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diff --git a/fnet_demos/build/frdmk64f/bench/iar/bench-frdmk64f.eww b/fnet_demos/build/frdmk64f/bench/iar/bench-frdmk64f.eww new file mode 100644 index 00000000..73cb23a1 --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/iar/bench-frdmk64f.eww @@ -0,0 +1,3 @@ + + +intflash-debugbench-frdmk64fint flash debugintflash-releasebench-frdmk64fint flash release$WS_DIR$\bench-frdmk64f.ewp diff --git a/fnet_demos/build/frdmk64f/bench/kds/.cproject b/fnet_demos/build/frdmk64f/bench/kds/.cproject new file mode 100644 index 00000000..e39cc70b --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/bench/kds/.project b/fnet_demos/build/frdmk64f/bench/kds/.project new file mode 100644 index 00000000..a6bcdbb1 --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/kds/.project @@ -0,0 +1,26 @@ + + + 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k/stack2virtual:/virtualfnet_stack/stack/fnet_netif_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_netif_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_prot.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_prot.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_prot.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_prot.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_raw.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_raw.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_raw.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_raw.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_socket.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_socket.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_socket.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_socket.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_socket_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_socket_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_config.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_config.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi_prv.hfnet_application2virtual:/virtualfnet_application/fapp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.cfnet_application2virtual:/virtualfnet_application/fapp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.hfnet_application2virtual:/virtualfnet_application/fapp_autoip.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.cfnet_application2virtual:/virtualfnet_application/fapp_autoip.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.hfnet_application2virtual:/virtualfnet_application/fapp_bench.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.cfnet_application2virtual:/virtualfnet_application/fapp_bench.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.hfnet_application2virtual:/virtualfnet_application/fapp_config.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_config.hfnet_application2virtual:/virtualfnet_application/fapp_dhcp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.cfnet_application2virtual:/virtualfnet_application/fapp_dhcp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.hfnet_application2virtual:/virtualfnet_application/fapp_dns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.cfnet_application2virtual:/virtualfnet_application/fapp_dns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.hfnet_application2virtual:/virtualfnet_application/fapp_fs.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.cfnet_application2virtual:/virtualfnet_application/fapp_fs.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.hfnet_application2virtual:/virtualfnet_application/fapp_fs_image.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs_image.cfnet_application2virtual:/virtualfnet_application/fapp_http.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.cfnet_application2virtual:/virtualfnet_application/fapp_http.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.hfnet_application2virtual:/virtualfnet_application/fapp_link.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.cfnet_application2virtual:/virtualfnet_application/fapp_link.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.hfnet_application2virtual:/virtualfnet_application/fapp_llmnr.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.cfnet_application2virtual:/virtualfnet_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK64F12.S1PARENT-4-PROJECT_LOC/common/startup/MK64F12/gcc/startup_MK64F12.S diff --git a/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash debug cmsisdap.launch new file mode 100644 index 00000000..27218b59 --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash debug jlink.launch b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash debug jlink.launch new file mode 100644 index 00000000..e4a2b35f --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash debug pne.launch b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash debug pne.launch new file mode 100644 index 00000000..032c135f --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash release cmsisdap.launch b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash release cmsisdap.launch new file mode 100644 index 00000000..1556e76d --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash release jlink.launch b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash release jlink.launch new file mode 100644 index 00000000..7eb517d1 --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash release pne.launch b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash release pne.launch new file mode 100644 index 00000000..fb90d431 --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f.wsd b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f.wsd new file mode 100644 index 00000000..c0456b5c --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/kds/bench_frdmk64f.wsd @@ -0,0 +1,9 @@ + + + + bench_frdmk64ftrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/frdmk64f/bench/kds/makedir.bat b/fnet_demos/build/frdmk64f/bench/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk64f/bench/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk64f/boot/iar/boot-frdmk64f.ewd b/fnet_demos/build/frdmk64f/boot/iar/boot-frdmk64f.ewd new file mode 100644 index 00000000..6b6d33fa --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/iar/boot-frdmk64f.ewd @@ -0,0 +1,2834 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + int flash release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/fnet_demos/build/frdmk64f/boot/iar/boot-frdmk64f.ewp b/fnet_demos/build/frdmk64f/boot/iar/boot-frdmk64f.ewp new file mode 100644 index 00000000..f8dccbf0 --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/iar/boot-frdmk64f.ewp @@ -0,0 +1,2032 @@ + + + 3 + + int flash debug + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + int flash release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + 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diff --git a/fnet_demos/build/frdmk64f/boot/iar/boot-frdmk64f.eww b/fnet_demos/build/frdmk64f/boot/iar/boot-frdmk64f.eww new file mode 100644 index 00000000..38ac9236 --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/iar/boot-frdmk64f.eww @@ -0,0 +1,3 @@ + + +intflash-debugboot-frdmk64fint flash debugintflash-releaseboot-frdmk64fint flash release$WS_DIR$\boot-frdmk64f.ewp diff --git a/fnet_demos/build/frdmk64f/boot/kds/.cproject b/fnet_demos/build/frdmk64f/boot/kds/.cproject new file mode 100644 index 00000000..3d1d5b84 --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/boot/kds/.project b/fnet_demos/build/frdmk64f/boot/kds/.project new file mode 100644 index 00000000..53b24fbf --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/kds/.project @@ -0,0 +1,26 @@ + + + boot_frdmk64f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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net_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK64F12.S1PARENT-4-PROJECT_LOC/common/startup/MK64F12/gcc/startup_MK64F12.S diff --git a/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash debug cmsisdap.launch new file mode 100644 index 00000000..dbb23a48 --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash debug jlink.launch b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash debug jlink.launch new file mode 100644 index 00000000..04cf564b --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash debug pne.launch b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash debug pne.launch new file mode 100644 index 00000000..33069f97 --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash release cmsisdap.launch b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash release cmsisdap.launch new file mode 100644 index 00000000..7a5819d3 --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash release jlink.launch b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash release jlink.launch new file mode 100644 index 00000000..b6c64118 --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash release pne.launch b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash release pne.launch new file mode 100644 index 00000000..8e935e44 --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f.wsd b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f.wsd new file mode 100644 index 00000000..78eddc83 --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/kds/boot_frdmk64f.wsd @@ -0,0 +1,9 @@ + + + + boot_frdmk64ftrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/frdmk64f/boot/kds/makedir.bat b/fnet_demos/build/frdmk64f/boot/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk64f/boot/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk64f/shell/iar/shell-frdmk64f.ewd b/fnet_demos/build/frdmk64f/shell/iar/shell-frdmk64f.ewd new file mode 100644 index 00000000..6b6d33fa --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/iar/shell-frdmk64f.ewd @@ -0,0 +1,2834 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + int flash release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/fnet_demos/build/frdmk64f/shell/iar/shell-frdmk64f.ewp b/fnet_demos/build/frdmk64f/shell/iar/shell-frdmk64f.ewp new file mode 100644 index 00000000..0c748682 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/iar/shell-frdmk64f.ewp @@ -0,0 +1,2032 @@ + + + 3 + + int flash debug + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + int flash release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 0 + + + + + + + + + + + + + + + + + + + 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diff --git a/fnet_demos/build/frdmk64f/shell/iar/shell-frdmk64f.eww b/fnet_demos/build/frdmk64f/shell/iar/shell-frdmk64f.eww new file mode 100644 index 00000000..3f1dee43 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/iar/shell-frdmk64f.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell-frdmk64fint flash debugintflash-releaseshell-frdmk64fint flash release$WS_DIR$\shell-frdmk64f.ewp diff --git a/fnet_demos/build/frdmk64f/shell/kds/.cproject b/fnet_demos/build/frdmk64f/shell/kds/.cproject new file mode 100644 index 00000000..498e24a0 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell/kds/.project b/fnet_demos/build/frdmk64f/shell/kds/.project new file mode 100644 index 00000000..337d6aef --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/kds/.project @@ -0,0 +1,26 @@ + + + shell_frdmk64f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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k/stack2virtual:/virtualfnet_stack/stack/fnet_netif_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_netif_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_prot.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_prot.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_prot.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_prot.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_raw.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_raw.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_raw.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_raw.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_socket.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_socket.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_socket.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_socket.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_socket_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_socket_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_config.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_config.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi_prv.hfnet_application2virtual:/virtualfnet_application/fapp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.cfnet_application2virtual:/virtualfnet_application/fapp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.hfnet_application2virtual:/virtualfnet_application/fapp_autoip.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.cfnet_application2virtual:/virtualfnet_application/fapp_autoip.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.hfnet_application2virtual:/virtualfnet_application/fapp_bench.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.cfnet_application2virtual:/virtualfnet_application/fapp_bench.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.hfnet_application2virtual:/virtualfnet_application/fapp_config.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_config.hfnet_application2virtual:/virtualfnet_application/fapp_dhcp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.cfnet_application2virtual:/virtualfnet_application/fapp_dhcp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.hfnet_application2virtual:/virtualfnet_application/fapp_dns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.cfnet_application2virtual:/virtualfnet_application/fapp_dns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.hfnet_application2virtual:/virtualfnet_application/fapp_fs.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.cfnet_application2virtual:/virtualfnet_application/fapp_fs.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.hfnet_application2virtual:/virtualfnet_application/fapp_fs_image.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs_image.cfnet_application2virtual:/virtualfnet_application/fapp_http.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.cfnet_application2virtual:/virtualfnet_application/fapp_http.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.hfnet_application2virtual:/virtualfnet_application/fapp_link.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.cfnet_application2virtual:/virtualfnet_application/fapp_link.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.hfnet_application2virtual:/virtualfnet_application/fapp_llmnr.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.cfnet_application2virtual:/virtualfnet_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK64F12.S1PARENT-4-PROJECT_LOC/common/startup/MK64F12/gcc/startup_MK64F12.S diff --git a/fnet_demos/build/frdmk64f/shell/kds/makedir.bat b/fnet_demos/build/frdmk64f/shell/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash debug cmsisdap.launch new file mode 100644 index 00000000..06b1361a --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash debug jlink.launch b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash debug jlink.launch new file mode 100644 index 00000000..85cd58b2 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash debug pne.launch b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash debug pne.launch new file mode 100644 index 00000000..7650b782 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash release cmsisdap.launch b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash release cmsisdap.launch new file mode 100644 index 00000000..745171d1 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash release jlink.launch b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash release jlink.launch new file mode 100644 index 00000000..d528d0da --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash release pne.launch b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash release pne.launch new file mode 100644 index 00000000..596569ae --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f.wsd b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f.wsd new file mode 100644 index 00000000..648dcb59 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell/kds/shell_frdmk64f.wsd @@ -0,0 +1,9 @@ + + + + shell_frdmk64ftrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_boot/iar/shell_boot-frdmk64f.ewd b/fnet_demos/build/frdmk64f/shell_boot/iar/shell_boot-frdmk64f.ewd new file mode 100644 index 00000000..6b6d33fa --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/iar/shell_boot-frdmk64f.ewd @@ -0,0 +1,2834 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 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$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + int flash release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/fnet_demos/build/frdmk64f/shell_boot/iar/shell_boot-frdmk64f.ewp b/fnet_demos/build/frdmk64f/shell_boot/iar/shell_boot-frdmk64f.ewp new file mode 100644 index 00000000..90034b31 --- /dev/null +++ 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diff --git a/fnet_demos/build/frdmk64f/shell_boot/iar/shell_boot-frdmk64f.eww b/fnet_demos/build/frdmk64f/shell_boot/iar/shell_boot-frdmk64f.eww new file mode 100644 index 00000000..8219c611 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/iar/shell_boot-frdmk64f.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell_boot-frdmk64fint flash debugintflash-releaseshell_boot-frdmk64fint flash release$WS_DIR$\shell_boot-frdmk64f.ewp diff --git a/fnet_demos/build/frdmk64f/shell_boot/kds/.cproject b/fnet_demos/build/frdmk64f/shell_boot/kds/.cproject new file mode 100644 index 00000000..700790e8 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_boot/kds/.project b/fnet_demos/build/frdmk64f/shell_boot/kds/.project new file mode 100644 index 00000000..8a9ca21c --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/kds/.project @@ -0,0 +1,26 @@ + + + shell_boot_frdmk64f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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etif.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_netif_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_netif_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_prot.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_prot.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_prot.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_prot.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_raw.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_raw.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_raw.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_raw.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_socket.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_socket.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_socket.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_socket.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_socket_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_socket_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_config.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_config.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi_prv.hfnet_application2virtual:/virtualfnet_application/fapp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.cfnet_application2virtual:/virtualfnet_application/fapp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.hfnet_application2virtual:/virtualfnet_application/fapp_autoip.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.cfnet_application2virtual:/virtualfnet_application/fapp_autoip.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.hfnet_application2virtual:/virtualfnet_application/fapp_bench.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.cfnet_application2virtual:/virtualfnet_application/fapp_bench.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.hfnet_application2virtual:/virtualfnet_application/fapp_config.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_config.hfnet_application2virtual:/virtualfnet_application/fapp_dhcp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.cfnet_application2virtual:/virtualfnet_application/fapp_dhcp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.hfnet_application2virtual:/virtualfnet_application/fapp_dns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.cfnet_application2virtual:/virtualfnet_application/fapp_dns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.hfnet_application2virtual:/virtualfnet_application/fapp_fs.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.cfnet_application2virtual:/virtualfnet_application/fapp_fs.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.hfnet_application2virtual:/virtualfnet_application/fapp_fs_image.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs_image.cfnet_application2virtual:/virtualfnet_application/fapp_http.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.cfnet_application2virtual:/virtualfnet_application/fapp_http.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.hfnet_application2virtual:/virtualfnet_application/fapp_link.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.cfnet_application2virtual:/virtualfnet_application/fapp_link.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.hfnet_application2virtual:/virtualfnet_application/fapp_llmnr.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.cfnet_application2virtual:/virtualfnet_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK64F12.S1PARENT-4-PROJECT_LOC/common/startup/MK64F12/gcc/startup_MK64F12.S diff --git a/fnet_demos/build/frdmk64f/shell_boot/kds/makedir.bat b/fnet_demos/build/frdmk64f/shell_boot/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash debug cmsisdap.launch new file mode 100644 index 00000000..525c149d --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash debug jlink.launch b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash debug jlink.launch new file mode 100644 index 00000000..e72b0278 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash debug pne.launch b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash debug pne.launch new file mode 100644 index 00000000..f2f00b2b --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash release cmsisdap.launch b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash release cmsisdap.launch new file mode 100644 index 00000000..e0460e1f --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash release jlink.launch b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash release jlink.launch new file mode 100644 index 00000000..07704935 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash release pne.launch b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash release pne.launch new file mode 100644 index 00000000..2822efd2 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f.wsd b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f.wsd new file mode 100644 index 00000000..9e038110 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_boot/kds/shell_boot_frdmk64f.wsd @@ -0,0 +1,9 @@ + + + + shell_boot_frdmk64ftrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos/iar/shell_freertos-frdmk64f.ewd b/fnet_demos/build/frdmk64f/shell_freertos/iar/shell_freertos-frdmk64f.ewd new file mode 100644 index 00000000..6b6d33fa --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/iar/shell_freertos-frdmk64f.ewd @@ -0,0 +1,2834 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + int flash release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + 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$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos/iar/shell_freertos-frdmk64f.ewp b/fnet_demos/build/frdmk64f/shell_freertos/iar/shell_freertos-frdmk64f.ewp new file mode 100644 index 00000000..7d9fbf16 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/iar/shell_freertos-frdmk64f.ewp @@ -0,0 +1,2032 @@ + + + 3 + + int flash debug + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + 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diff --git a/fnet_demos/build/frdmk64f/shell_freertos/iar/shell_freertos-frdmk64f.eww b/fnet_demos/build/frdmk64f/shell_freertos/iar/shell_freertos-frdmk64f.eww new file mode 100644 index 00000000..813dbf46 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/iar/shell_freertos-frdmk64f.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell_freertos-frdmk64fint flash debugintflash-releaseshell_freertos-frdmk64fint flash release$WS_DIR$\shell_freertos-frdmk64f.ewp diff --git a/fnet_demos/build/frdmk64f/shell_freertos/kds/.cproject b/fnet_demos/build/frdmk64f/shell_freertos/kds/.cproject new file mode 100644 index 00000000..c50b541d --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos/kds/.project b/fnet_demos/build/frdmk64f/shell_freertos/kds/.project new file mode 100644 index 00000000..3a0471dc --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/kds/.project @@ -0,0 +1,26 @@ + + + shell_freertos_frdmk64f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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diff --git a/fnet_demos/build/frdmk64f/shell_freertos/kds/makedir.bat b/fnet_demos/build/frdmk64f/shell_freertos/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash debug cmsisdap.launch new file mode 100644 index 00000000..39134d64 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash debug jlink.launch b/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash debug jlink.launch new file mode 100644 index 00000000..65e18920 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash debug pne.launch b/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash debug pne.launch new file mode 100644 index 00000000..8cd3fb6b --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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100644 index 00000000..e4af3498 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash release pne.launch b/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash release pne.launch new file mode 100644 index 00000000..bc4f6bb2 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos/kds/shell_freertos_frdmk64f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/iar/shell_freertos_wifi_qca-frdmk64f.eww b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/iar/shell_freertos_wifi_qca-frdmk64f.eww new file mode 100644 index 00000000..54fbc3a1 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/iar/shell_freertos_wifi_qca-frdmk64f.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell_freertos_wifi_qca-frdmk64fint flash debugintflash-releaseshell_freertos_wifi_qca-frdmk64fint flash release$WS_DIR$\shell_freertos_wifi_qca-frdmk64f.ewp diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/.cproject b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/.cproject new file mode 100644 index 00000000..a9b2608f --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/.project b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/.project new file mode 100644 index 00000000..64b4dd1f --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/.project @@ -0,0 +1,26 @@ + + + shell_freertos_wifi_qca_frdmk64f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/makedir.bat b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash debug cmsisdap.launch new file mode 100644 index 00000000..c2863de5 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash debug jlink.launch b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash debug jlink.launch new file mode 100644 index 00000000..6b39a082 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash debug pne.launch b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash debug pne.launch new file mode 100644 index 00000000..9bccf6f5 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash release cmsisdap.launch b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash release cmsisdap.launch new file mode 100644 index 00000000..bfb8dd83 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash release jlink.launch b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash release jlink.launch new file mode 100644 index 00000000..472c13e7 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash release pne.launch b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash release pne.launch new file mode 100644 index 00000000..371688c6 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f.wsd b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f.wsd new file mode 100644 index 00000000..a997e520 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_freertos_wifi_qca/kds/shell_freertos_wifi_qca_frdmk64f.wsd @@ -0,0 +1,9 @@ + + + + shell_freertos_wifi_qca_frdmk64ftrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_mbedtls/iar/shell_mbedtls-frdmk64f.ewd b/fnet_demos/build/frdmk64f/shell_mbedtls/iar/shell_mbedtls-frdmk64f.ewd new file mode 100644 index 00000000..6b6d33fa --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/iar/shell_mbedtls-frdmk64f.ewd @@ -0,0 +1,2834 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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diff --git a/fnet_demos/build/frdmk64f/shell_mbedtls/iar/shell_mbedtls-frdmk64f.eww b/fnet_demos/build/frdmk64f/shell_mbedtls/iar/shell_mbedtls-frdmk64f.eww new file mode 100644 index 00000000..e82ccf7d --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/iar/shell_mbedtls-frdmk64f.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell_mbedtls-frdmk64fint flash debugintflash-releaseshell_mbedtls-frdmk64fint flash release$WS_DIR$\shell_mbedtls-frdmk64f.ewp diff --git a/fnet_demos/build/frdmk64f/shell_mbedtls/kds/.cproject b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/.cproject new file mode 100644 index 00000000..d66f5423 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_mbedtls/kds/.project b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/.project new file mode 100644 index 00000000..65fa9fd8 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/.project @@ -0,0 +1,26 @@ + + + shell_mbedtls_frdmk64f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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diff --git a/fnet_demos/build/frdmk64f/shell_mbedtls/kds/makedir.bat b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash debug cmsisdap.launch new file mode 100644 index 00000000..918df18c --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash debug jlink.launch b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash debug jlink.launch new file mode 100644 index 00000000..fe9424fe --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash debug pne.launch b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash debug pne.launch new file mode 100644 index 00000000..80b90feb --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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--- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash release pne.launch b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash release pne.launch new file mode 100644 index 00000000..b0c48d38 --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f.wsd b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f.wsd new file mode 100644 index 00000000..6b634f6b --- /dev/null +++ b/fnet_demos/build/frdmk64f/shell_mbedtls/kds/shell_mbedtls_frdmk64f.wsd @@ -0,0 +1,9 @@ + + + + shell_mbedtls_frdmk64ftrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/frdmk66f/bench/iar/bench-frdmk66f.ewd b/fnet_demos/build/frdmk66f/bench/iar/bench-frdmk66f.ewd new file mode 100644 index 00000000..24c80613 --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/iar/bench-frdmk66f.ewd @@ -0,0 +1,2834 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + 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diff --git a/fnet_demos/build/frdmk66f/bench/iar/bench-frdmk66f.eww b/fnet_demos/build/frdmk66f/bench/iar/bench-frdmk66f.eww new file mode 100644 index 00000000..cab9f38e --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/iar/bench-frdmk66f.eww @@ -0,0 +1,3 @@ + + +intflash-debugbench-frdmk66fint flash debugintflash-releasebench-frdmk66fint flash release$WS_DIR$\bench-frdmk66f.ewp diff --git a/fnet_demos/build/frdmk66f/bench/kds/.cproject b/fnet_demos/build/frdmk66f/bench/kds/.cproject new file mode 100644 index 00000000..dd6c619d --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/bench/kds/.project b/fnet_demos/build/frdmk66f/bench/kds/.project new file mode 100644 index 00000000..1c687be1 --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/kds/.project @@ -0,0 +1,26 @@ + + + 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irtualfnet_stack/stack/fnet_stack_config.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_config.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi_prv.hfnet_application2virtual:/virtualfnet_application/fapp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.cfnet_application2virtual:/virtualfnet_application/fapp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.hfnet_application2virtual:/virtualfnet_application/fapp_autoip.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.cfnet_application2virtual:/virtualfnet_application/fapp_autoip.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.hfnet_application2virtual:/virtualfnet_application/fapp_bench.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.cfnet_application2virtual:/virtualfnet_application/fapp_bench.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.hfnet_application2virtual:/virtualfnet_application/fapp_config.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_config.hfnet_application2virtual:/virtualfnet_application/fapp_dhcp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.cfnet_application2virtual:/virtualfnet_application/fapp_dhcp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.hfnet_application2virtual:/virtualfnet_application/fapp_dns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.cfnet_application2virtual:/virtualfnet_application/fapp_dns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.hfnet_application2virtual:/virtualfnet_application/fapp_fs.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.cfnet_application2virtual:/virtualfnet_application/fapp_fs.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.hfnet_application2virtual:/virtualfnet_application/fapp_fs_image.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs_image.cfnet_application2virtual:/virtualfnet_application/fapp_http.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.cfnet_application2virtual:/virtualfnet_application/fapp_http.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.hfnet_application2virtual:/virtualfnet_application/fapp_link.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.cfnet_application2virtual:/virtualfnet_application/fapp_link.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.hfnet_application2virtual:/virtualfnet_application/fapp_llmnr.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.cfnet_application2virtual:/virtualfnet_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK66F18.S1PARENT-4-PROJECT_LOC/common/startup/MK66F18/gcc/startup_MK66F18.S diff --git a/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash debug cmsisdap.launch new file mode 100644 index 00000000..60a04edf --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash debug jlink.launch b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash debug jlink.launch new file mode 100644 index 00000000..4efbaeeb --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash debug pne.launch b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash debug pne.launch new file mode 100644 index 00000000..718ec6d6 --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash release cmsisdap.launch b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash release cmsisdap.launch new file mode 100644 index 00000000..9c5ff522 --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash release jlink.launch b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash release jlink.launch new file mode 100644 index 00000000..0dbe599e --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash release pne.launch b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash release pne.launch new file mode 100644 index 00000000..1060a1e4 --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f.wsd b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f.wsd new file mode 100644 index 00000000..430012e6 --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/kds/bench_frdmk66f.wsd @@ -0,0 +1,9 @@ + + + + bench_frdmk66ftrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/frdmk66f/bench/kds/makedir.bat b/fnet_demos/build/frdmk66f/bench/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk66f/bench/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk66f/boot/iar/boot-frdmk66f.ewd b/fnet_demos/build/frdmk66f/boot/iar/boot-frdmk66f.ewd new file mode 100644 index 00000000..24c80613 --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/iar/boot-frdmk66f.ewd @@ -0,0 +1,2834 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + int flash release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/fnet_demos/build/frdmk66f/boot/iar/boot-frdmk66f.ewp b/fnet_demos/build/frdmk66f/boot/iar/boot-frdmk66f.ewp new file mode 100644 index 00000000..9c77ad14 --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/iar/boot-frdmk66f.ewp @@ -0,0 +1,2032 @@ + + + 3 + + int flash debug + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + int flash release + + ARM + + 0 + + General + 3 + + 29 + 1 + 0 + + + + + + + + + + + + + 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diff --git a/fnet_demos/build/frdmk66f/boot/iar/boot-frdmk66f.eww b/fnet_demos/build/frdmk66f/boot/iar/boot-frdmk66f.eww new file mode 100644 index 00000000..e4af123b --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/iar/boot-frdmk66f.eww @@ -0,0 +1,3 @@ + + +intflash-debugboot-frdmk66fint flash debugintflash-releaseboot-frdmk66fint flash release$WS_DIR$\boot-frdmk66f.ewp diff --git a/fnet_demos/build/frdmk66f/boot/kds/.cproject b/fnet_demos/build/frdmk66f/boot/kds/.cproject new file mode 100644 index 00000000..d1688f44 --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/boot/kds/.project b/fnet_demos/build/frdmk66f/boot/kds/.project new file mode 100644 index 00000000..4ae0a8fc --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/kds/.project @@ -0,0 +1,26 @@ + + + boot_frdmk66f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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ualfnet_stack/stack/fnet_stack_config.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_config.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi_prv.hfnet_application2virtual:/virtualfnet_application/fapp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.cfnet_application2virtual:/virtualfnet_application/fapp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.hfnet_application2virtual:/virtualfnet_application/fapp_autoip.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.cfnet_application2virtual:/virtualfnet_application/fapp_autoip.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.hfnet_application2virtual:/virtualfnet_application/fapp_bench.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.cfnet_application2virtual:/virtualfnet_application/fapp_bench.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.hfnet_application2virtual:/virtualfnet_application/fapp_config.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_config.hfnet_application2virtual:/virtualfnet_application/fapp_dhcp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.cfnet_application2virtual:/virtualfnet_application/fapp_dhcp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.hfnet_application2virtual:/virtualfnet_application/fapp_dns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.cfnet_application2virtual:/virtualfnet_application/fapp_dns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.hfnet_application2virtual:/virtualfnet_application/fapp_fs.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.cfnet_application2virtual:/virtualfnet_application/fapp_fs.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.hfnet_application2virtual:/virtualfnet_application/fapp_fs_image.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs_image.cfnet_application2virtual:/virtualfnet_application/fapp_http.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.cfnet_application2virtual:/virtualfnet_application/fapp_http.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.hfnet_application2virtual:/virtualfnet_application/fapp_link.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.cfnet_application2virtual:/virtualfnet_application/fapp_link.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.hfnet_application2virtual:/virtualfnet_application/fapp_llmnr.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.cfnet_application2virtual:/virtualfnet_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK66F18.S1PARENT-4-PROJECT_LOC/common/startup/MK66F18/gcc/startup_MK66F18.S diff --git a/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash debug cmsisdap.launch new file mode 100644 index 00000000..772da22f --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash debug jlink.launch b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash debug jlink.launch new file mode 100644 index 00000000..9c20af36 --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash debug pne.launch b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash debug pne.launch new file mode 100644 index 00000000..854cfae6 --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash release cmsisdap.launch b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash release cmsisdap.launch new file mode 100644 index 00000000..48e7c376 --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash release jlink.launch b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash release jlink.launch new file mode 100644 index 00000000..652c5365 --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash release pne.launch b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash release pne.launch new file mode 100644 index 00000000..28e256cc --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f.wsd b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f.wsd new file mode 100644 index 00000000..81f4616a --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/kds/boot_frdmk66f.wsd @@ -0,0 +1,9 @@ + + + + boot_frdmk66ftrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/frdmk66f/boot/kds/makedir.bat b/fnet_demos/build/frdmk66f/boot/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk66f/boot/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk66f/shell/iar/shell-frdmk66f.ewd b/fnet_demos/build/frdmk66f/shell/iar/shell-frdmk66f.ewd new file mode 100644 index 00000000..24c80613 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/iar/shell-frdmk66f.ewd @@ -0,0 +1,2834 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + int flash release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/fnet_demos/build/frdmk66f/shell/iar/shell-frdmk66f.ewp b/fnet_demos/build/frdmk66f/shell/iar/shell-frdmk66f.ewp new file mode 100644 index 00000000..e6e76520 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/iar/shell-frdmk66f.ewp @@ -0,0 +1,2032 @@ + + + 3 + + int flash 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diff --git a/fnet_demos/build/frdmk66f/shell/iar/shell-frdmk66f.eww b/fnet_demos/build/frdmk66f/shell/iar/shell-frdmk66f.eww new file mode 100644 index 00000000..ce80d487 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/iar/shell-frdmk66f.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell-frdmk66fint flash debugintflash-releaseshell-frdmk66fint flash release$WS_DIR$\shell-frdmk66f.ewp diff --git a/fnet_demos/build/frdmk66f/shell/kds/.cproject b/fnet_demos/build/frdmk66f/shell/kds/.cproject new file mode 100644 index 00000000..df01eb5c --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell/kds/.project b/fnet_demos/build/frdmk66f/shell/kds/.project new file mode 100644 index 00000000..3dfd0b9e --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/kds/.project @@ -0,0 +1,26 @@ + + + shell_frdmk66f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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irtualfnet_stack/stack/fnet_stack_config.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_config.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi_prv.hfnet_application2virtual:/virtualfnet_application/fapp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.cfnet_application2virtual:/virtualfnet_application/fapp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.hfnet_application2virtual:/virtualfnet_application/fapp_autoip.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.cfnet_application2virtual:/virtualfnet_application/fapp_autoip.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.hfnet_application2virtual:/virtualfnet_application/fapp_bench.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.cfnet_application2virtual:/virtualfnet_application/fapp_bench.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.hfnet_application2virtual:/virtualfnet_application/fapp_config.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_config.hfnet_application2virtual:/virtualfnet_application/fapp_dhcp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.cfnet_application2virtual:/virtualfnet_application/fapp_dhcp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.hfnet_application2virtual:/virtualfnet_application/fapp_dns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.cfnet_application2virtual:/virtualfnet_application/fapp_dns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.hfnet_application2virtual:/virtualfnet_application/fapp_fs.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.cfnet_application2virtual:/virtualfnet_application/fapp_fs.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.hfnet_application2virtual:/virtualfnet_application/fapp_fs_image.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs_image.cfnet_application2virtual:/virtualfnet_application/fapp_http.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.cfnet_application2virtual:/virtualfnet_application/fapp_http.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.hfnet_application2virtual:/virtualfnet_application/fapp_link.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.cfnet_application2virtual:/virtualfnet_application/fapp_link.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.hfnet_application2virtual:/virtualfnet_application/fapp_llmnr.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.cfnet_application2virtual:/virtualfnet_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK66F18.S1PARENT-4-PROJECT_LOC/common/startup/MK66F18/gcc/startup_MK66F18.S diff --git a/fnet_demos/build/frdmk66f/shell/kds/makedir.bat b/fnet_demos/build/frdmk66f/shell/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash debug cmsisdap.launch new file mode 100644 index 00000000..63665c02 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash debug jlink.launch b/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash debug jlink.launch new file mode 100644 index 00000000..e303297e --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash debug pne.launch b/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash debug pne.launch new file mode 100644 index 00000000..18694770 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash release cmsisdap.launch b/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash release cmsisdap.launch new file mode 100644 index 00000000..f5c9ef40 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash release jlink.launch b/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash release jlink.launch new file mode 100644 index 00000000..7d9b9925 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell/kds/shell_frdmk66f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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diff --git a/fnet_demos/build/frdmk66f/shell_boot/iar/shell_boot-frdmk66f.eww b/fnet_demos/build/frdmk66f/shell_boot/iar/shell_boot-frdmk66f.eww new file mode 100644 index 00000000..2524bf24 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_boot/iar/shell_boot-frdmk66f.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell_boot-frdmk66fint flash debugintflash-releaseshell_boot-frdmk66fint flash release$WS_DIR$\shell_boot-frdmk66f.ewp diff --git a/fnet_demos/build/frdmk66f/shell_boot/kds/.cproject b/fnet_demos/build/frdmk66f/shell_boot/kds/.cproject new file mode 100644 index 00000000..21def917 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_boot/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_boot/kds/.project b/fnet_demos/build/frdmk66f/shell_boot/kds/.project new file mode 100644 index 00000000..4de4348f --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_boot/kds/.project @@ -0,0 +1,26 @@ + + + shell_boot_frdmk66f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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tack2virtual:/virtualfnet_stack/stack/fnet_stack_config.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_config.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi_prv.hfnet_application2virtual:/virtualfnet_application/fapp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.cfnet_application2virtual:/virtualfnet_application/fapp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.hfnet_application2virtual:/virtualfnet_application/fapp_autoip.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.cfnet_application2virtual:/virtualfnet_application/fapp_autoip.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.hfnet_application2virtual:/virtualfnet_application/fapp_bench.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.cfnet_application2virtual:/virtualfnet_application/fapp_bench.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.hfnet_application2virtual:/virtualfnet_application/fapp_config.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_config.hfnet_application2virtual:/virtualfnet_application/fapp_dhcp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.cfnet_application2virtual:/virtualfnet_application/fapp_dhcp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.hfnet_application2virtual:/virtualfnet_application/fapp_dns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.cfnet_application2virtual:/virtualfnet_application/fapp_dns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.hfnet_application2virtual:/virtualfnet_application/fapp_fs.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.cfnet_application2virtual:/virtualfnet_application/fapp_fs.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.hfnet_application2virtual:/virtualfnet_application/fapp_fs_image.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs_image.cfnet_application2virtual:/virtualfnet_application/fapp_http.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.cfnet_application2virtual:/virtualfnet_application/fapp_http.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.hfnet_application2virtual:/virtualfnet_application/fapp_link.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.cfnet_application2virtual:/virtualfnet_application/fapp_link.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.hfnet_application2virtual:/virtualfnet_application/fapp_llmnr.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.cfnet_application2virtual:/virtualfnet_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK66F18.S1PARENT-4-PROJECT_LOC/common/startup/MK66F18/gcc/startup_MK66F18.S diff --git a/fnet_demos/build/frdmk66f/shell_boot/kds/makedir.bat b/fnet_demos/build/frdmk66f/shell_boot/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_boot/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash debug cmsisdap.launch new file mode 100644 index 00000000..9ddf19fa --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash debug jlink.launch b/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash debug jlink.launch new file mode 100644 index 00000000..88027854 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash debug pne.launch b/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash debug pne.launch new file mode 100644 index 00000000..edcbd995 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash release cmsisdap.launch b/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash release cmsisdap.launch new file mode 100644 index 00000000..c3093b01 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash release jlink.launch b/fnet_demos/build/frdmk66f/shell_boot/kds/shell_boot_frdmk66f int flash release jlink.launch new file mode 100644 index 00000000..7879776f --- /dev/null +++ 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diff --git a/fnet_demos/build/frdmk66f/shell_freertos/iar/shell_freertos-frdmk66f.eww b/fnet_demos/build/frdmk66f/shell_freertos/iar/shell_freertos-frdmk66f.eww new file mode 100644 index 00000000..7cf75a28 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_freertos/iar/shell_freertos-frdmk66f.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell_freertos-frdmk66fint flash debugintflash-releaseshell_freertos-frdmk66fint flash release$WS_DIR$\shell_freertos-frdmk66f.ewp diff --git a/fnet_demos/build/frdmk66f/shell_freertos/kds/.cproject b/fnet_demos/build/frdmk66f/shell_freertos/kds/.cproject new file mode 100644 index 00000000..eefbdc7e --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_freertos/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_freertos/kds/.project b/fnet_demos/build/frdmk66f/shell_freertos/kds/.project new file mode 100644 index 00000000..43083e59 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_freertos/kds/.project @@ -0,0 +1,26 @@ + + + shell_freertos_frdmk66f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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diff --git a/fnet_demos/build/frdmk66f/shell_freertos/kds/makedir.bat b/fnet_demos/build/frdmk66f/shell_freertos/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_freertos/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash debug cmsisdap.launch new file mode 100644 index 00000000..85a9f8e9 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash debug jlink.launch b/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash debug jlink.launch new file mode 100644 index 00000000..3a3bed20 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash debug pne.launch b/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash debug pne.launch new file mode 100644 index 00000000..0699cafc --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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100644 index 00000000..a412069e --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash release pne.launch b/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash release pne.launch new file mode 100644 index 00000000..9d209ce2 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_freertos/kds/shell_freertos_frdmk66f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + int flash release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + 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$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/fnet_demos/build/frdmk66f/shell_mbedtls/iar/shell_mbedtls-frdmk66f.ewp b/fnet_demos/build/frdmk66f/shell_mbedtls/iar/shell_mbedtls-frdmk66f.ewp new file mode 100644 index 00000000..f679be9d --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/iar/shell_mbedtls-frdmk66f.ewp @@ -0,0 +1,2032 @@ + + + 3 + + int flash debug + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + 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diff --git a/fnet_demos/build/frdmk66f/shell_mbedtls/iar/shell_mbedtls-frdmk66f.eww b/fnet_demos/build/frdmk66f/shell_mbedtls/iar/shell_mbedtls-frdmk66f.eww new file mode 100644 index 00000000..35c692bb --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/iar/shell_mbedtls-frdmk66f.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell_mbedtls-frdmk66fint flash debugintflash-releaseshell_mbedtls-frdmk66fint flash release$WS_DIR$\shell_mbedtls-frdmk66f.ewp diff --git a/fnet_demos/build/frdmk66f/shell_mbedtls/kds/.cproject b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/.cproject new file mode 100644 index 00000000..de931a64 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_mbedtls/kds/.project b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/.project new file mode 100644 index 00000000..8b7a4554 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/.project @@ -0,0 +1,26 @@ + + + shell_mbedtls_frdmk66f + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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diff --git a/fnet_demos/build/frdmk66f/shell_mbedtls/kds/makedir.bat b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash debug cmsisdap.launch b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash debug cmsisdap.launch new file mode 100644 index 00000000..5224cf46 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash debug jlink.launch b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash debug jlink.launch new file mode 100644 index 00000000..1f107404 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash debug pne.launch b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash debug pne.launch new file mode 100644 index 00000000..d1b38bc2 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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--- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash release pne.launch b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash release pne.launch new file mode 100644 index 00000000..19d12c65 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f.wsd b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f.wsd new file mode 100644 index 00000000..541b05b0 --- /dev/null +++ b/fnet_demos/build/frdmk66f/shell_mbedtls/kds/shell_mbedtls_frdmk66f.wsd @@ -0,0 +1,9 @@ + + + + shell_mbedtls_frdmk66ftrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/lpcxpresso54628/bench/iar/bench-lpcxpresso54628.ewd b/fnet_demos/build/lpcxpresso54628/bench/iar/bench-lpcxpresso54628.ewd new file mode 100644 index 00000000..92c698e1 --- /dev/null +++ b/fnet_demos/build/lpcxpresso54628/bench/iar/bench-lpcxpresso54628.ewd @@ -0,0 +1,2842 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID 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$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 1 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\IARProbe\IarProbePlugin.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + int flash release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + 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diff --git a/fnet_demos/build/twrk60d100m/bench/iar/bench-twrk60d100m.eww b/fnet_demos/build/twrk60d100m/bench/iar/bench-twrk60d100m.eww new file mode 100644 index 00000000..1e95af36 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/iar/bench-twrk60d100m.eww @@ -0,0 +1,3 @@ + + +intflash-debugbench-twrk60d100mint flash debugintflash-releasebench-twrk60d100mint flash release$WS_DIR$\bench-twrk60d100m.ewp diff --git a/fnet_demos/build/twrk60d100m/bench/kds/.cproject b/fnet_demos/build/twrk60d100m/bench/kds/.cproject new file mode 100644 index 00000000..51996c16 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/bench/kds/.project b/fnet_demos/build/twrk60d100m/bench/kds/.project new file mode 100644 index 00000000..24b5beeb --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/kds/.project @@ -0,0 +1,26 @@ + + + bench_twrk60d100m + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK60D10.S1PARENT-4-PROJECT_LOC/common/startup/MK60D10/gcc/startup_MK60D10.S diff --git a/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash debug cmsisdap.launch b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash debug cmsisdap.launch new file mode 100644 index 00000000..993843f8 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash debug jlink.launch b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash debug jlink.launch new file mode 100644 index 00000000..dfdfa444 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash debug pne.launch b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash debug pne.launch new file mode 100644 index 00000000..920422d6 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash release cmsisdap.launch b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash release cmsisdap.launch new file mode 100644 index 00000000..c8abde30 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash release jlink.launch b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash release jlink.launch new file mode 100644 index 00000000..a07f3731 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash release pne.launch b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash release pne.launch new file mode 100644 index 00000000..c96bdac2 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m.wsd b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m.wsd new file mode 100644 index 00000000..09d85a2b --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/kds/bench_twrk60d100m.wsd @@ -0,0 +1,9 @@ + + + + bench_twrk60d100mtrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/twrk60d100m/bench/kds/makedir.bat b/fnet_demos/build/twrk60d100m/bench/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/bench/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/twrk60d100m/boot/iar/boot-twrk60d100m.ewd b/fnet_demos/build/twrk60d100m/boot/iar/boot-twrk60d100m.ewd new file mode 100644 index 00000000..6e22d4b0 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/iar/boot-twrk60d100m.ewd @@ -0,0 +1,2834 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + 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$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + int flash release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/fnet_demos/build/twrk60d100m/boot/iar/boot-twrk60d100m.ewp b/fnet_demos/build/twrk60d100m/boot/iar/boot-twrk60d100m.ewp new file mode 100644 index 00000000..679208ea --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/iar/boot-twrk60d100m.ewp @@ -0,0 +1,2032 @@ + + + 3 + + int flash debug + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + 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diff --git a/fnet_demos/build/twrk60d100m/boot/iar/boot-twrk60d100m.eww b/fnet_demos/build/twrk60d100m/boot/iar/boot-twrk60d100m.eww new file mode 100644 index 00000000..f40baa1e --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/iar/boot-twrk60d100m.eww @@ -0,0 +1,3 @@ + + +intflash-debugboot-twrk60d100mint flash debugintflash-releaseboot-twrk60d100mint flash release$WS_DIR$\boot-twrk60d100m.ewp diff --git a/fnet_demos/build/twrk60d100m/boot/kds/.cproject b/fnet_demos/build/twrk60d100m/boot/kds/.cproject new file mode 100644 index 00000000..cb51c962 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/boot/kds/.project b/fnet_demos/build/twrk60d100m/boot/kds/.project new file mode 100644 index 00000000..22dc8e9e --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/kds/.project @@ -0,0 +1,26 @@ + + + boot_twrk60d100m + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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ualfnet_stack/stack/fnet_stack_config.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_config.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi_prv.hfnet_application2virtual:/virtualfnet_application/fapp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.cfnet_application2virtual:/virtualfnet_application/fapp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.hfnet_application2virtual:/virtualfnet_application/fapp_autoip.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.cfnet_application2virtual:/virtualfnet_application/fapp_autoip.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.hfnet_application2virtual:/virtualfnet_application/fapp_bench.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.cfnet_application2virtual:/virtualfnet_application/fapp_bench.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.hfnet_application2virtual:/virtualfnet_application/fapp_config.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_config.hfnet_application2virtual:/virtualfnet_application/fapp_dhcp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.cfnet_application2virtual:/virtualfnet_application/fapp_dhcp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.hfnet_application2virtual:/virtualfnet_application/fapp_dns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.cfnet_application2virtual:/virtualfnet_application/fapp_dns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.hfnet_application2virtual:/virtualfnet_application/fapp_fs.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.cfnet_application2virtual:/virtualfnet_application/fapp_fs.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.hfnet_application2virtual:/virtualfnet_application/fapp_fs_image.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs_image.cfnet_application2virtual:/virtualfnet_application/fapp_http.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.cfnet_application2virtual:/virtualfnet_application/fapp_http.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.hfnet_application2virtual:/virtualfnet_application/fapp_link.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.cfnet_application2virtual:/virtualfnet_application/fapp_link.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.hfnet_application2virtual:/virtualfnet_application/fapp_llmnr.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.cfnet_application2virtual:/virtualfnet_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK60D10.S1PARENT-4-PROJECT_LOC/common/startup/MK60D10/gcc/startup_MK60D10.S diff --git a/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash debug cmsisdap.launch b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash debug cmsisdap.launch new file mode 100644 index 00000000..6201415a --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash debug jlink.launch b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash debug jlink.launch new file mode 100644 index 00000000..d8717707 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash debug pne.launch b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash debug pne.launch new file mode 100644 index 00000000..7071b770 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash release cmsisdap.launch b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash release cmsisdap.launch new file mode 100644 index 00000000..50aa844c --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash release jlink.launch b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash release jlink.launch new file mode 100644 index 00000000..1f576f79 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash release pne.launch b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash release pne.launch new file mode 100644 index 00000000..95c32a5e --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m.wsd b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m.wsd new file mode 100644 index 00000000..a2ddf790 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/kds/boot_twrk60d100m.wsd @@ -0,0 +1,9 @@ + + + + boot_twrk60d100mtrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/build/twrk60d100m/boot/kds/makedir.bat b/fnet_demos/build/twrk60d100m/boot/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/boot/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/twrk60d100m/shell/iar/shell-twrk60d100m.ewd b/fnet_demos/build/twrk60d100m/shell/iar/shell-twrk60d100m.ewd new file mode 100644 index 00000000..6e22d4b0 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell/iar/shell-twrk60d100m.ewd @@ -0,0 +1,2834 @@ + + + 3 + + int flash debug + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + int flash release + + ARM + + 0 + + C-SPY + 2 + + 29 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/fnet_demos/build/twrk60d100m/shell/iar/shell-twrk60d100m.ewp b/fnet_demos/build/twrk60d100m/shell/iar/shell-twrk60d100m.ewp new file mode 100644 index 00000000..0979488e --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell/iar/shell-twrk60d100m.ewp @@ -0,0 +1,2032 @@ + + + 3 + + int flash debug + + ARM + + 1 + + General + 3 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + 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diff --git a/fnet_demos/build/twrk60d100m/shell/iar/shell-twrk60d100m.eww b/fnet_demos/build/twrk60d100m/shell/iar/shell-twrk60d100m.eww new file mode 100644 index 00000000..01c3d1ab --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell/iar/shell-twrk60d100m.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell-twrk60d100mint flash debugintflash-releaseshell-twrk60d100mint flash release$WS_DIR$\shell-twrk60d100m.ewp diff --git a/fnet_demos/build/twrk60d100m/shell/kds/.cproject b/fnet_demos/build/twrk60d100m/shell/kds/.cproject new file mode 100644 index 00000000..d1c3793b --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/shell/kds/.project b/fnet_demos/build/twrk60d100m/shell/kds/.project new file mode 100644 index 00000000..db36449d --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell/kds/.project @@ -0,0 +1,26 @@ + + + shell_twrk60d100m + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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irtualfnet_stack/stack/fnet_stack_config.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_config.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi_prv.hfnet_application2virtual:/virtualfnet_application/fapp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.cfnet_application2virtual:/virtualfnet_application/fapp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.hfnet_application2virtual:/virtualfnet_application/fapp_autoip.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.cfnet_application2virtual:/virtualfnet_application/fapp_autoip.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.hfnet_application2virtual:/virtualfnet_application/fapp_bench.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.cfnet_application2virtual:/virtualfnet_application/fapp_bench.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.hfnet_application2virtual:/virtualfnet_application/fapp_config.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_config.hfnet_application2virtual:/virtualfnet_application/fapp_dhcp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.cfnet_application2virtual:/virtualfnet_application/fapp_dhcp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.hfnet_application2virtual:/virtualfnet_application/fapp_dns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.cfnet_application2virtual:/virtualfnet_application/fapp_dns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.hfnet_application2virtual:/virtualfnet_application/fapp_fs.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.cfnet_application2virtual:/virtualfnet_application/fapp_fs.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.hfnet_application2virtual:/virtualfnet_application/fapp_fs_image.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs_image.cfnet_application2virtual:/virtualfnet_application/fapp_http.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.cfnet_application2virtual:/virtualfnet_application/fapp_http.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.hfnet_application2virtual:/virtualfnet_application/fapp_link.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.cfnet_application2virtual:/virtualfnet_application/fapp_link.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.hfnet_application2virtual:/virtualfnet_application/fapp_llmnr.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.cfnet_application2virtual:/virtualfnet_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK60D10.S1PARENT-4-PROJECT_LOC/common/startup/MK60D10/gcc/startup_MK60D10.S diff --git a/fnet_demos/build/twrk60d100m/shell/kds/makedir.bat b/fnet_demos/build/twrk60d100m/shell/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/twrk60d100m/shell/kds/shell_twrk60d100m int flash debug cmsisdap.launch b/fnet_demos/build/twrk60d100m/shell/kds/shell_twrk60d100m int flash debug cmsisdap.launch new file mode 100644 index 00000000..8a5f6818 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell/kds/shell_twrk60d100m int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/shell/kds/shell_twrk60d100m int flash debug jlink.launch b/fnet_demos/build/twrk60d100m/shell/kds/shell_twrk60d100m int flash debug jlink.launch new file mode 100644 index 00000000..67c836eb --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell/kds/shell_twrk60d100m int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/shell/kds/shell_twrk60d100m int flash debug pne.launch b/fnet_demos/build/twrk60d100m/shell/kds/shell_twrk60d100m int flash debug pne.launch new file mode 100644 index 00000000..ce1d0511 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell/kds/shell_twrk60d100m int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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diff --git a/fnet_demos/build/twrk60d100m/shell_boot/iar/shell_boot-twrk60d100m.eww b/fnet_demos/build/twrk60d100m/shell_boot/iar/shell_boot-twrk60d100m.eww new file mode 100644 index 00000000..b50796db --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/iar/shell_boot-twrk60d100m.eww @@ -0,0 +1,3 @@ + + +intflash-debugshell_boot-twrk60d100mint flash debugintflash-releaseshell_boot-twrk60d100mint flash release$WS_DIR$\shell_boot-twrk60d100m.ewp diff --git a/fnet_demos/build/twrk60d100m/shell_boot/kds/.cproject b/fnet_demos/build/twrk60d100m/shell_boot/kds/.cproject new file mode 100644 index 00000000..d87b4b68 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/kds/.cproject @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/shell_boot/kds/.project b/fnet_demos/build/twrk60d100m/shell_boot/kds/.project new file mode 100644 index 00000000..3746d1a3 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/kds/.project @@ -0,0 +1,26 @@ + + + shell_boot_twrk60d100m + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + 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tack2virtual:/virtualfnet_stack/stack/fnet_stack_config.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_config.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stack_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stack_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_stdlib.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_stdlib.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_tcp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_tcp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_timer_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_timer_prv.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_udp.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_udp.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.c1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.cfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi.hfnet_stack/stack2virtual:/virtualfnet_stack/stack/fnet_wifi_prv.h1PARENT-5-PROJECT_LOC/fnet_stack/stack/fnet_wifi_prv.hfnet_application2virtual:/virtualfnet_application/fapp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.cfnet_application2virtual:/virtualfnet_application/fapp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp.hfnet_application2virtual:/virtualfnet_application/fapp_autoip.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.cfnet_application2virtual:/virtualfnet_application/fapp_autoip.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_autoip.hfnet_application2virtual:/virtualfnet_application/fapp_bench.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.cfnet_application2virtual:/virtualfnet_application/fapp_bench.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_bench.hfnet_application2virtual:/virtualfnet_application/fapp_config.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_config.hfnet_application2virtual:/virtualfnet_application/fapp_dhcp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.cfnet_application2virtual:/virtualfnet_application/fapp_dhcp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dhcp.hfnet_application2virtual:/virtualfnet_application/fapp_dns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.cfnet_application2virtual:/virtualfnet_application/fapp_dns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_dns.hfnet_application2virtual:/virtualfnet_application/fapp_fs.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.cfnet_application2virtual:/virtualfnet_application/fapp_fs.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs.hfnet_application2virtual:/virtualfnet_application/fapp_fs_image.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_fs_image.cfnet_application2virtual:/virtualfnet_application/fapp_http.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.cfnet_application2virtual:/virtualfnet_application/fapp_http.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_http.hfnet_application2virtual:/virtualfnet_application/fapp_link.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.cfnet_application2virtual:/virtualfnet_application/fapp_link.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_link.hfnet_application2virtual:/virtualfnet_application/fapp_llmnr.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.cfnet_application2virtual:/virtualfnet_application/fapp_llmnr.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_llmnr.hfnet_application2virtual:/virtualfnet_application/fapp_mdns.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.cfnet_application2virtual:/virtualfnet_application/fapp_mdns.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mdns.hfnet_application2virtual:/virtualfnet_application/fapp_mem.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.cfnet_application2virtual:/virtualfnet_application/fapp_mem.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_mem.hfnet_application2virtual:/virtualfnet_application/fapp_netif.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.cfnet_application2virtual:/virtualfnet_application/fapp_netif.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_netif.hfnet_application2virtual:/virtualfnet_application/fapp_params.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.cfnet_application2virtual:/virtualfnet_application/fapp_params.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params.hfnet_application2virtual:/virtualfnet_application/fapp_params_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_params_prv.hfnet_application2virtual:/virtualfnet_application/fapp_ping.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.cfnet_application2virtual:/virtualfnet_application/fapp_ping.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_ping.hfnet_application2virtual:/virtualfnet_application/fapp_prv.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_prv.hfnet_application2virtual:/virtualfnet_application/fapp_setget.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.cfnet_application2virtual:/virtualfnet_application/fapp_setget.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_setget.hfnet_application2virtual:/virtualfnet_application/fapp_shell.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.cfnet_application2virtual:/virtualfnet_application/fapp_shell.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_shell.hfnet_application2virtual:/virtualfnet_application/fapp_sntp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.cfnet_application2virtual:/virtualfnet_application/fapp_sntp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_sntp.hfnet_application2virtual:/virtualfnet_application/fapp_telnet.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.cfnet_application2virtual:/virtualfnet_application/fapp_telnet.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_telnet.hfnet_application2virtual:/virtualfnet_application/fapp_tftp.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.cfnet_application2virtual:/virtualfnet_application/fapp_tftp.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_tftp.hfnet_application2virtual:/virtualfnet_application/fapp_wifi.c1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.cfnet_application2virtual:/virtualfnet_application/fapp_wifi.h1PARENT-4-PROJECT_LOC/common/fnet_application/fapp_wifi.hstartup2virtual:/virtualstartup/startup_MK60D10.S1PARENT-4-PROJECT_LOC/common/startup/MK60D10/gcc/startup_MK60D10.S diff --git a/fnet_demos/build/twrk60d100m/shell_boot/kds/makedir.bat b/fnet_demos/build/twrk60d100m/shell_boot/kds/makedir.bat new file mode 100644 index 00000000..5e467fd4 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/kds/makedir.bat @@ -0,0 +1,4 @@ +set TARGETDIR=%1 +set TARGETDIR=%TARGETDIR:/=\% +set TARGETDIR=%TARGETDIR:"=% +IF NOT EXIST "%TARGETDIR%" mkdir "%TARGETDIR%" diff --git a/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash debug cmsisdap.launch b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash debug cmsisdap.launch new file mode 100644 index 00000000..d363d1a4 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash debug cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash debug jlink.launch b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash debug jlink.launch new file mode 100644 index 00000000..2c7320d4 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash debug jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash debug pne.launch b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash debug pne.launch new file mode 100644 index 00000000..b0196114 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash debug pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash release cmsisdap.launch b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash release cmsisdap.launch new file mode 100644 index 00000000..fb3e122a --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash release cmsisdap.launch @@ -0,0 +1,61 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash release jlink.launch b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash release jlink.launch new file mode 100644 index 00000000..a390c226 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash release jlink.launch @@ -0,0 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash release pne.launch b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash release pne.launch new file mode 100644 index 00000000..19f7a464 --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m int flash release pne.launch @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m.wsd b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m.wsd new file mode 100644 index 00000000..9ec996ec --- /dev/null +++ b/fnet_demos/build/twrk60d100m/shell_boot/kds/shell_boot_twrk60d100m.wsd @@ -0,0 +1,9 @@ + + + + shell_boot_twrk60d100mtrueint flash debugfalseint flash releasefalse + + + + + diff --git a/fnet_demos/common/fnet_application/fapp.c b/fnet_demos/common/fnet_application/fapp.c index dad03f14..ffeef78e 100644 --- a/fnet_demos/common/fnet_application/fapp.c +++ b/fnet_demos/common/fnet_application/fapp.c @@ -36,10 +36,10 @@ #endif #if FAPP_CFG_FREERTOS -/* FreeRTOS kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "event_groups.h" + /* FreeRTOS kernel includes. */ + #include "FreeRTOS.h" + #include "task.h" + #include "event_groups.h" #endif /************************************************************************ @@ -68,9 +68,9 @@ static void fapp_boot(fnet_shell_desc_t desc); static fnet_shell_desc_t fapp_shell_desc = 0; /* Shell descriptor. */ #if FAPP_CFG_FREERTOS -/* RX activity event. */ -#define FAPP_FREERTOS_EVENT_RX (0x1) -static EventGroupHandle_t fapp_freertos_event_group; + /* RX activity event. */ + #define FAPP_FREERTOS_EVENT_RX (0x1) + static EventGroupHandle_t fapp_freertos_event_group; #endif /****************************************************************************** @@ -268,15 +268,15 @@ static void fapp_init(void) if(fnet_init(&init_params) == FNET_OK) { /* Add event handler on duplicated IP address */ - #if FNET_CFG_IP4 +#if FNET_CFG_IP4 fnet_netif_set_callback_on_ip4_addr_conflict(fapp_dup_ip_callback); - #endif +#endif /* Init FS and mount FS Image. */ - #if (FAPP_CFG_EXP_CMD && FNET_CFG_FS) || ((FAPP_CFG_HTTP_CMD || FAPP_CFG_HTTP_TLS_CMD) && FNET_CFG_HTTP) - fapp_fs_mount(); - #endif - +#if (FAPP_CFG_EXP_CMD && FNET_CFG_FS) || ((FAPP_CFG_HTTP_CMD || FAPP_CFG_HTTP_TLS_CMD) && FNET_CFG_HTTP) + fapp_fs_mount(); +#endif + /* Init main shell. */ fapp_shell_desc = fapp_shell_init(); if(fapp_shell_desc) @@ -284,20 +284,20 @@ static void fapp_init(void) /* Initialize network interfaces.*/ if(fapp_netif_init(fapp_shell_desc) == FNET_OK) { - #if FAPP_CFG_PARAMS_READ_FLASH && FNET_CFG_CPU_FLASH +#if FAPP_CFG_PARAMS_READ_FLASH && FNET_CFG_CPU_FLASH /* During bootup, the most recently stored customer configuration data will be read and used to configure the interfaces.*/ if(fapp_params_from_flash() == FNET_OK) { fnet_shell_println(fapp_shell_desc, FAPP_PARAMS_LOAD_STR); } - #endif - +#endif + /* Check if we have atleast one initoalized networking interface.*/ if(fnet_netif_get_default() == FNET_NULL) { fnet_shell_println(fapp_shell_desc, FAPP_NET_ERR); } - + /* Start application */ fapp_boot(fapp_shell_desc); } @@ -378,31 +378,32 @@ static void fapp_release(fnet_shell_desc_t desc) /************************************************************************ * DESCRIPTION: Application poll. ************************************************************************/ +extern void fnet_enet_poll(fnet_netif_desc_t netif_desc); void fapp_poll(void) { - #if !FNET_CFG_TIMER_POLL_AUTOMATIC - fnet_timer_poll(); /* Poll FNET stack timeouts.*/ - #endif - fnet_service_poll(); /* Poll registered services.*/ +#if !FNET_CFG_TIMER_POLL_AUTOMATIC + fnet_timer_poll(); /* Poll FNET stack timeouts.*/ +#endif + fnet_service_poll(); /* Poll registered services.*/ - #if FAPP_CFG_FREERTOS /* FrerRTOS task sleep */ - { - #if 0 /* Sleep for some time. Simple version. */ - vTaskDelay(FAPP_CFG_FREERTOS_TASK_POLL_PERIOD/portTICK_PERIOD_MS); - #else /* Sleep for some time or for the FNET RX event */ - /* Wait a maximum of FAPP_CFG_FREERTOS_TASK_POLL_PERIOD_MS ms for either any bit to be set within - the event group. Clear the bits before exiting. */ - xEventGroupWaitBits( - fapp_freertos_event_group, /* The event group being tested. */ - FAPP_FREERTOS_EVENT_RX, /* The bits within the event group to wait for. */ - pdTRUE, /* BIT_0 & BIT_4 should be cleared before returning. */ - pdFALSE, /* Don't wait for both bits, either bit will do. */ - FAPP_CFG_FREERTOS_TASK_POLL_PERIOD_MS/portTICK_PERIOD_MS );/* Ticks to wait for either bit to be set. */ - - /* Returned because Socket RX event or ticks passed.*/ - #endif - } - #endif +#if FAPP_CFG_FREERTOS /* FrerRTOS task sleep */ + { +#if 0 /* Sleep for some time. Simple version. */ + vTaskDelay(FAPP_CFG_FREERTOS_TASK_POLL_PERIOD / portTICK_PERIOD_MS); +#else /* Sleep for some time or for the FNET RX event */ + /* Wait a maximum of FAPP_CFG_FREERTOS_TASK_POLL_PERIOD_MS ms for either any bit to be set within + the event group. Clear the bits before exiting. */ + xEventGroupWaitBits( + fapp_freertos_event_group, /* The event group being tested. */ + FAPP_FREERTOS_EVENT_RX, /* The bits within the event group to wait for. */ + pdTRUE, /* BIT_0 & BIT_4 should be cleared before returning. */ + pdFALSE, /* Don't wait for both bits, either bit will do. */ + FAPP_CFG_FREERTOS_TASK_POLL_PERIOD_MS / portTICK_PERIOD_MS ); /* Ticks to wait for either bit to be set. */ + + /* Returned because Socket RX event or ticks passed.*/ +#endif + } +#endif } /************************************************************************ @@ -412,7 +413,7 @@ void fapp_main(void) { /* Initilize FNET Demo application */ fapp_init(); - + while(1) { /* Application poll */ @@ -430,7 +431,7 @@ static void fapp_socket_rx_callback(void) { BaseType_t xHigherPriorityTaskWoken; - if(xEventGroupSetBitsFromISR(fapp_freertos_event_group, FAPP_FREERTOS_EVENT_RX, &xHigherPriorityTaskWoken)!= pdFAIL) + if(xEventGroupSetBitsFromISR(fapp_freertos_event_group, FAPP_FREERTOS_EVENT_RX, &xHigherPriorityTaskWoken) != pdFAIL) { /* If xHigherPriorityTaskWoken is now set to pdTRUE then a context switch should be requested. The macro used is port specific and will @@ -446,24 +447,24 @@ static void fapp_socket_rx_callback(void) ************************************************************************/ static void fapp_task(void *params) { - /* FNET demo application */ + /* FNET demo application */ fapp_main(); } /************************************************************************ * DESCRIPTION: Main entry point of the FreeRTOS shell demo. ************************************************************************/ -void fapp_main_freertos( void ) +void fapp_main_freertos( void ) { /* Create FNET demo application task */ if(xTaskCreate( - fapp_task, /* pointer to the task */ - FAPP_CFG_NAME, /* task name for kernel awareness debugging */ - FAPP_CFG_FREERTOS_TASK_STACK_SIZE/sizeof(portSTACK_TYPE), /* task stack size */ - NULL, /* optional task startup argument */ - FAPP_CFG_FREERTOS_TASK_PRIORITY, /* initial priority */ - NULL /* optional task handle to create */ - ) != pdPASS) + fapp_task, /* pointer to the task */ + FAPP_CFG_NAME, /* task name for kernel awareness debugging */ + FAPP_CFG_FREERTOS_TASK_STACK_SIZE / sizeof(portSTACK_TYPE), /* task stack size */ + NULL, /* optional task startup argument */ + FAPP_CFG_FREERTOS_TASK_PRIORITY, /* initial priority */ + NULL /* optional task handle to create */ + ) != pdPASS) { fnet_println("[FREERTOS] Failed to create task."); /* Probably out of memory */ } @@ -480,15 +481,15 @@ void fapp_main_freertos( void ) } else { - #if FNET_CFG_SOCKET_CALLBACK_ON_RX +#if FNET_CFG_SOCKET_CALLBACK_ON_RX /* Registers the "socket layer activity" event handler.*/ fnet_socket_set_callback_on_rx(fapp_socket_rx_callback); - #endif +#endif fnet_println("[FREERTOS] Starting scheduler."); vTaskStartScheduler(); - /* The code should never reach here. */ + /* The code should never reach here. */ } } } @@ -526,6 +527,33 @@ void fapp_addr_callback_updated(fnet_shell_desc_t desc, fnet_netif_desc_t netif) } #endif +/************************************************************************ +* DESCRIPTION: Board-specific HW initialization. +* Default serial port initialization. +* Interrupt enabling. +************************************************************************/ + + +void fapp_hw_init(void) +{ +#if FNET_MK /* Kinetis Board specific initialization */ +#include "clock_config.h" + /* Init clock to run mode */ + BOARD_BootClockRUN(); +#endif + +#if FNET_LPC /* LPC Board specific initialization */ + extern void BOARD_InitHardware(void); + BOARD_InitHardware(); +#endif + + /* Default serial port initialization. */ + fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200u); + + /* Enable Interrupts.*/ + fnet_cpu_irq_enable(0u); +} + /****************************************************************************** * Testing of mutex nesting conflict. * Used only for testing needs. diff --git a/fnet_demos/common/fnet_application/fapp.h b/fnet_demos/common/fnet_application/fapp.h index 3f88d63f..fd0c9e1c 100644 --- a/fnet_demos/common/fnet_application/fapp.h +++ b/fnet_demos/common/fnet_application/fapp.h @@ -34,6 +34,8 @@ extern "C" { #endif +void fapp_hw_init( void ); /* Board-specific HW initialization. Default serial port initialization. Interrupt enabling. */ + void fapp_main( void ); /* Main entry point of the bare-metal shell demo. */ #if FAPP_CFG_FREERTOS void fapp_main_freertos( void ); /* Main entry point of the FreeRTOS shell demo. */ diff --git a/fnet_demos/common/fnet_application/fapp_autoip.c b/fnet_demos/common/fnet_application/fapp_autoip.c index 8484e01e..fb980186 100644 --- a/fnet_demos/common/fnet_application/fapp_autoip.c +++ b/fnet_demos/common/fnet_application/fapp_autoip.c @@ -69,7 +69,7 @@ void fapp_autoip_release(void) fnet_autoip_desc_t autoip; /* Release all Auto-IP services.*/ - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { autoip = fnet_autoip_get_by_netif(netif); if(autoip) @@ -138,7 +138,7 @@ void fapp_autoip_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t **a } } - if(init == FNET_TRUE) + if(init == FNET_TRUE) { /* Save current IP address, to restore if cancelled. */ fapp_autoip_ip_old = fnet_netif_get_ip4_addr(netif); diff --git a/fnet_demos/common/fnet_application/fapp_bench.c b/fnet_demos/common/fnet_application/fapp_bench.c index 9df75223..242e7d5b 100644 --- a/fnet_demos/common/fnet_application/fapp_bench.c +++ b/fnet_demos/common/fnet_application/fapp_bench.c @@ -33,11 +33,11 @@ /************************************************************************ * Function Prototypes *************************************************************************/ -#if FNET_CFG_BENCH_SRV -static fnet_bench_srv_desc_t fapp_bench_srv_desc = 0; /* Benchmark server descriptor. */ +#if FNET_CFG_BENCH_SRV + static fnet_bench_srv_desc_t fapp_bench_srv_desc = 0; /* Benchmark server descriptor. */ #endif #if FNET_CFG_BENCH_CLN -static fnet_bench_cln_desc_t fapp_bench_cln_desc = 0; /* Benchmark client descriptor. */ + static fnet_bench_cln_desc_t fapp_bench_cln_desc = 0; /* Benchmark client descriptor. */ #endif /************************************************************************ @@ -52,21 +52,21 @@ static void fapp_bench_print_results (fnet_shell_desc_t desc, fnet_size_t megaby if(time_ms) { - kbits_sec = (((megabytes * 8 * 1000 /*sec*/) % time_ms)*1000 /*kbits*/)/time_ms; + kbits_sec = (((megabytes * 8 * 1000 /*sec*/) % time_ms) * 1000 /*kbits*/) / time_ms; kbits_sec = kbits_sec + (fnet_size_t)((bytes * 8) / time_ms); - megabits_sec = (fnet_size_t)((megabytes * 8 * 1000) / time_ms) + (kbits_sec/1000); - kbits_sec = (kbits_sec%1000); + megabits_sec = (fnet_size_t)((megabytes * 8 * 1000) / time_ms) + (kbits_sec / 1000); + kbits_sec = (kbits_sec % 1000); } /* Print benchmark results.*/ fnet_shell_println(desc, "\r\n[BENCH]\t%u.%06u MBytes in %u.%02u Seconds = %u.%03u Mbit/sec\n", megabytes, bytes, (time_ms / 1000), ((time_ms % 1000) / 10), - megabits_sec, kbits_sec); + megabits_sec, kbits_sec); } #endif -#if FNET_CFG_BENCH_SRV +#if FNET_CFG_BENCH_SRV /************************************************************************ * DESCRIPTION: Benchmark server "session begin" event handler callback. ************************************************************************/ @@ -139,7 +139,7 @@ void fapp_bench_srv_cmd( fnet_shell_desc_t shell_desc, fnet_index_t argc, fnet_c } else if (!fnet_strcmp(argv[i], "tcp")) /* TCP */ { - bench_srv_params.type = SOCK_STREAM; + bench_srv_params.type = SOCK_STREAM; } else if (!fnet_strcmp(argv[i], "udp")) /* udp */ { @@ -155,13 +155,13 @@ void fapp_bench_srv_cmd( fnet_shell_desc_t shell_desc, fnet_index_t argc, fnet_c } } - if(init == FNET_TRUE) + if(init == FNET_TRUE) { if(netif) /* Only on one interface */ { bench_srv_params.address.sa_scope_id = fnet_netif_get_scope_id(netif); } - + /* Start Benchmark server. */ bench_srv_desc = fnet_bench_srv_init(&bench_srv_params); if(bench_srv_desc) @@ -174,7 +174,7 @@ void fapp_bench_srv_cmd( fnet_shell_desc_t shell_desc, fnet_index_t argc, fnet_c fnet_shell_println(shell_desc, FAPP_DELIMITER_STR); fnet_shell_println(shell_desc, " Benchmark server started."); - + if(fnet_socket_addr_is_unspecified(&bench_srv_params.address) == FNET_FALSE) /* Listen on concrete address */ { fnet_char_t ip_str[FNET_IP_ADDR_STR_SIZE_MAX]; @@ -187,10 +187,10 @@ void fapp_bench_srv_cmd( fnet_shell_desc_t shell_desc, fnet_index_t argc, fnet_c { fapp_netif_addr_print(shell_desc, AF_SUPPORTED, netif, FNET_FALSE); } - fnet_shell_println(shell_desc, FAPP_SHELL_INFO_FORMAT_S, "Protocol", (bench_srv_params.type == SOCK_STREAM)?"TCP":"UDP"); + fnet_shell_println(shell_desc, FAPP_SHELL_INFO_FORMAT_S, "Protocol", (bench_srv_params.type == SOCK_STREAM) ? "TCP" : "UDP"); fnet_shell_println(shell_desc, FAPP_SHELL_INFO_FORMAT_D, "Local Port", FNET_NTOHS(FNET_CFG_BENCH_SRV_PORT)); fnet_shell_println(shell_desc, FAPP_DELIMITER_STR); - + } else { @@ -229,7 +229,7 @@ void fapp_bench_srv_info(fnet_shell_desc_t desc) #endif /* FNET_CFG_BENCH_SRV */ -#if FNET_CFG_BENCH_CLN +#if FNET_CFG_BENCH_CLN /************************************************************************ * DESCRIPTION: Benchmark client "session end" event handler callback. @@ -269,7 +269,7 @@ void fapp_bench_cln_cmd(fnet_shell_desc_t shell_desc, fnet_index_t argc, fnet_ch /* Set Benchmark client parameters.*/ fnet_memset_zero(&bench_cln_params, sizeof(bench_cln_params)); - + /* Default values */ bench_cln_params.type = SOCK_STREAM; /* TCP by default */ bench_cln_params.message_size = FAPP_BENCH_TX_MESSAGE_SIZE_DEFAULT; /* Default message size */ @@ -307,7 +307,7 @@ void fapp_bench_cln_cmd(fnet_shell_desc_t shell_desc, fnet_index_t argc, fnet_ch } else if (!fnet_strcmp(argv[i], "tcp")) /* TCP */ { - bench_cln_params.type = SOCK_STREAM; + bench_cln_params.type = SOCK_STREAM; } else if (!fnet_strcmp(argv[i], "udp")) /* udp */ { @@ -377,7 +377,7 @@ void fapp_bench_cln_cmd(fnet_shell_desc_t shell_desc, fnet_index_t argc, fnet_ch fnet_shell_println(shell_desc, FAPP_DELIMITER_STR); fnet_shell_println(shell_desc, " Benchmark client started."); - fnet_shell_println(shell_desc, FAPP_SHELL_INFO_FORMAT_S, "Protocol", (bench_cln_params.type == SOCK_STREAM)?"TCP":"UDP"); + fnet_shell_println(shell_desc, FAPP_SHELL_INFO_FORMAT_S, "Protocol", (bench_cln_params.type == SOCK_STREAM) ? "TCP" : "UDP"); fnet_shell_println(shell_desc, FAPP_SHELL_INFO_FORMAT_S, "Remote IP Addr", fnet_inet_ntop(bench_cln_params.address.sa_family, bench_cln_params.address.sa_data, ip_str, sizeof(ip_str))); fnet_shell_println(shell_desc, FAPP_SHELL_INFO_FORMAT_D, "Remote Port", FNET_NTOHS(FNET_CFG_BENCH_CLN_PORT)); fnet_shell_println(shell_desc, FAPP_SHELL_INFO_FORMAT_D, "Message Size", bench_cln_params.message_size); diff --git a/fnet_demos/common/fnet_application/fapp_config.h b/fnet_demos/common/fnet_application/fapp_config.h index 30901264..16d383ce 100644 --- a/fnet_demos/common/fnet_application/fapp_config.h +++ b/fnet_demos/common/fnet_application/fapp_config.h @@ -114,14 +114,14 @@ * @note "%s" will be replaced by the interface name.*/ /* All interfaces */ #ifndef FAPP_CFG_LINK_CONNECT_SCRIPT - #define FAPP_CFG_LINK_CONNECT_SCRIPT "dhcpc autoip -n %s; mdns -n %s; llmnr -n %s;" + #define FAPP_CFG_LINK_CONNECT_SCRIPT "dhcpc autoip -n %s; mdns -n %s; llmnr -n %s;" #endif #ifndef FAPP_CFG_LINK_DISCONNECT_SCRIPT #define FAPP_CFG_LINK_DISCONNECT_SCRIPT "mdns -n %s release; llmnr -n %s release; dhcpc -n %s release; autoip -n %s release;" #endif /* Wi-Fi interface connect/unconnect scrpts, in the access point operation mode.*/ #ifndef FAPP_CFG_LINK_CONNECT_WIFI_ACCESS_POINT_SCRIPT - #define FAPP_CFG_LINK_CONNECT_WIFI_ACCESS_POINT_SCRIPT "dhcp -n %s; mdns -n %s; llmnr -n %s;" + #define FAPP_CFG_LINK_CONNECT_WIFI_ACCESS_POINT_SCRIPT "dhcp -n %s; mdns -n %s; llmnr -n %s;" #endif #ifndef FAPP_CFG_LINK_DISCONNECT_WIFI_ACCESS_POINT_SCRIPT #define FAPP_CFG_LINK_DISCONNECT_WIFI_ACCESS_POINT_SCRIPT "mdns -n %s release; llmnr -n %s release; dhcp -n %s release;" @@ -309,7 +309,7 @@ #endif #ifndef FAPP_CFG_DHCPC_CMD_DISCOVER_MAX - #define FAPP_CFG_DHCPC_CMD_DISCOVER_MAX (-1) /* -1 means infinite. */ + #define FAPP_CFG_DHCPC_CMD_DISCOVER_MAX (-1) /* -1 means infinite. */ #endif @@ -627,7 +627,7 @@ #endif #ifndef FAPP_CFG_PARAMS_WIFI -#define FAPP_CFG_PARAMS_WIFI (FAPP_CFG_SETGET_CMD_SSID|FAPP_CFG_SETGET_CMD_PASSPHRASE) + #define FAPP_CFG_PARAMS_WIFI (FAPP_CFG_SETGET_CMD_SSID|FAPP_CFG_SETGET_CMD_PASSPHRASE) #endif @@ -694,7 +694,9 @@ #define FAPP_CFG_APPLICATION_ADDRESS FNET_CFG_CPU_FLASH_ADDRESS #endif -/* ROM memory size, reserved/protected for the application. Used by the bootloader application.*/ +/* ROM memory size, reserved/protected for the application. Used by the bootloader application. +* This value must be dividable by FNET_CFG_CPU_FLASH_PAGE_SIZE. +* On any change, must be updated the linker file of shell_boot application. */ #ifndef FAPP_CFG_BOOTLOADER_SIZE #define FAPP_CFG_BOOTLOADER_SIZE (52*1024) /* 52 KB */ #endif diff --git a/fnet_demos/common/fnet_application/fapp_dhcp.c b/fnet_demos/common/fnet_application/fapp_dhcp.c index 137671c4..982e43b8 100644 --- a/fnet_demos/common/fnet_application/fapp_dhcp.c +++ b/fnet_demos/common/fnet_application/fapp_dhcp.c @@ -33,26 +33,26 @@ * Definitions. *************************************************************************/ #if FAPP_CFG_DHCPC_CMD && FNET_CFG_DHCP_CLN -#define FAPP_DHCP_CLN_DISCOVER_STR "[DHCP] Discovering..." -#define FAPP_DHCP_CLN_COMMAND_REBOOT "reboot" -#define FAPP_DHCP_CLN_COMMAND_AUTOIP "autoip" -#define FAPP_DHCP_SRV_COMMAND_POOL "pool" - -static fnet_int32_t fapp_dhcp_cln_discover_counter; -static fnet_ip4_addr_t fapp_dhcp_cln_ip_old; -static fnet_ip4_addr_t fapp_dhcp_cln_subnet_mask_old; -#if FAPP_CFG_AUTOIP_CMD && FNET_CFG_AUTOIP - static fnet_bool_t fapp_dhcp_cln_autoip = FNET_FALSE; /* Flag that means to start the Auto-IP service automatically if a DHCP server is not found. */ -#endif + #define FAPP_DHCP_CLN_DISCOVER_STR "[DHCP] Discovering..." + #define FAPP_DHCP_CLN_COMMAND_REBOOT "reboot" + #define FAPP_DHCP_CLN_COMMAND_AUTOIP "autoip" + #define FAPP_DHCP_SRV_COMMAND_POOL "pool" + + static fnet_int32_t fapp_dhcp_cln_discover_counter; + static fnet_ip4_addr_t fapp_dhcp_cln_ip_old; + static fnet_ip4_addr_t fapp_dhcp_cln_subnet_mask_old; + #if FAPP_CFG_AUTOIP_CMD && FNET_CFG_AUTOIP + static fnet_bool_t fapp_dhcp_cln_autoip = FNET_FALSE; /* Flag that means to start the Auto-IP service automatically if a DHCP server is not found. */ + #endif #endif /* FAPP_CFG_DHCPC_CMD && FNET_CFG_DHCP_CLN */ /************************************************************************ * Function Prototypes *************************************************************************/ #if FAPP_CFG_DHCPC_CMD && FNET_CFG_DHCP_CLN -static void fapp_dhcp_cln_on_ctrlc(fnet_shell_desc_t desc, void *cookie); -static void fapp_dhcp_cln_callback_updated(fnet_dhcp_cln_desc_t dhcp_desc, fnet_netif_desc_t netif, void *shl_desc); -static void fapp_dhcp_cln_callback_discover(fnet_dhcp_cln_desc_t dhcp_desc, fnet_netif_desc_t netif, void *shl_desc); + static void fapp_dhcp_cln_on_ctrlc(fnet_shell_desc_t desc, void *cookie); + static void fapp_dhcp_cln_callback_updated(fnet_dhcp_cln_desc_t dhcp_desc, fnet_netif_desc_t netif, void *shl_desc); + static void fapp_dhcp_cln_callback_discover(fnet_dhcp_cln_desc_t dhcp_desc, fnet_netif_desc_t netif, void *shl_desc); #endif #if FAPP_CFG_DHCPC_CMD && FNET_CFG_DHCP_CLN @@ -132,7 +132,7 @@ void fapp_dhcp_cln_release(void) fnet_dhcp_cln_desc_t dhcp; /* Release all DHCP clients.*/ - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { dhcp = fnet_dhcp_cln_get_by_netif(netif); if(dhcp) @@ -178,9 +178,9 @@ void fapp_dhcp_cln_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t * } else if (!fnet_strcmp(argv[i], FAPP_DHCP_CLN_COMMAND_AUTOIP)) /* [autoip] */ { - #if FAPP_CFG_AUTOIP_CMD && FNET_CFG_AUTOIP +#if FAPP_CFG_AUTOIP_CMD && FNET_CFG_AUTOIP fapp_dhcp_cln_autoip = FNET_TRUE; - #endif +#endif } else/* Wrong parameter.*/ { @@ -188,7 +188,7 @@ void fapp_dhcp_cln_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t * } } - if(init == FNET_TRUE) + if(init == FNET_TRUE) { fapp_dhcp_cln_discover_counter = FAPP_CFG_DHCPC_CMD_DISCOVER_MAX; /* reset counter.*/ @@ -257,9 +257,9 @@ void fapp_dhcp_cln_info(fnet_shell_desc_t desc, fnet_netif_desc_t netif) fnet_inet_ntoa(*(struct fnet_in_addr *)( &options.dhcp_server), ip_str); fnet_shell_println(desc, FAPP_SHELL_INFO_FORMAT_S, "DHCP Server Address", ip_str); - #if 0 /* Not too important */ +#if 0 /* Not too important */ fnet_shell_println(desc, FAPP_SHELL_INFO_FORMAT_D, "Lease Time", fnet_ntohl(options.lease_time)); - #endif +#endif } } #endif /* FAPP_CFG_DHCPC_CMD && FNET_CFG_DHCP_CLN */ @@ -305,7 +305,7 @@ void fapp_dhcp_srv_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t * goto ERROR_PARAMETER; } } - + if(pool == FNET_TRUE) { fnet_dhcp_srv_addr_pool_info_t addr_pool_info; @@ -326,14 +326,14 @@ void fapp_dhcp_srv_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t * fnet_shell_println(desc, "\t"); } } - else if(init == FNET_TRUE) + else if(init == FNET_TRUE) { /* Set the default IPv4 address for the interface running the DHCP server.*/ fnet_netif_set_ip4_addr(netif, FAPP_CFG_DHCP_CMD_IP4_ADDR, FAPP_CFG_DHCP_CMD_IP4_MASK); fnet_netif_set_ip4_gateway(netif, FAPP_CFG_DHCP_CMD_IP4_GW); - #if FNET_CFG_DNS +#if FNET_CFG_DNS fnet_netif_set_ip4_dns(netif, FAPP_CFG_DHCP_CMD_IP4_DNS); - #endif +#endif /* Init parameters.*/ fnet_memset_zero(&dhcp_params, sizeof(dhcp_params)); @@ -379,7 +379,7 @@ void fapp_dhcp_srv_release(void) fnet_dhcp_srv_desc_t dhcp; /* Release all DHCP servers.*/ - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { dhcp = fnet_dhcp_srv_get_by_netif(netif); if(dhcp) diff --git a/fnet_demos/common/fnet_application/fapp_dns.c b/fnet_demos/common/fnet_application/fapp_dns.c index 1b8b208a..219a9cda 100644 --- a/fnet_demos/common/fnet_application/fapp_dns.c +++ b/fnet_demos/common/fnet_application/fapp_dns.c @@ -94,11 +94,11 @@ void fapp_dns_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t **argv /* Set DNS client/resolver parameters.*/ fnet_memset_zero(&dns_params, sizeof(struct fnet_dns_params)); - + dns_params.addr_family = AF_INET; /* [-n ] [-s ] [4|6] */ - for(i = 1u; i < (argc-1) /*avoid the last parameter.*/; i++) + for(i = 1u; i < (argc - 1) /*avoid the last parameter.*/; i++) { if (!fnet_strcmp(argv[i], "-n")) /*[-n ] */ { @@ -153,19 +153,19 @@ void fapp_dns_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t **argv else #endif #if FNET_CFG_IP6 - if(fnet_netif_get_ip6_dns(netif, 0U, (fnet_ip6_addr_t *)&dns_params.dns_server_addr.sa_data) == FNET_TRUE) - { - dns_params.dns_server_addr.sa_family = AF_INET6; - } - else + if(fnet_netif_get_ip6_dns(netif, 0U, (fnet_ip6_addr_t *)&dns_params.dns_server_addr.sa_data) == FNET_TRUE) + { + dns_params.dns_server_addr.sa_family = AF_INET6; + } + else #endif - { - fnet_shell_println(desc, FNET_DNS_UNKNOWN); - return; - } + { + fnet_shell_println(desc, FNET_DNS_UNKNOWN); + return; + } } - dns_params.host_name = argv[argc-1]; /* Host name to resolve - last parameter.*/ + dns_params.host_name = argv[argc - 1]; /* Host name to resolve - last parameter.*/ dns_params.callback = fapp_dns_callback_resolved; /* Callback function.*/ dns_params.cookie = desc; /* Application-specific parameter which will be passed to fapp_dns_callback_resolved().*/ diff --git a/fnet_demos/common/fnet_application/fapp_http.h b/fnet_demos/common/fnet_application/fapp_http.h index ff01e2e2..3b0702f6 100644 --- a/fnet_demos/common/fnet_application/fapp_http.h +++ b/fnet_demos/common/fnet_application/fapp_http.h @@ -44,7 +44,7 @@ void fapp_http_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t **arg void fapp_http_info(fnet_shell_desc_t desc); void fapp_http_release(void); -#if (FNET_CFG_HTTP_TLS && FNET_CFG_TLS) +#if FAPP_CFG_HTTP_TLS_CMD && FNET_CFG_HTTP_TLS && FNET_CFG_TLS extern fnet_http_desc_t fapp_http_tls_desc; /* HTTPS service descriptor. */ void fapp_http_tls_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t **argv ); void fapp_http_tls_release(void); diff --git a/fnet_demos/common/fnet_application/fapp_link.c b/fnet_demos/common/fnet_application/fapp_link.c index 4c80d5e4..18dcb109 100644 --- a/fnet_demos/common/fnet_application/fapp_link.c +++ b/fnet_demos/common/fnet_application/fapp_link.c @@ -41,7 +41,7 @@ static void fapp_link_callback(fnet_netif_desc_t netif, fnet_bool_t connected, v fnet_char_t netif_name[FNET_NETIF_NAMELEN]; fnet_char_t *script_p; fnet_char_t script[FAPP_CFG_SHELL_MAX_LINE_LENGTH]; - + fnet_netif_get_name(netif, netif_name, sizeof(netif_name)); /* connect/disconnect script.*/ @@ -106,8 +106,8 @@ static void fapp_link_script_add_netif_name(fnet_char_t *script_out, fnet_size_t #endif /* Very rude. TBD better way */ - fnet_snprintf(script_out, script_out_size, script_in, - netif_name, netif_name, netif_name, netif_name, netif_name, netif_name, netif_name, netif_name, netif_name, netif_name); + fnet_snprintf(script_out, script_out_size, script_in, + netif_name, netif_name, netif_name, netif_name, netif_name, netif_name, netif_name, netif_name, netif_name, netif_name); } /************************************************************************ @@ -130,9 +130,9 @@ void fapp_link_init(fnet_shell_desc_t desc, fnet_netif_desc_t netif) { #if 0 fnet_char_t netif_name[FNET_NETIF_NAMELEN]; - + fnet_netif_get_name(netif, netif_name, sizeof(netif_name)); - + fnet_shell_println(desc, FAPP_DELIMITER_STR); fnet_shell_println(desc, " Link-Detection service started."); fnet_shell_println(desc, FAPP_SHELL_INFO_FORMAT_S, "Interface", netif_name ); @@ -155,7 +155,7 @@ void fapp_link_release(void) fnet_link_desc_t link; /* Release all Link services.*/ - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { link = fnet_link_get_by_netif(netif); if(link) diff --git a/fnet_demos/common/fnet_application/fapp_llmnr.c b/fnet_demos/common/fnet_application/fapp_llmnr.c index d1792c15..f3264b4d 100644 --- a/fnet_demos/common/fnet_application/fapp_llmnr.c +++ b/fnet_demos/common/fnet_application/fapp_llmnr.c @@ -40,7 +40,7 @@ void fapp_llmnr_release(void) fnet_llmnr_desc_t llmnr; /* Release all LLMNR servers.*/ - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { llmnr = fnet_llmnr_get_by_netif(netif); if(llmnr) @@ -85,7 +85,7 @@ void fapp_llmnr_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t **ar } } - if(init == FNET_TRUE) + if(init == FNET_TRUE) { /* Init parameters.*/ fnet_memset_zero(¶ms, sizeof(params)); diff --git a/fnet_demos/common/fnet_application/fapp_mdns.c b/fnet_demos/common/fnet_application/fapp_mdns.c index ce47a8ee..abc6b84c 100644 --- a/fnet_demos/common/fnet_application/fapp_mdns.c +++ b/fnet_demos/common/fnet_application/fapp_mdns.c @@ -54,7 +54,7 @@ void fapp_mdns_release(void) fnet_mdns_desc_t mdns; /* Release all MDNS servers.*/ - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { mdns = fnet_mdns_get_by_netif(netif); if(mdns) @@ -99,7 +99,7 @@ void fapp_mdns_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t **arg } } - if(init == FNET_TRUE) + if(init == FNET_TRUE) { /* Init parameters.*/ fnet_memset_zero(¶ms, sizeof(params)); @@ -157,12 +157,15 @@ void fapp_mdns_service_register_http( void ) fnet_index_t i; fnet_mdns_desc_t mdns; - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + if(fapp_http_desc) { - mdns = fnet_mdns_get_by_netif(netif); - if(mdns) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { - fnet_mdns_service_register(mdns, &fapp_mdns_http_service); + mdns = fnet_mdns_get_by_netif(netif); + if(mdns) + { + fnet_mdns_service_register(mdns, &fapp_mdns_http_service); + } } } #endif @@ -178,12 +181,15 @@ void fapp_mdns_service_register_http_tls( void ) fnet_index_t i; fnet_mdns_desc_t mdns; - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + if(fapp_http_tls_desc) { - mdns = fnet_mdns_get_by_netif(netif); - if(mdns) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { - fnet_mdns_service_register(mdns, &fapp_mdns_http_tls_service); + mdns = fnet_mdns_get_by_netif(netif); + if(mdns) + { + fnet_mdns_service_register(mdns, &fapp_mdns_http_tls_service); + } } } #endif @@ -199,18 +205,18 @@ void fapp_mdns_service_unregister_http( void ) fnet_index_t i; fnet_mdns_desc_t mdns; - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { mdns = fnet_mdns_get_by_netif(netif); if(mdns) { fnet_mdns_service_desc_t service_desc; - + service_desc = fnet_mdns_service_get_by_type(mdns, fapp_mdns_http_service.service_type); /* If HTTP service is registered.*/ if(service_desc) { - fnet_mdns_service_unregister(service_desc); + fnet_mdns_service_unregister(service_desc); } } } @@ -227,18 +233,18 @@ void fapp_mdns_service_unregister_http_tls( void ) fnet_index_t i; fnet_mdns_desc_t mdns; - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { mdns = fnet_mdns_get_by_netif(netif); if(mdns) { fnet_mdns_service_desc_t service_desc; - + service_desc = fnet_mdns_service_get_by_type(mdns, fapp_mdns_http_tls_service.service_type); /* If HTTP service is registered.*/ if(service_desc) { - fnet_mdns_service_unregister(service_desc); + fnet_mdns_service_unregister(service_desc); } } } diff --git a/fnet_demos/common/fnet_application/fapp_netif.c b/fnet_demos/common/fnet_application/fapp_netif.c index 333ac02c..d002b772 100644 --- a/fnet_demos/common/fnet_application/fapp_netif.c +++ b/fnet_demos/common/fnet_application/fapp_netif.c @@ -99,20 +99,24 @@ struct fapp_netif_init_param fapp_netif_init_param_list[] = /* String equivalent to fnet_netif_ip_addr_type_t */ static const fnet_char_t *const fapp_netif_ip_addr_type_str[] = {"manual", /* FNET_NETIF_IP_ADDR_TYPE_MANUAL */ "autoconfigurable", /* FNET_NETIF_IP_ADDR_TYPE_AUTOCONFIGURABLE */ - "dhcp" /* FNET_NETIF_IP_ADDR_TYPE_DHCP */}; + "dhcp" /* FNET_NETIF_IP_ADDR_TYPE_DHCP */ + }; /* Connection state string */ const fnet_char_t *const fapp_netif_connection_state_str[] = {"disconnected", /* false */ - "connected" /* true */}; + "connected" /* true */ + }; static const fnet_char_t *const fapp_netif_type_str[] = { "", /* FNET_NETIF_TYPE_OTHER */ "Ethernet", /* FNET_NETIF_TYPE_ETHERNET */ "Wi-Fi", /* FNET_NETIF_TYPE_WIFI */ - "Loopback" /* FNET_NETIF_TYPE_LOOPBACK */}; + "Loopback" /* FNET_NETIF_TYPE_LOOPBACK */ + }; static const fnet_char_t *const fapp_wifi_op_mode[] = { "", /* FNET_WIFI_OP_MODE_NONE */ "station", /* FNET_WIFI_OP_MODE_STATION */ - "access point" /* FNET_WIFI_OP_MODE_ACCESS_POINT */}; + "access point" /* FNET_WIFI_OP_MODE_ACCESS_POINT */ + }; /************************************************************************ * DESCRIPTION: Initialization of all supported interfaces. @@ -138,26 +142,26 @@ fnet_return_t fapp_netif_init(fnet_shell_desc_t desc) { fnet_netif_set_ip4_addr(netif, fapp_netif_init_param_list[i].netif_ip4_addr, fapp_netif_init_param_list[i].netif_ip4_subnet_mask); fnet_netif_set_ip4_gateway(netif, fapp_netif_init_param_list[i].netif_ip4_gateway); - #if FNET_CFG_DNS +#if FNET_CFG_DNS fnet_netif_set_ip4_dns(netif, fapp_netif_init_param_list[i].netif_ip4_dns); - #endif +#endif - #if FNET_CFG_LINK +#if FNET_CFG_LINK /* Start Link-Detection. */ fapp_link_init(desc, netif); - #endif +#endif } } /* Set default interface.*/ - { + { fnet_netif_desc_t netif_desc; netif_desc = fnet_netif_get_by_name(FAPP_CFG_PARAMS_NETIF_NAME); if(netif_desc) { - fnet_netif_set_default(netif_desc); + fnet_netif_set_default(netif_desc); } } @@ -174,7 +178,7 @@ void fapp_netif_info_print( fnet_shell_desc_t desc, fnet_netif_desc_t netif) fnet_netif_type_t netif_type; netif_type = fnet_netif_get_type(netif); - fnet_shell_println(desc, "%s Interface%s:", fapp_netif_type_str[netif_type], ((netif == fnet_netif_get_default()) ? " ":"")); + fnet_shell_println(desc, "%s Interface%s:", fapp_netif_type_str[netif_type], ((netif == fnet_netif_get_default()) ? " " : "")); fnet_netif_get_name(netif, name, sizeof(name)); fnet_shell_println(desc, FAPP_SHELL_INFO_FORMAT_S, "Name", name); @@ -239,26 +243,26 @@ void fapp_netif_info_print( fnet_shell_desc_t desc, fnet_netif_desc_t netif) } #endif /* FNET_CFG_IP4 */ - #if FAPP_CFG_DHCP_CMD && FNET_CFG_DHCP_SRV && FNET_CFG_IP4 - fapp_dhcp_srv_info(desc, netif); - #endif +#if FAPP_CFG_DHCP_CMD && FNET_CFG_DHCP_SRV && FNET_CFG_IP4 + fapp_dhcp_srv_info(desc, netif); +#endif - #if FAPP_CFG_DHCPC_CMD && FNET_CFG_DHCP_CLN && FNET_CFG_IP4 - fapp_dhcp_cln_info(desc, netif); - #endif +#if FAPP_CFG_DHCPC_CMD && FNET_CFG_DHCP_CLN && FNET_CFG_IP4 + fapp_dhcp_cln_info(desc, netif); +#endif - #if FAPP_CFG_AUTOIP_CMD && FNET_CFG_AUTOIP && FNET_CFG_IP4 - fapp_autoip_info(desc, netif); - #endif +#if FAPP_CFG_AUTOIP_CMD && FNET_CFG_AUTOIP && FNET_CFG_IP4 + fapp_autoip_info(desc, netif); +#endif - #if FAPP_CFG_LLMNR_CMD && FNET_CFG_LLMNR - fapp_llmnr_info(desc, netif); - #endif +#if FAPP_CFG_LLMNR_CMD && FNET_CFG_LLMNR + fapp_llmnr_info(desc, netif); +#endif - #if FAPP_CFG_MDNS_CMD && FNET_CFG_MDNS - fapp_mdns_info(desc, netif); - #endif - fnet_shell_println(desc,""); +#if FAPP_CFG_MDNS_CMD && FNET_CFG_MDNS + fapp_mdns_info(desc, netif); +#endif + fnet_shell_println(desc, ""); } /************************************************************************ @@ -359,13 +363,13 @@ void fapp_netif_info_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t } if(netif) - { + { fapp_netif_info_print(desc, netif); } else { /* Print info for all initialized interfaces.*/ - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { fapp_netif_info_print(desc, netif); } @@ -374,21 +378,21 @@ void fapp_netif_info_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t #if ((FAPP_CFG_HTTP_CMD || FAPP_CFG_HTTP_TLS_CMD) && FNET_CFG_HTTP) || (FAPP_CFG_TELNET_CMD && FNET_CFG_TELNET) || (FAPP_CFG_TFTP_CMD && FNET_CFG_TFTP_SRV) || (FAPP_CFG_BENCH_CMD && FNET_CFG_BENCH_SRV) fnet_shell_println(desc, "Services:"); /* General services.*/ - #if (FAPP_CFG_HTTP_CMD || FAPP_CFG_HTTP_TLS_CMD) && FNET_CFG_HTTP - fapp_http_info(desc); - #endif +#if (FAPP_CFG_HTTP_CMD || FAPP_CFG_HTTP_TLS_CMD) && FNET_CFG_HTTP + fapp_http_info(desc); +#endif - #if FAPP_CFG_TELNET_CMD && FNET_CFG_TELNET - fapp_telnet_info(desc); - #endif +#if FAPP_CFG_TELNET_CMD && FNET_CFG_TELNET + fapp_telnet_info(desc); +#endif - #if FAPP_CFG_TFTP_CMD && FNET_CFG_TFTP_SRV - fapp_tftp_srv_info(desc); - #endif +#if FAPP_CFG_TFTP_CMD && FNET_CFG_TFTP_SRV + fapp_tftp_srv_info(desc); +#endif - #if FAPP_CFG_BENCH_CMD && FNET_CFG_BENCH_SRV - fapp_bench_srv_info(desc); - #endif +#if FAPP_CFG_BENCH_CMD && FNET_CFG_BENCH_SRV + fapp_bench_srv_info(desc); +#endif #endif return; @@ -409,8 +413,8 @@ static void fapp_netif_stat_print( fnet_shell_desc_t desc, fnet_netif_desc_t net struct fnet_netif_statistics statistics; fnet_char_t name[FNET_NETIF_NAMELEN]; - fnet_shell_println(desc, "%s Interface%s:", fapp_netif_type_str[fnet_netif_get_type(netif)], - ((netif == fnet_netif_get_default()) ? " ":"")); + fnet_shell_println(desc, "%s Interface%s:", fapp_netif_type_str[fnet_netif_get_type(netif)], + ((netif == fnet_netif_get_default()) ? " " : "")); fnet_netif_get_name(netif, name, sizeof(name)); fnet_shell_println(desc, FAPP_SHELL_INFO_FORMAT_S, "Name", name); @@ -479,7 +483,7 @@ static void fapp_netif_stat_print( fnet_shell_desc_t desc, fnet_netif_desc_t net } } #endif - fnet_shell_println(desc,""); + fnet_shell_println(desc, ""); } /************************************************************************ @@ -512,13 +516,13 @@ void fapp_netif_stat_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t } if(netif) - { + { fapp_netif_stat_print(desc, netif); } else { /* Print info for all initialized interfaces.*/ - for(i=0; (netif = fnet_netif_get_by_number(i)); i++) + for(i = 0; (netif = fnet_netif_get_by_number(i)); i++) { fapp_netif_stat_print(desc, netif); } diff --git a/fnet_demos/common/fnet_application/fapp_params.c b/fnet_demos/common/fnet_application/fapp_params.c index 699cce80..7acd652e 100644 --- a/fnet_demos/common/fnet_application/fapp_params.c +++ b/fnet_demos/common/fnet_application/fapp_params.c @@ -69,17 +69,17 @@ static const struct fapp_params_flash fapp_params_config .fnet_params = { .netif_name = FAPP_CFG_PARAMS_NETIF_NAME, /* Default interface */ - .address = FAPP_CFG_PARAMS_IP_ADDR, - .netmask = FAPP_CFG_PARAMS_IP_MASK, - .gateway = FAPP_CFG_PARAMS_IP_GW, - .dns = FAPP_CFG_PARAMS_IP_DNS, - .mac = FAPP_CFG_PARAMS_MAC_ADDR, - .host_name = FAPP_CFG_PARAMS_HOST_NAME + .address = FAPP_CFG_PARAMS_IP_ADDR, + .netmask = FAPP_CFG_PARAMS_IP_MASK, + .gateway = FAPP_CFG_PARAMS_IP_GW, + .dns = FAPP_CFG_PARAMS_IP_DNS, + .mac = FAPP_CFG_PARAMS_MAC_ADDR, + .host_name = FAPP_CFG_PARAMS_HOST_NAME }, .boot_params = { .mode = FAPP_CFG_PARAMS_BOOT_MODE, - .delay = FAPP_CFG_PARAMS_BOOT_DELAY, + .delay = FAPP_CFG_PARAMS_BOOT_DELAY, .go_address = FAPP_CFG_PARAMS_BOOT_GO_ADDRESS, .script = FAPP_CFG_PARAMS_BOOT_SCRIPT }, diff --git a/fnet_demos/common/fnet_application/fapp_shell.c b/fnet_demos/common/fnet_application/fapp_shell.c index 0ec80e13..4904c71c 100644 --- a/fnet_demos/common/fnet_application/fapp_shell.c +++ b/fnet_demos/common/fnet_application/fapp_shell.c @@ -251,7 +251,8 @@ const struct fnet_shell_command fapp_cmd_table [] = /* Connection state string */ const fnet_char_t *const fapp_is_enabled_str[] = {"off", /* Disabled */ - "on" /* Enabled */}; + "on" /* Enabled */ + }; /* Shell command-line buffer.*/ static fnet_char_t fapp_cmd_line_buffer[FAPP_CFG_SHELL_MAX_LINE_LENGTH]; @@ -272,14 +273,14 @@ static const struct fnet_shell fapp_shell = fnet_shell_desc_t fapp_shell_init(void) { struct fnet_shell_params shell_params; - + /* Init main shell. */ shell_params.shell = &fapp_shell; shell_params.cmd_line_buffer = fapp_cmd_line_buffer; shell_params.cmd_line_buffer_size = sizeof(fapp_cmd_line_buffer); shell_params.stream = FNET_SERIAL_STREAM_DEFAULT; shell_params.echo = FNET_TRUE; - + return fnet_shell_init(&shell_params); } @@ -516,7 +517,7 @@ static void fapp_bind_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_ { if(argc > 2u) /* There are additional parameters */ { - for(i = 1u; i < (argc-1)/*avoid the last parameter.*/ ; i++) + for(i = 1u; i < (argc - 1)/*avoid the last parameter.*/ ; i++) { if (!fnet_strcmp(argv[i], "-n")) /*[-n ] */ { @@ -537,7 +538,7 @@ static void fapp_bind_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_ } } } - + /* Bind Ipv6 address.*/ if(fnet_netif_bind_ip6_addr(netif, &addr, FNET_NETIF_IP_ADDR_TYPE_MANUAL) == FNET_ERR) { @@ -571,7 +572,7 @@ static void fapp_unbind_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_cha { if(argc > 2u) /* There are additional parameters */ { - for(i = 1u; i < (argc-1)/*avoid the last parameter.*/ ; i++) + for(i = 1u; i < (argc - 1)/*avoid the last parameter.*/ ; i++) { if (!fnet_strcmp(argv[i], "-n")) /*[-n ] */ { @@ -592,7 +593,7 @@ static void fapp_unbind_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_cha } } } - + /* Unbind Ipv6 address.*/ if(fnet_netif_unbind_ip6_addr(netif, &addr) == FNET_ERR) { diff --git a/fnet_demos/common/fnet_application/fapp_tftp.c b/fnet_demos/common/fnet_application/fapp_tftp.c index 73be2e4c..09935474 100644 --- a/fnet_demos/common/fnet_application/fapp_tftp.c +++ b/fnet_demos/common/fnet_application/fapp_tftp.c @@ -1202,7 +1202,7 @@ static fnet_return_t fapp_tftps_request_handler(fnet_tftp_request_t request_type /* Do erase all, on WRITE request.*/ if(request_type == FNET_TFTP_REQUEST_WRITE) { - if(fnet_shell_script(desc, FAPP_CFG_TFTPS_ON_WRITE_REQUEST_SCRIPT)== FNET_ERR) + if(fnet_shell_script(desc, FAPP_CFG_TFTPS_ON_WRITE_REQUEST_SCRIPT) == FNET_ERR) { fnet_shell_println(desc, "Script error!"); } @@ -1259,7 +1259,7 @@ static fnet_int32_t fapp_tftps_data_handler(fnet_tftp_request_t request, fnet_shell_println(desc, FAPP_TFTP_COMPLETED_STR, fapp_tftps_handler_control.image_size); /* Set "go" state and save settings..*/ - if(fnet_shell_script(desc, FAPP_CFG_TFTPS_AFTER_WRITE_REQUEST_SCRIPT)== FNET_ERR) + if(fnet_shell_script(desc, FAPP_CFG_TFTPS_AFTER_WRITE_REQUEST_SCRIPT) == FNET_ERR) { fnet_shell_println(desc, "Script error!"); } diff --git a/fnet_demos/common/fnet_application/fapp_wifi.c b/fnet_demos/common/fnet_application/fapp_wifi.c index 9bd3c5ef..1f6dd858 100644 --- a/fnet_demos/common/fnet_application/fapp_wifi.c +++ b/fnet_demos/common/fnet_application/fapp_wifi.c @@ -50,7 +50,7 @@ void fapp_wifi_connect_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char } } - if(fnet_wifi_connect(FNET_CPU_WIFI_IF, &connect_params)== FNET_ERR) + if(fnet_wifi_connect(FNET_CPU_WIFI_IF, &connect_params) == FNET_ERR) { fnet_shell_println(desc, "Wi-Fi connection is failed."); } @@ -86,15 +86,14 @@ void fapp_wifi_ap_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t ** if(argc >= 3u) { access_point_params.wpa_passphrase = argv[2]; - + if(argc >= 4u) { - if (!fnet_strcmp(argv[3], "wpa")) + if (!fnet_strcmp(argv[3], "wpa")) { access_point_params.wpa_mode = FNET_WIFI_WPA; } - else - if (!fnet_strcmp(argv[3], "wpa2")) + else if (!fnet_strcmp(argv[3], "wpa2")) { access_point_params.wpa_mode = FNET_WIFI_WPA2; } @@ -107,7 +106,7 @@ void fapp_wifi_ap_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t ** } } - if(fnet_wifi_access_point(FNET_CPU_WIFI_IF, &access_point_params)== FNET_ERR) + if(fnet_wifi_access_point(FNET_CPU_WIFI_IF, &access_point_params) == FNET_ERR) { fnet_shell_println(desc, "Wi-Fi Access Point is failed."); } @@ -122,9 +121,9 @@ void fapp_wifi_ap_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t ** /* Set default IPv4 parameters for Wi-Fi AP mode */ fnet_netif_set_ip4_addr(FNET_CPU_WIFI_IF, FAPP_CFG_WIFI_AP_IP4_ADDR, FAPP_CFG_WIFI_AP_IP4_MASK); fnet_netif_set_ip4_gateway(FNET_CPU_WIFI_IF, FAPP_CFG_WIFI_AP_IP4_GW); - #if FNET_CFG_DNS +#if FNET_CFG_DNS fnet_netif_set_ip4_dns(FNET_CPU_WIFI_IF, FAPP_CFG_WIFI_AP_IP4_DNS); - #endif +#endif } return; @@ -139,7 +138,7 @@ void fapp_wifi_ap_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t ** *************************************************************************/ void fapp_wifi_disconnect_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t **argv ) { - if(fnet_wifi_disconnect(FNET_CPU_WIFI_IF)== FNET_ERR) + if(fnet_wifi_disconnect(FNET_CPU_WIFI_IF) == FNET_ERR) { fnet_shell_println(desc, "Wi-Fi disconnection is failed."); } @@ -162,7 +161,7 @@ void fapp_wifi_fw_cmd( fnet_shell_desc_t desc, fnet_index_t argc, fnet_char_t ** result = fnet_wifi_fw_update(FNET_CPU_WIFI_IF, FAPP_WIFI_FW_IMAGE, sizeof(FAPP_WIFI_FW_IMAGE)); - fnet_shell_println(desc, "Wi-Fi FW update is %s", (result == FNET_OK)?"completed":"failed"); + fnet_shell_println(desc, "Wi-Fi FW update is %s", (result == FNET_OK) ? "completed" : "failed"); } #endif /* FNET_CFG_CPU_WIFI_FW_UPDATE */ diff --git a/fnet_demos/common/fnet_webpage/src/index.html b/fnet_demos/common/fnet_webpage/src/index.html index b8071f78..9ba52d19 100644 --- a/fnet_demos/common/fnet_webpage/src/index.html +++ b/fnet_demos/common/fnet_webpage/src/index.html @@ -65,7 +65,7 @@
- © 2005-2017 by Andrey Butok, FNET Community. + © 2005-2018 by Andrey Butok, FNET Community.
diff --git a/fnet_demos/common/startup/LPC54628/LPC54628.h b/fnet_demos/common/startup/LPC54628/LPC54628.h new file mode 100644 index 00000000..50bbe5a0 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/LPC54628.h @@ -0,0 +1,12527 @@ +/* +** ################################################################### +** Processor: LPC54628J512ET180 +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 +** Version: rev. 1.2, 2017-06-08 +** Build: b170609 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC54628 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-08-12) +** Initial version. +** - rev. 1.1 (2016-11-25) +** Update CANFD and Classic CAN register. +** Add MAC TIMERSTAMP registers. +** - rev. 1.2 (2017-06-08) +** Remove RTC_CTRL_RTC_OSC_BYPASS. +** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. +** Remove RESET and HALT from SYSCON_AHBCLKDIV. +** +** ################################################################### +*/ + +/*! + * @file LPC54628.h + * @version 1.2 + * @date 2017-06-08 + * @brief CMSIS Peripheral Access Layer for LPC54628 + * + * CMSIS Peripheral Access Layer for LPC54628 + */ + +#ifndef _LPC54628_H_ +#define _LPC54628_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0002U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ + DMA0_IRQn = 1, /**< DMA controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */ + ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ + ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ + ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ + DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */ + HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + Reserved47_IRQn = 31, /**< Reserved interrupt */ + PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ + PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ + PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ + PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ + CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ + CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ + RIT_IRQn = 38, /**< Repetitive Interrupt Timer */ + SPIFI0_IRQn = 39, /**< SPI flash interface */ + FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */ + FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */ + SDIO_IRQn = 42, /**< SD/MMC */ + CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ + CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ + CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */ + CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */ + USB1_IRQn = 47, /**< USB1 interrupt */ + USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ + ETHERNET_IRQn = 49, /**< Ethernet */ + ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */ + ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */ + EEPROM_IRQn = 52, /**< EEPROM interrupt */ + LCD_IRQn = 53, /**< LCD interrupt */ + SHA_IRQn = 54, /**< SHA interrupt */ + SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */ + SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_LPC54628.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ + __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ + __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ + __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ + uint8_t RESERVED_0[8]; + __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ + __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ + __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ + __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ + __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ + __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ + __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ + __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ + __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ + __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ +#define ADC_CTRL_CLKDIV_MASK (0xFFU) +#define ADC_CTRL_CLKDIV_SHIFT (0U) +#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) +#define ADC_CTRL_ASYNMODE_MASK (0x100U) +#define ADC_CTRL_ASYNMODE_SHIFT (8U) +#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) +#define ADC_CTRL_RESOL_MASK (0x600U) +#define ADC_CTRL_RESOL_SHIFT (9U) +#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) +#define ADC_CTRL_BYPASSCAL_MASK (0x800U) +#define ADC_CTRL_BYPASSCAL_SHIFT (11U) +#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) +#define ADC_CTRL_TSAMP_MASK (0x7000U) +#define ADC_CTRL_TSAMP_SHIFT (12U) +#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) + +/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ +#define ADC_INSEL_SEL_MASK (0x3U) +#define ADC_INSEL_SEL_SHIFT (0U) +#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) + +/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ +#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) +#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) +#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) +#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) +#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) +#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) +#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) +#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) +#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) +#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) +#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) +#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) +#define ADC_SEQ_CTRL_START_MASK (0x4000000U) +#define ADC_SEQ_CTRL_START_SHIFT (26U) +#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) +#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) +#define ADC_SEQ_CTRL_BURST_SHIFT (27U) +#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) +#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) +#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) +#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) +#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) +#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) +#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) +#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) +#define ADC_SEQ_CTRL_MODE_SHIFT (30U) +#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) +#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) +#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) +#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) + +/* The count of ADC_SEQ_CTRL */ +#define ADC_SEQ_CTRL_COUNT (2U) + +/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ +#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) +#define ADC_SEQ_GDAT_RESULT_SHIFT (4U) +#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) +#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) +#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) +#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) +#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) +#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) +#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) +#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) +#define ADC_SEQ_GDAT_CHN_SHIFT (26U) +#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) +#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) +#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) +#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) +#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) +#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) +#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) + +/* The count of ADC_SEQ_GDAT */ +#define ADC_SEQ_GDAT_COUNT (2U) + +/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ +#define ADC_DAT_RESULT_MASK (0xFFF0U) +#define ADC_DAT_RESULT_SHIFT (4U) +#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) +#define ADC_DAT_THCMPRANGE_MASK (0x30000U) +#define ADC_DAT_THCMPRANGE_SHIFT (16U) +#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) +#define ADC_DAT_THCMPCROSS_MASK (0xC0000U) +#define ADC_DAT_THCMPCROSS_SHIFT (18U) +#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) +#define ADC_DAT_CHANNEL_MASK (0x3C000000U) +#define ADC_DAT_CHANNEL_SHIFT (26U) +#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) +#define ADC_DAT_OVERRUN_MASK (0x40000000U) +#define ADC_DAT_OVERRUN_SHIFT (30U) +#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) +#define ADC_DAT_DATAVALID_MASK (0x80000000U) +#define ADC_DAT_DATAVALID_SHIFT (31U) +#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) + +/* The count of ADC_DAT */ +#define ADC_DAT_COUNT (12U) + +/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) +#define ADC_THR0_LOW_THRLOW_SHIFT (4U) +#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) + +/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) +#define ADC_THR1_LOW_THRLOW_SHIFT (4U) +#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) + +/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) +#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) +#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) + +/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) +#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) +#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) + +/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ +#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) +#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) +#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) +#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) +#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) +#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) +#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) +#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) +#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) +#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) +#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) +#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) +#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) +#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) +#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) +#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) +#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) +#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) +#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) +#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) +#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) +#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) +#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) +#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) +#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) + +/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ +#define ADC_INTEN_SEQA_INTEN_MASK (0x1U) +#define ADC_INTEN_SEQA_INTEN_SHIFT (0U) +#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) +#define ADC_INTEN_SEQB_INTEN_MASK (0x2U) +#define ADC_INTEN_SEQB_INTEN_SHIFT (1U) +#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) +#define ADC_INTEN_OVR_INTEN_MASK (0x4U) +#define ADC_INTEN_OVR_INTEN_SHIFT (2U) +#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) +#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) +#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) +#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) +#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) +#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) +#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) +#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) +#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) +#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) +#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) +#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) +#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) +#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) +#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) +#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) +#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) +#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) +#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) +#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) +#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) +#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) +#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) +#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) +#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) +#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) +#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) +#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) +#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) +#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) +#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) +#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) +#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) +#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) +#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) +#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) +#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) + +/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ +#define ADC_FLAGS_THCMP0_MASK (0x1U) +#define ADC_FLAGS_THCMP0_SHIFT (0U) +#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) +#define ADC_FLAGS_THCMP1_MASK (0x2U) +#define ADC_FLAGS_THCMP1_SHIFT (1U) +#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) +#define ADC_FLAGS_THCMP2_MASK (0x4U) +#define ADC_FLAGS_THCMP2_SHIFT (2U) +#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) +#define ADC_FLAGS_THCMP3_MASK (0x8U) +#define ADC_FLAGS_THCMP3_SHIFT (3U) +#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) +#define ADC_FLAGS_THCMP4_MASK (0x10U) +#define ADC_FLAGS_THCMP4_SHIFT (4U) +#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) +#define ADC_FLAGS_THCMP5_MASK (0x20U) +#define ADC_FLAGS_THCMP5_SHIFT (5U) +#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) +#define ADC_FLAGS_THCMP6_MASK (0x40U) +#define ADC_FLAGS_THCMP6_SHIFT (6U) +#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) +#define ADC_FLAGS_THCMP7_MASK (0x80U) +#define ADC_FLAGS_THCMP7_SHIFT (7U) +#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) +#define ADC_FLAGS_THCMP8_MASK (0x100U) +#define ADC_FLAGS_THCMP8_SHIFT (8U) +#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) +#define ADC_FLAGS_THCMP9_MASK (0x200U) +#define ADC_FLAGS_THCMP9_SHIFT (9U) +#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) +#define ADC_FLAGS_THCMP10_MASK (0x400U) +#define ADC_FLAGS_THCMP10_SHIFT (10U) +#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) +#define ADC_FLAGS_THCMP11_MASK (0x800U) +#define ADC_FLAGS_THCMP11_SHIFT (11U) +#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) +#define ADC_FLAGS_OVERRUN0_MASK (0x1000U) +#define ADC_FLAGS_OVERRUN0_SHIFT (12U) +#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) +#define ADC_FLAGS_OVERRUN1_MASK (0x2000U) +#define ADC_FLAGS_OVERRUN1_SHIFT (13U) +#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) +#define ADC_FLAGS_OVERRUN2_MASK (0x4000U) +#define ADC_FLAGS_OVERRUN2_SHIFT (14U) +#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) +#define ADC_FLAGS_OVERRUN3_MASK (0x8000U) +#define ADC_FLAGS_OVERRUN3_SHIFT (15U) +#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) +#define ADC_FLAGS_OVERRUN4_MASK (0x10000U) +#define ADC_FLAGS_OVERRUN4_SHIFT (16U) +#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) +#define ADC_FLAGS_OVERRUN5_MASK (0x20000U) +#define ADC_FLAGS_OVERRUN5_SHIFT (17U) +#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) +#define ADC_FLAGS_OVERRUN6_MASK (0x40000U) +#define ADC_FLAGS_OVERRUN6_SHIFT (18U) +#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) +#define ADC_FLAGS_OVERRUN7_MASK (0x80000U) +#define ADC_FLAGS_OVERRUN7_SHIFT (19U) +#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) +#define ADC_FLAGS_OVERRUN8_MASK (0x100000U) +#define ADC_FLAGS_OVERRUN8_SHIFT (20U) +#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) +#define ADC_FLAGS_OVERRUN9_MASK (0x200000U) +#define ADC_FLAGS_OVERRUN9_SHIFT (21U) +#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) +#define ADC_FLAGS_OVERRUN10_MASK (0x400000U) +#define ADC_FLAGS_OVERRUN10_SHIFT (22U) +#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) +#define ADC_FLAGS_OVERRUN11_MASK (0x800000U) +#define ADC_FLAGS_OVERRUN11_SHIFT (23U) +#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) +#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) +#define ADC_FLAGS_SEQA_OVR_SHIFT (24U) +#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) +#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) +#define ADC_FLAGS_SEQB_OVR_SHIFT (25U) +#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) +#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) +#define ADC_FLAGS_SEQA_INT_SHIFT (28U) +#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) +#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) +#define ADC_FLAGS_SEQB_INT_SHIFT (29U) +#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) +#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) +#define ADC_FLAGS_THCMP_INT_SHIFT (30U) +#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) +#define ADC_FLAGS_OVR_INT_MASK (0x80000000U) +#define ADC_FLAGS_OVR_INT_SHIFT (31U) +#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) + +/*! @name STARTUP - ADC Startup register. */ +#define ADC_STARTUP_ADC_ENA_MASK (0x1U) +#define ADC_STARTUP_ADC_ENA_SHIFT (0U) +#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) +#define ADC_STARTUP_ADC_INIT_MASK (0x2U) +#define ADC_STARTUP_ADC_INIT_SHIFT (1U) +#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) + +/*! @name CALIB - ADC Calibration register. */ +#define ADC_CALIB_CALIB_MASK (0x1U) +#define ADC_CALIB_CALIB_SHIFT (0U) +#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) +#define ADC_CALIB_CALREQD_MASK (0x2U) +#define ADC_CALIB_CALREQD_SHIFT (1U) +#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) +#define ADC_CALIB_CALVALUE_MASK (0x1FCU) +#define ADC_CALIB_CALVALUE_SHIFT (2U) +#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400A0000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } +#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ASYNC_SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer + * @{ + */ + +/** ASYNC_SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ + __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ + __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ + __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ + __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ +} ASYNC_SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- ASYNC_SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks + * @{ + */ + +/*! @name ASYNCPRESETCTRL - Async peripheral reset control */ +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) + +/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) + +/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) + +/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) + +/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) + +/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) + +/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) + + +/*! + * @} + */ /* end of group ASYNC_SYSCON_Register_Masks */ + + +/* ASYNC_SYSCON - Peripheral instance base addresses */ +/** Peripheral ASYNC_SYSCON base address */ +#define ASYNC_SYSCON_BASE (0x40040000u) +/** Peripheral ASYNC_SYSCON base pointer */ +#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) +/** Array initializer of ASYNC_SYSCON peripheral base addresses */ +#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } +/** Array initializer of ASYNC_SYSCON peripheral base pointers */ +#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } + +/*! + * @} + */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[12]; + __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */ + __IO uint32_t TEST; /**< Test Register, offset: 0x10 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */ + __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */ + __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ + __IO uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ + __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ + __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ + uint8_t RESERVED_2[16]; + __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */ + __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */ + __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */ + __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ + __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ + __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ + uint8_t RESERVED_4[32]; + __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ + __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ + __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ + uint8_t RESERVED_5[4]; + __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ + __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ + __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ + __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ + __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ + __IO uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ + __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ + __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ + __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ + __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ + __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ + __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ + __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ + __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ + __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ + __IO uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ + __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ + __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ + __IO uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ + __IO uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ + __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ + __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ + uint8_t RESERVED_6[8]; + __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ + __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ + __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ + uint8_t RESERVED_7[260]; + __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */ + uint8_t RESERVED_8[508]; + __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ + uint8_t RESERVED_9[508]; + __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name DBTP - Data Bit Timing Prescaler Register */ +#define CAN_DBTP_DSJW_MASK (0xFU) +#define CAN_DBTP_DSJW_SHIFT (0U) +#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK) +#define CAN_DBTP_DTSEG2_MASK (0xF0U) +#define CAN_DBTP_DTSEG2_SHIFT (4U) +#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK) +#define CAN_DBTP_DTSEG1_MASK (0x1F00U) +#define CAN_DBTP_DTSEG1_SHIFT (8U) +#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK) +#define CAN_DBTP_DBRP_MASK (0x1F0000U) +#define CAN_DBTP_DBRP_SHIFT (16U) +#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK) +#define CAN_DBTP_TDC_MASK (0x800000U) +#define CAN_DBTP_TDC_SHIFT (23U) +#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK) + +/*! @name TEST - Test Register */ +#define CAN_TEST_LBCK_MASK (0x10U) +#define CAN_TEST_LBCK_SHIFT (4U) +#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) +#define CAN_TEST_TX_MASK (0x60U) +#define CAN_TEST_TX_SHIFT (5U) +#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) +#define CAN_TEST_RX_MASK (0x80U) +#define CAN_TEST_RX_SHIFT (7U) +#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) + +/*! @name CCCR - CC Control Register */ +#define CAN_CCCR_INIT_MASK (0x1U) +#define CAN_CCCR_INIT_SHIFT (0U) +#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) +#define CAN_CCCR_CCE_MASK (0x2U) +#define CAN_CCCR_CCE_SHIFT (1U) +#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) +#define CAN_CCCR_ASM_MASK (0x4U) +#define CAN_CCCR_ASM_SHIFT (2U) +#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) +#define CAN_CCCR_CSA_MASK (0x8U) +#define CAN_CCCR_CSA_SHIFT (3U) +#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) +#define CAN_CCCR_CSR_MASK (0x10U) +#define CAN_CCCR_CSR_SHIFT (4U) +#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) +#define CAN_CCCR_MON_MASK (0x20U) +#define CAN_CCCR_MON_SHIFT (5U) +#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) +#define CAN_CCCR_DAR_MASK (0x40U) +#define CAN_CCCR_DAR_SHIFT (6U) +#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) +#define CAN_CCCR_TEST_MASK (0x80U) +#define CAN_CCCR_TEST_SHIFT (7U) +#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) +#define CAN_CCCR_FDOE_MASK (0x100U) +#define CAN_CCCR_FDOE_SHIFT (8U) +#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK) +#define CAN_CCCR_BRSE_MASK (0x200U) +#define CAN_CCCR_BRSE_SHIFT (9U) +#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK) +#define CAN_CCCR_PXHD_MASK (0x1000U) +#define CAN_CCCR_PXHD_SHIFT (12U) +#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) +#define CAN_CCCR_EFBI_MASK (0x2000U) +#define CAN_CCCR_EFBI_SHIFT (13U) +#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) +#define CAN_CCCR_TXP_MASK (0x4000U) +#define CAN_CCCR_TXP_SHIFT (14U) +#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) +#define CAN_CCCR_NISO_MASK (0x8000U) +#define CAN_CCCR_NISO_SHIFT (15U) +#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK) + +/*! @name NBTP - Nominal Bit Timing and Prescaler Register */ +#define CAN_NBTP_NTSEG2_MASK (0x7FU) +#define CAN_NBTP_NTSEG2_SHIFT (0U) +#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) +#define CAN_NBTP_NTSEG1_MASK (0xFF00U) +#define CAN_NBTP_NTSEG1_SHIFT (8U) +#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) +#define CAN_NBTP_NBRP_MASK (0x1FF0000U) +#define CAN_NBTP_NBRP_SHIFT (16U) +#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) +#define CAN_NBTP_NSJW_MASK (0xFE000000U) +#define CAN_NBTP_NSJW_SHIFT (25U) +#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) + +/*! @name TSCC - Timestamp Counter Configuration */ +#define CAN_TSCC_TSS_MASK (0x3U) +#define CAN_TSCC_TSS_SHIFT (0U) +#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) +#define CAN_TSCC_TCP_MASK (0xF0000U) +#define CAN_TSCC_TCP_SHIFT (16U) +#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) + +/*! @name TSCV - Timestamp Counter Value */ +#define CAN_TSCV_TSC_MASK (0xFFFFU) +#define CAN_TSCV_TSC_SHIFT (0U) +#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) + +/*! @name TOCC - Timeout Counter Configuration */ +#define CAN_TOCC_ETOC_MASK (0x1U) +#define CAN_TOCC_ETOC_SHIFT (0U) +#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) +#define CAN_TOCC_TOS_MASK (0x6U) +#define CAN_TOCC_TOS_SHIFT (1U) +#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) +#define CAN_TOCC_TOP_MASK (0xFFFF0000U) +#define CAN_TOCC_TOP_SHIFT (16U) +#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) + +/*! @name TOCV - Timeout Counter Value */ +#define CAN_TOCV_TOC_MASK (0xFFFFU) +#define CAN_TOCV_TOC_SHIFT (0U) +#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) + +/*! @name ECR - Error Counter Register */ +#define CAN_ECR_TEC_MASK (0xFFU) +#define CAN_ECR_TEC_SHIFT (0U) +#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) +#define CAN_ECR_REC_MASK (0x7F00U) +#define CAN_ECR_REC_SHIFT (8U) +#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) +#define CAN_ECR_RP_MASK (0x8000U) +#define CAN_ECR_RP_SHIFT (15U) +#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) +#define CAN_ECR_CEL_MASK (0xFF0000U) +#define CAN_ECR_CEL_SHIFT (16U) +#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) + +/*! @name PSR - Protocol Status Register */ +#define CAN_PSR_LEC_MASK (0x7U) +#define CAN_PSR_LEC_SHIFT (0U) +#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) +#define CAN_PSR_ACT_MASK (0x18U) +#define CAN_PSR_ACT_SHIFT (3U) +#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) +#define CAN_PSR_EP_MASK (0x20U) +#define CAN_PSR_EP_SHIFT (5U) +#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) +#define CAN_PSR_EW_MASK (0x40U) +#define CAN_PSR_EW_SHIFT (6U) +#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) +#define CAN_PSR_BO_MASK (0x80U) +#define CAN_PSR_BO_SHIFT (7U) +#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) +#define CAN_PSR_DLEC_MASK (0x700U) +#define CAN_PSR_DLEC_SHIFT (8U) +#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK) +#define CAN_PSR_RESI_MASK (0x800U) +#define CAN_PSR_RESI_SHIFT (11U) +#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK) +#define CAN_PSR_RBRS_MASK (0x1000U) +#define CAN_PSR_RBRS_SHIFT (12U) +#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK) +#define CAN_PSR_RFDF_MASK (0x2000U) +#define CAN_PSR_RFDF_SHIFT (13U) +#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK) +#define CAN_PSR_PXE_MASK (0x4000U) +#define CAN_PSR_PXE_SHIFT (14U) +#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) +#define CAN_PSR_TDCV_MASK (0x7F0000U) +#define CAN_PSR_TDCV_SHIFT (16U) +#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) + +/*! @name TDCR - Transmitter Delay Compensator Register */ +#define CAN_TDCR_TDCF_MASK (0x7FU) +#define CAN_TDCR_TDCF_SHIFT (0U) +#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) +#define CAN_TDCR_TDCO_MASK (0x7F00U) +#define CAN_TDCR_TDCO_SHIFT (8U) +#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) + +/*! @name IR - Interrupt Register */ +#define CAN_IR_RF0N_MASK (0x1U) +#define CAN_IR_RF0N_SHIFT (0U) +#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) +#define CAN_IR_RF0W_MASK (0x2U) +#define CAN_IR_RF0W_SHIFT (1U) +#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) +#define CAN_IR_RF0F_MASK (0x4U) +#define CAN_IR_RF0F_SHIFT (2U) +#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) +#define CAN_IR_RF0L_MASK (0x8U) +#define CAN_IR_RF0L_SHIFT (3U) +#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) +#define CAN_IR_RF1N_MASK (0x10U) +#define CAN_IR_RF1N_SHIFT (4U) +#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) +#define CAN_IR_RF1W_MASK (0x20U) +#define CAN_IR_RF1W_SHIFT (5U) +#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) +#define CAN_IR_RF1F_MASK (0x40U) +#define CAN_IR_RF1F_SHIFT (6U) +#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) +#define CAN_IR_RF1L_MASK (0x80U) +#define CAN_IR_RF1L_SHIFT (7U) +#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) +#define CAN_IR_HPM_MASK (0x100U) +#define CAN_IR_HPM_SHIFT (8U) +#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) +#define CAN_IR_TC_MASK (0x200U) +#define CAN_IR_TC_SHIFT (9U) +#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) +#define CAN_IR_TCF_MASK (0x400U) +#define CAN_IR_TCF_SHIFT (10U) +#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) +#define CAN_IR_TFE_MASK (0x800U) +#define CAN_IR_TFE_SHIFT (11U) +#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) +#define CAN_IR_TEFN_MASK (0x1000U) +#define CAN_IR_TEFN_SHIFT (12U) +#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) +#define CAN_IR_TEFW_MASK (0x2000U) +#define CAN_IR_TEFW_SHIFT (13U) +#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) +#define CAN_IR_TEFF_MASK (0x4000U) +#define CAN_IR_TEFF_SHIFT (14U) +#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) +#define CAN_IR_TEFL_MASK (0x8000U) +#define CAN_IR_TEFL_SHIFT (15U) +#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) +#define CAN_IR_TSW_MASK (0x10000U) +#define CAN_IR_TSW_SHIFT (16U) +#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) +#define CAN_IR_MRAF_MASK (0x20000U) +#define CAN_IR_MRAF_SHIFT (17U) +#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) +#define CAN_IR_TOO_MASK (0x40000U) +#define CAN_IR_TOO_SHIFT (18U) +#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) +#define CAN_IR_DRX_MASK (0x80000U) +#define CAN_IR_DRX_SHIFT (19U) +#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) +#define CAN_IR_BEC_MASK (0x100000U) +#define CAN_IR_BEC_SHIFT (20U) +#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) +#define CAN_IR_BEU_MASK (0x200000U) +#define CAN_IR_BEU_SHIFT (21U) +#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) +#define CAN_IR_ELO_MASK (0x400000U) +#define CAN_IR_ELO_SHIFT (22U) +#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) +#define CAN_IR_EP_MASK (0x800000U) +#define CAN_IR_EP_SHIFT (23U) +#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) +#define CAN_IR_EW_MASK (0x1000000U) +#define CAN_IR_EW_SHIFT (24U) +#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) +#define CAN_IR_BO_MASK (0x2000000U) +#define CAN_IR_BO_SHIFT (25U) +#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) +#define CAN_IR_WDI_MASK (0x4000000U) +#define CAN_IR_WDI_SHIFT (26U) +#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) +#define CAN_IR_PEA_MASK (0x8000000U) +#define CAN_IR_PEA_SHIFT (27U) +#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) +#define CAN_IR_PED_MASK (0x10000000U) +#define CAN_IR_PED_SHIFT (28U) +#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) +#define CAN_IR_ARA_MASK (0x20000000U) +#define CAN_IR_ARA_SHIFT (29U) +#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) + +/*! @name IE - Interrupt Enable */ +#define CAN_IE_RF0NE_MASK (0x1U) +#define CAN_IE_RF0NE_SHIFT (0U) +#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) +#define CAN_IE_RF0WE_MASK (0x2U) +#define CAN_IE_RF0WE_SHIFT (1U) +#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) +#define CAN_IE_RF0FE_MASK (0x4U) +#define CAN_IE_RF0FE_SHIFT (2U) +#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) +#define CAN_IE_RF0LE_MASK (0x8U) +#define CAN_IE_RF0LE_SHIFT (3U) +#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) +#define CAN_IE_RF1NE_MASK (0x10U) +#define CAN_IE_RF1NE_SHIFT (4U) +#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) +#define CAN_IE_RF1WE_MASK (0x20U) +#define CAN_IE_RF1WE_SHIFT (5U) +#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) +#define CAN_IE_RF1FE_MASK (0x40U) +#define CAN_IE_RF1FE_SHIFT (6U) +#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) +#define CAN_IE_RF1LE_MASK (0x80U) +#define CAN_IE_RF1LE_SHIFT (7U) +#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) +#define CAN_IE_HPME_MASK (0x100U) +#define CAN_IE_HPME_SHIFT (8U) +#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) +#define CAN_IE_TCE_MASK (0x200U) +#define CAN_IE_TCE_SHIFT (9U) +#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) +#define CAN_IE_TCFE_MASK (0x400U) +#define CAN_IE_TCFE_SHIFT (10U) +#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) +#define CAN_IE_TFEE_MASK (0x800U) +#define CAN_IE_TFEE_SHIFT (11U) +#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) +#define CAN_IE_TEFNE_MASK (0x1000U) +#define CAN_IE_TEFNE_SHIFT (12U) +#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) +#define CAN_IE_TEFWE_MASK (0x2000U) +#define CAN_IE_TEFWE_SHIFT (13U) +#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) +#define CAN_IE_TEFFE_MASK (0x4000U) +#define CAN_IE_TEFFE_SHIFT (14U) +#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) +#define CAN_IE_TEFLE_MASK (0x8000U) +#define CAN_IE_TEFLE_SHIFT (15U) +#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) +#define CAN_IE_TSWE_MASK (0x10000U) +#define CAN_IE_TSWE_SHIFT (16U) +#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) +#define CAN_IE_MRAFE_MASK (0x20000U) +#define CAN_IE_MRAFE_SHIFT (17U) +#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) +#define CAN_IE_TOOE_MASK (0x40000U) +#define CAN_IE_TOOE_SHIFT (18U) +#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) +#define CAN_IE_DRXE_MASK (0x80000U) +#define CAN_IE_DRXE_SHIFT (19U) +#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) +#define CAN_IE_BECE_MASK (0x100000U) +#define CAN_IE_BECE_SHIFT (20U) +#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) +#define CAN_IE_BEUE_MASK (0x200000U) +#define CAN_IE_BEUE_SHIFT (21U) +#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) +#define CAN_IE_ELOE_MASK (0x400000U) +#define CAN_IE_ELOE_SHIFT (22U) +#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) +#define CAN_IE_EPE_MASK (0x800000U) +#define CAN_IE_EPE_SHIFT (23U) +#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) +#define CAN_IE_EWE_MASK (0x1000000U) +#define CAN_IE_EWE_SHIFT (24U) +#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) +#define CAN_IE_BOE_MASK (0x2000000U) +#define CAN_IE_BOE_SHIFT (25U) +#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) +#define CAN_IE_WDIE_MASK (0x4000000U) +#define CAN_IE_WDIE_SHIFT (26U) +#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) +#define CAN_IE_PEAE_MASK (0x8000000U) +#define CAN_IE_PEAE_SHIFT (27U) +#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) +#define CAN_IE_PEDE_MASK (0x10000000U) +#define CAN_IE_PEDE_SHIFT (28U) +#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) +#define CAN_IE_ARAE_MASK (0x20000000U) +#define CAN_IE_ARAE_SHIFT (29U) +#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) + +/*! @name ILS - Interrupt Line Select */ +#define CAN_ILS_RF0NL_MASK (0x1U) +#define CAN_ILS_RF0NL_SHIFT (0U) +#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) +#define CAN_ILS_RF0WL_MASK (0x2U) +#define CAN_ILS_RF0WL_SHIFT (1U) +#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) +#define CAN_ILS_RF0FL_MASK (0x4U) +#define CAN_ILS_RF0FL_SHIFT (2U) +#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) +#define CAN_ILS_RF0LL_MASK (0x8U) +#define CAN_ILS_RF0LL_SHIFT (3U) +#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) +#define CAN_ILS_RF1NL_MASK (0x10U) +#define CAN_ILS_RF1NL_SHIFT (4U) +#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) +#define CAN_ILS_RF1WL_MASK (0x20U) +#define CAN_ILS_RF1WL_SHIFT (5U) +#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) +#define CAN_ILS_RF1FL_MASK (0x40U) +#define CAN_ILS_RF1FL_SHIFT (6U) +#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) +#define CAN_ILS_RF1LL_MASK (0x80U) +#define CAN_ILS_RF1LL_SHIFT (7U) +#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) +#define CAN_ILS_HPML_MASK (0x100U) +#define CAN_ILS_HPML_SHIFT (8U) +#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) +#define CAN_ILS_TCL_MASK (0x200U) +#define CAN_ILS_TCL_SHIFT (9U) +#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) +#define CAN_ILS_TCFL_MASK (0x400U) +#define CAN_ILS_TCFL_SHIFT (10U) +#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) +#define CAN_ILS_TFEL_MASK (0x800U) +#define CAN_ILS_TFEL_SHIFT (11U) +#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) +#define CAN_ILS_TEFNL_MASK (0x1000U) +#define CAN_ILS_TEFNL_SHIFT (12U) +#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) +#define CAN_ILS_TEFWL_MASK (0x2000U) +#define CAN_ILS_TEFWL_SHIFT (13U) +#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) +#define CAN_ILS_TEFFL_MASK (0x4000U) +#define CAN_ILS_TEFFL_SHIFT (14U) +#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) +#define CAN_ILS_TEFLL_MASK (0x8000U) +#define CAN_ILS_TEFLL_SHIFT (15U) +#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) +#define CAN_ILS_TSWL_MASK (0x10000U) +#define CAN_ILS_TSWL_SHIFT (16U) +#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) +#define CAN_ILS_MRAFL_MASK (0x20000U) +#define CAN_ILS_MRAFL_SHIFT (17U) +#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) +#define CAN_ILS_TOOL_MASK (0x40000U) +#define CAN_ILS_TOOL_SHIFT (18U) +#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) +#define CAN_ILS_DRXL_MASK (0x80000U) +#define CAN_ILS_DRXL_SHIFT (19U) +#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) +#define CAN_ILS_BECL_MASK (0x100000U) +#define CAN_ILS_BECL_SHIFT (20U) +#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) +#define CAN_ILS_BEUL_MASK (0x200000U) +#define CAN_ILS_BEUL_SHIFT (21U) +#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) +#define CAN_ILS_ELOL_MASK (0x400000U) +#define CAN_ILS_ELOL_SHIFT (22U) +#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) +#define CAN_ILS_EPL_MASK (0x800000U) +#define CAN_ILS_EPL_SHIFT (23U) +#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) +#define CAN_ILS_EWL_MASK (0x1000000U) +#define CAN_ILS_EWL_SHIFT (24U) +#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) +#define CAN_ILS_BOL_MASK (0x2000000U) +#define CAN_ILS_BOL_SHIFT (25U) +#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) +#define CAN_ILS_WDIL_MASK (0x4000000U) +#define CAN_ILS_WDIL_SHIFT (26U) +#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) +#define CAN_ILS_PEAL_MASK (0x8000000U) +#define CAN_ILS_PEAL_SHIFT (27U) +#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) +#define CAN_ILS_PEDL_MASK (0x10000000U) +#define CAN_ILS_PEDL_SHIFT (28U) +#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) +#define CAN_ILS_ARAL_MASK (0x20000000U) +#define CAN_ILS_ARAL_SHIFT (29U) +#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) + +/*! @name ILE - Interrupt Line Enable */ +#define CAN_ILE_EINT0_MASK (0x1U) +#define CAN_ILE_EINT0_SHIFT (0U) +#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) +#define CAN_ILE_EINT1_MASK (0x2U) +#define CAN_ILE_EINT1_SHIFT (1U) +#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) + +/*! @name GFC - Global Filter Configuration */ +#define CAN_GFC_RRFE_MASK (0x1U) +#define CAN_GFC_RRFE_SHIFT (0U) +#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) +#define CAN_GFC_RRFS_MASK (0x2U) +#define CAN_GFC_RRFS_SHIFT (1U) +#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) +#define CAN_GFC_ANFE_MASK (0xCU) +#define CAN_GFC_ANFE_SHIFT (2U) +#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) +#define CAN_GFC_ANFS_MASK (0x30U) +#define CAN_GFC_ANFS_SHIFT (4U) +#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) + +/*! @name SIDFC - Standard ID Filter Configuration */ +#define CAN_SIDFC_FLSSA_MASK (0xFFFCU) +#define CAN_SIDFC_FLSSA_SHIFT (2U) +#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) +#define CAN_SIDFC_LSS_MASK (0xFF0000U) +#define CAN_SIDFC_LSS_SHIFT (16U) +#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) + +/*! @name XIDFC - Extended ID Filter Configuration */ +#define CAN_XIDFC_FLESA_MASK (0xFFFCU) +#define CAN_XIDFC_FLESA_SHIFT (2U) +#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) +#define CAN_XIDFC_LSE_MASK (0xFF0000U) +#define CAN_XIDFC_LSE_SHIFT (16U) +#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) + +/*! @name XIDAM - Extended ID AND Mask */ +#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) +#define CAN_XIDAM_EIDM_SHIFT (0U) +#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) + +/*! @name HPMS - High Priority Message Status */ +#define CAN_HPMS_BIDX_MASK (0x3FU) +#define CAN_HPMS_BIDX_SHIFT (0U) +#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) +#define CAN_HPMS_MSI_MASK (0xC0U) +#define CAN_HPMS_MSI_SHIFT (6U) +#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) +#define CAN_HPMS_FIDX_MASK (0x7F00U) +#define CAN_HPMS_FIDX_SHIFT (8U) +#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) +#define CAN_HPMS_FLST_MASK (0x8000U) +#define CAN_HPMS_FLST_SHIFT (15U) +#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) + +/*! @name NDAT1 - New Data 1 */ +#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) +#define CAN_NDAT1_ND_SHIFT (0U) +#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) + +/*! @name NDAT2 - New Data 2 */ +#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) +#define CAN_NDAT2_ND_SHIFT (0U) +#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) + +/*! @name RXF0C - Rx FIFO 0 Configuration */ +#define CAN_RXF0C_F0SA_MASK (0xFFFCU) +#define CAN_RXF0C_F0SA_SHIFT (2U) +#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) +#define CAN_RXF0C_F0S_MASK (0x7F0000U) +#define CAN_RXF0C_F0S_SHIFT (16U) +#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) +#define CAN_RXF0C_F0WM_MASK (0x7F000000U) +#define CAN_RXF0C_F0WM_SHIFT (24U) +#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) +#define CAN_RXF0C_F0OM_MASK (0x80000000U) +#define CAN_RXF0C_F0OM_SHIFT (31U) +#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) + +/*! @name RXF0S - Rx FIFO 0 Status */ +#define CAN_RXF0S_F0FL_MASK (0x7FU) +#define CAN_RXF0S_F0FL_SHIFT (0U) +#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) +#define CAN_RXF0S_F0GI_MASK (0x3F00U) +#define CAN_RXF0S_F0GI_SHIFT (8U) +#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) +#define CAN_RXF0S_F0PI_MASK (0x3F0000U) +#define CAN_RXF0S_F0PI_SHIFT (16U) +#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) +#define CAN_RXF0S_F0F_MASK (0x1000000U) +#define CAN_RXF0S_F0F_SHIFT (24U) +#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) +#define CAN_RXF0S_RF0L_MASK (0x2000000U) +#define CAN_RXF0S_RF0L_SHIFT (25U) +#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) + +/*! @name RXF0A - Rx FIFO 0 Acknowledge */ +#define CAN_RXF0A_F0AI_MASK (0x3FU) +#define CAN_RXF0A_F0AI_SHIFT (0U) +#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) + +/*! @name RXBC - Rx Buffer Configuration */ +#define CAN_RXBC_RBSA_MASK (0xFFFCU) +#define CAN_RXBC_RBSA_SHIFT (2U) +#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) + +/*! @name RXF1C - Rx FIFO 1 Configuration */ +#define CAN_RXF1C_F1SA_MASK (0xFFFCU) +#define CAN_RXF1C_F1SA_SHIFT (2U) +#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) +#define CAN_RXF1C_F1S_MASK (0x7F0000U) +#define CAN_RXF1C_F1S_SHIFT (16U) +#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) +#define CAN_RXF1C_F1WM_MASK (0x7F000000U) +#define CAN_RXF1C_F1WM_SHIFT (24U) +#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) +#define CAN_RXF1C_F1OM_MASK (0x80000000U) +#define CAN_RXF1C_F1OM_SHIFT (31U) +#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) + +/*! @name RXF1S - Rx FIFO 1 Status */ +#define CAN_RXF1S_F1FL_MASK (0x7FU) +#define CAN_RXF1S_F1FL_SHIFT (0U) +#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) +#define CAN_RXF1S_F1GI_MASK (0x3F00U) +#define CAN_RXF1S_F1GI_SHIFT (8U) +#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) +#define CAN_RXF1S_F1PI_MASK (0x3F0000U) +#define CAN_RXF1S_F1PI_SHIFT (16U) +#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) +#define CAN_RXF1S_F1F_MASK (0x1000000U) +#define CAN_RXF1S_F1F_SHIFT (24U) +#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) +#define CAN_RXF1S_RF1L_MASK (0x2000000U) +#define CAN_RXF1S_RF1L_SHIFT (25U) +#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) + +/*! @name RXF1A - Rx FIFO 1 Acknowledge */ +#define CAN_RXF1A_F1AI_MASK (0x3FU) +#define CAN_RXF1A_F1AI_SHIFT (0U) +#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) + +/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ +#define CAN_RXESC_F0DS_MASK (0x7U) +#define CAN_RXESC_F0DS_SHIFT (0U) +#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) +#define CAN_RXESC_F1DS_MASK (0x70U) +#define CAN_RXESC_F1DS_SHIFT (4U) +#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) +#define CAN_RXESC_RBDS_MASK (0x700U) +#define CAN_RXESC_RBDS_SHIFT (8U) +#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) + +/*! @name TXBC - Tx Buffer Configuration */ +#define CAN_TXBC_TBSA_MASK (0xFFFCU) +#define CAN_TXBC_TBSA_SHIFT (2U) +#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) +#define CAN_TXBC_NDTB_MASK (0x3F0000U) +#define CAN_TXBC_NDTB_SHIFT (16U) +#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) +#define CAN_TXBC_TFQS_MASK (0x3F000000U) +#define CAN_TXBC_TFQS_SHIFT (24U) +#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) +#define CAN_TXBC_TFQM_MASK (0x40000000U) +#define CAN_TXBC_TFQM_SHIFT (30U) +#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) + +/*! @name TXFQS - Tx FIFO/Queue Status */ +#define CAN_TXFQS_TFGI_MASK (0x1F00U) +#define CAN_TXFQS_TFGI_SHIFT (8U) +#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) +#define CAN_TXFQS_TFQPI_MASK (0x1F0000U) +#define CAN_TXFQS_TFQPI_SHIFT (16U) +#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) +#define CAN_TXFQS_TFQF_MASK (0x200000U) +#define CAN_TXFQS_TFQF_SHIFT (21U) +#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) + +/*! @name TXESC - Tx Buffer Element Size Configuration */ +#define CAN_TXESC_TBDS_MASK (0x7U) +#define CAN_TXESC_TBDS_SHIFT (0U) +#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) + +/*! @name TXBRP - Tx Buffer Request Pending */ +#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) +#define CAN_TXBRP_TRP_SHIFT (0U) +#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) + +/*! @name TXBAR - Tx Buffer Add Request */ +#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) +#define CAN_TXBAR_AR_SHIFT (0U) +#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) + +/*! @name TXBCR - Tx Buffer Cancellation Request */ +#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) +#define CAN_TXBCR_CR_SHIFT (0U) +#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) + +/*! @name TXBTO - Tx Buffer Transmission Occurred */ +#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) +#define CAN_TXBTO_TO_SHIFT (0U) +#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) + +/*! @name TXBCF - Tx Buffer Cancellation Finished */ +#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) +#define CAN_TXBCF_TO_SHIFT (0U) +#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) + +/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ +#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) +#define CAN_TXBTIE_TIE_SHIFT (0U) +#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) + +/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ +#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) +#define CAN_TXBCIE_CFIE_SHIFT (0U) +#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) + +/*! @name TXEFC - Tx Event FIFO Configuration */ +#define CAN_TXEFC_EFSA_MASK (0xFFFCU) +#define CAN_TXEFC_EFSA_SHIFT (2U) +#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) +#define CAN_TXEFC_EFS_MASK (0x3F0000U) +#define CAN_TXEFC_EFS_SHIFT (16U) +#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) +#define CAN_TXEFC_EFWM_MASK (0x3F000000U) +#define CAN_TXEFC_EFWM_SHIFT (24U) +#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) + +/*! @name TXEFS - Tx Event FIFO Status */ +#define CAN_TXEFS_EFFL_MASK (0x3FU) +#define CAN_TXEFS_EFFL_SHIFT (0U) +#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) +#define CAN_TXEFS_EFGI_MASK (0x1F00U) +#define CAN_TXEFS_EFGI_SHIFT (8U) +#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) +#define CAN_TXEFS_EFPI_MASK (0x3F0000U) +#define CAN_TXEFS_EFPI_SHIFT (16U) +#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) +#define CAN_TXEFS_EFF_MASK (0x1000000U) +#define CAN_TXEFS_EFF_SHIFT (24U) +#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) +#define CAN_TXEFS_TEFL_MASK (0x2000000U) +#define CAN_TXEFS_TEFL_SHIFT (25U) +#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) + +/*! @name TXEFA - Tx Event FIFO Acknowledge */ +#define CAN_TXEFA_EFAI_MASK (0x1FU) +#define CAN_TXEFA_EFAI_SHIFT (0U) +#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) + +/*! @name MRBA - CAN Message RAM Base Address */ +#define CAN_MRBA_BA_MASK (0xFFFFFFFFU) +#define CAN_MRBA_BA_SHIFT (0U) +#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) + +/*! @name ETSCC - External Timestamp Counter Configuration */ +#define CAN_ETSCC_ETCP_MASK (0x7FFU) +#define CAN_ETSCC_ETCP_SHIFT (0U) +#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) +#define CAN_ETSCC_ETCE_MASK (0x80000000U) +#define CAN_ETSCC_ETCE_SHIFT (31U) +#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) + +/*! @name ETSCV - External Timestamp Counter Value */ +#define CAN_ETSCV_ETSC_MASK (0xFFFFU) +#define CAN_ETSCV_ETSC_SHIFT (0U) +#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x4009D000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x4009E000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0, CAN1 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) + +/*! @name SEED - CRC seed register */ +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) + +/*! @name SUM - CRC checksum register */ +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) + +/*! @name WR_DATA - CRC data register */ +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC_ENGINE base address */ +#define CRC_ENGINE_BASE (0x40095000u) +/** Peripheral CRC_ENGINE base pointer */ +#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC_ENGINE_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC_ENGINE } + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) + +/*! @name TC - Timer Counter */ +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) + +/*! @name PR - Prescale Register */ +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) + +/*! @name PC - Prescale Counter */ +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) + +/*! @name MCR - Match Control Register */ +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) + +/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) + +/*! @name MSR - Match Shadow Register */ +#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_SHADOWW_SHIFT (0U) +#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK) + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40008000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40009000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40028000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40048000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40049000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[1]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[30]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) + +/*! @name INTSTAT - Interrupt status. */ +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (30U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (30U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (30U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40082000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMIC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer + * @{ + */ + +/** DMIC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x100 */ + __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */ + __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */ + __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */ + __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */ + __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */ + uint8_t RESERVED_0[108]; + __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */ + __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */ + __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */ + __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */ + __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */ + uint8_t RESERVED_1[108]; + } CHANNEL[2]; + uint8_t RESERVED_0[3328]; + __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ + uint8_t RESERVED_1[8]; + __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */ + __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */ + uint8_t RESERVED_2[108]; + __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */ + __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */ + __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */ + __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */ + __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */ + __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */ + __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */ + uint8_t RESERVED_3[96]; + __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */ +} DMIC_Type; + +/* ---------------------------------------------------------------------------- + -- DMIC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMIC_Register_Masks DMIC Register Masks + * @{ + */ + +/*! @name CHANNEL_OSR - Oversample Rate register 0 */ +#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) +#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) +#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) + +/* The count of DMIC_CHANNEL_OSR */ +#define DMIC_CHANNEL_OSR_COUNT (2U) + +/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) +#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) + +/* The count of DMIC_CHANNEL_DIVHFCLK */ +#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) + +/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) +#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) + +/* The count of DMIC_CHANNEL_PREAC2FSCOEF */ +#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) + +/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) +#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) + +/* The count of DMIC_CHANNEL_PREAC4FSCOEF */ +#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) + +/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ +#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) +#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) +#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) + +/* The count of DMIC_CHANNEL_GAINSHIFT */ +#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) + +/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) +#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) +#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) +#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) +#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) +#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) +#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) +#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) + +/* The count of DMIC_CHANNEL_FIFO_CTRL */ +#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) + +/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ +#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) +#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) +#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) +#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) +#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) + +/* The count of DMIC_CHANNEL_FIFO_STATUS */ +#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) + +/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ +#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) +#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) +#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) + +/* The count of DMIC_CHANNEL_FIFO_DATA */ +#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) + +/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) +#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) + +/* The count of DMIC_CHANNEL_PHY_CTRL */ +#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) + +/*! @name CHANNEL_DC_CTRL - DC Control register 0 */ +#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) +#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) +#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) +#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) +#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) +#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) +#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) + +/* The count of DMIC_CHANNEL_DC_CTRL */ +#define DMIC_CHANNEL_DC_CTRL_COUNT (2U) + +/*! @name CHANEN - Channel Enable register */ +#define DMIC_CHANEN_EN_CH0_MASK (0x1U) +#define DMIC_CHANEN_EN_CH0_SHIFT (0U) +#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) +#define DMIC_CHANEN_EN_CH1_MASK (0x2U) +#define DMIC_CHANEN_EN_CH1_SHIFT (1U) +#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) + +/*! @name IOCFG - I/O Configuration register */ +#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) +#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) +#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) +#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U) +#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U) +#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK) +#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) +#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) +#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) + +/*! @name USE2FS - Use 2FS register */ +#define DMIC_USE2FS_USE2FS_MASK (0x1U) +#define DMIC_USE2FS_USE2FS_SHIFT (0U) +#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) + +/*! @name HWVADGAIN - HWVAD input gain register */ +#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) +#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) +#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) + +/*! @name HWVADHPFS - HWVAD filter control register */ +#define DMIC_HWVADHPFS_HPFS_MASK (0x3U) +#define DMIC_HWVADHPFS_HPFS_SHIFT (0U) +#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) + +/*! @name HWVADST10 - HWVAD control register */ +#define DMIC_HWVADST10_ST10_MASK (0x1U) +#define DMIC_HWVADST10_ST10_SHIFT (0U) +#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) + +/*! @name HWVADRSTT - HWVAD filter reset register */ +#define DMIC_HWVADRSTT_RSTT_MASK (0x1U) +#define DMIC_HWVADRSTT_RSTT_SHIFT (0U) +#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) + +/*! @name HWVADTHGN - HWVAD noise estimator gain register */ +#define DMIC_HWVADTHGN_THGN_MASK (0xFU) +#define DMIC_HWVADTHGN_THGN_SHIFT (0U) +#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) + +/*! @name HWVADTHGS - HWVAD signal estimator gain register */ +#define DMIC_HWVADTHGS_THGS_MASK (0xFU) +#define DMIC_HWVADTHGS_THGS_SHIFT (0U) +#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) + +/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ +#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) +#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) +#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) + +/*! @name ID - Module Identification register */ +#define DMIC_ID_ID_MASK (0xFFFFFFFFU) +#define DMIC_ID_ID_SHIFT (0U) +#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) + + +/*! + * @} + */ /* end of group DMIC_Register_Masks */ + + +/* DMIC - Peripheral instance base addresses */ +/** Peripheral DMIC0 base address */ +#define DMIC0_BASE (0x40090000u) +/** Peripheral DMIC0 base pointer */ +#define DMIC0 ((DMIC_Type *)DMIC0_BASE) +/** Array initializer of DMIC peripheral base addresses */ +#define DMIC_BASE_ADDRS { DMIC0_BASE } +/** Array initializer of DMIC peripheral base pointers */ +#define DMIC_BASE_PTRS { DMIC0 } +/** Interrupt vectors for the DMIC peripheral type */ +#define DMIC_IRQS { DMIC0_IRQn } +#define DMIC_HWVAD_IRQS { HWVAD0_IRQn } + +/*! + * @} + */ /* end of group DMIC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EEPROM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer + * @{ + */ + +/** EEPROM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CMD; /**< EEPROM command register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RWSTATE; /**< EEPROM read wait state register, offset: 0x8 */ + __IO uint32_t AUTOPROG; /**< EEPROM auto programming register, offset: 0xC */ + __IO uint32_t WSTATE; /**< EEPROM wait state register, offset: 0x10 */ + __IO uint32_t CLKDIV; /**< EEPROM clock divider register, offset: 0x14 */ + __IO uint32_t PWRDWN; /**< EEPROM power-down register, offset: 0x18 */ + uint8_t RESERVED_1[4028]; + __O uint32_t INTENCLR; /**< EEPROM interrupt enable clear, offset: 0xFD8 */ + __O uint32_t INTENSET; /**< EEPROM interrupt enable set, offset: 0xFDC */ + __I uint32_t INTSTAT; /**< EEPROM interrupt status, offset: 0xFE0 */ + __I uint32_t INTEN; /**< EEPROM interrupt enable, offset: 0xFE4 */ + __O uint32_t INTSTATCLR; /**< EEPROM interrupt status clear, offset: 0xFE8 */ + __O uint32_t INTSTATSET; /**< EEPROM interrupt status set, offset: 0xFEC */ +} EEPROM_Type; + +/* ---------------------------------------------------------------------------- + -- EEPROM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EEPROM_Register_Masks EEPROM Register Masks + * @{ + */ + +/*! @name CMD - EEPROM command register */ +#define EEPROM_CMD_CMD_MASK (0x7U) +#define EEPROM_CMD_CMD_SHIFT (0U) +#define EEPROM_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK) + +/*! @name RWSTATE - EEPROM read wait state register */ +#define EEPROM_RWSTATE_RPHASE2_MASK (0xFFU) +#define EEPROM_RWSTATE_RPHASE2_SHIFT (0U) +#define EEPROM_RWSTATE_RPHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK) +#define EEPROM_RWSTATE_RPHASE1_MASK (0xFF00U) +#define EEPROM_RWSTATE_RPHASE1_SHIFT (8U) +#define EEPROM_RWSTATE_RPHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK) + +/*! @name AUTOPROG - EEPROM auto programming register */ +#define EEPROM_AUTOPROG_AUTOPROG_MASK (0x3U) +#define EEPROM_AUTOPROG_AUTOPROG_SHIFT (0U) +#define EEPROM_AUTOPROG_AUTOPROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK) + +/*! @name WSTATE - EEPROM wait state register */ +#define EEPROM_WSTATE_PHASE3_MASK (0xFFU) +#define EEPROM_WSTATE_PHASE3_SHIFT (0U) +#define EEPROM_WSTATE_PHASE3(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK) +#define EEPROM_WSTATE_PHASE2_MASK (0xFF00U) +#define EEPROM_WSTATE_PHASE2_SHIFT (8U) +#define EEPROM_WSTATE_PHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK) +#define EEPROM_WSTATE_PHASE1_MASK (0xFF0000U) +#define EEPROM_WSTATE_PHASE1_SHIFT (16U) +#define EEPROM_WSTATE_PHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK) +#define EEPROM_WSTATE_LCK_PARWEP_MASK (0x80000000U) +#define EEPROM_WSTATE_LCK_PARWEP_SHIFT (31U) +#define EEPROM_WSTATE_LCK_PARWEP(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK) + +/*! @name CLKDIV - EEPROM clock divider register */ +#define EEPROM_CLKDIV_CLKDIV_MASK (0xFFFFU) +#define EEPROM_CLKDIV_CLKDIV_SHIFT (0U) +#define EEPROM_CLKDIV_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK) + +/*! @name PWRDWN - EEPROM power-down register */ +#define EEPROM_PWRDWN_PWRDWN_MASK (0x1U) +#define EEPROM_PWRDWN_PWRDWN_SHIFT (0U) +#define EEPROM_PWRDWN_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK) + +/*! @name INTENCLR - EEPROM interrupt enable clear */ +#define EEPROM_INTENCLR_PROG_CLR_EN_MASK (0x4U) +#define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT (2U) +#define EEPROM_INTENCLR_PROG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK) + +/*! @name INTENSET - EEPROM interrupt enable set */ +#define EEPROM_INTENSET_PROG_SET_EN_MASK (0x4U) +#define EEPROM_INTENSET_PROG_SET_EN_SHIFT (2U) +#define EEPROM_INTENSET_PROG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK) + +/*! @name INTSTAT - EEPROM interrupt status */ +#define EEPROM_INTSTAT_END_OF_PROG_MASK (0x4U) +#define EEPROM_INTSTAT_END_OF_PROG_SHIFT (2U) +#define EEPROM_INTSTAT_END_OF_PROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK) + +/*! @name INTEN - EEPROM interrupt enable */ +#define EEPROM_INTEN_EE_PROG_DONE_MASK (0x4U) +#define EEPROM_INTEN_EE_PROG_DONE_SHIFT (2U) +#define EEPROM_INTEN_EE_PROG_DONE(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK) + +/*! @name INTSTATCLR - EEPROM interrupt status clear */ +#define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK (0x4U) +#define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT (2U) +#define EEPROM_INTSTATCLR_PROG_CLR_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK) + +/*! @name INTSTATSET - EEPROM interrupt status set */ +#define EEPROM_INTSTATSET_PROG_SET_ST_MASK (0x4U) +#define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT (2U) +#define EEPROM_INTSTATSET_PROG_SET_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK) + + +/*! + * @} + */ /* end of group EEPROM_Register_Masks */ + + +/* EEPROM - Peripheral instance base addresses */ +/** Peripheral EEPROM base address */ +#define EEPROM_BASE (0x40014000u) +/** Peripheral EEPROM base pointer */ +#define EEPROM ((EEPROM_Type *)EEPROM_BASE) +/** Array initializer of EEPROM peripheral base addresses */ +#define EEPROM_BASE_ADDRS { EEPROM_BASE } +/** Array initializer of EEPROM peripheral base pointers */ +#define EEPROM_BASE_PTRS { EEPROM } +/** Interrupt vectors for the EEPROM peripheral type */ +#define EEPROM_IRQS { EEPROM_IRQn } + +/*! + * @} + */ /* end of group EEPROM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer + * @{ + */ + +/** EMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */ + __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */ + __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */ + uint8_t RESERVED_0[20]; + __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */ + __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */ + __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */ + __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */ + __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */ + __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */ + __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */ + __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */ + __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */ + __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */ + __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */ + __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */ + __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */ + uint8_t RESERVED_2[36]; + __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */ + uint8_t RESERVED_3[124]; + struct { /* offset: 0x100, array step: 0x20 */ + __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */ + __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */ + uint8_t RESERVED_0[24]; + } DYNAMIC[4]; + uint8_t RESERVED_4[128]; + struct { /* offset: 0x200, array step: 0x20 */ + __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */ + __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */ + __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */ + __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */ + __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */ + __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */ + __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */ + uint8_t RESERVED_0[4]; + } STATIC[4]; +} EMC_Type; + +/* ---------------------------------------------------------------------------- + -- EMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EMC_Register_Masks EMC Register Masks + * @{ + */ + +/*! @name CONTROL - Controls operation of the memory controller */ +#define EMC_CONTROL_E_MASK (0x1U) +#define EMC_CONTROL_E_SHIFT (0U) +#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK) +#define EMC_CONTROL_M_MASK (0x2U) +#define EMC_CONTROL_M_SHIFT (1U) +#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK) +#define EMC_CONTROL_L_MASK (0x4U) +#define EMC_CONTROL_L_SHIFT (2U) +#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK) + +/*! @name STATUS - Provides EMC status information */ +#define EMC_STATUS_B_MASK (0x1U) +#define EMC_STATUS_B_SHIFT (0U) +#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK) +#define EMC_STATUS_S_MASK (0x2U) +#define EMC_STATUS_S_SHIFT (1U) +#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK) +#define EMC_STATUS_SA_MASK (0x4U) +#define EMC_STATUS_SA_SHIFT (2U) +#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK) + +/*! @name CONFIG - Configures operation of the memory controller */ +#define EMC_CONFIG_EM_MASK (0x1U) +#define EMC_CONFIG_EM_SHIFT (0U) +#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK) +#define EMC_CONFIG_CLKR_MASK (0x100U) +#define EMC_CONFIG_CLKR_SHIFT (8U) +#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK) + +/*! @name DYNAMICCONTROL - Controls dynamic memory operation */ +#define EMC_DYNAMICCONTROL_CE_MASK (0x1U) +#define EMC_DYNAMICCONTROL_CE_SHIFT (0U) +#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK) +#define EMC_DYNAMICCONTROL_CS_MASK (0x2U) +#define EMC_DYNAMICCONTROL_CS_SHIFT (1U) +#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK) +#define EMC_DYNAMICCONTROL_SR_MASK (0x4U) +#define EMC_DYNAMICCONTROL_SR_SHIFT (2U) +#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK) +#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U) +#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U) +#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK) +#define EMC_DYNAMICCONTROL_I_MASK (0x180U) +#define EMC_DYNAMICCONTROL_I_SHIFT (7U) +#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK) + +/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */ +#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU) +#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U) +#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK) + +/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */ +#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U) +#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U) +#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK) + +/*! @name DYNAMICRP - Precharge command period */ +#define EMC_DYNAMICRP_TRP_MASK (0xFU) +#define EMC_DYNAMICRP_TRP_SHIFT (0U) +#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK) + +/*! @name DYNAMICRAS - Active to precharge command period */ +#define EMC_DYNAMICRAS_TRAS_MASK (0xFU) +#define EMC_DYNAMICRAS_TRAS_SHIFT (0U) +#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK) + +/*! @name DYNAMICSREX - Self-refresh exit time */ +#define EMC_DYNAMICSREX_TSREX_MASK (0xFU) +#define EMC_DYNAMICSREX_TSREX_SHIFT (0U) +#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK) + +/*! @name DYNAMICAPR - Last-data-out to active command time */ +#define EMC_DYNAMICAPR_TAPR_MASK (0xFU) +#define EMC_DYNAMICAPR_TAPR_SHIFT (0U) +#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK) + +/*! @name DYNAMICDAL - Data-in to active command time */ +#define EMC_DYNAMICDAL_TDAL_MASK (0xFU) +#define EMC_DYNAMICDAL_TDAL_SHIFT (0U) +#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK) + +/*! @name DYNAMICWR - Write recovery time */ +#define EMC_DYNAMICWR_TWR_MASK (0xFU) +#define EMC_DYNAMICWR_TWR_SHIFT (0U) +#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK) + +/*! @name DYNAMICRC - Selects the active to active command period */ +#define EMC_DYNAMICRC_TRC_MASK (0x1FU) +#define EMC_DYNAMICRC_TRC_SHIFT (0U) +#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK) + +/*! @name DYNAMICRFC - Selects the auto-refresh period */ +#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU) +#define EMC_DYNAMICRFC_TRFC_SHIFT (0U) +#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK) + +/*! @name DYNAMICXSR - Time for exit self-refresh to active command */ +#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU) +#define EMC_DYNAMICXSR_TXSR_SHIFT (0U) +#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK) + +/*! @name DYNAMICRRD - Latency for active bank A to active bank B */ +#define EMC_DYNAMICRRD_TRRD_MASK (0xFU) +#define EMC_DYNAMICRRD_TRRD_SHIFT (0U) +#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK) + +/*! @name DYNAMICMRD - Time for load mode register to active command */ +#define EMC_DYNAMICMRD_TMRD_MASK (0xFU) +#define EMC_DYNAMICMRD_TMRD_SHIFT (0U) +#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK) + +/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */ +#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU) +#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U) +#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK) + +/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */ +#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U) +#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U) +#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK) +#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U) +#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U) +#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK) +#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U) +#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U) +#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK) +#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U) +#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U) +#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK) +#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U) +#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U) +#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK) + +/* The count of EMC_DYNAMIC_DYNAMICCONFIG */ +#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U) + +/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */ +#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U) +#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U) +#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK) +#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U) +#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U) +#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK) + +/* The count of EMC_DYNAMIC_DYNAMICRASCAS */ +#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U) + +/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */ +#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U) +#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U) +#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK) +#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U) +#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U) +#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK) +#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U) +#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U) +#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK) +#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U) +#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U) +#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK) +#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U) +#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U) +#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK) +#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U) +#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U) +#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK) +#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U) +#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U) +#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK) + +/* The count of EMC_STATIC_STATICCONFIG */ +#define EMC_STATIC_STATICCONFIG_COUNT (4U) + +/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */ +#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU) +#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U) +#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK) + +/* The count of EMC_STATIC_STATICWAITWEN */ +#define EMC_STATIC_STATICWAITWEN_COUNT (4U) + +/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */ +#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU) +#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U) +#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK) + +/* The count of EMC_STATIC_STATICWAITOEN */ +#define EMC_STATIC_STATICWAITOEN_COUNT (4U) + +/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */ +#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU) +#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U) +#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK) + +/* The count of EMC_STATIC_STATICWAITRD */ +#define EMC_STATIC_STATICWAITRD_COUNT (4U) + +/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */ +#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU) +#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U) +#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK) + +/* The count of EMC_STATIC_STATICWAITPAGE */ +#define EMC_STATIC_STATICWAITPAGE_COUNT (4U) + +/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */ +#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU) +#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U) +#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK) + +/* The count of EMC_STATIC_STATICWAITWR */ +#define EMC_STATIC_STATICWAITWR_COUNT (4U) + +/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */ +#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU) +#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U) +#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK) + +/* The count of EMC_STATIC_STATICWAITTURN */ +#define EMC_STATIC_STATICWAITTURN_COUNT (4U) + + +/*! + * @} + */ /* end of group EMC_Register_Masks */ + + +/* EMC - Peripheral instance base addresses */ +/** Peripheral EMC base address */ +#define EMC_BASE (0x40081000u) +/** Peripheral EMC base pointer */ +#define EMC ((EMC_Type *)EMC_BASE) +/** Array initializer of EMC peripheral base addresses */ +#define EMC_BASE_ADDRS { EMC_BASE } +/** Array initializer of EMC peripheral base pointers */ +#define EMC_BASE_PTRS { EMC } + +/*! + * @} + */ /* end of group EMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */ + __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */ + __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */ + __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */ + uint8_t RESERVED_0[64]; + __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */ + uint8_t RESERVED_1[28]; + __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */ + uint8_t RESERVED_2[24]; + __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[4]; + __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */ + __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */ + __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */ + uint8_t RESERVED_6[4]; + __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */ + __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */ + uint8_t RESERVED_7[8]; + __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */ + __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */ + __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */ + __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */ + uint8_t RESERVED_8[48]; + __IO uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */ + __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */ + uint8_t RESERVED_9[4]; + __IO uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */ + uint8_t RESERVED_10[216]; + __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */ + __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */ + uint8_t RESERVED_11[248]; + __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */ + __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */ + uint8_t RESERVED_12[2040]; + __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */ + __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */ + __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */ + __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */ + __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */ + __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */ + __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */ + __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */ + __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */ + uint8_t RESERVED_13[12]; + __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */ + __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */ + uint8_t RESERVED_14[32]; + __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */ + __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */ + uint8_t RESERVED_15[160]; + __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */ + uint8_t RESERVED_16[28]; + __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */ + uint8_t RESERVED_17[12]; + __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */ + uint8_t RESERVED_18[204]; + struct { /* offset: 0xD00, array step: 0x40 */ + __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */ + __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */ + __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */ + __IO uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */ + __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */ + __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */ + __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */ + __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */ + __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */ + __IO uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */ + __IO uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */ + __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */ + } MTL_QUEUE[2]; + uint8_t RESERVED_19[640]; + __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */ + __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */ + __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */ + __IO uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */ + uint8_t RESERVED_20[240]; + struct { /* offset: 0x1100, array step: 0x80 */ + __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */ + __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */ + __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */ + uint8_t RESERVED_0[8]; + __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */ + __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */ + uint8_t RESERVED_2[4]; + __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */ + __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */ + __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */ + __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */ + __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */ + __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */ + uint8_t RESERVED_3[4]; + __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */ + uint8_t RESERVED_4[4]; + __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */ + uint8_t RESERVED_5[4]; + __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */ + uint8_t RESERVED_6[4]; + __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */ + __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */ + uint8_t RESERVED_7[28]; + } DMA_CH[2]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name MAC_CONFIG - MAC configuration register */ +#define ENET_MAC_CONFIG_RE_MASK (0x1U) +#define ENET_MAC_CONFIG_RE_SHIFT (0U) +#define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK) +#define ENET_MAC_CONFIG_TE_MASK (0x2U) +#define ENET_MAC_CONFIG_TE_SHIFT (1U) +#define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK) +#define ENET_MAC_CONFIG_PRELEN_MASK (0xCU) +#define ENET_MAC_CONFIG_PRELEN_SHIFT (2U) +#define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK) +#define ENET_MAC_CONFIG_DC_MASK (0x10U) +#define ENET_MAC_CONFIG_DC_SHIFT (4U) +#define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK) +#define ENET_MAC_CONFIG_BL_MASK (0x60U) +#define ENET_MAC_CONFIG_BL_SHIFT (5U) +#define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK) +#define ENET_MAC_CONFIG_DR_MASK (0x100U) +#define ENET_MAC_CONFIG_DR_SHIFT (8U) +#define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK) +#define ENET_MAC_CONFIG_DCRS_MASK (0x200U) +#define ENET_MAC_CONFIG_DCRS_SHIFT (9U) +#define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK) +#define ENET_MAC_CONFIG_DO_MASK (0x400U) +#define ENET_MAC_CONFIG_DO_SHIFT (10U) +#define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK) +#define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U) +#define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U) +#define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK) +#define ENET_MAC_CONFIG_LM_MASK (0x1000U) +#define ENET_MAC_CONFIG_LM_SHIFT (12U) +#define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK) +#define ENET_MAC_CONFIG_DM_MASK (0x2000U) +#define ENET_MAC_CONFIG_DM_SHIFT (13U) +#define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK) +#define ENET_MAC_CONFIG_FES_MASK (0x4000U) +#define ENET_MAC_CONFIG_FES_SHIFT (14U) +#define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK) +#define ENET_MAC_CONFIG_PS_MASK (0x8000U) +#define ENET_MAC_CONFIG_PS_SHIFT (15U) +#define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK) +#define ENET_MAC_CONFIG_JE_MASK (0x10000U) +#define ENET_MAC_CONFIG_JE_SHIFT (16U) +#define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK) +#define ENET_MAC_CONFIG_JD_MASK (0x20000U) +#define ENET_MAC_CONFIG_JD_SHIFT (17U) +#define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK) +#define ENET_MAC_CONFIG_BE_MASK (0x40000U) +#define ENET_MAC_CONFIG_BE_SHIFT (18U) +#define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK) +#define ENET_MAC_CONFIG_WD_MASK (0x80000U) +#define ENET_MAC_CONFIG_WD_SHIFT (19U) +#define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK) +#define ENET_MAC_CONFIG_ACS_MASK (0x100000U) +#define ENET_MAC_CONFIG_ACS_SHIFT (20U) +#define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK) +#define ENET_MAC_CONFIG_CST_MASK (0x200000U) +#define ENET_MAC_CONFIG_CST_SHIFT (21U) +#define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK) +#define ENET_MAC_CONFIG_S2KP_MASK (0x400000U) +#define ENET_MAC_CONFIG_S2KP_SHIFT (22U) +#define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK) +#define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U) +#define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U) +#define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK) +#define ENET_MAC_CONFIG_IPG_MASK (0x7000000U) +#define ENET_MAC_CONFIG_IPG_SHIFT (24U) +#define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK) +#define ENET_MAC_CONFIG_IPC_MASK (0x8000000U) +#define ENET_MAC_CONFIG_IPC_SHIFT (27U) +#define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK) + +/*! @name MAC_EXT_CONFIG - */ +#define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU) +#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U) +#define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK) +#define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U) +#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U) +#define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK) +#define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U) +#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U) +#define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK) +#define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U) +#define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U) +#define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK) + +/*! @name MAC_FRAME_FILTER - MAC frame filter register */ +#define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U) +#define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U) +#define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK) +#define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U) +#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U) +#define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK) +#define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U) +#define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U) +#define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK) +#define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U) +#define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U) +#define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK) +#define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U) +#define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U) +#define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK) +#define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U) +#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U) +#define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK) +#define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U) +#define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U) +#define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK) +#define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U) +#define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U) +#define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK) + +/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */ +#define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU) +#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U) +#define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK) +#define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U) +#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U) +#define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK) + +/*! @name MAC_VLAN_TAG - MAC vlan tag register */ +#define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU) +#define ENET_MAC_VLAN_TAG_VL_SHIFT (0U) +#define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK) +#define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U) +#define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U) +#define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK) +#define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U) +#define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U) +#define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK) +#define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U) +#define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U) +#define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK) +#define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U) +#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U) +#define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK) +#define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U) +#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U) +#define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK) +#define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U) +#define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U) +#define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK) +#define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U) +#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U) +#define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK) +#define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U) +#define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U) +#define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK) +#define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U) +#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U) +#define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK) +#define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U) +#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U) +#define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK) +#define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U) +#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U) +#define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK) +#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U) +#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U) +#define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK) + +/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */ +#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U) +#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U) +#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK) +#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U) +#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U) +#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK) +#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U) +#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U) +#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK) +#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U) +#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U) +#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK) +#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U) +#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U) +#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK) + +/* The count of ENET_MAC_TX_FLOW_CTRL_Q */ +#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U) + +/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */ +#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U) +#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U) +#define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK) +#define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U) +#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U) +#define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK) + +/*! @name MAC_TXQ_PRIO_MAP - */ +#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU) +#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U) +#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK) +#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U) +#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U) +#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK) + +/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */ +#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U) +#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U) +#define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK) +#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU) +#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U) +#define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK) +#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U) +#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U) +#define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK) +#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU) +#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U) +#define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK) +#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U) +#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U) +#define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK) +#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U) +#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U) +#define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK) +#define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U) +#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U) +#define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK) +#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U) +#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U) +#define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK) +#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U) +#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U) +#define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK) +#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U) +#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U) +#define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK) +#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U) +#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U) +#define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK) + +/* The count of ENET_MAC_RXQ_CTRL */ +#define ENET_MAC_RXQ_CTRL_COUNT (3U) + +/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */ +#define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U) +#define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U) +#define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK) +#define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U) +#define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U) +#define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK) +#define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U) +#define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U) +#define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK) +#define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U) +#define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U) +#define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK) +#define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U) +#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U) +#define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK) +#define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U) +#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U) +#define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK) + +/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */ +#define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U) +#define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U) +#define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK) +#define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U) +#define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U) +#define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK) +#define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U) +#define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U) +#define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK) +#define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U) +#define ENET_MAC_INTR_EN_TSIE_SHIFT (12U) +#define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK) +#define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U) +#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U) +#define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK) +#define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U) +#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U) +#define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK) + +/*! @name MAC_RXTX_STAT - Receive Transmit Status register */ +#define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U) +#define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U) +#define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK) +#define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U) +#define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U) +#define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK) +#define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U) +#define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U) +#define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK) +#define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U) +#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U) +#define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK) +#define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U) +#define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U) +#define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK) +#define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U) +#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U) +#define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK) +#define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U) +#define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U) +#define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK) + +/*! @name MAC_PMT_CRTL_STAT - */ +#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U) +#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U) +#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK) +#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U) +#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U) +#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK) +#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U) +#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U) +#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK) +#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U) +#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U) +#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK) +#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U) +#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U) +#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK) +#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U) +#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U) +#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK) +#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U) +#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U) +#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK) +#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U) +#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U) +#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK) +#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U) +#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U) +#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK) + +/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */ +#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU) +#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U) +#define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK) + +/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */ +#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U) +#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U) +#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK) +#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U) +#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U) +#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK) +#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U) +#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U) +#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK) +#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U) +#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U) +#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK) +#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U) +#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U) +#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK) +#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U) +#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U) +#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK) +#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U) +#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U) +#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK) +#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U) +#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U) +#define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK) +#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U) +#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U) +#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK) +#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U) +#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U) +#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK) +#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U) +#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U) +#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK) + +/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */ +#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU) +#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U) +#define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK) +#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U) +#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U) +#define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK) + +/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */ +#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U) +#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U) +#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK) + +/*! @name MAC_1US_TIC_COUNTR - */ +#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU) +#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U) +#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK) + +/*! @name MAC_VERSION - MAC version register */ +#define ENET_MAC_VERSION_SNPVER_MASK (0xFFU) +#define ENET_MAC_VERSION_SNPVER_SHIFT (0U) +#define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK) +#define ENET_MAC_VERSION_USERVER_MASK (0xFF00U) +#define ENET_MAC_VERSION_USERVER_SHIFT (8U) +#define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK) + +/*! @name MAC_DBG - MAC debug register */ +#define ENET_MAC_DBG_REPESTS_MASK (0x1U) +#define ENET_MAC_DBG_REPESTS_SHIFT (0U) +#define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK) +#define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U) +#define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U) +#define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK) +#define ENET_MAC_DBG_TPESTS_MASK (0x10000U) +#define ENET_MAC_DBG_TPESTS_SHIFT (16U) +#define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK) +#define ENET_MAC_DBG_TFCSTS_MASK (0x60000U) +#define ENET_MAC_DBG_TFCSTS_SHIFT (17U) +#define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK) + +/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */ +#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU) +#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U) +#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK) +#define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU) +#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U) +#define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK) +#define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U) +#define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U) +#define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK) +#define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U) +#define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U) +#define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK) +#define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U) +#define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U) +#define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK) +#define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U) +#define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U) +#define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK) +#define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U) +#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U) +#define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK) +#define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U) +#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U) +#define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK) +#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U) +#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U) +#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK) +#define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U) +#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U) +#define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK) +#define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U) +#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U) +#define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK) +#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U) +#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U) +#define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK) +#define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U) +#define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U) +#define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK) +#define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U) +#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U) +#define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK) +#define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U) +#define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U) +#define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK) +#define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U) +#define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U) +#define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK) +#define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U) +#define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U) +#define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK) +#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U) +#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U) +#define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK) +#define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U) +#define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U) +#define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK) +#define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U) +#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U) +#define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK) +#define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U) +#define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U) +#define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK) +#define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U) +#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U) +#define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK) +#define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U) +#define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U) +#define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK) +#define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U) +#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U) +#define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK) +#define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U) +#define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U) +#define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK) +#define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U) +#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U) +#define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK) +#define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U) +#define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U) +#define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK) +#define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U) +#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U) +#define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK) +#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U) +#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U) +#define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK) +#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U) +#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U) +#define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK) +#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U) +#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U) +#define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK) +#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U) +#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U) +#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK) +#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U) +#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U) +#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK) +#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U) +#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U) +#define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK) + +/* The count of ENET_MAC_HW_FEAT */ +#define ENET_MAC_HW_FEAT_COUNT (3U) + +/*! @name MAC_MDIO_ADDR - MIDO address Register */ +#define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U) +#define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U) +#define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK) +#define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU) +#define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U) +#define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK) +#define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U) +#define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U) +#define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK) +#define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U) +#define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U) +#define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK) +#define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U) +#define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U) +#define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK) +#define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U) +#define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U) +#define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK) +#define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U) +#define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U) +#define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK) +#define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U) +#define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U) +#define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK) + +/*! @name MAC_MDIO_DATA - MDIO Data register */ +#define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU) +#define ENET_MAC_MDIO_DATA_MD_SHIFT (0U) +#define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK) + +/*! @name MAC_ADDR_HIGH - MAC address0 high register */ +#define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU) +#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U) +#define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK) +#define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U) +#define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U) +#define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK) +#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U) +#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U) +#define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK) + +/*! @name MAC_ADDR_LOW - MAC address0 low register */ +#define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU) +#define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U) +#define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK) + +/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */ +#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U) +#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U) +#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U) +#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U) +#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U) +#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U) +#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U) +#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U) +#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U) +#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U) +#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U) +#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U) +#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U) +#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U) +#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U) +#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U) +#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U) +#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U) +#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U) +#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U) +#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U) +#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U) +#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U) +#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U) +#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U) +#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U) +#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U) +#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U) +#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U) +#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U) +#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U) +#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U) +#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U) +#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U) +#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK) +#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U) +#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U) +#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK) + +/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */ +#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U) +#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U) +#define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK) + +/*! @name MAC_SYS_TIME_SCND - System time seconds register */ +#define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU) +#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U) +#define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK) + +/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */ +#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU) +#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U) +#define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK) + +/*! @name MAC_SYS_TIME_SCND_UPD - */ +#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU) +#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U) +#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK) + +/*! @name MAC_SYS_TIME_NSCND_UPD - */ +#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU) +#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U) +#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK) +#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U) +#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U) +#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK) + +/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */ +#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU) +#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U) +#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK) + +/*! @name MAC_SYS_TIME_HWORD_SCND - */ +#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU) +#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U) +#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK) + +/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */ +#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U) +#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U) +#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK) + +/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */ +#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU) +#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U) +#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK) +#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U) +#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U) +#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK) + +/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */ +#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU) +#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U) +#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK) + +/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */ +#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU) +#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U) +#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) + +/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */ +#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU) +#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U) +#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) + +/*! @name MTL_OP_MODE - MTL Operation Mode Register */ +#define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U) +#define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U) +#define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK) +#define ENET_MTL_OP_MODE_RAA_MASK (0x4U) +#define ENET_MTL_OP_MODE_RAA_SHIFT (2U) +#define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK) +#define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U) +#define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U) +#define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK) +#define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U) +#define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U) +#define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK) +#define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U) +#define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U) +#define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK) + +/*! @name MTL_INTR_STAT - MTL Interrupt Status register */ +#define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U) +#define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U) +#define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK) +#define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U) +#define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U) +#define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK) + +/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */ +#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U) +#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U) +#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK) +#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U) +#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U) +#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK) +#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U) +#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U) +#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK) +#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U) +#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U) +#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK) + +/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */ +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U) +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */ +#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */ +#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU) +#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U) +#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U) +#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */ +#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */ +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U) +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */ +#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */ +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U) +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U) +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U) +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U) +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U) +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U) +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */ +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */ +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU) +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */ +#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */ +#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU) +#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */ +#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */ +#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU) +#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */ +#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */ +#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU) +#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */ +#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */ +#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU) +#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */ +#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */ +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U) +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */ +#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */ +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U) +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */ +#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */ +#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU) +#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK) +#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U) +#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U) +#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */ +#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */ +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U) +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */ +#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U) + +/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */ +#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U) +#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U) +#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK) +#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U) +#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U) +#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK) + +/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */ +#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U) + +/*! @name DMA_MODE - DMA mode register */ +#define ENET_DMA_MODE_SWR_MASK (0x1U) +#define ENET_DMA_MODE_SWR_SHIFT (0U) +#define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK) +#define ENET_DMA_MODE_DA_MASK (0x2U) +#define ENET_DMA_MODE_DA_SHIFT (1U) +#define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK) +#define ENET_DMA_MODE_TAA_MASK (0x1CU) +#define ENET_DMA_MODE_TAA_SHIFT (2U) +#define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK) +#define ENET_DMA_MODE_TXPR_MASK (0x800U) +#define ENET_DMA_MODE_TXPR_SHIFT (11U) +#define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK) +#define ENET_DMA_MODE_PR_MASK (0x7000U) +#define ENET_DMA_MODE_PR_SHIFT (12U) +#define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK) + +/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */ +#define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U) +#define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U) +#define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK) +#define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) +#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U) +#define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK) +#define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U) +#define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U) +#define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK) +#define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U) +#define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U) +#define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK) + +/*! @name DMA_INTR_STAT - DMA Interrupt status */ +#define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U) +#define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U) +#define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK) +#define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U) +#define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U) +#define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK) +#define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U) +#define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U) +#define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK) +#define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U) +#define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U) +#define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK) + +/*! @name DMA_DBG_STAT - DMA Debug Status */ +#define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U) +#define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U) +#define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK) +#define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U) +#define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U) +#define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK) +#define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U) +#define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U) +#define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK) +#define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U) +#define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U) +#define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK) +#define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U) +#define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U) +#define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK) + +/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */ +#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U) +#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U) +#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK) +#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U) +#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U) +#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_CTRL */ +#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */ +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U) +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */ +#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */ +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U) +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */ +#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */ +#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU) +#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U) +#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */ +#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */ +#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU) +#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U) +#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */ +#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */ +#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU) +#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U) +#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */ +#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */ +#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU) +#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U) +#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */ +#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */ +#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) +#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */ +#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */ +#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU) +#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */ +#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */ +#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK) +#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U) +#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */ +#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */ +#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU) +#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */ +#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */ +#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U) +#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK) +#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U) +#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U) +#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK) +#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U) +#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U) +#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */ +#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */ +#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU) +#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */ +#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */ +#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU) +#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */ +#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */ +#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU) +#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */ +#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */ +#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU) +#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */ +#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U) + +/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */ +#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U) +#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U) +#define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U) +#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U) +#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U) +#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U) +#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U) +#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U) +#define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U) +#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U) +#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U) +#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U) +#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U) +#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U) +#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U) +#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U) +#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U) +#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U) +#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U) +#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U) +#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U) +#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U) +#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U) +#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U) +#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK) +#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U) +#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U) +#define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK) + +/* The count of ENET_DMA_CH_DMA_CHX_STAT */ +#define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET base address */ +#define ENET_BASE (0x40092000u) +/** Peripheral ENET base pointer */ +#define ENET ((ENET_Type *)ENET_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { ENET_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { ENET } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_IRQS { ETHERNET_IRQn } +#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn } +#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn } + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __IO uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) + +/*! @name PID - Peripheral identification register. */ +#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) +#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) +#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) +#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) +#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) +#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +/** Peripheral FLEXCOMM0 base address */ +#define FLEXCOMM0_BASE (0x40086000u) +/** Peripheral FLEXCOMM0 base pointer */ +#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) +/** Peripheral FLEXCOMM1 base address */ +#define FLEXCOMM1_BASE (0x40087000u) +/** Peripheral FLEXCOMM1 base pointer */ +#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) +/** Peripheral FLEXCOMM2 base address */ +#define FLEXCOMM2_BASE (0x40088000u) +/** Peripheral FLEXCOMM2 base pointer */ +#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) +/** Peripheral FLEXCOMM3 base address */ +#define FLEXCOMM3_BASE (0x40089000u) +/** Peripheral FLEXCOMM3 base pointer */ +#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) +/** Peripheral FLEXCOMM4 base address */ +#define FLEXCOMM4_BASE (0x4008A000u) +/** Peripheral FLEXCOMM4 base pointer */ +#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) +/** Peripheral FLEXCOMM5 base address */ +#define FLEXCOMM5_BASE (0x40096000u) +/** Peripheral FLEXCOMM5 base pointer */ +#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) +/** Peripheral FLEXCOMM6 base address */ +#define FLEXCOMM6_BASE (0x40097000u) +/** Peripheral FLEXCOMM6 base pointer */ +#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) +/** Peripheral FLEXCOMM7 base address */ +#define FLEXCOMM7_BASE (0x40098000u) +/** Peripheral FLEXCOMM7 base pointer */ +#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) +/** Peripheral FLEXCOMM8 base address */ +#define FLEXCOMM8_BASE (0x40099000u) +/** Peripheral FLEXCOMM8 base pointer */ +#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) +/** Peripheral FLEXCOMM9 base address */ +#define FLEXCOMM9_BASE (0x4009A000u) +/** Peripheral FLEXCOMM9 base pointer */ +#define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE) +/** Array initializer of FLEXCOMM peripheral base addresses */ +#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE } +/** Array initializer of FLEXCOMM peripheral base pointers */ +#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9 } +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer + * @{ + */ + +/** FMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t FCTR; /**< Control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t FBWST; /**< Wait state register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FMSSTART; /**< Signature start address register, offset: 0x20 */ + __IO uint32_t FMSSTOP; /**< Signature stop-address register, offset: 0x24 */ + uint8_t RESERVED_2[4]; + __I uint32_t FMSW[4]; /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */ + uint8_t RESERVED_3[4004]; + __I uint32_t FMSTAT; /**< Signature generation status register, offset: 0xFE0 */ + uint8_t RESERVED_4[4]; + __O uint32_t FMSTATCLR; /**< Signature generation status clear register, offset: 0xFE8 */ +} FMC_Type; + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/*! @name FCTR - Control register */ +#define FMC_FCTR_FS_RD0_MASK (0x8U) +#define FMC_FCTR_FS_RD0_SHIFT (3U) +#define FMC_FCTR_FS_RD0(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK) +#define FMC_FCTR_FS_RD1_MASK (0x10U) +#define FMC_FCTR_FS_RD1_SHIFT (4U) +#define FMC_FCTR_FS_RD1(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK) + +/*! @name FBWST - Wait state register */ +#define FMC_FBWST_WAITSTATES_MASK (0xFFU) +#define FMC_FBWST_WAITSTATES_SHIFT (0U) +#define FMC_FBWST_WAITSTATES(x) (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK) + +/*! @name FMSSTART - Signature start address register */ +#define FMC_FMSSTART_START_MASK (0x1FFFFU) +#define FMC_FMSSTART_START_SHIFT (0U) +#define FMC_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK) + +/*! @name FMSSTOP - Signature stop-address register */ +#define FMC_FMSSTOP_STOP_MASK (0x1FFFFU) +#define FMC_FMSSTOP_STOP_SHIFT (0U) +#define FMC_FMSSTOP_STOP(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK) +#define FMC_FMSSTOP_SIG_START_MASK (0x20000U) +#define FMC_FMSSTOP_SIG_START_SHIFT (17U) +#define FMC_FMSSTOP_SIG_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK) + +/*! @name FMSW - Words of 128-bit signature word */ +#define FMC_FMSW_SW_MASK (0xFFFFFFFFU) +#define FMC_FMSW_SW_SHIFT (0U) +#define FMC_FMSW_SW(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK) + +/* The count of FMC_FMSW */ +#define FMC_FMSW_COUNT (4U) + +/*! @name FMSTAT - Signature generation status register */ +#define FMC_FMSTAT_SIG_DONE_MASK (0x4U) +#define FMC_FMSTAT_SIG_DONE_SHIFT (2U) +#define FMC_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK) + +/*! @name FMSTATCLR - Signature generation status clear register */ +#define FMC_FMSTATCLR_SIG_DONE_CLR_MASK (0x4U) +#define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT (2U) +#define FMC_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK) + + +/*! + * @} + */ /* end of group FMC_Register_Masks */ + + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC base address */ +#define FMC_BASE (0x40034000u) +/** Peripheral FMC base pointer */ +#define FMC ((FMC_Type *)FMC_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC } + +/*! + * @} + */ /* end of group FMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +/** Peripheral GINT0 base address */ +#define GINT0_BASE (0x40002000u) +/** Peripheral GINT0 base pointer */ +#define GINT0 ((GINT_Type *)GINT0_BASE) +/** Peripheral GINT1 base address */ +#define GINT1_BASE (0x40003000u) +/** Peripheral GINT1 base pointer */ +#define GINT1 ((GINT_Type *)GINT1_BASE) +/** Array initializer of GINT peripheral base addresses */ +#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } +/** Array initializer of GINT peripheral base pointers */ +#define GINT_BASE_PTRS { GINT0, GINT1 } +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[3904]; + __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3328]; + __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[104]; + __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[104]; + __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[104]; + __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[104]; + __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[104]; + __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[104]; + __O uint32_t NOT[6]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[104]; + __O uint32_t DIRSET[6]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[104]; + __O uint32_t DIRCLR[6]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[104]; + __O uint32_t DIRNOT[6]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT (6U) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT (6U) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers */ +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (6U) + +/*! @name MASK - Mask register */ +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (6U) + +/*! @name PIN - Port pin register */ +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (6U) + +/*! @name MPIN - Masked port register */ +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (6U) + +/*! @name SET - Write: Set register for port Read: output bits for port */ +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (6U) + +/*! @name CLR - Clear port */ +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (6U) + +/*! @name NOT - Toggle port */ +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (6U) + +/*! @name DIRSET - Set pin direction bits for port */ +#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (6U) + +/*! @name DIRCLR - Clear pin direction bits for port */ +#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (6U) + +/*! @name DIRNOT - Toggle pin direction bits for port */ +#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (6U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO base address */ +#define GPIO_BASE (0x4008C000u) +/** Peripheral GPIO base pointer */ +#define GPIO ((GPIO_Type *)GPIO_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ + uint8_t RESERVED_4[1912]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) + +/*! @name TIMEOUT - Time-out value register. */ +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) + +/*! @name MSTCTL - Master control register. */ +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) + +/*! @name MSTTIME - Master timing configuration. */ +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) + +/*! @name SLVCTL - Slave control register. */ +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) + +/*! @name SLVADR - Slave address register. */ +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) + +/*! @name MONRXDAT - Monitor receiver data register. */ +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) + +/*! @name ID - Peripheral identification register. */ +#define I2C_ID_APERTURE_MASK (0xFFU) +#define I2C_ID_APERTURE_SHIFT (0U) +#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) +#define I2C_ID_MINOR_REV_MASK (0xF00U) +#define I2C_ID_MINOR_REV_SHIFT (8U) +#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) +#define I2C_ID_MAJOR_REV_MASK (0xF000U) +#define I2C_ID_MAJOR_REV_SHIFT (12U) +#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) +#define I2C_ID_ID_MASK (0xFFFF0000U) +#define I2C_ID_ID_SHIFT (16U) +#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C0 base address */ +#define I2C0_BASE (0x40086000u) +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_Type *)I2C0_BASE) +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x40087000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x40088000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Peripheral I2C3 base address */ +#define I2C3_BASE (0x40089000u) +/** Peripheral I2C3 base pointer */ +#define I2C3 ((I2C_Type *)I2C3_BASE) +/** Peripheral I2C4 base address */ +#define I2C4_BASE (0x4008A000u) +/** Peripheral I2C4 base pointer */ +#define I2C4 ((I2C_Type *)I2C4_BASE) +/** Peripheral I2C5 base address */ +#define I2C5_BASE (0x40096000u) +/** Peripheral I2C5 base pointer */ +#define I2C5 ((I2C_Type *)I2C5_BASE) +/** Peripheral I2C6 base address */ +#define I2C6_BASE (0x40097000u) +/** Peripheral I2C6 base pointer */ +#define I2C6 ((I2C_Type *)I2C6_BASE) +/** Peripheral I2C7 base address */ +#define I2C7_BASE (0x40098000u) +/** Peripheral I2C7 base pointer */ +#define I2C7 ((I2C_Type *)I2C7_BASE) +/** Peripheral I2C8 base address */ +#define I2C8_BASE (0x40099000u) +/** Peripheral I2C8 base pointer */ +#define I2C8 ((I2C_Type *)I2C8_BASE) +/** Peripheral I2C9 base address */ +#define I2C9_BASE (0x4009A000u) +/** Peripheral I2C9 base pointer */ +#define I2C9 ((I2C_Type *)I2C9_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + struct { /* offset: 0x20, array step: 0x20 */ + __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0x20, array step: 0x20 */ + __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0x24, array step: 0x20 */ + __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0x28, array step: 0x20 */ + uint8_t RESERVED_0[20]; + } SECCHANNEL[3]; + uint8_t RESERVED_1[2944]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_2[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + uint8_t RESERVED_3[480]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_4[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_5[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_7[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ + uint8_t RESERVED_8[4020]; + __I uint32_t ID; /**< I2S Module identification, offset: 0x1DFC */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) +#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) +#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) + +/* The count of I2S_SECCHANNEL_PCFG1 */ +#define I2S_SECCHANNEL_PCFG1_COUNT (3U) + +/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ +#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) +#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) +#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) + +/* The count of I2S_SECCHANNEL_PCFG2 */ +#define I2S_SECCHANNEL_PCFG2_COUNT (3U) + +/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ +#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) +#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) +#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) +#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) +#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) +#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) +#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) +#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) + +/* The count of I2S_SECCHANNEL_PSTAT */ +#define I2S_SECCHANNEL_PSTAT_COUNT (3U) + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) +#define I2S_CFG1_PDMDATA_MASK (0x800U) +#define I2S_CFG1_PDMDATA_SHIFT (11U) +#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) + +/*! @name STAT - Status register for the primary channel pair. */ +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) + +/*! @name DIV - Clock divider, used by all channel pairs. */ +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) +#define I2S_FIFOCFG_POPDBG_SHIFT (18U) +#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) + +/*! @name FIFOSTAT - FIFO status register. */ +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) + +/*! @name FIFOWR - FIFO write data. */ +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) + +/*! @name FIFORD - FIFO read data. */ +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) + +/*! @name ID - I2S Module identification */ +#define I2S_ID_Aperture_MASK (0xFFU) +#define I2S_ID_Aperture_SHIFT (0U) +#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) +#define I2S_ID_Minor_Rev_MASK (0xF00U) +#define I2S_ID_Minor_Rev_SHIFT (8U) +#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) +#define I2S_ID_Major_Rev_MASK (0xF000U) +#define I2S_ID_Major_Rev_SHIFT (12U) +#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) +#define I2S_ID_ID_MASK (0xFFFF0000U) +#define I2S_ID_ID_SHIFT (16U) +#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S0 base address */ +#define I2S0_BASE (0x40097000u) +/** Peripheral I2S0 base pointer */ +#define I2S0 ((I2S_Type *)I2S0_BASE) +/** Peripheral I2S1 base address */ +#define I2S1_BASE (0x40098000u) +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_Type *)I2S1_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { I2S0, I2S1 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCT0_INMUX[7]; /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[164]; + __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t DMA_ITRIG_INMUX[30]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name SCT0_INMUX - Trigger select register for DMA channel */ +#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) +#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) +#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) + +/* The count of INPUTMUX_SCT0_INMUX */ +#define INPUTMUX_SCT0_INMUX_COUNT (7U) + +/*! @name PINTSEL - Pin interrupt select register */ +#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (8U) + +/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ +#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) + +/* The count of INPUTMUX_DMA_ITRIG_INMUX */ +#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (30U) + +/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ +#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) + +/* The count of INPUTMUX_DMA_OTRIG_INMUX */ +#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX base address */ +#define INPUTMUX_BASE (0x40005000u) +/** Peripheral INPUTMUX base pointer */ +#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX } + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[6][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */ +#define IOCON_PIO_FUNC_MASK (0xFU) +#define IOCON_PIO_FUNC_SHIFT (0U) +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) +#define IOCON_PIO_MODE_MASK (0x30U) +#define IOCON_PIO_MODE_SHIFT (4U) +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) +#define IOCON_PIO_I2CSLEW_MASK (0x40U) +#define IOCON_PIO_I2CSLEW_SHIFT (6U) +#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) +#define IOCON_PIO_INVERT_MASK (0x80U) +#define IOCON_PIO_INVERT_SHIFT (7U) +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) +#define IOCON_PIO_DIGIMODE_MASK (0x100U) +#define IOCON_PIO_DIGIMODE_SHIFT (8U) +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) +#define IOCON_PIO_FILTEROFF_MASK (0x200U) +#define IOCON_PIO_FILTEROFF_SHIFT (9U) +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) +#define IOCON_PIO_I2CDRIVE_MASK (0x400U) +#define IOCON_PIO_I2CDRIVE_SHIFT (10U) +#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) +#define IOCON_PIO_SLEW_MASK (0x400U) +#define IOCON_PIO_SLEW_SHIFT (10U) +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) +#define IOCON_PIO_OD_MASK (0x800U) +#define IOCON_PIO_OD_SHIFT (11U) +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) +#define IOCON_PIO_I2CFILTER_MASK (0x800U) +#define IOCON_PIO_I2CFILTER_SHIFT (11U) +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (6U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +/** Peripheral IOCON base address */ +#define IOCON_BASE (0x40001000u) +/** Peripheral IOCON base pointer */ +#define IOCON ((IOCON_Type *)IOCON_BASE) +/** Array initializer of IOCON peripheral base addresses */ +#define IOCON_BASE_ADDRS { IOCON_BASE } +/** Array initializer of IOCON peripheral base pointers */ +#define IOCON_BASE_PTRS { IOCON } + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer + * @{ + */ + +/** LCD - Register Layout Typedef */ +typedef struct { + __IO uint32_t TIMH; /**< Horizontal Timing Control register, offset: 0x0 */ + __IO uint32_t TIMV; /**< Vertical Timing Control register, offset: 0x4 */ + __IO uint32_t POL; /**< Clock and Signal Polarity Control register, offset: 0x8 */ + __IO uint32_t LE; /**< Line End Control register, offset: 0xC */ + __IO uint32_t UPBASE; /**< Upper Panel Frame Base Address register, offset: 0x10 */ + __IO uint32_t LPBASE; /**< Lower Panel Frame Base Address register, offset: 0x14 */ + __IO uint32_t CTRL; /**< LCD Control register, offset: 0x18 */ + __IO uint32_t INTMSK; /**< Interrupt Mask register, offset: 0x1C */ + __I uint32_t INTRAW; /**< Raw Interrupt Status register, offset: 0x20 */ + __I uint32_t INTSTAT; /**< Masked Interrupt Status register, offset: 0x24 */ + __IO uint32_t INTCLR; /**< Interrupt Clear register, offset: 0x28 */ + __I uint32_t UPCURR; /**< Upper Panel Current Address Value register, offset: 0x2C */ + __I uint32_t LPCURR; /**< Lower Panel Current Address Value register, offset: 0x30 */ + uint8_t RESERVED_0[460]; + __IO uint32_t PAL[128]; /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_1[1024]; + __IO uint32_t CRSR_IMG[256]; /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */ + __IO uint32_t CRSR_CTRL; /**< Cursor Control register, offset: 0xC00 */ + __IO uint32_t CRSR_CFG; /**< Cursor Configuration register, offset: 0xC04 */ + __IO uint32_t CRSR_PAL0; /**< Cursor Palette register 0, offset: 0xC08 */ + __IO uint32_t CRSR_PAL1; /**< Cursor Palette register 1, offset: 0xC0C */ + __IO uint32_t CRSR_XY; /**< Cursor XY Position register, offset: 0xC10 */ + __IO uint32_t CRSR_CLIP; /**< Cursor Clip Position register, offset: 0xC14 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CRSR_INTMSK; /**< Cursor Interrupt Mask register, offset: 0xC20 */ + __O uint32_t CRSR_INTCLR; /**< Cursor Interrupt Clear register, offset: 0xC24 */ + __I uint32_t CRSR_INTRAW; /**< Cursor Raw Interrupt Status register, offset: 0xC28 */ + __I uint32_t CRSR_INTSTAT; /**< Cursor Masked Interrupt Status register, offset: 0xC2C */ +} LCD_Type; + +/* ---------------------------------------------------------------------------- + -- LCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCD_Register_Masks LCD Register Masks + * @{ + */ + +/*! @name TIMH - Horizontal Timing Control register */ +#define LCD_TIMH_PPL_MASK (0xFCU) +#define LCD_TIMH_PPL_SHIFT (2U) +#define LCD_TIMH_PPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK) +#define LCD_TIMH_HSW_MASK (0xFF00U) +#define LCD_TIMH_HSW_SHIFT (8U) +#define LCD_TIMH_HSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK) +#define LCD_TIMH_HFP_MASK (0xFF0000U) +#define LCD_TIMH_HFP_SHIFT (16U) +#define LCD_TIMH_HFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK) +#define LCD_TIMH_HBP_MASK (0xFF000000U) +#define LCD_TIMH_HBP_SHIFT (24U) +#define LCD_TIMH_HBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK) + +/*! @name TIMV - Vertical Timing Control register */ +#define LCD_TIMV_LPP_MASK (0x3FFU) +#define LCD_TIMV_LPP_SHIFT (0U) +#define LCD_TIMV_LPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK) +#define LCD_TIMV_VSW_MASK (0xFC00U) +#define LCD_TIMV_VSW_SHIFT (10U) +#define LCD_TIMV_VSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK) +#define LCD_TIMV_VFP_MASK (0xFF0000U) +#define LCD_TIMV_VFP_SHIFT (16U) +#define LCD_TIMV_VFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK) +#define LCD_TIMV_VBP_MASK (0xFF000000U) +#define LCD_TIMV_VBP_SHIFT (24U) +#define LCD_TIMV_VBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK) + +/*! @name POL - Clock and Signal Polarity Control register */ +#define LCD_POL_PCD_LO_MASK (0x1FU) +#define LCD_POL_PCD_LO_SHIFT (0U) +#define LCD_POL_PCD_LO(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK) +#define LCD_POL_ACB_MASK (0x7C0U) +#define LCD_POL_ACB_SHIFT (6U) +#define LCD_POL_ACB(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK) +#define LCD_POL_IVS_MASK (0x800U) +#define LCD_POL_IVS_SHIFT (11U) +#define LCD_POL_IVS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK) +#define LCD_POL_IHS_MASK (0x1000U) +#define LCD_POL_IHS_SHIFT (12U) +#define LCD_POL_IHS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK) +#define LCD_POL_IPC_MASK (0x2000U) +#define LCD_POL_IPC_SHIFT (13U) +#define LCD_POL_IPC(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK) +#define LCD_POL_IOE_MASK (0x4000U) +#define LCD_POL_IOE_SHIFT (14U) +#define LCD_POL_IOE(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK) +#define LCD_POL_CPL_MASK (0x3FF0000U) +#define LCD_POL_CPL_SHIFT (16U) +#define LCD_POL_CPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK) +#define LCD_POL_BCD_MASK (0x4000000U) +#define LCD_POL_BCD_SHIFT (26U) +#define LCD_POL_BCD(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK) +#define LCD_POL_PCD_HI_MASK (0xF8000000U) +#define LCD_POL_PCD_HI_SHIFT (27U) +#define LCD_POL_PCD_HI(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK) + +/*! @name LE - Line End Control register */ +#define LCD_LE_LED_MASK (0x7FU) +#define LCD_LE_LED_SHIFT (0U) +#define LCD_LE_LED(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK) +#define LCD_LE_LEE_MASK (0x10000U) +#define LCD_LE_LEE_SHIFT (16U) +#define LCD_LE_LEE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK) + +/*! @name UPBASE - Upper Panel Frame Base Address register */ +#define LCD_UPBASE_LCDUPBASE_MASK (0xFFFFFFF8U) +#define LCD_UPBASE_LCDUPBASE_SHIFT (3U) +#define LCD_UPBASE_LCDUPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK) + +/*! @name LPBASE - Lower Panel Frame Base Address register */ +#define LCD_LPBASE_LCDLPBASE_MASK (0xFFFFFFF8U) +#define LCD_LPBASE_LCDLPBASE_SHIFT (3U) +#define LCD_LPBASE_LCDLPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK) + +/*! @name CTRL - LCD Control register */ +#define LCD_CTRL_LCDEN_MASK (0x1U) +#define LCD_CTRL_LCDEN_SHIFT (0U) +#define LCD_CTRL_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK) +#define LCD_CTRL_LCDBPP_MASK (0xEU) +#define LCD_CTRL_LCDBPP_SHIFT (1U) +#define LCD_CTRL_LCDBPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK) +#define LCD_CTRL_LCDBW_MASK (0x10U) +#define LCD_CTRL_LCDBW_SHIFT (4U) +#define LCD_CTRL_LCDBW(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK) +#define LCD_CTRL_LCDTFT_MASK (0x20U) +#define LCD_CTRL_LCDTFT_SHIFT (5U) +#define LCD_CTRL_LCDTFT(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK) +#define LCD_CTRL_LCDMONO8_MASK (0x40U) +#define LCD_CTRL_LCDMONO8_SHIFT (6U) +#define LCD_CTRL_LCDMONO8(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK) +#define LCD_CTRL_LCDDUAL_MASK (0x80U) +#define LCD_CTRL_LCDDUAL_SHIFT (7U) +#define LCD_CTRL_LCDDUAL(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK) +#define LCD_CTRL_BGR_MASK (0x100U) +#define LCD_CTRL_BGR_SHIFT (8U) +#define LCD_CTRL_BGR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK) +#define LCD_CTRL_BEBO_MASK (0x200U) +#define LCD_CTRL_BEBO_SHIFT (9U) +#define LCD_CTRL_BEBO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK) +#define LCD_CTRL_BEPO_MASK (0x400U) +#define LCD_CTRL_BEPO_SHIFT (10U) +#define LCD_CTRL_BEPO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK) +#define LCD_CTRL_LCDPWR_MASK (0x800U) +#define LCD_CTRL_LCDPWR_SHIFT (11U) +#define LCD_CTRL_LCDPWR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK) +#define LCD_CTRL_LCDVCOMP_MASK (0x3000U) +#define LCD_CTRL_LCDVCOMP_SHIFT (12U) +#define LCD_CTRL_LCDVCOMP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK) +#define LCD_CTRL_WATERMARK_MASK (0x10000U) +#define LCD_CTRL_WATERMARK_SHIFT (16U) +#define LCD_CTRL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK) + +/*! @name INTMSK - Interrupt Mask register */ +#define LCD_INTMSK_FUFIM_MASK (0x2U) +#define LCD_INTMSK_FUFIM_SHIFT (1U) +#define LCD_INTMSK_FUFIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK) +#define LCD_INTMSK_LNBUIM_MASK (0x4U) +#define LCD_INTMSK_LNBUIM_SHIFT (2U) +#define LCD_INTMSK_LNBUIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK) +#define LCD_INTMSK_VCOMPIM_MASK (0x8U) +#define LCD_INTMSK_VCOMPIM_SHIFT (3U) +#define LCD_INTMSK_VCOMPIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK) +#define LCD_INTMSK_BERIM_MASK (0x10U) +#define LCD_INTMSK_BERIM_SHIFT (4U) +#define LCD_INTMSK_BERIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK) + +/*! @name INTRAW - Raw Interrupt Status register */ +#define LCD_INTRAW_FUFRIS_MASK (0x2U) +#define LCD_INTRAW_FUFRIS_SHIFT (1U) +#define LCD_INTRAW_FUFRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK) +#define LCD_INTRAW_LNBURIS_MASK (0x4U) +#define LCD_INTRAW_LNBURIS_SHIFT (2U) +#define LCD_INTRAW_LNBURIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK) +#define LCD_INTRAW_VCOMPRIS_MASK (0x8U) +#define LCD_INTRAW_VCOMPRIS_SHIFT (3U) +#define LCD_INTRAW_VCOMPRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK) +#define LCD_INTRAW_BERRAW_MASK (0x10U) +#define LCD_INTRAW_BERRAW_SHIFT (4U) +#define LCD_INTRAW_BERRAW(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK) + +/*! @name INTSTAT - Masked Interrupt Status register */ +#define LCD_INTSTAT_FUFMIS_MASK (0x2U) +#define LCD_INTSTAT_FUFMIS_SHIFT (1U) +#define LCD_INTSTAT_FUFMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK) +#define LCD_INTSTAT_LNBUMIS_MASK (0x4U) +#define LCD_INTSTAT_LNBUMIS_SHIFT (2U) +#define LCD_INTSTAT_LNBUMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK) +#define LCD_INTSTAT_VCOMPMIS_MASK (0x8U) +#define LCD_INTSTAT_VCOMPMIS_SHIFT (3U) +#define LCD_INTSTAT_VCOMPMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK) +#define LCD_INTSTAT_BERMIS_MASK (0x10U) +#define LCD_INTSTAT_BERMIS_SHIFT (4U) +#define LCD_INTSTAT_BERMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK) + +/*! @name INTCLR - Interrupt Clear register */ +#define LCD_INTCLR_FUFIC_MASK (0x2U) +#define LCD_INTCLR_FUFIC_SHIFT (1U) +#define LCD_INTCLR_FUFIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK) +#define LCD_INTCLR_LNBUIC_MASK (0x4U) +#define LCD_INTCLR_LNBUIC_SHIFT (2U) +#define LCD_INTCLR_LNBUIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK) +#define LCD_INTCLR_VCOMPIC_MASK (0x8U) +#define LCD_INTCLR_VCOMPIC_SHIFT (3U) +#define LCD_INTCLR_VCOMPIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK) +#define LCD_INTCLR_BERIC_MASK (0x10U) +#define LCD_INTCLR_BERIC_SHIFT (4U) +#define LCD_INTCLR_BERIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK) + +/*! @name UPCURR - Upper Panel Current Address Value register */ +#define LCD_UPCURR_LCDUPCURR_MASK (0xFFFFFFFFU) +#define LCD_UPCURR_LCDUPCURR_SHIFT (0U) +#define LCD_UPCURR_LCDUPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK) + +/*! @name LPCURR - Lower Panel Current Address Value register */ +#define LCD_LPCURR_LCDLPCURR_MASK (0xFFFFFFFFU) +#define LCD_LPCURR_LCDLPCURR_SHIFT (0U) +#define LCD_LPCURR_LCDLPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK) + +/*! @name PAL - 256x16-bit Color Palette registers */ +#define LCD_PAL_R04_0_MASK (0x1FU) +#define LCD_PAL_R04_0_SHIFT (0U) +#define LCD_PAL_R04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK) +#define LCD_PAL_G04_0_MASK (0x3E0U) +#define LCD_PAL_G04_0_SHIFT (5U) +#define LCD_PAL_G04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK) +#define LCD_PAL_B04_0_MASK (0x7C00U) +#define LCD_PAL_B04_0_SHIFT (10U) +#define LCD_PAL_B04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK) +#define LCD_PAL_I0_MASK (0x8000U) +#define LCD_PAL_I0_SHIFT (15U) +#define LCD_PAL_I0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK) +#define LCD_PAL_R14_0_MASK (0x1F0000U) +#define LCD_PAL_R14_0_SHIFT (16U) +#define LCD_PAL_R14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK) +#define LCD_PAL_G14_0_MASK (0x3E00000U) +#define LCD_PAL_G14_0_SHIFT (21U) +#define LCD_PAL_G14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK) +#define LCD_PAL_B14_0_MASK (0x7C000000U) +#define LCD_PAL_B14_0_SHIFT (26U) +#define LCD_PAL_B14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK) +#define LCD_PAL_I1_MASK (0x80000000U) +#define LCD_PAL_I1_SHIFT (31U) +#define LCD_PAL_I1(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK) + +/* The count of LCD_PAL */ +#define LCD_PAL_COUNT (128U) + +/*! @name CRSR_IMG - Cursor Image registers */ +#define LCD_CRSR_IMG_CRSR_IMG_MASK (0xFFFFFFFFU) +#define LCD_CRSR_IMG_CRSR_IMG_SHIFT (0U) +#define LCD_CRSR_IMG_CRSR_IMG(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK) + +/* The count of LCD_CRSR_IMG */ +#define LCD_CRSR_IMG_COUNT (256U) + +/*! @name CRSR_CTRL - Cursor Control register */ +#define LCD_CRSR_CTRL_CRSRON_MASK (0x1U) +#define LCD_CRSR_CTRL_CRSRON_SHIFT (0U) +#define LCD_CRSR_CTRL_CRSRON(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK) +#define LCD_CRSR_CTRL_CRSRNUM1_0_MASK (0x30U) +#define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT (4U) +#define LCD_CRSR_CTRL_CRSRNUM1_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK) + +/*! @name CRSR_CFG - Cursor Configuration register */ +#define LCD_CRSR_CFG_CRSRSIZE_MASK (0x1U) +#define LCD_CRSR_CFG_CRSRSIZE_SHIFT (0U) +#define LCD_CRSR_CFG_CRSRSIZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK) +#define LCD_CRSR_CFG_FRAMESYNC_MASK (0x2U) +#define LCD_CRSR_CFG_FRAMESYNC_SHIFT (1U) +#define LCD_CRSR_CFG_FRAMESYNC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK) + +/*! @name CRSR_PAL0 - Cursor Palette register 0 */ +#define LCD_CRSR_PAL0_RED_MASK (0xFFU) +#define LCD_CRSR_PAL0_RED_SHIFT (0U) +#define LCD_CRSR_PAL0_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK) +#define LCD_CRSR_PAL0_GREEN_MASK (0xFF00U) +#define LCD_CRSR_PAL0_GREEN_SHIFT (8U) +#define LCD_CRSR_PAL0_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK) +#define LCD_CRSR_PAL0_BLUE_MASK (0xFF0000U) +#define LCD_CRSR_PAL0_BLUE_SHIFT (16U) +#define LCD_CRSR_PAL0_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK) + +/*! @name CRSR_PAL1 - Cursor Palette register 1 */ +#define LCD_CRSR_PAL1_RED_MASK (0xFFU) +#define LCD_CRSR_PAL1_RED_SHIFT (0U) +#define LCD_CRSR_PAL1_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK) +#define LCD_CRSR_PAL1_GREEN_MASK (0xFF00U) +#define LCD_CRSR_PAL1_GREEN_SHIFT (8U) +#define LCD_CRSR_PAL1_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK) +#define LCD_CRSR_PAL1_BLUE_MASK (0xFF0000U) +#define LCD_CRSR_PAL1_BLUE_SHIFT (16U) +#define LCD_CRSR_PAL1_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK) + +/*! @name CRSR_XY - Cursor XY Position register */ +#define LCD_CRSR_XY_CRSRX_MASK (0x3FFU) +#define LCD_CRSR_XY_CRSRX_SHIFT (0U) +#define LCD_CRSR_XY_CRSRX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK) +#define LCD_CRSR_XY_CRSRY_MASK (0x3FF0000U) +#define LCD_CRSR_XY_CRSRY_SHIFT (16U) +#define LCD_CRSR_XY_CRSRY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK) + +/*! @name CRSR_CLIP - Cursor Clip Position register */ +#define LCD_CRSR_CLIP_CRSRCLIPX_MASK (0x3FU) +#define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT (0U) +#define LCD_CRSR_CLIP_CRSRCLIPX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK) +#define LCD_CRSR_CLIP_CRSRCLIPY_MASK (0x3F00U) +#define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT (8U) +#define LCD_CRSR_CLIP_CRSRCLIPY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK) + +/*! @name CRSR_INTMSK - Cursor Interrupt Mask register */ +#define LCD_CRSR_INTMSK_CRSRIM_MASK (0x1U) +#define LCD_CRSR_INTMSK_CRSRIM_SHIFT (0U) +#define LCD_CRSR_INTMSK_CRSRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK) + +/*! @name CRSR_INTCLR - Cursor Interrupt Clear register */ +#define LCD_CRSR_INTCLR_CRSRIC_MASK (0x1U) +#define LCD_CRSR_INTCLR_CRSRIC_SHIFT (0U) +#define LCD_CRSR_INTCLR_CRSRIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK) + +/*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */ +#define LCD_CRSR_INTRAW_CRSRRIS_MASK (0x1U) +#define LCD_CRSR_INTRAW_CRSRRIS_SHIFT (0U) +#define LCD_CRSR_INTRAW_CRSRRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK) + +/*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */ +#define LCD_CRSR_INTSTAT_CRSRMIS_MASK (0x1U) +#define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT (0U) +#define LCD_CRSR_INTSTAT_CRSRMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK) + + +/*! + * @} + */ /* end of group LCD_Register_Masks */ + + +/* LCD - Peripheral instance base addresses */ +/** Peripheral LCD base address */ +#define LCD_BASE (0x40083000u) +/** Peripheral LCD base pointer */ +#define LCD ((LCD_Type *)LCD_BASE) +/** Array initializer of LCD peripheral base addresses */ +#define LCD_BASE_ADDRS { LCD_BASE } +/** Array initializer of LCD peripheral base pointers */ +#define LCD_BASE_PTRS { LCD } +/** Interrupt vectors for the LCD peripheral type */ +#define LCD_IRQS { LCD_IRQn } + +/*! + * @} + */ /* end of group LCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) + +/*! @name IRQ_FLAG - Global interrupt flag register */ +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +/** Peripheral MRT0 base address */ +#define MRT0_BASE (0x4000D000u) +/** Peripheral MRT0 base pointer */ +#define MRT0 ((MRT_Type *)MRT0_BASE) +/** Array initializer of MRT peripheral base addresses */ +#define MRT_BASE_ADDRS { MRT0_BASE } +/** Array initializer of MRT peripheral base pointers */ +#define MRT_BASE_PTRS { MRT0 } +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OTPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer + * @{ + */ + +/** OTPC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __I uint32_t AESKEY[8]; /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */ + __I uint32_t ECRP; /**< ECRP options., offset: 0x30 */ + uint8_t RESERVED_1[4]; + __I uint32_t USER0; /**< User application specific options., offset: 0x38 */ + __I uint32_t USER1; /**< User application specific options., offset: 0x3C */ +} OTPC_Type; + +/* ---------------------------------------------------------------------------- + -- OTPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTPC_Register_Masks OTPC Register Masks + * @{ + */ + +/*! @name AESKEY - Register for reading the AES key. */ +#define OTPC_AESKEY_KEY_MASK (0xFFFFFFFFU) +#define OTPC_AESKEY_KEY_SHIFT (0U) +#define OTPC_AESKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK) + +/* The count of OTPC_AESKEY */ +#define OTPC_AESKEY_COUNT (8U) + +/*! @name ECRP - ECRP options. */ +#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK (0x10U) +#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT (4U) +#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK) +#define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK (0x20U) +#define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT (5U) +#define OTPC_ECRP_IAP_PROTECTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK) +#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK (0x40U) +#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT (6U) +#define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK) +#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK (0x80U) +#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT (7U) +#define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK) +#define OTPC_ECRP_CRP_ALLOW_ZERO_MASK (0x200U) +#define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT (9U) +#define OTPC_ECRP_CRP_ALLOW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK) +#define OTPC_ECRP_JTAG_DISABLE_MASK (0x80000000U) +#define OTPC_ECRP_JTAG_DISABLE_SHIFT (31U) +#define OTPC_ECRP_JTAG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK) + +/*! @name USER0 - User application specific options. */ +#define OTPC_USER0_USER0_MASK (0xFFFFFFFFU) +#define OTPC_USER0_USER0_SHIFT (0U) +#define OTPC_USER0_USER0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK) + +/*! @name USER1 - User application specific options. */ +#define OTPC_USER1_USER1_MASK (0xFFFFFFFFU) +#define OTPC_USER1_USER1_SHIFT (0U) +#define OTPC_USER1_USER1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK) + + +/*! + * @} + */ /* end of group OTPC_Register_Masks */ + + +/* OTPC - Peripheral instance base addresses */ +/** Peripheral OTPC base address */ +#define OTPC_BASE (0x40015000u) +/** Peripheral OTPC base pointer */ +#define OTPC ((OTPC_Type *)OTPC_BASE) +/** Array initializer of OTPC peripheral base addresses */ +#define OTPC_BASE_ADDRS { OTPC_BASE } +/** Array initializer of OTPC peripheral base pointers */ +#define OTPC_BASE_PTRS { OTPC } + +/*! + * @} + */ /* end of group OTPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) + +/*! @name RISE - Pin interrupt rising edge register */ +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) + +/*! @name FALL - Pin interrupt falling edge register */ +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) + +/*! @name IST - Pin interrupt status register */ +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) + +/*! @name PMCTRL - Pattern match interrupt control register */ +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +/** Peripheral PINT base address */ +#define PINT_BASE (0x40004000u) +/** Peripheral PINT base pointer */ +#define PINT ((PINT_Type *)PINT_BASE) +/** Array initializer of PINT peripheral base addresses */ +#define PINT_BASE_ADDRS { PINT_BASE } +/** Array initializer of PINT peripheral base pointers */ +#define PINT_BASE_PTRS { PINT } +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer + * @{ + */ + +/** RIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t COMPVAL; /**< Compare value LSB register, offset: 0x0 */ + __IO uint32_t MASK; /**< Mask LSB register, offset: 0x4 */ + __IO uint32_t CTRL; /**< Control register, offset: 0x8 */ + __IO uint32_t COUNTER; /**< Counter LSB register, offset: 0xC */ + __IO uint32_t COMPVAL_H; /**< Compare value MSB register, offset: 0x10 */ + __IO uint32_t MASK_H; /**< Mask MSB register, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t COUNTER_H; /**< Counter MSB register, offset: 0x1C */ +} RIT_Type; + +/* ---------------------------------------------------------------------------- + -- RIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RIT_Register_Masks RIT Register Masks + * @{ + */ + +/*! @name COMPVAL - Compare value LSB register */ +#define RIT_COMPVAL_RICOMP_MASK (0xFFFFFFFFU) +#define RIT_COMPVAL_RICOMP_SHIFT (0U) +#define RIT_COMPVAL_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK) + +/*! @name MASK - Mask LSB register */ +#define RIT_MASK_RIMASK_MASK (0xFFFFFFFFU) +#define RIT_MASK_RIMASK_SHIFT (0U) +#define RIT_MASK_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK) + +/*! @name CTRL - Control register */ +#define RIT_CTRL_RITINT_MASK (0x1U) +#define RIT_CTRL_RITINT_SHIFT (0U) +#define RIT_CTRL_RITINT(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK) +#define RIT_CTRL_RITENCLR_MASK (0x2U) +#define RIT_CTRL_RITENCLR_SHIFT (1U) +#define RIT_CTRL_RITENCLR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK) +#define RIT_CTRL_RITENBR_MASK (0x4U) +#define RIT_CTRL_RITENBR_SHIFT (2U) +#define RIT_CTRL_RITENBR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK) +#define RIT_CTRL_RITEN_MASK (0x8U) +#define RIT_CTRL_RITEN_SHIFT (3U) +#define RIT_CTRL_RITEN(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK) + +/*! @name COUNTER - Counter LSB register */ +#define RIT_COUNTER_RICOUNTER_MASK (0xFFFFFFFFU) +#define RIT_COUNTER_RICOUNTER_SHIFT (0U) +#define RIT_COUNTER_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK) + +/*! @name COMPVAL_H - Compare value MSB register */ +#define RIT_COMPVAL_H_RICOMP_MASK (0xFFFFU) +#define RIT_COMPVAL_H_RICOMP_SHIFT (0U) +#define RIT_COMPVAL_H_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK) + +/*! @name MASK_H - Mask MSB register */ +#define RIT_MASK_H_RIMASK_MASK (0xFFFFU) +#define RIT_MASK_H_RIMASK_SHIFT (0U) +#define RIT_MASK_H_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK) + +/*! @name COUNTER_H - Counter MSB register */ +#define RIT_COUNTER_H_RICOUNTER_MASK (0xFFFFU) +#define RIT_COUNTER_H_RICOUNTER_SHIFT (0U) +#define RIT_COUNTER_H_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK) + + +/*! + * @} + */ /* end of group RIT_Register_Masks */ + + +/* RIT - Peripheral instance base addresses */ +/** Peripheral RIT base address */ +#define RIT_BASE (0x4002D000u) +/** Peripheral RIT base pointer */ +#define RIT ((RIT_Type *)RIT_BASE) +/** Array initializer of RIT peripheral base addresses */ +#define RIT_BASE_ADDRS { RIT_BASE } +/** Array initializer of RIT peripheral base pointers */ +#define RIT_BASE_PTRS { RIT } +/** Interrupt vectors for the RIT peripheral type */ +#define RIT_IRQS { RIT_IRQn } + +/*! + * @} + */ /* end of group RIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ + uint8_t RESERVED_0[48]; + __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) + +/*! @name MATCH - RTC match register */ +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) + +/*! @name COUNT - RTC counter register */ +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) + +/*! @name WAKE - High-resolution/wake-up timer control register */ +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) + +/*! @name GPREG - General Purpose register */ +#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) +#define RTC_GPREG_GPDATA_SHIFT (0U) +#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) + +/* The count of RTC_GPREG */ +#define RTC_GPREG_COUNT (8U) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE (0x4002C000u) +/** Peripheral RTC base pointer */ +#define RTC ((RTC_Type *)RTC_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + uint8_t RESERVED_0[40]; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_2[216]; + union { /* offset: 0x200 */ + __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_3[216]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EVENT[10]; + uint8_t RESERVED_4[432]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[10]; +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) +#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) +#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) +#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) + +/*! @name CTRL - SCT control register */ +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) + +/*! @name LIMIT - SCT limit event select register */ +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) + +/*! @name HALT - SCT halt event select register */ +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) + +/*! @name STOP - SCT stop event select register */ +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) + +/*! @name START - SCT start event select register */ +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) + +/*! @name COUNT - SCT counter register */ +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) + +/*! @name STATE - SCT state register */ +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) + +/*! @name INPUT - SCT input register */ +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) + +/*! @name REGMODE - SCT match/capture mode register */ +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) + +/*! @name OUTPUT - SCT output register */ +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) + +/*! @name RES - SCT conflict resolution register */ +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) + +/*! @name DMA0REQUEST - SCT DMA request 0 register */ +#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) +#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) +#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) +#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) +#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) +#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) +#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) +#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) +#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) + +/*! @name DMA1REQUEST - SCT DMA request 1 register */ +#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) +#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) +#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) +#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) +#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) +#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) +#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) +#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) +#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) + +/*! @name EVEN - SCT event interrupt enable register */ +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) + +/*! @name EVFLAG - SCT event flag register */ +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) + +/*! @name CONEN - SCT conflict interrupt enable register */ +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) + +/*! @name CONFLAG - SCT conflict flag register */ +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) + +/*! @name SCTCAP - SCT capture register of capture channel */ +#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) +#define SCT_SCTCAP_CAPn_L_SHIFT (0U) +#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) +#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAP_CAPn_H_SHIFT (16U) +#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) + +/* The count of SCT_SCTCAP */ +#define SCT_SCTCAP_COUNT (10U) + +/*! @name SCTMATCH - SCT match value register of match channels */ +#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) +#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) +#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) +#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) + +/* The count of SCT_SCTMATCH */ +#define SCT_SCTMATCH_COUNT (10U) + +/*! @name SCTCAPCTRL - SCT capture control register */ +#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) +#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) +#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) +#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) + +/* The count of SCT_SCTCAPCTRL */ +#define SCT_SCTCAPCTRL_COUNT (10U) + +/*! @name SCTMATCHREL - SCT match reload value register */ +#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) +#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) +#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) +#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) + +/* The count of SCT_SCTMATCHREL */ +#define SCT_SCTMATCHREL_COUNT (10U) + +/*! @name EVENT_STATE - SCT event state register 0 */ +#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) +#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) + +/* The count of SCT_EVENT_STATE */ +#define SCT_EVENT_STATE_COUNT (10U) + +/*! @name EVENT_CTRL - SCT event control register 0 */ +#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) +#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) +#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) +#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) +#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) +#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) +#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) +#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) +#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) +#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) +#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) +#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) +#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) +#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) +#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) +#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) +#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) +#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) +#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) +#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) +#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) +#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) + +/* The count of SCT_EVENT_CTRL */ +#define SCT_EVENT_CTRL_COUNT (10U) + +/*! @name OUT_SET - SCT output 0 set register */ +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (10U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (10U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +/** Peripheral SCT0 base address */ +#define SCT0_BASE (0x40085000u) +/** Peripheral SCT0 base pointer */ +#define SCT0 ((SCT_Type *)SCT0_BASE) +/** Array initializer of SCT peripheral base addresses */ +#define SCT_BASE_ADDRS { SCT0_BASE } +/** Array initializer of SCT peripheral base pointers */ +#define SCT_BASE_PTRS { SCT0 } +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer + * @{ + */ + +/** SDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ + __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ + __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ + __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ + __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ + __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ + __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ + __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ + __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ + __IO uint32_t CMD; /**< Command register, offset: 0x2C */ + __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ + __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ + __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ + __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ + __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ + __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ + __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ + __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ + __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ + uint8_t RESERVED_2[16]; + __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ + uint8_t RESERVED_3[4]; + __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ + __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ + __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ + __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ + __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ + __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ + __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ + uint8_t RESERVED_4[100]; + __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ + __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ + uint8_t RESERVED_5[248]; + __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ +} SDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDIF_Register_Masks SDIF Register Masks + * @{ + */ + +/*! @name CTRL - Control register */ +#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) +#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) +#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) +#define SDIF_CTRL_FIFO_RESET_MASK (0x2U) +#define SDIF_CTRL_FIFO_RESET_SHIFT (1U) +#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) +#define SDIF_CTRL_DMA_RESET_MASK (0x4U) +#define SDIF_CTRL_DMA_RESET_SHIFT (2U) +#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) +#define SDIF_CTRL_INT_ENABLE_MASK (0x10U) +#define SDIF_CTRL_INT_ENABLE_SHIFT (4U) +#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) +#define SDIF_CTRL_READ_WAIT_MASK (0x40U) +#define SDIF_CTRL_READ_WAIT_SHIFT (6U) +#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) +#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) +#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) +#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) +#define SDIF_CTRL_SEND_CCSD_MASK (0x200U) +#define SDIF_CTRL_SEND_CCSD_SHIFT (9U) +#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) +#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) +#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) +#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) +#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) +#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) +#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) +#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) +#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) +#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) + +/*! @name PWREN - Power Enable register */ +#define SDIF_PWREN_POWER_ENABLE_MASK (0x1U) +#define SDIF_PWREN_POWER_ENABLE_SHIFT (0U) +#define SDIF_PWREN_POWER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK) + +/*! @name CLKDIV - Clock Divider register */ +#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) +#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) + +/*! @name CLKENA - Clock Enable register */ +#define SDIF_CLKENA_CCLK_ENABLE_MASK (0x1U) +#define SDIF_CLKENA_CCLK_ENABLE_SHIFT (0U) +#define SDIF_CLKENA_CCLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK) +#define SDIF_CLKENA_CCLK_LOW_POWER_MASK (0x10000U) +#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT (16U) +#define SDIF_CLKENA_CCLK_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK) + +/*! @name TMOUT - Time-out register */ +#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) +#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) +#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) +#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) +#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) + +/*! @name CTYPE - Card Type register */ +#define SDIF_CTYPE_CARD_WIDTH0_MASK (0x1U) +#define SDIF_CTYPE_CARD_WIDTH0_SHIFT (0U) +#define SDIF_CTYPE_CARD_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK) +#define SDIF_CTYPE_CARD_WIDTH1_MASK (0x10000U) +#define SDIF_CTYPE_CARD_WIDTH1_SHIFT (16U) +#define SDIF_CTYPE_CARD_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK) + +/*! @name BLKSIZ - Block Size register */ +#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) +#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) + +/*! @name BYTCNT - Byte Count register */ +#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) +#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) + +/*! @name INTMASK - Interrupt Mask register */ +#define SDIF_INTMASK_CDET_MASK (0x1U) +#define SDIF_INTMASK_CDET_SHIFT (0U) +#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) +#define SDIF_INTMASK_RE_MASK (0x2U) +#define SDIF_INTMASK_RE_SHIFT (1U) +#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) +#define SDIF_INTMASK_CDONE_MASK (0x4U) +#define SDIF_INTMASK_CDONE_SHIFT (2U) +#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) +#define SDIF_INTMASK_DTO_MASK (0x8U) +#define SDIF_INTMASK_DTO_SHIFT (3U) +#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) +#define SDIF_INTMASK_TXDR_MASK (0x10U) +#define SDIF_INTMASK_TXDR_SHIFT (4U) +#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) +#define SDIF_INTMASK_RXDR_MASK (0x20U) +#define SDIF_INTMASK_RXDR_SHIFT (5U) +#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) +#define SDIF_INTMASK_RCRC_MASK (0x40U) +#define SDIF_INTMASK_RCRC_SHIFT (6U) +#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) +#define SDIF_INTMASK_DCRC_MASK (0x80U) +#define SDIF_INTMASK_DCRC_SHIFT (7U) +#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) +#define SDIF_INTMASK_RTO_MASK (0x100U) +#define SDIF_INTMASK_RTO_SHIFT (8U) +#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) +#define SDIF_INTMASK_DRTO_MASK (0x200U) +#define SDIF_INTMASK_DRTO_SHIFT (9U) +#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) +#define SDIF_INTMASK_HTO_MASK (0x400U) +#define SDIF_INTMASK_HTO_SHIFT (10U) +#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) +#define SDIF_INTMASK_FRUN_MASK (0x800U) +#define SDIF_INTMASK_FRUN_SHIFT (11U) +#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) +#define SDIF_INTMASK_HLE_MASK (0x1000U) +#define SDIF_INTMASK_HLE_SHIFT (12U) +#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) +#define SDIF_INTMASK_SBE_MASK (0x2000U) +#define SDIF_INTMASK_SBE_SHIFT (13U) +#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) +#define SDIF_INTMASK_ACD_MASK (0x4000U) +#define SDIF_INTMASK_ACD_SHIFT (14U) +#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) +#define SDIF_INTMASK_EBE_MASK (0x8000U) +#define SDIF_INTMASK_EBE_SHIFT (15U) +#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) +#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) +#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) +#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) + +/*! @name CMDARG - Command Argument register */ +#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) +#define SDIF_CMDARG_CMD_ARG_SHIFT (0U) +#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) + +/*! @name CMD - Command register */ +#define SDIF_CMD_CMD_INDEX_MASK (0x3FU) +#define SDIF_CMD_CMD_INDEX_SHIFT (0U) +#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) +#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) +#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) +#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) +#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) +#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) +#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) +#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) +#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) +#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) +#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) +#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) +#define SDIF_CMD_READ_WRITE_MASK (0x400U) +#define SDIF_CMD_READ_WRITE_SHIFT (10U) +#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) +#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) +#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) +#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) +#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) +#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) +#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) +#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) +#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) +#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) +#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) +#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) +#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) +#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) +#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) +#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) +#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) +#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) +#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) +#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) +#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) +#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) +#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) +#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) +#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) +#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) +#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) +#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) +#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) +#define SDIF_CMD_BOOT_MODE_SHIFT (27U) +#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) +#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) +#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) +#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) +#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) +#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) +#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) +#define SDIF_CMD_START_CMD_MASK (0x80000000U) +#define SDIF_CMD_START_CMD_SHIFT (31U) +#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) + +/*! @name RESP - Response register */ +#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) +#define SDIF_RESP_RESPONSE_SHIFT (0U) +#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) + +/* The count of SDIF_RESP */ +#define SDIF_RESP_COUNT (4U) + +/*! @name MINTSTS - Masked Interrupt Status register */ +#define SDIF_MINTSTS_CDET_MASK (0x1U) +#define SDIF_MINTSTS_CDET_SHIFT (0U) +#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) +#define SDIF_MINTSTS_RE_MASK (0x2U) +#define SDIF_MINTSTS_RE_SHIFT (1U) +#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) +#define SDIF_MINTSTS_CDONE_MASK (0x4U) +#define SDIF_MINTSTS_CDONE_SHIFT (2U) +#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) +#define SDIF_MINTSTS_DTO_MASK (0x8U) +#define SDIF_MINTSTS_DTO_SHIFT (3U) +#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) +#define SDIF_MINTSTS_TXDR_MASK (0x10U) +#define SDIF_MINTSTS_TXDR_SHIFT (4U) +#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) +#define SDIF_MINTSTS_RXDR_MASK (0x20U) +#define SDIF_MINTSTS_RXDR_SHIFT (5U) +#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) +#define SDIF_MINTSTS_RCRC_MASK (0x40U) +#define SDIF_MINTSTS_RCRC_SHIFT (6U) +#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) +#define SDIF_MINTSTS_DCRC_MASK (0x80U) +#define SDIF_MINTSTS_DCRC_SHIFT (7U) +#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) +#define SDIF_MINTSTS_RTO_MASK (0x100U) +#define SDIF_MINTSTS_RTO_SHIFT (8U) +#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) +#define SDIF_MINTSTS_DRTO_MASK (0x200U) +#define SDIF_MINTSTS_DRTO_SHIFT (9U) +#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) +#define SDIF_MINTSTS_HTO_MASK (0x400U) +#define SDIF_MINTSTS_HTO_SHIFT (10U) +#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) +#define SDIF_MINTSTS_FRUN_MASK (0x800U) +#define SDIF_MINTSTS_FRUN_SHIFT (11U) +#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) +#define SDIF_MINTSTS_HLE_MASK (0x1000U) +#define SDIF_MINTSTS_HLE_SHIFT (12U) +#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) +#define SDIF_MINTSTS_SBE_MASK (0x2000U) +#define SDIF_MINTSTS_SBE_SHIFT (13U) +#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) +#define SDIF_MINTSTS_ACD_MASK (0x4000U) +#define SDIF_MINTSTS_ACD_SHIFT (14U) +#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) +#define SDIF_MINTSTS_EBE_MASK (0x8000U) +#define SDIF_MINTSTS_EBE_SHIFT (15U) +#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) +#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) +#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) + +/*! @name RINTSTS - Raw Interrupt Status register */ +#define SDIF_RINTSTS_CDET_MASK (0x1U) +#define SDIF_RINTSTS_CDET_SHIFT (0U) +#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) +#define SDIF_RINTSTS_RE_MASK (0x2U) +#define SDIF_RINTSTS_RE_SHIFT (1U) +#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) +#define SDIF_RINTSTS_CDONE_MASK (0x4U) +#define SDIF_RINTSTS_CDONE_SHIFT (2U) +#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) +#define SDIF_RINTSTS_DTO_MASK (0x8U) +#define SDIF_RINTSTS_DTO_SHIFT (3U) +#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) +#define SDIF_RINTSTS_TXDR_MASK (0x10U) +#define SDIF_RINTSTS_TXDR_SHIFT (4U) +#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) +#define SDIF_RINTSTS_RXDR_MASK (0x20U) +#define SDIF_RINTSTS_RXDR_SHIFT (5U) +#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) +#define SDIF_RINTSTS_RCRC_MASK (0x40U) +#define SDIF_RINTSTS_RCRC_SHIFT (6U) +#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) +#define SDIF_RINTSTS_DCRC_MASK (0x80U) +#define SDIF_RINTSTS_DCRC_SHIFT (7U) +#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) +#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) +#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) +#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) +#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) +#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) +#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) +#define SDIF_RINTSTS_HTO_MASK (0x400U) +#define SDIF_RINTSTS_HTO_SHIFT (10U) +#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) +#define SDIF_RINTSTS_FRUN_MASK (0x800U) +#define SDIF_RINTSTS_FRUN_SHIFT (11U) +#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) +#define SDIF_RINTSTS_HLE_MASK (0x1000U) +#define SDIF_RINTSTS_HLE_SHIFT (12U) +#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) +#define SDIF_RINTSTS_SBE_MASK (0x2000U) +#define SDIF_RINTSTS_SBE_SHIFT (13U) +#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) +#define SDIF_RINTSTS_ACD_MASK (0x4000U) +#define SDIF_RINTSTS_ACD_SHIFT (14U) +#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) +#define SDIF_RINTSTS_EBE_MASK (0x8000U) +#define SDIF_RINTSTS_EBE_SHIFT (15U) +#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) +#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) +#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) +#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) + +/*! @name STATUS - Status register */ +#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) +#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) +#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) +#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) +#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) +#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) +#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) +#define SDIF_STATUS_FIFO_FULL_MASK (0x8U) +#define SDIF_STATUS_FIFO_FULL_SHIFT (3U) +#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) +#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) +#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) +#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) +#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) +#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) +#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) +#define SDIF_STATUS_DATA_BUSY_MASK (0x200U) +#define SDIF_STATUS_DATA_BUSY_SHIFT (9U) +#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) +#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) +#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) +#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) +#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) +#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) +#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) +#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) +#define SDIF_STATUS_DMA_ACK_SHIFT (30U) +#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) +#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) +#define SDIF_STATUS_DMA_REQ_SHIFT (31U) +#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) + +/*! @name FIFOTH - FIFO Threshold Watermark register */ +#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) +#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) +#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) +#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) +#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) +#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) +#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) +#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) +#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) + +/*! @name CDETECT - Card Detect register */ +#define SDIF_CDETECT_CARD_DETECT_MASK (0x1U) +#define SDIF_CDETECT_CARD_DETECT_SHIFT (0U) +#define SDIF_CDETECT_CARD_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK) + +/*! @name WRTPRT - Write Protect register */ +#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) +#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) +#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) + +/*! @name TCBCNT - Transferred CIU Card Byte Count register */ +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) + +/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) + +/*! @name DEBNCE - Debounce Count register */ +#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) +#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) + +/*! @name RST_N - Hardware Reset */ +#define SDIF_RST_N_CARD_RESET_MASK (0x1U) +#define SDIF_RST_N_CARD_RESET_SHIFT (0U) +#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) + +/*! @name BMOD - Bus Mode register */ +#define SDIF_BMOD_SWR_MASK (0x1U) +#define SDIF_BMOD_SWR_SHIFT (0U) +#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) +#define SDIF_BMOD_FB_MASK (0x2U) +#define SDIF_BMOD_FB_SHIFT (1U) +#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) +#define SDIF_BMOD_DSL_MASK (0x7CU) +#define SDIF_BMOD_DSL_SHIFT (2U) +#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) +#define SDIF_BMOD_DE_MASK (0x80U) +#define SDIF_BMOD_DE_SHIFT (7U) +#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) +#define SDIF_BMOD_PBL_MASK (0x700U) +#define SDIF_BMOD_PBL_SHIFT (8U) +#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) + +/*! @name PLDMND - Poll Demand register */ +#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) +#define SDIF_PLDMND_PD_SHIFT (0U) +#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) + +/*! @name DBADDR - Descriptor List Base Address register */ +#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) +#define SDIF_DBADDR_SDL_SHIFT (0U) +#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) + +/*! @name IDSTS - Internal DMAC Status register */ +#define SDIF_IDSTS_TI_MASK (0x1U) +#define SDIF_IDSTS_TI_SHIFT (0U) +#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) +#define SDIF_IDSTS_RI_MASK (0x2U) +#define SDIF_IDSTS_RI_SHIFT (1U) +#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) +#define SDIF_IDSTS_FBE_MASK (0x4U) +#define SDIF_IDSTS_FBE_SHIFT (2U) +#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) +#define SDIF_IDSTS_DU_MASK (0x10U) +#define SDIF_IDSTS_DU_SHIFT (4U) +#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) +#define SDIF_IDSTS_CES_MASK (0x20U) +#define SDIF_IDSTS_CES_SHIFT (5U) +#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) +#define SDIF_IDSTS_NIS_MASK (0x100U) +#define SDIF_IDSTS_NIS_SHIFT (8U) +#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) +#define SDIF_IDSTS_AIS_MASK (0x200U) +#define SDIF_IDSTS_AIS_SHIFT (9U) +#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) +#define SDIF_IDSTS_EB_MASK (0x1C00U) +#define SDIF_IDSTS_EB_SHIFT (10U) +#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) +#define SDIF_IDSTS_FSM_MASK (0x1E000U) +#define SDIF_IDSTS_FSM_SHIFT (13U) +#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) + +/*! @name IDINTEN - Internal DMAC Interrupt Enable register */ +#define SDIF_IDINTEN_TI_MASK (0x1U) +#define SDIF_IDINTEN_TI_SHIFT (0U) +#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) +#define SDIF_IDINTEN_RI_MASK (0x2U) +#define SDIF_IDINTEN_RI_SHIFT (1U) +#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) +#define SDIF_IDINTEN_FBE_MASK (0x4U) +#define SDIF_IDINTEN_FBE_SHIFT (2U) +#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) +#define SDIF_IDINTEN_DU_MASK (0x10U) +#define SDIF_IDINTEN_DU_SHIFT (4U) +#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) +#define SDIF_IDINTEN_CES_MASK (0x20U) +#define SDIF_IDINTEN_CES_SHIFT (5U) +#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) +#define SDIF_IDINTEN_NIS_MASK (0x100U) +#define SDIF_IDINTEN_NIS_SHIFT (8U) +#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) +#define SDIF_IDINTEN_AIS_MASK (0x200U) +#define SDIF_IDINTEN_AIS_SHIFT (9U) +#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) + +/*! @name DSCADDR - Current Host Descriptor Address register */ +#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) +#define SDIF_DSCADDR_HDA_SHIFT (0U) +#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) + +/*! @name BUFADDR - Current Buffer Descriptor Address register */ +#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) +#define SDIF_BUFADDR_HBA_SHIFT (0U) +#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) + +/*! @name CARDTHRCTL - Card Threshold Control */ +#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) +#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) +#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) +#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) +#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) + +/*! @name BACKENDPWR - Power control */ +#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) +#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) +#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) + +/*! @name FIFO - SDIF FIFO */ +#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) +#define SDIF_FIFO_DATA_SHIFT (0U) +#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) + +/* The count of SDIF_FIFO */ +#define SDIF_FIFO_COUNT (64U) + + +/*! + * @} + */ /* end of group SDIF_Register_Masks */ + + +/* SDIF - Peripheral instance base addresses */ +/** Peripheral SDIF base address */ +#define SDIF_BASE (0x4009B000u) +/** Peripheral SDIF base pointer */ +#define SDIF ((SDIF_Type *)SDIF_BASE) +/** Array initializer of SDIF peripheral base addresses */ +#define SDIF_BASE_ADDRS { SDIF_BASE } +/** Array initializer of SDIF peripheral base pointers */ +#define SDIF_BASE_PTRS { SDIF } +/** Interrupt vectors for the SDIF peripheral type */ +#define SDIF_IRQS { SDIO_IRQn } + +/*! + * @} + */ /* end of group SDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SHA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SHA_Peripheral_Access_Layer SHA Peripheral Access Layer + * @{ + */ + +/** SHA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ + __IO uint32_t STATUS; /**< Status register, offset: 0x4 */ + __IO uint32_t INTENSET; /**< Interrupt Enable register, offset: 0x8 */ + __IO uint32_t INTENCLR; /**< Interrupt Clear register, offset: 0xC */ + __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ + __IO uint32_t MEMADDR; /**< Memory Address register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __IO uint32_t INDATA; /**< Input Data register, offset: 0x20 */ + __IO uint32_t ALIAS[7]; /**< Alias register, array offset: 0x24, array step: 0x4 */ + __I uint32_t DIGEST[8]; /**< Digest register, array offset: 0x40, array step: 0x4 */ +} SHA_Type; + +/* ---------------------------------------------------------------------------- + -- SHA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SHA_Register_Masks SHA Register Masks + * @{ + */ + +/*! @name CTRL - Control register */ +#define SHA_CTRL_MODE_MASK (0x3U) +#define SHA_CTRL_MODE_SHIFT (0U) +#define SHA_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_MODE_SHIFT)) & SHA_CTRL_MODE_MASK) +#define SHA_CTRL_NEW_MASK (0x10U) +#define SHA_CTRL_NEW_SHIFT (4U) +#define SHA_CTRL_NEW(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_NEW_SHIFT)) & SHA_CTRL_NEW_MASK) +#define SHA_CTRL_DMA_MASK (0x100U) +#define SHA_CTRL_DMA_SHIFT (8U) +#define SHA_CTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_DMA_SHIFT)) & SHA_CTRL_DMA_MASK) + +/*! @name STATUS - Status register */ +#define SHA_STATUS_WAITING_MASK (0x1U) +#define SHA_STATUS_WAITING_SHIFT (0U) +#define SHA_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_WAITING_SHIFT)) & SHA_STATUS_WAITING_MASK) +#define SHA_STATUS_DIGEST_MASK (0x2U) +#define SHA_STATUS_DIGEST_SHIFT (1U) +#define SHA_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_DIGEST_SHIFT)) & SHA_STATUS_DIGEST_MASK) +#define SHA_STATUS_ERROR_MASK (0x4U) +#define SHA_STATUS_ERROR_SHIFT (2U) +#define SHA_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_ERROR_SHIFT)) & SHA_STATUS_ERROR_MASK) + +/*! @name INTENSET - Interrupt Enable register */ +#define SHA_INTENSET_WAITING_MASK (0x1U) +#define SHA_INTENSET_WAITING_SHIFT (0U) +#define SHA_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_WAITING_SHIFT)) & SHA_INTENSET_WAITING_MASK) +#define SHA_INTENSET_DIGEST_MASK (0x2U) +#define SHA_INTENSET_DIGEST_SHIFT (1U) +#define SHA_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_DIGEST_SHIFT)) & SHA_INTENSET_DIGEST_MASK) +#define SHA_INTENSET_ERROR_MASK (0x4U) +#define SHA_INTENSET_ERROR_SHIFT (2U) +#define SHA_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_ERROR_SHIFT)) & SHA_INTENSET_ERROR_MASK) + +/*! @name INTENCLR - Interrupt Clear register */ +#define SHA_INTENCLR_WAITING_MASK (0x1U) +#define SHA_INTENCLR_WAITING_SHIFT (0U) +#define SHA_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_WAITING_SHIFT)) & SHA_INTENCLR_WAITING_MASK) +#define SHA_INTENCLR_DIGEST_MASK (0x2U) +#define SHA_INTENCLR_DIGEST_SHIFT (1U) +#define SHA_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_DIGEST_SHIFT)) & SHA_INTENCLR_DIGEST_MASK) +#define SHA_INTENCLR_ERROR_MASK (0x4U) +#define SHA_INTENCLR_ERROR_SHIFT (2U) +#define SHA_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_ERROR_SHIFT)) & SHA_INTENCLR_ERROR_MASK) + +/*! @name MEMCTRL - Memory Control register */ +#define SHA_MEMCTRL_MASTER_MASK (0x1U) +#define SHA_MEMCTRL_MASTER_SHIFT (0U) +#define SHA_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_MASTER_SHIFT)) & SHA_MEMCTRL_MASTER_MASK) +#define SHA_MEMCTRL_COUNT_MASK (0x7FF0000U) +#define SHA_MEMCTRL_COUNT_SHIFT (16U) +#define SHA_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_COUNT_SHIFT)) & SHA_MEMCTRL_COUNT_MASK) + +/*! @name MEMADDR - Memory Address register */ +#define SHA_MEMADDR_BASEADDR_MASK (0xFFFFFFFFU) +#define SHA_MEMADDR_BASEADDR_SHIFT (0U) +#define SHA_MEMADDR_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMADDR_BASEADDR_SHIFT)) & SHA_MEMADDR_BASEADDR_MASK) + +/*! @name INDATA - Input Data register */ +#define SHA_INDATA_DATA_MASK (0xFFFFFFFFU) +#define SHA_INDATA_DATA_SHIFT (0U) +#define SHA_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_INDATA_DATA_SHIFT)) & SHA_INDATA_DATA_MASK) + +/*! @name ALIAS - Alias register */ +#define SHA_ALIAS_DATA_MASK (0xFFFFFFFFU) +#define SHA_ALIAS_DATA_SHIFT (0U) +#define SHA_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_ALIAS_DATA_SHIFT)) & SHA_ALIAS_DATA_MASK) + +/* The count of SHA_ALIAS */ +#define SHA_ALIAS_COUNT (7U) + +/*! @name DIGEST - Digest register */ +#define SHA_DIGEST_DIGEST_MASK (0xFFFFFFFFU) +#define SHA_DIGEST_DIGEST_SHIFT (0U) +#define SHA_DIGEST_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_DIGEST_DIGEST_SHIFT)) & SHA_DIGEST_DIGEST_MASK) + +/* The count of SHA_DIGEST */ +#define SHA_DIGEST_COUNT (8U) + + +/*! + * @} + */ /* end of group SHA_Register_Masks */ + + +/* SHA - Peripheral instance base addresses */ +/** Peripheral SHA0 base address */ +#define SHA0_BASE (0x400A4000u) +/** Peripheral SHA0 base pointer */ +#define SHA0 ((SHA_Type *)SHA0_BASE) +/** Array initializer of SHA peripheral base addresses */ +#define SHA_BASE_ADDRS { SHA0_BASE } +/** Array initializer of SHA peripheral base pointers */ +#define SHA_BASE_PTRS { SHA0 } + +/*! + * @} + */ /* end of group SHA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SMARTCARD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer + * @{ + */ + +/** SMARTCARD - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + __IO uint32_t DLL; /**< Divisor Latch LSB, offset: 0x0 */ + __I uint32_t RBR; /**< Receiver Buffer Register, offset: 0x0 */ + __O uint32_t THR; /**< Transmit Holding Register, offset: 0x0 */ + }; + union { /* offset: 0x4 */ + __IO uint32_t DLM; /**< Divisor Latch MSB, offset: 0x4 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */ + __I uint32_t IIR; /**< Interrupt ID Register, offset: 0x8 */ + }; + __IO uint32_t LCR; /**< Line Control Register, offset: 0xC */ + uint8_t RESERVED_0[4]; + __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SCR; /**< Scratch Pad Register, offset: 0x1C */ + uint8_t RESERVED_2[12]; + __IO uint32_t OSR; /**< Oversampling register, offset: 0x2C */ + uint8_t RESERVED_3[24]; + __IO uint32_t SCICTRL; /**< Smart Card Interface control register, offset: 0x48 */ +} SMARTCARD_Type; + +/* ---------------------------------------------------------------------------- + -- SMARTCARD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks + * @{ + */ + +/*! @name DLL - Divisor Latch LSB */ +#define SMARTCARD_DLL_DLLSB_MASK (0xFFU) +#define SMARTCARD_DLL_DLLSB_SHIFT (0U) +#define SMARTCARD_DLL_DLLSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK) + +/*! @name RBR - Receiver Buffer Register */ +#define SMARTCARD_RBR_RBR_MASK (0xFFU) +#define SMARTCARD_RBR_RBR_SHIFT (0U) +#define SMARTCARD_RBR_RBR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK) + +/*! @name THR - Transmit Holding Register */ +#define SMARTCARD_THR_THR_MASK (0xFFU) +#define SMARTCARD_THR_THR_SHIFT (0U) +#define SMARTCARD_THR_THR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK) + +/*! @name DLM - Divisor Latch MSB */ +#define SMARTCARD_DLM_DLMSB_MASK (0xFFU) +#define SMARTCARD_DLM_DLMSB_SHIFT (0U) +#define SMARTCARD_DLM_DLMSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK) + +/*! @name IER - Interrupt Enable Register */ +#define SMARTCARD_IER_RBRIE_MASK (0x1U) +#define SMARTCARD_IER_RBRIE_SHIFT (0U) +#define SMARTCARD_IER_RBRIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK) +#define SMARTCARD_IER_THREIE_MASK (0x2U) +#define SMARTCARD_IER_THREIE_SHIFT (1U) +#define SMARTCARD_IER_THREIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK) +#define SMARTCARD_IER_RXIE_MASK (0x4U) +#define SMARTCARD_IER_RXIE_SHIFT (2U) +#define SMARTCARD_IER_RXIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK) + +/*! @name FCR - FIFO Control Register */ +#define SMARTCARD_FCR_FIFOEN_MASK (0x1U) +#define SMARTCARD_FCR_FIFOEN_SHIFT (0U) +#define SMARTCARD_FCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK) +#define SMARTCARD_FCR_RXFIFORES_MASK (0x2U) +#define SMARTCARD_FCR_RXFIFORES_SHIFT (1U) +#define SMARTCARD_FCR_RXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK) +#define SMARTCARD_FCR_TXFIFORES_MASK (0x4U) +#define SMARTCARD_FCR_TXFIFORES_SHIFT (2U) +#define SMARTCARD_FCR_TXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK) +#define SMARTCARD_FCR_DMAMODE_MASK (0x8U) +#define SMARTCARD_FCR_DMAMODE_SHIFT (3U) +#define SMARTCARD_FCR_DMAMODE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK) +#define SMARTCARD_FCR_RXTRIGLVL_MASK (0xC0U) +#define SMARTCARD_FCR_RXTRIGLVL_SHIFT (6U) +#define SMARTCARD_FCR_RXTRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK) + +/*! @name IIR - Interrupt ID Register */ +#define SMARTCARD_IIR_INTSTATUS_MASK (0x1U) +#define SMARTCARD_IIR_INTSTATUS_SHIFT (0U) +#define SMARTCARD_IIR_INTSTATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK) +#define SMARTCARD_IIR_INTID_MASK (0xEU) +#define SMARTCARD_IIR_INTID_SHIFT (1U) +#define SMARTCARD_IIR_INTID(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK) +#define SMARTCARD_IIR_FIFOENABLE_MASK (0xC0U) +#define SMARTCARD_IIR_FIFOENABLE_SHIFT (6U) +#define SMARTCARD_IIR_FIFOENABLE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK) + +/*! @name LCR - Line Control Register */ +#define SMARTCARD_LCR_WLS_MASK (0x3U) +#define SMARTCARD_LCR_WLS_SHIFT (0U) +#define SMARTCARD_LCR_WLS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK) +#define SMARTCARD_LCR_SBS_MASK (0x4U) +#define SMARTCARD_LCR_SBS_SHIFT (2U) +#define SMARTCARD_LCR_SBS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK) +#define SMARTCARD_LCR_PE_MASK (0x8U) +#define SMARTCARD_LCR_PE_SHIFT (3U) +#define SMARTCARD_LCR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK) +#define SMARTCARD_LCR_PS_MASK (0x30U) +#define SMARTCARD_LCR_PS_SHIFT (4U) +#define SMARTCARD_LCR_PS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK) +#define SMARTCARD_LCR_DLAB_MASK (0x80U) +#define SMARTCARD_LCR_DLAB_SHIFT (7U) +#define SMARTCARD_LCR_DLAB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK) + +/*! @name LSR - Line Status Register */ +#define SMARTCARD_LSR_RDR_MASK (0x1U) +#define SMARTCARD_LSR_RDR_SHIFT (0U) +#define SMARTCARD_LSR_RDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK) +#define SMARTCARD_LSR_OE_MASK (0x2U) +#define SMARTCARD_LSR_OE_SHIFT (1U) +#define SMARTCARD_LSR_OE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK) +#define SMARTCARD_LSR_PE_MASK (0x4U) +#define SMARTCARD_LSR_PE_SHIFT (2U) +#define SMARTCARD_LSR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK) +#define SMARTCARD_LSR_FE_MASK (0x8U) +#define SMARTCARD_LSR_FE_SHIFT (3U) +#define SMARTCARD_LSR_FE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK) +#define SMARTCARD_LSR_THRE_MASK (0x20U) +#define SMARTCARD_LSR_THRE_SHIFT (5U) +#define SMARTCARD_LSR_THRE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK) +#define SMARTCARD_LSR_TEMT_MASK (0x40U) +#define SMARTCARD_LSR_TEMT_SHIFT (6U) +#define SMARTCARD_LSR_TEMT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK) +#define SMARTCARD_LSR_RXFE_MASK (0x80U) +#define SMARTCARD_LSR_RXFE_SHIFT (7U) +#define SMARTCARD_LSR_RXFE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK) + +/*! @name SCR - Scratch Pad Register */ +#define SMARTCARD_SCR_PAD_MASK (0xFFU) +#define SMARTCARD_SCR_PAD_SHIFT (0U) +#define SMARTCARD_SCR_PAD(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK) + +/*! @name OSR - Oversampling register */ +#define SMARTCARD_OSR_OSFRAC_MASK (0xEU) +#define SMARTCARD_OSR_OSFRAC_SHIFT (1U) +#define SMARTCARD_OSR_OSFRAC(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK) +#define SMARTCARD_OSR_OSINT_MASK (0xF0U) +#define SMARTCARD_OSR_OSINT_SHIFT (4U) +#define SMARTCARD_OSR_OSINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK) +#define SMARTCARD_OSR_FDINT_MASK (0x7F00U) +#define SMARTCARD_OSR_FDINT_SHIFT (8U) +#define SMARTCARD_OSR_FDINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK) + +/*! @name SCICTRL - Smart Card Interface control register */ +#define SMARTCARD_SCICTRL_SCIEN_MASK (0x1U) +#define SMARTCARD_SCICTRL_SCIEN_SHIFT (0U) +#define SMARTCARD_SCICTRL_SCIEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK) +#define SMARTCARD_SCICTRL_NACKDIS_MASK (0x2U) +#define SMARTCARD_SCICTRL_NACKDIS_SHIFT (1U) +#define SMARTCARD_SCICTRL_NACKDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK) +#define SMARTCARD_SCICTRL_PROTSEL_MASK (0x4U) +#define SMARTCARD_SCICTRL_PROTSEL_SHIFT (2U) +#define SMARTCARD_SCICTRL_PROTSEL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK) +#define SMARTCARD_SCICTRL_TXRETRY_MASK (0xE0U) +#define SMARTCARD_SCICTRL_TXRETRY_SHIFT (5U) +#define SMARTCARD_SCICTRL_TXRETRY(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK) +#define SMARTCARD_SCICTRL_GUARDTIME_MASK (0xFF00U) +#define SMARTCARD_SCICTRL_GUARDTIME_SHIFT (8U) +#define SMARTCARD_SCICTRL_GUARDTIME(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK) + + +/*! + * @} + */ /* end of group SMARTCARD_Register_Masks */ + + +/* SMARTCARD - Peripheral instance base addresses */ +/** Peripheral SMARTCARD0 base address */ +#define SMARTCARD0_BASE (0x40036000u) +/** Peripheral SMARTCARD0 base pointer */ +#define SMARTCARD0 ((SMARTCARD_Type *)SMARTCARD0_BASE) +/** Peripheral SMARTCARD1 base address */ +#define SMARTCARD1_BASE (0x40037000u) +/** Peripheral SMARTCARD1 base pointer */ +#define SMARTCARD1 ((SMARTCARD_Type *)SMARTCARD1_BASE) +/** Array initializer of SMARTCARD peripheral base addresses */ +#define SMARTCARD_BASE_ADDRS { SMARTCARD0_BASE, SMARTCARD1_BASE } +/** Array initializer of SMARTCARD peripheral base pointers */ +#define SMARTCARD_BASE_PTRS { SMARTCARD0, SMARTCARD1 } +/** Interrupt vectors for the SMARTCARD peripheral type */ +#define SMARTCARD_IRQS { SMARTCARD0_IRQn, SMARTCARD1_IRQn } + +/*! + * @} + */ /* end of group SMARTCARD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_7[440]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) + +/*! @name DLY - SPI Delay register */ +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) + +/*! @name DIV - SPI clock Divider */ +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) + +/*! @name INTSTAT - SPI Interrupt Status */ +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +#define SPI_FIFOCFG_POPDBG_MASK (0x40000U) +#define SPI_FIFOCFG_POPDBG_SHIFT (18U) +#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) + +/*! @name FIFOSTAT - FIFO status register. */ +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) + +/*! @name FIFOWR - FIFO write data. */ +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) + +/*! @name FIFORD - FIFO read data. */ +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) + +/*! @name ID - Peripheral identification register. */ +#define SPI_ID_APERTURE_MASK (0xFFU) +#define SPI_ID_APERTURE_SHIFT (0U) +#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) +#define SPI_ID_MINOR_REV_MASK (0xF00U) +#define SPI_ID_MINOR_REV_SHIFT (8U) +#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) +#define SPI_ID_MAJOR_REV_MASK (0xF000U) +#define SPI_ID_MAJOR_REV_SHIFT (12U) +#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) +#define SPI_ID_ID_MASK (0xFFFF0000U) +#define SPI_ID_ID_SHIFT (16U) +#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +/** Peripheral SPI0 base address */ +#define SPI0_BASE (0x40086000u) +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) +/** Peripheral SPI1 base address */ +#define SPI1_BASE (0x40087000u) +/** Peripheral SPI1 base pointer */ +#define SPI1 ((SPI_Type *)SPI1_BASE) +/** Peripheral SPI2 base address */ +#define SPI2_BASE (0x40088000u) +/** Peripheral SPI2 base pointer */ +#define SPI2 ((SPI_Type *)SPI2_BASE) +/** Peripheral SPI3 base address */ +#define SPI3_BASE (0x40089000u) +/** Peripheral SPI3 base pointer */ +#define SPI3 ((SPI_Type *)SPI3_BASE) +/** Peripheral SPI4 base address */ +#define SPI4_BASE (0x4008A000u) +/** Peripheral SPI4 base pointer */ +#define SPI4 ((SPI_Type *)SPI4_BASE) +/** Peripheral SPI5 base address */ +#define SPI5_BASE (0x40096000u) +/** Peripheral SPI5 base pointer */ +#define SPI5 ((SPI_Type *)SPI5_BASE) +/** Peripheral SPI6 base address */ +#define SPI6_BASE (0x40097000u) +/** Peripheral SPI6 base pointer */ +#define SPI6 ((SPI_Type *)SPI6_BASE) +/** Peripheral SPI7 base address */ +#define SPI7_BASE (0x40098000u) +/** Peripheral SPI7 base pointer */ +#define SPI7 ((SPI_Type *)SPI7_BASE) +/** Peripheral SPI8 base address */ +#define SPI8_BASE (0x40099000u) +/** Peripheral SPI8 base pointer */ +#define SPI8 ((SPI_Type *)SPI8_BASE) +/** Peripheral SPI9 base address */ +#define SPI9_BASE (0x4009A000u) +/** Peripheral SPI9 base pointer */ +#define SPI9 ((SPI_Type *)SPI9_BASE) +/** Array initializer of SPI peripheral base addresses */ +#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE } +/** Array initializer of SPI peripheral base pointers */ +#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPIFI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer + * @{ + */ + +/** SPIFI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */ + __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */ + __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */ + __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */ + __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */ + __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */ + __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */ + __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */ +} SPIFI_Type; + +/* ---------------------------------------------------------------------------- + -- SPIFI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPIFI_Register_Masks SPIFI Register Masks + * @{ + */ + +/*! @name CTRL - SPIFI control register */ +#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) +#define SPIFI_CTRL_TIMEOUT_SHIFT (0U) +#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) +#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U) +#define SPIFI_CTRL_CSHIGH_SHIFT (16U) +#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK) +#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U) +#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U) +#define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK) +#define SPIFI_CTRL_INTEN_MASK (0x400000U) +#define SPIFI_CTRL_INTEN_SHIFT (22U) +#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK) +#define SPIFI_CTRL_MODE3_MASK (0x800000U) +#define SPIFI_CTRL_MODE3_SHIFT (23U) +#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK) +#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U) +#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U) +#define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK) +#define SPIFI_CTRL_DUAL_MASK (0x10000000U) +#define SPIFI_CTRL_DUAL_SHIFT (28U) +#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK) +#define SPIFI_CTRL_RFCLK_MASK (0x20000000U) +#define SPIFI_CTRL_RFCLK_SHIFT (29U) +#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK) +#define SPIFI_CTRL_FBCLK_MASK (0x40000000U) +#define SPIFI_CTRL_FBCLK_SHIFT (30U) +#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK) +#define SPIFI_CTRL_DMAEN_MASK (0x80000000U) +#define SPIFI_CTRL_DMAEN_SHIFT (31U) +#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) + +/*! @name CMD - SPIFI command register */ +#define SPIFI_CMD_DATALEN_MASK (0x3FFFU) +#define SPIFI_CMD_DATALEN_SHIFT (0U) +#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) +#define SPIFI_CMD_POLL_MASK (0x4000U) +#define SPIFI_CMD_POLL_SHIFT (14U) +#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK) +#define SPIFI_CMD_DOUT_MASK (0x8000U) +#define SPIFI_CMD_DOUT_SHIFT (15U) +#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK) +#define SPIFI_CMD_INTLEN_MASK (0x70000U) +#define SPIFI_CMD_INTLEN_SHIFT (16U) +#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK) +#define SPIFI_CMD_FIELDFORM_MASK (0x180000U) +#define SPIFI_CMD_FIELDFORM_SHIFT (19U) +#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK) +#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U) +#define SPIFI_CMD_FRAMEFORM_SHIFT (21U) +#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK) +#define SPIFI_CMD_OPCODE_MASK (0xFF000000U) +#define SPIFI_CMD_OPCODE_SHIFT (24U) +#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) + +/*! @name ADDR - SPIFI address register */ +#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) +#define SPIFI_ADDR_ADDRESS_SHIFT (0U) +#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) + +/*! @name IDATA - SPIFI intermediate data register */ +#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) +#define SPIFI_IDATA_IDATA_SHIFT (0U) +#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) + +/*! @name CLIMIT - SPIFI limit register */ +#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) +#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) +#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) + +/*! @name DATA - SPIFI data register */ +#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) +#define SPIFI_DATA_DATA_SHIFT (0U) +#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) + +/*! @name MCMD - SPIFI memory command register */ +#define SPIFI_MCMD_POLL_MASK (0x4000U) +#define SPIFI_MCMD_POLL_SHIFT (14U) +#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) +#define SPIFI_MCMD_DOUT_MASK (0x8000U) +#define SPIFI_MCMD_DOUT_SHIFT (15U) +#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK) +#define SPIFI_MCMD_INTLEN_MASK (0x70000U) +#define SPIFI_MCMD_INTLEN_SHIFT (16U) +#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK) +#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U) +#define SPIFI_MCMD_FIELDFORM_SHIFT (19U) +#define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK) +#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U) +#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U) +#define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK) +#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) +#define SPIFI_MCMD_OPCODE_SHIFT (24U) +#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) + +/*! @name STAT - SPIFI status register */ +#define SPIFI_STAT_MCINIT_MASK (0x1U) +#define SPIFI_STAT_MCINIT_SHIFT (0U) +#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) +#define SPIFI_STAT_CMD_MASK (0x2U) +#define SPIFI_STAT_CMD_SHIFT (1U) +#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK) +#define SPIFI_STAT_RESET_MASK (0x10U) +#define SPIFI_STAT_RESET_SHIFT (4U) +#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK) +#define SPIFI_STAT_INTRQ_MASK (0x20U) +#define SPIFI_STAT_INTRQ_SHIFT (5U) +#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK) + + +/*! + * @} + */ /* end of group SPIFI_Register_Masks */ + + +/* SPIFI - Peripheral instance base addresses */ +/** Peripheral SPIFI0 base address */ +#define SPIFI0_BASE (0x40080000u) +/** Peripheral SPIFI0 base pointer */ +#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE) +/** Array initializer of SPIFI peripheral base addresses */ +#define SPIFI_BASE_ADDRS { SPIFI0_BASE } +/** Array initializer of SPIFI peripheral base pointers */ +#define SPIFI_BASE_PTRS { SPIFI0 } +/** Interrupt vectors for the SPIFI peripheral type */ +#define SPIFI_IRQS { SPIFI0_IRQn } + +/*! + * @} + */ /* end of group SPIFI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ + uint8_t RESERVED_1[44]; + __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ + uint8_t RESERVED_3[112]; + __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ + uint8_t RESERVED_5[40]; + __IO uint32_t PRESETCTRL[3]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_6[20]; + __O uint32_t PRESETCTRLSET[3]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_7[20]; + __O uint32_t PRESETCTRLCLR[3]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_8[164]; + __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t AHBCLKCTRL[3]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[20]; + __O uint32_t AHBCLKCTRLSET[3]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_11[20]; + __O uint32_t AHBCLKCTRLCLR[3]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_12[52]; + __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ + __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ + uint8_t RESERVED_13[4]; + __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ + uint8_t RESERVED_14[4]; + __IO uint32_t AUDPLLCLKSEL; /**< Audio PLL clock source select, offset: 0x298 */ + uint8_t RESERVED_15[4]; + __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */ + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USB0CLKSEL; /**< USB0 clock source select, offset: 0x2A8 */ + __IO uint32_t USB1CLKSEL; /**< USB1 clock source select, offset: 0x2AC */ + __IO uint32_t FCLKSEL[10]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */ + uint8_t RESERVED_16[8]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_17[4]; + __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ + __IO uint32_t DMICCLKSEL; /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */ + __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ + __IO uint32_t LCDCLKSEL; /**< LCD clock source select, offset: 0x2F4 */ + __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ + uint8_t RESERVED_18[4]; + __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ + __IO uint32_t ARMTRACECLKDIV; /**< ARM Trace clock divider, offset: 0x304 */ + __IO uint32_t CAN0CLKDIV; /**< MCAN0 clock divider, offset: 0x308 */ + __IO uint32_t CAN1CLKDIV; /**< MCAN1 clock divider, offset: 0x30C */ + __IO uint32_t SC0CLKDIV; /**< Smartcard0 clock divider, offset: 0x310 */ + __IO uint32_t SC1CLKDIV; /**< Smartcard1 clock divider, offset: 0x314 */ + uint8_t RESERVED_19[104]; + __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + __IO uint32_t FROHFCLKDIV; /**< FROHF clock divider, offset: 0x388 */ + uint8_t RESERVED_20[4]; + __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */ + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USB0CLKDIV; /**< USB0 clock divider, offset: 0x398 */ + __IO uint32_t USB1CLKDIV; /**< USB1 clock divider, offset: 0x39C */ + __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ + uint8_t RESERVED_21[4]; + __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */ + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + __IO uint32_t LCDCLKDIV; /**< LCD clock divider, offset: 0x3B0 */ + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ + __IO uint32_t EMCCLKDIV; /**< EMC clock divider, offset: 0x3B8 */ + __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + uint8_t RESERVED_22[64]; + __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ + uint8_t RESERVED_23[8]; + __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */ + __IO uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */ + uint8_t RESERVED_24[4]; + __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ + uint8_t RESERVED_25[4]; + __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ + __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */ + __IO uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */ + uint8_t RESERVED_26[24]; + __IO uint32_t EMCSYSCTRL; /**< EMC system control, offset: 0x444 */ + __IO uint32_t EMCDLYCTRL; /**< EMC clock delay control, offset: 0x448 */ + __IO uint32_t EMCDLYCAL; /**< EMC delay chain calibration control, offset: 0x44C */ + __IO uint32_t ETHPHYSEL; /**< Ethernet PHY Selection, offset: 0x450 */ + __IO uint32_t ETHSBDCTRL; /**< Ethernet SBD flow control, offset: 0x454 */ + uint8_t RESERVED_27[8]; + __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ + uint8_t RESERVED_28[156]; + __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ + __IO uint32_t SYSOSCCTRL; /**< System oscillator control, offset: 0x504 */ + __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ + __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ + uint8_t RESERVED_29[12]; + __IO uint32_t USBPLLCTRL; /**< USB PLL control, offset: 0x51C */ + __IO uint32_t USBPLLSTAT; /**< USB PLL status, offset: 0x520 */ + uint8_t RESERVED_30[92]; + __IO uint32_t SYSPLLCTRL; /**< System PLL control, offset: 0x580 */ + __IO uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ + __IO uint32_t SYSPLLNDEC; /**< PLL N divider, offset: 0x588 */ + __IO uint32_t SYSPLLPDEC; /**< PLL P divider, offset: 0x58C */ + __IO uint32_t SYSPLLMDEC; /**< System PLL M divider, offset: 0x590 */ + uint8_t RESERVED_31[12]; + __IO uint32_t AUDPLLCTRL; /**< Audio PLL control, offset: 0x5A0 */ + __IO uint32_t AUDPLLSTAT; /**< Audio PLL status, offset: 0x5A4 */ + __IO uint32_t AUDPLLNDEC; /**< Audio PLL N divider, offset: 0x5A8 */ + __IO uint32_t AUDPLLPDEC; /**< Audio PLL P divider, offset: 0x5AC */ + __IO uint32_t AUDPLLMDEC; /**< Audio PLL M divider, offset: 0x5B0 */ + __IO uint32_t AUDPLLFRAC; /**< Audio PLL fractional divider control, offset: 0x5B4 */ + uint8_t RESERVED_32[72]; + __IO uint32_t PDSLEEPCFG[2]; /**< Power configuration register 0, array offset: 0x600, array step: 0x4 */ + uint8_t RESERVED_33[8]; + __IO uint32_t PDRUNCFG[2]; /**< Power configuration register 0, array offset: 0x610, array step: 0x4 */ + uint8_t RESERVED_34[8]; + __IO uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFG0, array offset: 0x620, array step: 0x4 */ + uint8_t RESERVED_35[8]; + __IO uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFG0, array offset: 0x630, array step: 0x4 */ + uint8_t RESERVED_36[72]; + __IO uint32_t STARTER[2]; /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_37[24]; + __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ + uint8_t RESERVED_38[24]; + __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */ + uint8_t RESERVED_39[184]; + __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ + uint8_t RESERVED_40[1664]; + __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */ + uint8_t RESERVED_41[492]; + __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ + __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ + uint8_t RESERVED_42[127044]; + __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name AHBMATPRIO - AHB multilayer matrix priority control */ +#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) +#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) +#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) +#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) +#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) +#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) +#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0x3C0U) +#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (6U) +#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) +#define SYSCON_AHBMATPRIO_PRI_ETH_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT (10U) +#define SYSCON_AHBMATPRIO_PRI_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK) +#define SYSCON_AHBMATPRIO_PRI_LCD_MASK (0x3000U) +#define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT (12U) +#define SYSCON_AHBMATPRIO_PRI_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB0_MASK (0xC000U) +#define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT (14U) +#define SYSCON_AHBMATPRIO_PRI_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB1_MASK (0x30000U) +#define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT (16U) +#define SYSCON_AHBMATPRIO_PRI_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK) +#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0xC0000U) +#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (18U) +#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) +#define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK (0x300000U) +#define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT (20U) +#define SYSCON_AHBMATPRIO_PRI_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK) +#define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK (0xC00000U) +#define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT (22U) +#define SYSCON_AHBMATPRIO_PRI_MCAN2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK) +#define SYSCON_AHBMATPRIO_PRI_SHA_MASK (0x3000000U) +#define SYSCON_AHBMATPRIO_PRI_SHA_SHIFT (24U) +#define SYSCON_AHBMATPRIO_PRI_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA_MASK) + +/*! @name SYSTCKCAL - System tick counter calibration */ +#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) +#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) +#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) +#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) +#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) +#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) +#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) + +/*! @name NMISRC - NMI Source Select */ +#define SYSCON_NMISRC_IRQM4_MASK (0x3FU) +#define SYSCON_NMISRC_IRQM4_SHIFT (0U) +#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) +#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENM4_SHIFT (31U) +#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) + +/*! @name ASYNCAPBCTRL - Asynchronous APB Control */ +#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) +#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) +#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) + +/*! @name PIOPORCAP - POR captured value of port n */ +#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) +#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) +#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) + +/* The count of SYSCON_PIOPORCAP */ +#define SYSCON_PIOPORCAP_COUNT (2U) + +/*! @name PIORESCAP - Reset captured value of port n */ +#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) +#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) +#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) + +/* The count of SYSCON_PIORESCAP */ +#define SYSCON_PIORESCAP_COUNT (2U) + +/*! @name PRESETCTRL - Peripheral reset control n */ +#define SYSCON_PRESETCTRL_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL_MRT_RST_SHIFT (0U) +#define SYSCON_PRESETCTRL_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK) +#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) +#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) +#define SYSCON_PRESETCTRL_LCD_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL_LCD_RST_SHIFT (2U) +#define SYSCON_PRESETCTRL_LCD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK) +#define SYSCON_PRESETCTRL_SDIO_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL_SDIO_RST_SHIFT (3U) +#define SYSCON_PRESETCTRL_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK) +#define SYSCON_PRESETCTRL_USB1H_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL_USB1H_RST_SHIFT (4U) +#define SYSCON_PRESETCTRL_USB1H_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK) +#define SYSCON_PRESETCTRL_USB1D_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL_USB1D_RST_SHIFT (5U) +#define SYSCON_PRESETCTRL_USB1D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK) +#define SYSCON_PRESETCTRL_USB1RAM_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT (6U) +#define SYSCON_PRESETCTRL_USB1RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK) +#define SYSCON_PRESETCTRL_EMC_RESET_MASK (0x80U) +#define SYSCON_PRESETCTRL_EMC_RESET_SHIFT (7U) +#define SYSCON_PRESETCTRL_EMC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK) +#define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) +#define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) +#define SYSCON_PRESETCTRL_MCAN0_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT (7U) +#define SYSCON_PRESETCTRL_MCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK) +#define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) +#define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) +#define SYSCON_PRESETCTRL_ETH_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL_ETH_RST_SHIFT (8U) +#define SYSCON_PRESETCTRL_ETH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK) +#define SYSCON_PRESETCTRL_MCAN1_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT (8U) +#define SYSCON_PRESETCTRL_MCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO4_RST_MASK (0x200U) +#define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT (9U) +#define SYSCON_PRESETCTRL_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK) +#define SYSCON_PRESETCTRL_EEPROM_RST_MASK (0x200U) +#define SYSCON_PRESETCTRL_EEPROM_RST_SHIFT (9U) +#define SYSCON_PRESETCTRL_EEPROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EEPROM_RST_SHIFT)) & SYSCON_PRESETCTRL_EEPROM_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO5_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT (10U) +#define SYSCON_PRESETCTRL_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK) +#define SYSCON_PRESETCTRL_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL_UTICK_RST_SHIFT (10U) +#define SYSCON_PRESETCTRL_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK) +#define SYSCON_PRESETCTRL_SPIFI_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT (10U) +#define SYSCON_PRESETCTRL_SPIFI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK) +#define SYSCON_PRESETCTRL_AES_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_AES_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_AES_RST_SHIFT)) & SYSCON_PRESETCTRL_AES_RST_MASK) +#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) +#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) +#define SYSCON_PRESETCTRL_OTP_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL_OTP_RST_SHIFT (12U) +#define SYSCON_PRESETCTRL_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK) +#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) +#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) +#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) +#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) +#define SYSCON_PRESETCTRL_RNG_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL_RNG_RST_SHIFT (13U) +#define SYSCON_PRESETCTRL_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK) +#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) +#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) +#define SYSCON_PRESETCTRL_FC8_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL_FC8_RST_SHIFT (14U) +#define SYSCON_PRESETCTRL_FC8_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK) +#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) +#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) +#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) +#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) +#define SYSCON_PRESETCTRL_FC9_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL_FC9_RST_SHIFT (15U) +#define SYSCON_PRESETCTRL_FC9_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK) +#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) +#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) +#define SYSCON_PRESETCTRL_USB0HMR_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT (16U) +#define SYSCON_PRESETCTRL_USB0HMR_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO2_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT (16U) +#define SYSCON_PRESETCTRL_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK) +#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) +#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO3_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT (17U) +#define SYSCON_PRESETCTRL_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK) +#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) +#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) +#define SYSCON_PRESETCTRL_USB0HSL_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT (17U) +#define SYSCON_PRESETCTRL_USB0HSL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK) +#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) +#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) +#define SYSCON_PRESETCTRL_SHA_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL_SHA_RST_SHIFT (18U) +#define SYSCON_PRESETCTRL_SHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK) +#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) +#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) +#define SYSCON_PRESETCTRL_DMIC_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL_DMIC_RST_SHIFT (19U) +#define SYSCON_PRESETCTRL_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK) +#define SYSCON_PRESETCTRL_SC0_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL_SC0_RST_SHIFT (19U) +#define SYSCON_PRESETCTRL_SC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK) +#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) +#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) +#define SYSCON_PRESETCTRL_SC1_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL_SC1_RST_SHIFT (20U) +#define SYSCON_PRESETCTRL_SC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK) +#define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) +#define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) +#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) +#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U) +#define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK) +#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) +#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) +#define SYSCON_PRESETCTRL_USB0D_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL_USB0D_RST_SHIFT (25U) +#define SYSCON_PRESETCTRL_USB0D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) +#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) +#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) +#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) +#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) + +/* The count of SYSCON_PRESETCTRL */ +#define SYSCON_PRESETCTRL_COUNT (3U) + +/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ +#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) +#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (3U) + +/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ +#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) +#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (3U) + +/*! @name SYSRSTSTAT - System reset status register */ +#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) +#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) +#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) +#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) +#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) +#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) +#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) +#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) +#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) +#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) +#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) +#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) +#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) +#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) +#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) + +/*! @name AHBCLKCTRL - AHB Clock control n */ +#define SYSCON_AHBCLKCTRL_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL_MRT_SHIFT (0U) +#define SYSCON_AHBCLKCTRL_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK) +#define SYSCON_AHBCLKCTRL_RIT_MASK (0x2U) +#define SYSCON_AHBCLKCTRL_RIT_SHIFT (1U) +#define SYSCON_AHBCLKCTRL_RIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK) +#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) +#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) +#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) +#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) +#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) +#define SYSCON_AHBCLKCTRL_LCD_MASK (0x4U) +#define SYSCON_AHBCLKCTRL_LCD_SHIFT (2U) +#define SYSCON_AHBCLKCTRL_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK) +#define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U) +#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U) +#define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK) +#define SYSCON_AHBCLKCTRL_SDIO_MASK (0x8U) +#define SYSCON_AHBCLKCTRL_SDIO_SHIFT (3U) +#define SYSCON_AHBCLKCTRL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK) +#define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U) +#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U) +#define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK) +#define SYSCON_AHBCLKCTRL_USB1H_MASK (0x10U) +#define SYSCON_AHBCLKCTRL_USB1H_SHIFT (4U) +#define SYSCON_AHBCLKCTRL_USB1H(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK) +#define SYSCON_AHBCLKCTRL_SRAM3_MASK (0x20U) +#define SYSCON_AHBCLKCTRL_SRAM3_SHIFT (5U) +#define SYSCON_AHBCLKCTRL_SRAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK) +#define SYSCON_AHBCLKCTRL_USB1D_MASK (0x20U) +#define SYSCON_AHBCLKCTRL_USB1D_SHIFT (5U) +#define SYSCON_AHBCLKCTRL_USB1D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK) +#define SYSCON_AHBCLKCTRL_USB1RAM_MASK (0x40U) +#define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT (6U) +#define SYSCON_AHBCLKCTRL_USB1RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK) +#define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) +#define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) +#define SYSCON_AHBCLKCTRL_EMC_MASK (0x80U) +#define SYSCON_AHBCLKCTRL_EMC_SHIFT (7U) +#define SYSCON_AHBCLKCTRL_EMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK) +#define SYSCON_AHBCLKCTRL_MCAN0_MASK (0x80U) +#define SYSCON_AHBCLKCTRL_MCAN0_SHIFT (7U) +#define SYSCON_AHBCLKCTRL_MCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK) +#define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) +#define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) +#define SYSCON_AHBCLKCTRL_ETH_MASK (0x100U) +#define SYSCON_AHBCLKCTRL_ETH_SHIFT (8U) +#define SYSCON_AHBCLKCTRL_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK) +#define SYSCON_AHBCLKCTRL_MCAN1_MASK (0x100U) +#define SYSCON_AHBCLKCTRL_MCAN1_SHIFT (8U) +#define SYSCON_AHBCLKCTRL_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK) +#define SYSCON_AHBCLKCTRL_EEPROM_MASK (0x200U) +#define SYSCON_AHBCLKCTRL_EEPROM_SHIFT (9U) +#define SYSCON_AHBCLKCTRL_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EEPROM_SHIFT)) & SYSCON_AHBCLKCTRL_EEPROM_MASK) +#define SYSCON_AHBCLKCTRL_GPIO4_MASK (0x200U) +#define SYSCON_AHBCLKCTRL_GPIO4_SHIFT (9U) +#define SYSCON_AHBCLKCTRL_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK) +#define SYSCON_AHBCLKCTRL_GPIO5_MASK (0x400U) +#define SYSCON_AHBCLKCTRL_GPIO5_SHIFT (10U) +#define SYSCON_AHBCLKCTRL_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK) +#define SYSCON_AHBCLKCTRL_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL_UTICK_SHIFT (10U) +#define SYSCON_AHBCLKCTRL_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK) +#define SYSCON_AHBCLKCTRL_SPIFI_MASK (0x400U) +#define SYSCON_AHBCLKCTRL_SPIFI_SHIFT (10U) +#define SYSCON_AHBCLKCTRL_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK) +#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) +#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) +#define SYSCON_AHBCLKCTRL_AES_MASK (0x800U) +#define SYSCON_AHBCLKCTRL_AES_SHIFT (11U) +#define SYSCON_AHBCLKCTRL_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_AES_SHIFT)) & SYSCON_AHBCLKCTRL_AES_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) +#define SYSCON_AHBCLKCTRL_OTP_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL_OTP_SHIFT (12U) +#define SYSCON_AHBCLKCTRL_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) +#define SYSCON_AHBCLKCTRL_RNG_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_RNG_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK) +#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) +#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT (15U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) +#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) +#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) +#define SYSCON_AHBCLKCTRL_GPIO2_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL_GPIO2_SHIFT (16U) +#define SYSCON_AHBCLKCTRL_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK) +#define SYSCON_AHBCLKCTRL_USB0HMR_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT (16U) +#define SYSCON_AHBCLKCTRL_USB0HMR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) +#define SYSCON_AHBCLKCTRL_GPIO3_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL_GPIO3_SHIFT (17U) +#define SYSCON_AHBCLKCTRL_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK) +#define SYSCON_AHBCLKCTRL_USB0HSL_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT (17U) +#define SYSCON_AHBCLKCTRL_USB0HSL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK) +#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) +#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) +#define SYSCON_AHBCLKCTRL_SHA0_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL_SHA0_SHIFT (18U) +#define SYSCON_AHBCLKCTRL_SHA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA0_SHIFT)) & SYSCON_AHBCLKCTRL_SHA0_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) +#define SYSCON_AHBCLKCTRL_DMIC_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL_DMIC_SHIFT (19U) +#define SYSCON_AHBCLKCTRL_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK) +#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) +#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) +#define SYSCON_AHBCLKCTRL_SC0_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL_SC0_SHIFT (19U) +#define SYSCON_AHBCLKCTRL_SC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK) +#define SYSCON_AHBCLKCTRL_SC1_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL_SC1_SHIFT (20U) +#define SYSCON_AHBCLKCTRL_SC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK) +#define SYSCON_AHBCLKCTRL_DMA_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL_DMA_SHIFT (20U) +#define SYSCON_AHBCLKCTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK) +#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) +#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) +#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) +#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U) +#define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK) +#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) +#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) +#define SYSCON_AHBCLKCTRL_USB0D_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL_USB0D_SHIFT (25U) +#define SYSCON_AHBCLKCTRL_USB0D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) +#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) +#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) +#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) +#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) + +/* The count of SYSCON_AHBCLKCTRL */ +#define SYSCON_AHBCLKCTRL_COUNT (3U) + +/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ +#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) +#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (3U) + +/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (3U) + +/*! @name MAINCLKSELA - Main clock source select A */ +#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) + +/*! @name MAINCLKSELB - Main clock source select B */ +#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) + +/*! @name CLKOUTSELA - CLKOUT clock source select A */ +#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) +#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) +#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) + +/*! @name SYSPLLCLKSEL - PLL clock source select */ +#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) +#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) + +/*! @name AUDPLLCLKSEL - Audio PLL clock source select */ +#define SYSCON_AUDPLLCLKSEL_SEL_MASK (0x7U) +#define SYSCON_AUDPLLCLKSEL_SEL_SHIFT (0U) +#define SYSCON_AUDPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK) + +/*! @name SPIFICLKSEL - SPIFI clock source select */ +#define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) +#define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) +#define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) + +/*! @name ADCCLKSEL - ADC clock source select */ +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) + +/*! @name USB0CLKSEL - USB0 clock source select */ +#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) +#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) + +/*! @name USB1CLKSEL - USB1 clock source select */ +#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U) +#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK) + +/*! @name FCLKSEL - Flexcomm 0 clock source select */ +#define SYSCON_FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FCLKSEL_SEL_SHIFT (0U) +#define SYSCON_FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK) + +/* The count of SYSCON_FCLKSEL */ +#define SYSCON_FCLKSEL_COUNT (10U) + +/*! @name MCLKCLKSEL - MCLK clock source select */ +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) + +/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ +#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) +#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) + +/*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */ +#define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) +#define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) +#define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) + +/*! @name SCTCLKSEL - SCTimer/PWM clock source select */ +#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) +#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) + +/*! @name LCDCLKSEL - LCD clock source select */ +#define SYSCON_LCDCLKSEL_SEL_MASK (0x3U) +#define SYSCON_LCDCLKSEL_SEL_SHIFT (0U) +#define SYSCON_LCDCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK) + +/*! @name SDIOCLKSEL - SDIO clock source select */ +#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) +#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) + +/*! @name SYSTICKCLKDIV - SYSTICK clock divider */ +#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) +#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) +#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) +#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) +#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) +#define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_SYSTICKCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK) + +/*! @name ARMTRACECLKDIV - ARM Trace clock divider */ +#define SYSCON_ARMTRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_ARMTRACECLKDIV_DIV_SHIFT (0U) +#define SYSCON_ARMTRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK) +#define SYSCON_ARMTRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ARMTRACECLKDIV_RESET_SHIFT (29U) +#define SYSCON_ARMTRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK) +#define SYSCON_ARMTRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ARMTRACECLKDIV_HALT_SHIFT (30U) +#define SYSCON_ARMTRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK) +#define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_ARMTRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK) + +/*! @name CAN0CLKDIV - MCAN0 clock divider */ +#define SYSCON_CAN0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_CAN0CLKDIV_DIV_SHIFT (0U) +#define SYSCON_CAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK) +#define SYSCON_CAN0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CAN0CLKDIV_RESET_SHIFT (29U) +#define SYSCON_CAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK) +#define SYSCON_CAN0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CAN0CLKDIV_HALT_SHIFT (30U) +#define SYSCON_CAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK) +#define SYSCON_CAN0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_CAN0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK) + +/*! @name CAN1CLKDIV - MCAN1 clock divider */ +#define SYSCON_CAN1CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_CAN1CLKDIV_DIV_SHIFT (0U) +#define SYSCON_CAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK) +#define SYSCON_CAN1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CAN1CLKDIV_RESET_SHIFT (29U) +#define SYSCON_CAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK) +#define SYSCON_CAN1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CAN1CLKDIV_HALT_SHIFT (30U) +#define SYSCON_CAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK) +#define SYSCON_CAN1CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_CAN1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK) + +/*! @name SC0CLKDIV - Smartcard0 clock divider */ +#define SYSCON_SC0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SC0CLKDIV_DIV_SHIFT (0U) +#define SYSCON_SC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK) +#define SYSCON_SC0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SC0CLKDIV_RESET_SHIFT (29U) +#define SYSCON_SC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK) +#define SYSCON_SC0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SC0CLKDIV_HALT_SHIFT (30U) +#define SYSCON_SC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK) +#define SYSCON_SC0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SC0CLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_SC0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK) + +/*! @name SC1CLKDIV - Smartcard1 clock divider */ +#define SYSCON_SC1CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SC1CLKDIV_DIV_SHIFT (0U) +#define SYSCON_SC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK) +#define SYSCON_SC1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SC1CLKDIV_RESET_SHIFT (29U) +#define SYSCON_SC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK) +#define SYSCON_SC1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SC1CLKDIV_HALT_SHIFT (30U) +#define SYSCON_SC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK) +#define SYSCON_SC1CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SC1CLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_SC1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK) + +/*! @name AHBCLKDIV - AHB clock divider */ +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) +#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) +#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) +#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) + +/*! @name FROHFCLKDIV - FROHF clock divider */ +#define SYSCON_FROHFCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFCLKDIV_DIV_SHIFT (0U) +#define SYSCON_FROHFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_DIV_SHIFT)) & SYSCON_FROHFCLKDIV_DIV_MASK) +#define SYSCON_FROHFCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FROHFCLKDIV_RESET_SHIFT (29U) +#define SYSCON_FROHFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_RESET_SHIFT)) & SYSCON_FROHFCLKDIV_RESET_MASK) +#define SYSCON_FROHFCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFCLKDIV_HALT_SHIFT (30U) +#define SYSCON_FROHFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_HALT_SHIFT)) & SYSCON_FROHFCLKDIV_HALT_MASK) +#define SYSCON_FROHFCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_FROHFCLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_FROHFCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_REQFLAG_SHIFT)) & SYSCON_FROHFCLKDIV_REQFLAG_MASK) + +/*! @name SPIFICLKDIV - SPIFI clock divider */ +#define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) +#define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) +#define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U) +#define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK) +#define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) +#define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) +#define SYSCON_SPIFICLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_SPIFICLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK) + +/*! @name ADCCLKDIV - ADC clock divider */ +#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) +#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) +#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) +#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) +#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) +#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) + +/*! @name USB0CLKDIV - USB0 clock divider */ +#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) +#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) +#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) +#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) +#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) +#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) + +/*! @name USB1CLKDIV - USB1 clock divider */ +#define SYSCON_USB1CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USB1CLKDIV_DIV_SHIFT (0U) +#define SYSCON_USB1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK) +#define SYSCON_USB1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_USB1CLKDIV_RESET_SHIFT (29U) +#define SYSCON_USB1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK) +#define SYSCON_USB1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_USB1CLKDIV_HALT_SHIFT (30U) +#define SYSCON_USB1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK) +#define SYSCON_USB1CLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_USB1CLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_USB1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK) + +/*! @name FRGCTRL - Fractional rate divider */ +#define SYSCON_FRGCTRL_DIV_MASK (0xFFU) +#define SYSCON_FRGCTRL_DIV_SHIFT (0U) +#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) +#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) +#define SYSCON_FRGCTRL_MULT_SHIFT (8U) +#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) + +/*! @name DMICCLKDIV - DMIC clock divider */ +#define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) +#define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) +#define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_DMICCLKDIV_RESET_SHIFT (29U) +#define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK) +#define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) +#define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) +#define SYSCON_DMICCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_DMICCLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_DMICCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK) + +/*! @name MCLKDIV - I2S MCLK clock divider */ +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) +#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MCLKDIV_RESET_SHIFT (29U) +#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) +#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MCLKDIV_HALT_SHIFT (30U) +#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) +#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) + +/*! @name LCDCLKDIV - LCD clock divider */ +#define SYSCON_LCDCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_LCDCLKDIV_DIV_SHIFT (0U) +#define SYSCON_LCDCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK) +#define SYSCON_LCDCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_LCDCLKDIV_RESET_SHIFT (29U) +#define SYSCON_LCDCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK) +#define SYSCON_LCDCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_LCDCLKDIV_HALT_SHIFT (30U) +#define SYSCON_LCDCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK) +#define SYSCON_LCDCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_LCDCLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_LCDCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK) + +/*! @name SCTCLKDIV - SCT/PWM clock divider */ +#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) +#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) +#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) +#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) +#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) +#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) + +/*! @name EMCCLKDIV - EMC clock divider */ +#define SYSCON_EMCCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_EMCCLKDIV_DIV_SHIFT (0U) +#define SYSCON_EMCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK) +#define SYSCON_EMCCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_EMCCLKDIV_RESET_SHIFT (29U) +#define SYSCON_EMCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK) +#define SYSCON_EMCCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_EMCCLKDIV_HALT_SHIFT (30U) +#define SYSCON_EMCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK) +#define SYSCON_EMCCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_EMCCLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_EMCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK) + +/*! @name SDIOCLKDIV - SDIO clock divider */ +#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) +#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) +#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) +#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) +#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) +#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) +#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) +#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) + +/*! @name FLASHCFG - Flash wait states configuration */ +#define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) +#define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) +#define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) +#define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) +#define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) +#define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) +#define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) +#define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) +#define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) +#define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) +#define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) +#define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) +#define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) +#define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) +#define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) +#define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) +#define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) +#define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) + +/*! @name USB0CLKCTRL - USB0 clock control */ +#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) +#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) +#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK) +#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) +#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) +#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK) +#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) +#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) +#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK) +#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) +#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) +#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK) +#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U) +#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U) +#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK) + +/*! @name USB0CLKSTAT - USB0 clock status */ +#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) +#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) +#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK) +#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) +#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) +#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK) + +/*! @name FREQMECTRL - Frequency measure register */ +#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) +#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) +#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) +#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) +#define SYSCON_FREQMECTRL_PROG_SHIFT (31U) +#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) + +/*! @name MCLKIO - MCLK input/output control */ +#define SYSCON_MCLKIO_DIR_MASK (0x1U) +#define SYSCON_MCLKIO_DIR_SHIFT (0U) +#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) + +/*! @name USB1CLKCTRL - USB1 clock control */ +#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) +#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) +#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK) +#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) +#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) +#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK) +#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) +#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) +#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK) +#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) +#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) +#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK) +#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) +#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) +#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK) + +/*! @name USB1CLKSTAT - USB1 clock status */ +#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) +#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) +#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK) +#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) +#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) +#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK) + +/*! @name EMCSYSCTRL - EMC system control */ +#define SYSCON_EMCSYSCTRL_EMCSC_MASK (0x1U) +#define SYSCON_EMCSYSCTRL_EMCSC_SHIFT (0U) +#define SYSCON_EMCSYSCTRL_EMCSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK) +#define SYSCON_EMCSYSCTRL_EMCRD_MASK (0x2U) +#define SYSCON_EMCSYSCTRL_EMCRD_SHIFT (1U) +#define SYSCON_EMCSYSCTRL_EMCRD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK) +#define SYSCON_EMCSYSCTRL_EMCBC_MASK (0x4U) +#define SYSCON_EMCSYSCTRL_EMCBC_SHIFT (2U) +#define SYSCON_EMCSYSCTRL_EMCBC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK) +#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK (0x8U) +#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT (3U) +#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK) + +/*! @name EMCDLYCTRL - EMC clock delay control */ +#define SYSCON_EMCDLYCTRL_CMD_DELAY_MASK (0x1FU) +#define SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT (0U) +#define SYSCON_EMCDLYCTRL_CMD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_CMD_DELAY_MASK) +#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK (0x1F00U) +#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT (8U) +#define SYSCON_EMCDLYCTRL_FBCLK_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK) + +/*! @name EMCDLYCAL - EMC delay chain calibration control */ +#define SYSCON_EMCDLYCAL_CALVALUE_MASK (0xFFU) +#define SYSCON_EMCDLYCAL_CALVALUE_SHIFT (0U) +#define SYSCON_EMCDLYCAL_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_CALVALUE_SHIFT)) & SYSCON_EMCDLYCAL_CALVALUE_MASK) +#define SYSCON_EMCDLYCAL_START_MASK (0x4000U) +#define SYSCON_EMCDLYCAL_START_SHIFT (14U) +#define SYSCON_EMCDLYCAL_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_START_SHIFT)) & SYSCON_EMCDLYCAL_START_MASK) +#define SYSCON_EMCDLYCAL_DONE_MASK (0x8000U) +#define SYSCON_EMCDLYCAL_DONE_SHIFT (15U) +#define SYSCON_EMCDLYCAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_DONE_SHIFT)) & SYSCON_EMCDLYCAL_DONE_MASK) + +/*! @name ETHPHYSEL - Ethernet PHY Selection */ +#define SYSCON_ETHPHYSEL_PHY_SEL_MASK (0x4U) +#define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT (2U) +#define SYSCON_ETHPHYSEL_PHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK) + +/*! @name ETHSBDCTRL - Ethernet SBD flow control */ +#define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK (0x3U) +#define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT (0U) +#define SYSCON_ETHSBDCTRL_SBD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK) + +/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) +#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) +#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) +#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) + +/*! @name FROCTRL - FRO oscillator control */ +#define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) +#define SYSCON_FROCTRL_TRIM_SHIFT (0U) +#define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) +#define SYSCON_FROCTRL_SEL_MASK (0x4000U) +#define SYSCON_FROCTRL_SEL_SHIFT (14U) +#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) +#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) +#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) +#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) +#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) +#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) +#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) +#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) +#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) +#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) +#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) +#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) +#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) +#define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) +#define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) +#define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) + +/*! @name SYSOSCCTRL - System oscillator control */ +#define SYSCON_SYSOSCCTRL_BYPASS_MASK (0x1U) +#define SYSCON_SYSOSCCTRL_BYPASS_SHIFT (0U) +#define SYSCON_SYSOSCCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK) +#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U) +#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U) +#define SYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK) + +/*! @name WDTOSCCTRL - Watchdog oscillator control */ +#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) +#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) +#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) +#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) +#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) +#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) + +/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ +#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) +#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) +#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) + +/*! @name USBPLLCTRL - USB PLL control */ +#define SYSCON_USBPLLCTRL_MSEL_MASK (0xFFU) +#define SYSCON_USBPLLCTRL_MSEL_SHIFT (0U) +#define SYSCON_USBPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK) +#define SYSCON_USBPLLCTRL_PSEL_MASK (0x300U) +#define SYSCON_USBPLLCTRL_PSEL_SHIFT (8U) +#define SYSCON_USBPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK) +#define SYSCON_USBPLLCTRL_NSEL_MASK (0xC00U) +#define SYSCON_USBPLLCTRL_NSEL_SHIFT (10U) +#define SYSCON_USBPLLCTRL_NSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK) +#define SYSCON_USBPLLCTRL_DIRECT_MASK (0x1000U) +#define SYSCON_USBPLLCTRL_DIRECT_SHIFT (12U) +#define SYSCON_USBPLLCTRL_DIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK) +#define SYSCON_USBPLLCTRL_BYPASS_MASK (0x2000U) +#define SYSCON_USBPLLCTRL_BYPASS_SHIFT (13U) +#define SYSCON_USBPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK) +#define SYSCON_USBPLLCTRL_FBSEL_MASK (0x4000U) +#define SYSCON_USBPLLCTRL_FBSEL_SHIFT (14U) +#define SYSCON_USBPLLCTRL_FBSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK) + +/*! @name USBPLLSTAT - USB PLL status */ +#define SYSCON_USBPLLSTAT_LOCK_MASK (0x1U) +#define SYSCON_USBPLLSTAT_LOCK_SHIFT (0U) +#define SYSCON_USBPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK) + +/*! @name SYSPLLCTRL - System PLL control */ +#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) +#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) +#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) +#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) +#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) +#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) +#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) +#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) +#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) +#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) +#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) +#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) +#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) +#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) +#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) +#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) +#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) +#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) +#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) +#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) +#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) + +/*! @name SYSPLLSTAT - PLL status */ +#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) +#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) +#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) + +/*! @name SYSPLLNDEC - PLL N divider */ +#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) +#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) +#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) +#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) +#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) +#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) + +/*! @name SYSPLLPDEC - PLL P divider */ +#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) +#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) +#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) +#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) +#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) +#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) + +/*! @name SYSPLLMDEC - System PLL M divider */ +#define SYSCON_SYSPLLMDEC_MDEC_MASK (0x1FFFFU) +#define SYSCON_SYSPLLMDEC_MDEC_SHIFT (0U) +#define SYSCON_SYSPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK) +#define SYSCON_SYSPLLMDEC_MREQ_MASK (0x20000U) +#define SYSCON_SYSPLLMDEC_MREQ_SHIFT (17U) +#define SYSCON_SYSPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK) + +/*! @name AUDPLLCTRL - Audio PLL control */ +#define SYSCON_AUDPLLCTRL_SELR_MASK (0xFU) +#define SYSCON_AUDPLLCTRL_SELR_SHIFT (0U) +#define SYSCON_AUDPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK) +#define SYSCON_AUDPLLCTRL_SELI_MASK (0x3F0U) +#define SYSCON_AUDPLLCTRL_SELI_SHIFT (4U) +#define SYSCON_AUDPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK) +#define SYSCON_AUDPLLCTRL_SELP_MASK (0x7C00U) +#define SYSCON_AUDPLLCTRL_SELP_SHIFT (10U) +#define SYSCON_AUDPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK) +#define SYSCON_AUDPLLCTRL_BYPASS_MASK (0x8000U) +#define SYSCON_AUDPLLCTRL_BYPASS_SHIFT (15U) +#define SYSCON_AUDPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK) +#define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK (0x20000U) +#define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT (17U) +#define SYSCON_AUDPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK) +#define SYSCON_AUDPLLCTRL_DIRECTI_MASK (0x80000U) +#define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT (19U) +#define SYSCON_AUDPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK) +#define SYSCON_AUDPLLCTRL_DIRECTO_MASK (0x100000U) +#define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT (20U) +#define SYSCON_AUDPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK) + +/*! @name AUDPLLSTAT - Audio PLL status */ +#define SYSCON_AUDPLLSTAT_LOCK_MASK (0x1U) +#define SYSCON_AUDPLLSTAT_LOCK_SHIFT (0U) +#define SYSCON_AUDPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK) + +/*! @name AUDPLLNDEC - Audio PLL N divider */ +#define SYSCON_AUDPLLNDEC_NDEC_MASK (0x3FFU) +#define SYSCON_AUDPLLNDEC_NDEC_SHIFT (0U) +#define SYSCON_AUDPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK) +#define SYSCON_AUDPLLNDEC_NREQ_MASK (0x400U) +#define SYSCON_AUDPLLNDEC_NREQ_SHIFT (10U) +#define SYSCON_AUDPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK) + +/*! @name AUDPLLPDEC - Audio PLL P divider */ +#define SYSCON_AUDPLLPDEC_PDEC_MASK (0x7FU) +#define SYSCON_AUDPLLPDEC_PDEC_SHIFT (0U) +#define SYSCON_AUDPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK) +#define SYSCON_AUDPLLPDEC_PREQ_MASK (0x80U) +#define SYSCON_AUDPLLPDEC_PREQ_SHIFT (7U) +#define SYSCON_AUDPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK) + +/*! @name AUDPLLMDEC - Audio PLL M divider */ +#define SYSCON_AUDPLLMDEC_MDEC_MASK (0x1FFFFU) +#define SYSCON_AUDPLLMDEC_MDEC_SHIFT (0U) +#define SYSCON_AUDPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK) +#define SYSCON_AUDPLLMDEC_MREQ_MASK (0x20000U) +#define SYSCON_AUDPLLMDEC_MREQ_SHIFT (17U) +#define SYSCON_AUDPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK) + +/*! @name AUDPLLFRAC - Audio PLL fractional divider control */ +#define SYSCON_AUDPLLFRAC_CTRL_MASK (0x3FFFFFU) +#define SYSCON_AUDPLLFRAC_CTRL_SHIFT (0U) +#define SYSCON_AUDPLLFRAC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK) +#define SYSCON_AUDPLLFRAC_REQ_MASK (0x400000U) +#define SYSCON_AUDPLLFRAC_REQ_SHIFT (22U) +#define SYSCON_AUDPLLFRAC_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK) +#define SYSCON_AUDPLLFRAC_SEL_EXT_MASK (0x800000U) +#define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT (23U) +#define SYSCON_AUDPLLFRAC_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK) + +/*! @name PDSLEEPCFG - Power configuration register 0 */ +#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK (0x1U) +#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT (0U) +#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK (0x2U) +#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT (1U) +#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK (0x4U) +#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT (2U) +#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK (0x8U) +#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT (3U) +#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK (0x10U) +#define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT (4U) +#define SYSCON_PDSLEEPCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK (0x20U) +#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT (5U) +#define SYSCON_PDSLEEPCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_TS_MASK (0x40U) +#define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT (6U) +#define SYSCON_PDSLEEPCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK (0x80U) +#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT (7U) +#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK (0x80U) +#define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT (7U) +#define SYSCON_PDSLEEPCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK (0x100U) +#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT (8U) +#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK (0x200U) +#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT (9U) +#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK (0x400U) +#define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT (10U) +#define SYSCON_PDSLEEPCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK (0x2000U) +#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT (13U) +#define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK (0x4000U) +#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT (14U) +#define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK (0x8000U) +#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT (15U) +#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK (0x10000U) +#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT (16U) +#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK (0x20000U) +#define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT (17U) +#define SYSCON_PDSLEEPCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK (0x80000U) +#define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT (19U) +#define SYSCON_PDSLEEPCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK (0x100000U) +#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT (20U) +#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK (0x200000U) +#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT (21U) +#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK (0x400000U) +#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT (22U) +#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK (0x800000U) +#define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT (23U) +#define SYSCON_PDSLEEPCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK (0x4000000U) +#define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT (26U) +#define SYSCON_PDSLEEPCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK (0x8000000U) +#define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT (27U) +#define SYSCON_PDSLEEPCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK (0x10000000U) +#define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT (28U) +#define SYSCON_PDSLEEPCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK) +#define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK (0x20000000U) +#define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT (29U) +#define SYSCON_PDSLEEPCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK) + +/* The count of SYSCON_PDSLEEPCFG */ +#define SYSCON_PDSLEEPCFG_COUNT (2U) + +/*! @name PDRUNCFG - Power configuration register 0 */ +#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK (0x1U) +#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT (0U) +#define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK) +#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK (0x2U) +#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT (1U) +#define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK) +#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK (0x4U) +#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT (2U) +#define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK) +#define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK (0x8U) +#define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT (3U) +#define SYSCON_PDRUNCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK) +#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) +#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) +#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) +#define SYSCON_PDRUNCFG_PDEN_EEPROM_MASK (0x20U) +#define SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT (5U) +#define SYSCON_PDRUNCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_EEPROM_MASK) +#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) +#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) +#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) +#define SYSCON_PDRUNCFG_PDEN_RNG_MASK (0x80U) +#define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT (7U) +#define SYSCON_PDRUNCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) +#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK (0x200U) +#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT (9U) +#define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK) +#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) +#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) +#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x2000U) +#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (13U) +#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x4000U) +#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (14U) +#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK (0x8000U) +#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT (15U) +#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK) +#define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK (0x10000U) +#define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT (16U) +#define SYSCON_PDRUNCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK) +#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) +#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) +#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) +#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) +#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) +#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) +#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK (0x200000U) +#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT (21U) +#define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) +#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) +#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) +#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) +#define SYSCON_PDRUNCFG_PDEN_VD3_MASK (0x4000000U) +#define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT (26U) +#define SYSCON_PDRUNCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK) +#define SYSCON_PDRUNCFG_PDEN_VD4_MASK (0x8000000U) +#define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT (27U) +#define SYSCON_PDRUNCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK) +#define SYSCON_PDRUNCFG_PDEN_VD5_MASK (0x10000000U) +#define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT (28U) +#define SYSCON_PDRUNCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK) +#define SYSCON_PDRUNCFG_PDEN_VD6_MASK (0x20000000U) +#define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT (29U) +#define SYSCON_PDRUNCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK) + +/* The count of SYSCON_PDRUNCFG */ +#define SYSCON_PDRUNCFG_COUNT (2U) + +/*! @name PDRUNCFGSET - Set bits in PDRUNCFG0 */ +#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK (0x1U) +#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT (0U) +#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK (0x2U) +#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT (1U) +#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK (0x4U) +#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT (2U) +#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK (0x8U) +#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT (3U) +#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK (0x10U) +#define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT (4U) +#define SYSCON_PDRUNCFGSET_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK (0x20U) +#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT (5U) +#define SYSCON_PDRUNCFGSET_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_TS_MASK (0x40U) +#define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT (6U) +#define SYSCON_PDRUNCFGSET_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK (0x80U) +#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT (7U) +#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK (0x80U) +#define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT (7U) +#define SYSCON_PDRUNCFGSET_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK (0x100U) +#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT (8U) +#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK (0x200U) +#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT (9U) +#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK (0x400U) +#define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT (10U) +#define SYSCON_PDRUNCFGSET_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK (0x2000U) +#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT (13U) +#define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK (0x4000U) +#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT (14U) +#define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK (0x8000U) +#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT (15U) +#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK (0x10000U) +#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT (16U) +#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK (0x20000U) +#define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT (17U) +#define SYSCON_PDRUNCFGSET_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK (0x80000U) +#define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT (19U) +#define SYSCON_PDRUNCFGSET_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK (0x100000U) +#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT (20U) +#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK (0x200000U) +#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT (21U) +#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK (0x400000U) +#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT (22U) +#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK (0x800000U) +#define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT (23U) +#define SYSCON_PDRUNCFGSET_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK (0x4000000U) +#define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT (26U) +#define SYSCON_PDRUNCFGSET_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK (0x8000000U) +#define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT (27U) +#define SYSCON_PDRUNCFGSET_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK (0x10000000U) +#define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT (28U) +#define SYSCON_PDRUNCFGSET_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK) +#define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK (0x20000000U) +#define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT (29U) +#define SYSCON_PDRUNCFGSET_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK) + +/* The count of SYSCON_PDRUNCFGSET */ +#define SYSCON_PDRUNCFGSET_COUNT (2U) + +/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFG0 */ +#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK (0x1U) +#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT (0U) +#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK (0x2U) +#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT (1U) +#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK (0x4U) +#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT (2U) +#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK (0x8U) +#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT (3U) +#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK (0x10U) +#define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT (4U) +#define SYSCON_PDRUNCFGCLR_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK (0x20U) +#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT (5U) +#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK (0x40U) +#define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT (6U) +#define SYSCON_PDRUNCFGCLR_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK (0x80U) +#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT (7U) +#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK (0x80U) +#define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT (7U) +#define SYSCON_PDRUNCFGCLR_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK (0x100U) +#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT (8U) +#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK (0x200U) +#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT (9U) +#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK (0x400U) +#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT (10U) +#define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK (0x2000U) +#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT (13U) +#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK (0x4000U) +#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT (14U) +#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK (0x8000U) +#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT (15U) +#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK (0x10000U) +#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT (16U) +#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK (0x20000U) +#define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT (17U) +#define SYSCON_PDRUNCFGCLR_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK (0x80000U) +#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT (19U) +#define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK (0x100000U) +#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT (20U) +#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK (0x200000U) +#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT (21U) +#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK (0x400000U) +#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT (22U) +#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK (0x800000U) +#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT (23U) +#define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK (0x4000000U) +#define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT (26U) +#define SYSCON_PDRUNCFGCLR_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK (0x8000000U) +#define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT (27U) +#define SYSCON_PDRUNCFGCLR_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK (0x10000000U) +#define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT (28U) +#define SYSCON_PDRUNCFGCLR_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK) +#define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK (0x20000000U) +#define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT (29U) +#define SYSCON_PDRUNCFGCLR_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK) + +/* The count of SYSCON_PDRUNCFGCLR */ +#define SYSCON_PDRUNCFGCLR_COUNT (2U) + +/*! @name STARTER - Start logic 0 wake-up enable register */ +#define SYSCON_STARTER_WDT_BOD_MASK (0x1U) +#define SYSCON_STARTER_WDT_BOD_SHIFT (0U) +#define SYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK) +#define SYSCON_STARTER_PINT4_MASK (0x1U) +#define SYSCON_STARTER_PINT4_SHIFT (0U) +#define SYSCON_STARTER_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK) +#define SYSCON_STARTER_PINT5_MASK (0x2U) +#define SYSCON_STARTER_PINT5_SHIFT (1U) +#define SYSCON_STARTER_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK) +#define SYSCON_STARTER_DMA_MASK (0x2U) +#define SYSCON_STARTER_DMA_SHIFT (1U) +#define SYSCON_STARTER_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK) +#define SYSCON_STARTER_GINT0_MASK (0x4U) +#define SYSCON_STARTER_GINT0_SHIFT (2U) +#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) +#define SYSCON_STARTER_PINT6_MASK (0x4U) +#define SYSCON_STARTER_PINT6_SHIFT (2U) +#define SYSCON_STARTER_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK) +#define SYSCON_STARTER_GINT1_MASK (0x8U) +#define SYSCON_STARTER_GINT1_SHIFT (3U) +#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) +#define SYSCON_STARTER_PINT7_MASK (0x8U) +#define SYSCON_STARTER_PINT7_SHIFT (3U) +#define SYSCON_STARTER_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK) +#define SYSCON_STARTER_CTIMER2_MASK (0x10U) +#define SYSCON_STARTER_CTIMER2_SHIFT (4U) +#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) +#define SYSCON_STARTER_PIN_INT0_MASK (0x10U) +#define SYSCON_STARTER_PIN_INT0_SHIFT (4U) +#define SYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK) +#define SYSCON_STARTER_CTIMER4_MASK (0x20U) +#define SYSCON_STARTER_CTIMER4_SHIFT (5U) +#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) +#define SYSCON_STARTER_PIN_INT1_MASK (0x20U) +#define SYSCON_STARTER_PIN_INT1_SHIFT (5U) +#define SYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK) +#define SYSCON_STARTER_PIN_INT2_MASK (0x40U) +#define SYSCON_STARTER_PIN_INT2_SHIFT (6U) +#define SYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK) +#define SYSCON_STARTER_PIN_INT3_MASK (0x80U) +#define SYSCON_STARTER_PIN_INT3_SHIFT (7U) +#define SYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK) +#define SYSCON_STARTER_SPIFI_MASK (0x80U) +#define SYSCON_STARTER_SPIFI_SHIFT (7U) +#define SYSCON_STARTER_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPIFI_SHIFT)) & SYSCON_STARTER_SPIFI_MASK) +#define SYSCON_STARTER_FLEXCOMM8_MASK (0x100U) +#define SYSCON_STARTER_FLEXCOMM8_SHIFT (8U) +#define SYSCON_STARTER_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK) +#define SYSCON_STARTER_UTICK_MASK (0x100U) +#define SYSCON_STARTER_UTICK_SHIFT (8U) +#define SYSCON_STARTER_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK) +#define SYSCON_STARTER_MRT_MASK (0x200U) +#define SYSCON_STARTER_MRT_SHIFT (9U) +#define SYSCON_STARTER_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT_SHIFT)) & SYSCON_STARTER_MRT_MASK) +#define SYSCON_STARTER_FLEXCOMM9_MASK (0x200U) +#define SYSCON_STARTER_FLEXCOMM9_SHIFT (9U) +#define SYSCON_STARTER_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK) +#define SYSCON_STARTER_CTIMER0_MASK (0x400U) +#define SYSCON_STARTER_CTIMER0_SHIFT (10U) +#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) +#define SYSCON_STARTER_CTIMER1_MASK (0x800U) +#define SYSCON_STARTER_CTIMER1_SHIFT (11U) +#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) +#define SYSCON_STARTER_SCT0_MASK (0x1000U) +#define SYSCON_STARTER_SCT0_SHIFT (12U) +#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) +#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) +#define SYSCON_STARTER_CTIMER3_SHIFT (13U) +#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) +#define SYSCON_STARTER_FLEXCOMM0_MASK (0x4000U) +#define SYSCON_STARTER_FLEXCOMM0_SHIFT (14U) +#define SYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK) +#define SYSCON_STARTER_FLEXCOMM1_MASK (0x8000U) +#define SYSCON_STARTER_FLEXCOMM1_SHIFT (15U) +#define SYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK) +#define SYSCON_STARTER_USB1_MASK (0x8000U) +#define SYSCON_STARTER_USB1_SHIFT (15U) +#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK) +#define SYSCON_STARTER_FLEXCOMM2_MASK (0x10000U) +#define SYSCON_STARTER_FLEXCOMM2_SHIFT (16U) +#define SYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK) +#define SYSCON_STARTER_USB1_ACT_MASK (0x10000U) +#define SYSCON_STARTER_USB1_ACT_SHIFT (16U) +#define SYSCON_STARTER_USB1_ACT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK) +#define SYSCON_STARTER_ENET_INT1_MASK (0x20000U) +#define SYSCON_STARTER_ENET_INT1_SHIFT (17U) +#define SYSCON_STARTER_ENET_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT1_SHIFT)) & SYSCON_STARTER_ENET_INT1_MASK) +#define SYSCON_STARTER_FLEXCOMM3_MASK (0x20000U) +#define SYSCON_STARTER_FLEXCOMM3_SHIFT (17U) +#define SYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK) +#define SYSCON_STARTER_ENET_INT2_MASK (0x40000U) +#define SYSCON_STARTER_ENET_INT2_SHIFT (18U) +#define SYSCON_STARTER_ENET_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT2_SHIFT)) & SYSCON_STARTER_ENET_INT2_MASK) +#define SYSCON_STARTER_FLEXCOMM4_MASK (0x40000U) +#define SYSCON_STARTER_FLEXCOMM4_SHIFT (18U) +#define SYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK) +#define SYSCON_STARTER_ENET_INT0_MASK (0x80000U) +#define SYSCON_STARTER_ENET_INT0_SHIFT (19U) +#define SYSCON_STARTER_ENET_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT0_SHIFT)) & SYSCON_STARTER_ENET_INT0_MASK) +#define SYSCON_STARTER_FLEXCOMM5_MASK (0x80000U) +#define SYSCON_STARTER_FLEXCOMM5_SHIFT (19U) +#define SYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK) +#define SYSCON_STARTER_FLEXCOMM6_MASK (0x100000U) +#define SYSCON_STARTER_FLEXCOMM6_SHIFT (20U) +#define SYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK) +#define SYSCON_STARTER_FLEXCOMM7_MASK (0x200000U) +#define SYSCON_STARTER_FLEXCOMM7_SHIFT (21U) +#define SYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK) +#define SYSCON_STARTER_ADC0_SEQA_MASK (0x400000U) +#define SYSCON_STARTER_ADC0_SEQA_SHIFT (22U) +#define SYSCON_STARTER_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQA_SHIFT)) & SYSCON_STARTER_ADC0_SEQA_MASK) +#define SYSCON_STARTER_SMARTCARD0_MASK (0x800000U) +#define SYSCON_STARTER_SMARTCARD0_SHIFT (23U) +#define SYSCON_STARTER_SMARTCARD0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD0_SHIFT)) & SYSCON_STARTER_SMARTCARD0_MASK) +#define SYSCON_STARTER_ADC0_SEQB_MASK (0x800000U) +#define SYSCON_STARTER_ADC0_SEQB_SHIFT (23U) +#define SYSCON_STARTER_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQB_SHIFT)) & SYSCON_STARTER_ADC0_SEQB_MASK) +#define SYSCON_STARTER_ADC0_THCMP_MASK (0x1000000U) +#define SYSCON_STARTER_ADC0_THCMP_SHIFT (24U) +#define SYSCON_STARTER_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_MASK) +#define SYSCON_STARTER_SMARTCARD1_MASK (0x1000000U) +#define SYSCON_STARTER_SMARTCARD1_SHIFT (24U) +#define SYSCON_STARTER_SMARTCARD1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD1_SHIFT)) & SYSCON_STARTER_SMARTCARD1_MASK) +#define SYSCON_STARTER_DMIC_MASK (0x2000000U) +#define SYSCON_STARTER_DMIC_SHIFT (25U) +#define SYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK) +#define SYSCON_STARTER_HWVAD_MASK (0x4000000U) +#define SYSCON_STARTER_HWVAD_SHIFT (26U) +#define SYSCON_STARTER_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK) +#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) +#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) +#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) +#define SYSCON_STARTER_USB0_MASK (0x10000000U) +#define SYSCON_STARTER_USB0_SHIFT (28U) +#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) +#define SYSCON_STARTER_RTC_MASK (0x20000000U) +#define SYSCON_STARTER_RTC_SHIFT (29U) +#define SYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK) + +/* The count of SYSCON_STARTER */ +#define SYSCON_STARTER_COUNT (2U) + +/*! @name STARTERSET - Set bits in STARTER */ +#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) +#define SYSCON_STARTERSET_START_SET_SHIFT (0U) +#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) + +/* The count of SYSCON_STARTERSET */ +#define SYSCON_STARTERSET_COUNT (2U) + +/*! @name STARTERCLR - Clear bits in STARTER0 */ +#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) +#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) + +/* The count of SYSCON_STARTERCLR */ +#define SYSCON_STARTERCLR_COUNT (2U) + +/*! @name HWWAKE - Configures special cases of hardware wake-up */ +#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) +#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) +#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) +#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) +#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) +#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) +#define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U) +#define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U) +#define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK) +#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) +#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) +#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) + +/*! @name AUTOCGOR - Auto Clock-Gate Override Register */ +#define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) +#define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) +#define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) +#define SYSCON_AUTOCGOR_RAM1_MASK (0x4U) +#define SYSCON_AUTOCGOR_RAM1_SHIFT (2U) +#define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK) +#define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) +#define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) +#define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) +#define SYSCON_AUTOCGOR_RAM3_MASK (0x10U) +#define SYSCON_AUTOCGOR_RAM3_SHIFT (4U) +#define SYSCON_AUTOCGOR_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK) + +/*! @name JTAGIDCODE - JTAG ID code register */ +#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) +#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) +#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) + +/*! @name DEVICE_ID0 - Part ID register */ +#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) +#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) + +/*! @name DEVICE_ID1 - Boot ROM and die revision register */ +#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) +#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) + +/*! @name BODCTRL - Brown-Out Detect control */ +#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) +#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) +#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) +#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) +#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) +#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) +#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) +#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) +#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) +#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) +#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) +#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) +#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) +#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) +#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) +#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) +#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) +#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40000000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_6[440]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) + +/*! @name ADDR - Address register for automatic address matching. */ +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +#define USART_FIFOCFG_POPDBG_MASK (0x40000U) +#define USART_FIFOCFG_POPDBG_SHIFT (18U) +#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) + +/*! @name FIFOSTAT - FIFO status register. */ +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) + +/*! @name FIFOWR - FIFO write data. */ +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) + +/*! @name FIFORD - FIFO read data. */ +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) + +/*! @name ID - Peripheral identification register. */ +#define USART_ID_APERTURE_MASK (0xFFU) +#define USART_ID_APERTURE_SHIFT (0U) +#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) +#define USART_ID_MINOR_REV_MASK (0xF00U) +#define USART_ID_MINOR_REV_SHIFT (8U) +#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) +#define USART_ID_MAJOR_REV_MASK (0xF000U) +#define USART_ID_MAJOR_REV_SHIFT (12U) +#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) +#define USART_ID_ID_MASK (0xFFFF0000U) +#define USART_ID_ID_SHIFT (16U) +#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +/** Peripheral USART0 base address */ +#define USART0_BASE (0x40086000u) +/** Peripheral USART0 base pointer */ +#define USART0 ((USART_Type *)USART0_BASE) +/** Peripheral USART1 base address */ +#define USART1_BASE (0x40087000u) +/** Peripheral USART1 base pointer */ +#define USART1 ((USART_Type *)USART1_BASE) +/** Peripheral USART2 base address */ +#define USART2_BASE (0x40088000u) +/** Peripheral USART2 base pointer */ +#define USART2 ((USART_Type *)USART2_BASE) +/** Peripheral USART3 base address */ +#define USART3_BASE (0x40089000u) +/** Peripheral USART3 base pointer */ +#define USART3 ((USART_Type *)USART3_BASE) +/** Peripheral USART4 base address */ +#define USART4_BASE (0x4008A000u) +/** Peripheral USART4 base pointer */ +#define USART4 ((USART_Type *)USART4_BASE) +/** Peripheral USART5 base address */ +#define USART5_BASE (0x40096000u) +/** Peripheral USART5 base pointer */ +#define USART5 ((USART_Type *)USART5_BASE) +/** Peripheral USART6 base address */ +#define USART6_BASE (0x40097000u) +/** Peripheral USART6 base pointer */ +#define USART6 ((USART_Type *)USART6_BASE) +/** Peripheral USART7 base address */ +#define USART7_BASE (0x40098000u) +/** Peripheral USART7 base pointer */ +#define USART7 ((USART_Type *)USART7_BASE) +/** Peripheral USART8 base address */ +#define USART8_BASE (0x40099000u) +/** Peripheral USART8 base pointer */ +#define USART8 ((USART_Type *)USART8_BASE) +/** Peripheral USART9 base address */ +#define USART9_BASE (0x4009A000u) +/** Peripheral USART9 base pointer */ +#define USART9 ((USART_Type *)USART9_BASE) +/** Array initializer of USART peripheral base addresses */ +#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE } +/** Array initializer of USART peripheral base pointers */ +#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 } +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) + +/*! @name INFO - USB Info register */ +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) +#define USB_INFO_MINREV_MASK (0xFF0000U) +#define USB_INFO_MINREV_SHIFT (16U) +#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) +#define USB_INFO_MAJREV_MASK (0xFF000000U) +#define USB_INFO_MAJREV_SHIFT (24U) +#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) + +/*! @name DATABUFSTART - USB Data buffer start address */ +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) + +/*! @name LPM - USB Link Power Management register */ +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) + +/*! @name EPSKIP - USB Endpoint skip */ +#define USB_EPSKIP_SKIP_MASK (0x3FFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) + +/*! @name INTSTAT - USB interrupt status register */ +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) + +/*! @name INTEN - USB interrupt enable register */ +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) + +/*! @name INTSETSTAT - USB set interrupt status register */ +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x40084000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBFSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer + * @{ + */ + +/** USBFSH - Register Layout Typedef */ +typedef struct { + __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ + __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ + __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ + __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ + __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ + __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ + __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ + __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ + __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ + __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ + __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ + __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ + __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ + __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ + __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ + __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ + __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ + __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ + __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ + __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ + __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ + __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ +} USBFSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBFSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBFSH_Register_Masks USBFSH Register Masks + * @{ + */ + +/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ +#define USBFSH_HCREVISION_REV_MASK (0xFFU) +#define USBFSH_HCREVISION_REV_SHIFT (0U) +#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) + +/*! @name HCCONTROL - Defines the operating modes of the HC */ +#define USBFSH_HCCONTROL_CBSR_MASK (0x3U) +#define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) +#define USBFSH_HCCONTROL_PLE_MASK (0x4U) +#define USBFSH_HCCONTROL_PLE_SHIFT (2U) +#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) +#define USBFSH_HCCONTROL_IE_MASK (0x8U) +#define USBFSH_HCCONTROL_IE_SHIFT (3U) +#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) +#define USBFSH_HCCONTROL_CLE_MASK (0x10U) +#define USBFSH_HCCONTROL_CLE_SHIFT (4U) +#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) +#define USBFSH_HCCONTROL_BLE_MASK (0x20U) +#define USBFSH_HCCONTROL_BLE_SHIFT (5U) +#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) +#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) +#define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) +#define USBFSH_HCCONTROL_IR_MASK (0x100U) +#define USBFSH_HCCONTROL_IR_SHIFT (8U) +#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) +#define USBFSH_HCCONTROL_RWC_MASK (0x200U) +#define USBFSH_HCCONTROL_RWC_SHIFT (9U) +#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) +#define USBFSH_HCCONTROL_RWE_MASK (0x400U) +#define USBFSH_HCCONTROL_RWE_SHIFT (10U) +#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) + +/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ +#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) +#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) +#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) +#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) +#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) +#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) +#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) +#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) +#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) +#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) + +/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ +#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) +#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) +#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) +#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) +#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) +#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) +#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) +#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) + +/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ +#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) +#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) +#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) +#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) +#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) +#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) +#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) +#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) +#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) + +/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ +#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) +#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) +#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) +#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) +#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) +#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) +#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) +#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) +#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) +#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) +#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) +#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) +#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) +#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) +#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) +#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) + +/*! @name HCHCCA - Contains the physical address of the host controller communication area */ +#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) +#define USBFSH_HCHCCA_HCCA_SHIFT (8U) +#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) + +/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ +#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) + +/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ +#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) + +/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ +#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) + +/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ +#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) + +/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ +#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) +#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) + +/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ +#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) +#define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) + +/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ +#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) +#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) +#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) +#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) +#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) +#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) + +/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ +#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) +#define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) +#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) +#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) + +/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ +#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) +#define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) + +/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ +#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) +#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) + +/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ +#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) +#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) + +/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ +#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) +#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) +#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) +#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) +#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) +#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) +#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) +#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) +#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) +#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) +#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) +#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) + +/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ +#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) +#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) +#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) +#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) + +/*! @name HCRHSTATUS - This register is divided into two parts */ +#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) +#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) +#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) +#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) +#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) +#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) +#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) +#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) +#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) +#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) +#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) +#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) + +/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ +#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) +#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) +#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) +#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) +#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) +#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) +#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) +#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) +#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) +#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) +#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) +#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) +#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) +#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) +#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) +#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) +#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) +#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) +#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) +#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) +#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) +#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) +#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) +#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +#define USBFSH_PORTMODE_ID_MASK (0x1U) +#define USBFSH_PORTMODE_ID_SHIFT (0U) +#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) +#define USBFSH_PORTMODE_ID_EN_MASK (0x100U) +#define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) +#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) + + +/*! + * @} + */ /* end of group USBFSH_Register_Masks */ + + +/* USBFSH - Peripheral instance base addresses */ +/** Peripheral USBFSH base address */ +#define USBFSH_BASE (0x400A2000u) +/** Peripheral USBFSH base pointer */ +#define USBFSH ((USBFSH_Type *)USBFSH_BASE) +/** Array initializer of USBFSH peripheral base addresses */ +#define USBFSH_BASE_ADDRS { USBFSH_BASE } +/** Array initializer of USBFSH peripheral base pointers */ +#define USBFSH_BASE_PTRS { USBFSH } +/** Interrupt vectors for the USBFSH peripheral type */ +#define USBFSH_IRQS { USB0_IRQn } +#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBFSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer + * @{ + */ + +/** USBHSD - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __I uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */ +} USBHSD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSD_Register_Masks USBHSD Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) +#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) +#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U) +#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U) +#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) +#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) +#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) +#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) +#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) +#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) +#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) +#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) +#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) +#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) +#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) +#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) + +/*! @name INFO - USB Info register */ +#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) +#define USBHSD_INFO_FRAME_NR_SHIFT (0U) +#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) +#define USBHSD_INFO_ERR_CODE_MASK (0x7800U) +#define USBHSD_INFO_ERR_CODE_SHIFT (11U) +#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) +#define USBHSD_INFO_Minrev_MASK (0xFF0000U) +#define USBHSD_INFO_Minrev_SHIFT (16U) +#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK) +#define USBHSD_INFO_Majrev_MASK (0xFF000000U) +#define USBHSD_INFO_Majrev_SHIFT (24U) +#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK) + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) +#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) +#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) + +/*! @name DATABUFSTART - USB Data buffer start address */ +#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) +#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) +#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) + +/*! @name LPM - USB Link Power Management register */ +#define USBHSD_LPM_HIRD_HW_MASK (0xFU) +#define USBHSD_LPM_HIRD_HW_SHIFT (0U) +#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) +#define USBHSD_LPM_HIRD_SW_MASK (0xF0U) +#define USBHSD_LPM_HIRD_SW_SHIFT (4U) +#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) +#define USBHSD_LPM_DATA_PENDING_MASK (0x100U) +#define USBHSD_LPM_DATA_PENDING_SHIFT (8U) +#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) + +/*! @name EPSKIP - USB Endpoint skip */ +#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) +#define USBHSD_EPSKIP_SKIP_SHIFT (0U) +#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +#define USBHSD_EPINUSE_BUF_MASK (0xFFCU) +#define USBHSD_EPINUSE_BUF_SHIFT (2U) +#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) +#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) + +/*! @name INTSTAT - USB interrupt status register */ +#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) +#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) +#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) +#define USBHSD_INTSTAT_EP0IN_MASK (0x2U) +#define USBHSD_INTSTAT_EP0IN_SHIFT (1U) +#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) +#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) +#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) +#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) +#define USBHSD_INTSTAT_EP1IN_MASK (0x8U) +#define USBHSD_INTSTAT_EP1IN_SHIFT (3U) +#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) +#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) +#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) +#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) +#define USBHSD_INTSTAT_EP2IN_MASK (0x20U) +#define USBHSD_INTSTAT_EP2IN_SHIFT (5U) +#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) +#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) +#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) +#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) +#define USBHSD_INTSTAT_EP3IN_MASK (0x80U) +#define USBHSD_INTSTAT_EP3IN_SHIFT (7U) +#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) +#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) +#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) +#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) +#define USBHSD_INTSTAT_EP4IN_MASK (0x200U) +#define USBHSD_INTSTAT_EP4IN_SHIFT (9U) +#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) +#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) +#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) +#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) +#define USBHSD_INTSTAT_EP5IN_MASK (0x800U) +#define USBHSD_INTSTAT_EP5IN_SHIFT (11U) +#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) +#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) +#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) +#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) +#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) + +/*! @name INTEN - USB interrupt enable register */ +#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) +#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) +#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) +#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) +#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) +#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) + +/*! @name INTSETSTAT - USB set interrupt status register */ +#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) +#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) +#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) +#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) + +/*! @name ULPIDEBUG - UTMI/ULPI debug register */ +#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU) +#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U) +#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK) +#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U) +#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U) +#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK) +#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U) +#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U) +#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK) +#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U) +#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U) +#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK) +#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U) +#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U) +#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK) +#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U) +#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U) +#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK) + + +/*! + * @} + */ /* end of group USBHSD_Register_Masks */ + + +/* USBHSD - Peripheral instance base addresses */ +/** Peripheral USBHSD base address */ +#define USBHSD_BASE (0x40094000u) +/** Peripheral USBHSD base pointer */ +#define USBHSD ((USBHSD_Type *)USBHSD_BASE) +/** Array initializer of USBHSD peripheral base addresses */ +#define USBHSD_BASE_ADDRS { USBHSD_BASE } +/** Array initializer of USBHSD peripheral base pointers */ +#define USBHSD_BASE_PTRS { USBHSD } +/** Interrupt vectors for the USBHSD peripheral type */ +#define USBHSD_IRQS { USB1_IRQn } +#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer + * @{ + */ + +/** USBHSH - Register Layout Typedef */ +typedef struct { + __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ + __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ + __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ + __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ + __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ + __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ + __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ + __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ + __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ + __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ + __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */ + __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */ + __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */ + __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */ + __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */ + __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */ + __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ + __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */ + __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ +} USBHSH_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSH_Register_Masks USBHSH Register Masks + * @{ + */ + +/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) +#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) +#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) +#define USBHSH_HCSPARAMS_PPC_MASK (0x10U) +#define USBHSH_HCSPARAMS_PPC_SHIFT (4U) +#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) +#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) +#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) +#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) +#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) +#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) + +/*! @name FLADJ_FRINDEX - Frame Length Adjustment */ +#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) +#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) +#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) +#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) + +/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */ +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U) +#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK) + +/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */ +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U) +#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK) + +/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */ +#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK) +#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U) +#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK) + +/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */ +#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U) +#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U) +#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK) + +/*! @name USBCMD - USB Command register */ +#define USBHSH_USBCMD_RS_MASK (0x1U) +#define USBHSH_USBCMD_RS_SHIFT (0U) +#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) +#define USBHSH_USBCMD_HCRESET_MASK (0x2U) +#define USBHSH_USBCMD_HCRESET_SHIFT (1U) +#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) +#define USBHSH_USBCMD_FLS_MASK (0xCU) +#define USBHSH_USBCMD_FLS_SHIFT (2U) +#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) +#define USBHSH_USBCMD_LHCR_MASK (0x80U) +#define USBHSH_USBCMD_LHCR_SHIFT (7U) +#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) +#define USBHSH_USBCMD_ATL_EN_MASK (0x100U) +#define USBHSH_USBCMD_ATL_EN_SHIFT (8U) +#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) +#define USBHSH_USBCMD_ISO_EN_MASK (0x200U) +#define USBHSH_USBCMD_ISO_EN_SHIFT (9U) +#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) +#define USBHSH_USBCMD_INT_EN_MASK (0x400U) +#define USBHSH_USBCMD_INT_EN_SHIFT (10U) +#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) +#define USBHSH_USBCMD_HIRD_MASK (0xF000000U) +#define USBHSH_USBCMD_HIRD_SHIFT (24U) +#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) +#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) +#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) +#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) + +/*! @name USBSTS - USB Interrupt Status register */ +#define USBHSH_USBSTS_PCD_MASK (0x4U) +#define USBHSH_USBSTS_PCD_SHIFT (2U) +#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) +#define USBHSH_USBSTS_FLR_MASK (0x8U) +#define USBHSH_USBSTS_FLR_SHIFT (3U) +#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) +#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) +#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) +#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) +#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) +#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) +#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) +#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) +#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) +#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) +#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) +#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) +#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) + +/*! @name USBINTR - USB Interrupt Enable register */ +#define USBHSH_USBINTR_PCDE_MASK (0x4U) +#define USBHSH_USBINTR_PCDE_SHIFT (2U) +#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) +#define USBHSH_USBINTR_FLRE_MASK (0x8U) +#define USBHSH_USBINTR_FLRE_SHIFT (3U) +#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) +#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) +#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) +#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) +#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) +#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) +#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) +#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) +#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) +#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) +#define USBHSH_USBINTR_SOF_E_MASK (0x80000U) +#define USBHSH_USBINTR_SOF_E_SHIFT (19U) +#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) + +/*! @name PORTSC1 - Port Status and Control register */ +#define USBHSH_PORTSC1_CCS_MASK (0x1U) +#define USBHSH_PORTSC1_CCS_SHIFT (0U) +#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) +#define USBHSH_PORTSC1_CSC_MASK (0x2U) +#define USBHSH_PORTSC1_CSC_SHIFT (1U) +#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) +#define USBHSH_PORTSC1_PED_MASK (0x4U) +#define USBHSH_PORTSC1_PED_SHIFT (2U) +#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) +#define USBHSH_PORTSC1_PEDC_MASK (0x8U) +#define USBHSH_PORTSC1_PEDC_SHIFT (3U) +#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) +#define USBHSH_PORTSC1_OCA_MASK (0x10U) +#define USBHSH_PORTSC1_OCA_SHIFT (4U) +#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) +#define USBHSH_PORTSC1_OCC_MASK (0x20U) +#define USBHSH_PORTSC1_OCC_SHIFT (5U) +#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) +#define USBHSH_PORTSC1_FPR_MASK (0x40U) +#define USBHSH_PORTSC1_FPR_SHIFT (6U) +#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) +#define USBHSH_PORTSC1_SUSP_MASK (0x80U) +#define USBHSH_PORTSC1_SUSP_SHIFT (7U) +#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) +#define USBHSH_PORTSC1_PR_MASK (0x100U) +#define USBHSH_PORTSC1_PR_SHIFT (8U) +#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) +#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) +#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) +#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) +#define USBHSH_PORTSC1_LS_MASK (0xC00U) +#define USBHSH_PORTSC1_LS_SHIFT (10U) +#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) +#define USBHSH_PORTSC1_PP_MASK (0x1000U) +#define USBHSH_PORTSC1_PP_SHIFT (12U) +#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) +#define USBHSH_PORTSC1_PIC_MASK (0xC000U) +#define USBHSH_PORTSC1_PIC_SHIFT (14U) +#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) +#define USBHSH_PORTSC1_PTC_MASK (0xF0000U) +#define USBHSH_PORTSC1_PTC_SHIFT (16U) +#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) +#define USBHSH_PORTSC1_PSPD_MASK (0x300000U) +#define USBHSH_PORTSC1_PSPD_SHIFT (20U) +#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) +#define USBHSH_PORTSC1_WOO_MASK (0x400000U) +#define USBHSH_PORTSC1_WOO_SHIFT (22U) +#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) +#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) +#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) +#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) +#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) +#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) +#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) + +/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */ +#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U) +#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK) + +/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */ +#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U) +#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK) + +/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */ +#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U) +#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK) + +/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */ +#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U) +#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK) + +/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */ +#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U) +#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK) + +/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */ +#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U) +#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK) + +/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */ +#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU) +#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U) +#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK) +#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U) +#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U) +#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK) +#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U) +#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U) +#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK) + +/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */ +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U) +#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK) + +/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ +#define USBHSH_PORTMODE_ID0_MASK (0x1U) +#define USBHSH_PORTMODE_ID0_SHIFT (0U) +#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK) +#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U) +#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U) +#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK) +#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) +#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) +#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) +#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) +#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) +#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) + + +/*! + * @} + */ /* end of group USBHSH_Register_Masks */ + + +/* USBHSH - Peripheral instance base addresses */ +/** Peripheral USBHSH base address */ +#define USBHSH_BASE (0x400A3000u) +/** Peripheral USBHSH base pointer */ +#define USBHSH ((USBHSH_Type *)USBHSH_BASE) +/** Array initializer of USBHSH peripheral base addresses */ +#define USBHSH_BASE_ADDRS { USBHSH_BASE } +/** Array initializer of USBHSH peripheral base pointers */ +#define USBHSH_BASE_PTRS { USBHSH } +/** Interrupt vectors for the USBHSH peripheral type */ +#define USBHSH_IRQS { USB1_IRQn } +#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USBHSH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) + +/*! @name STAT - Status register. */ +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) + +/*! @name CFG - Capture configuration register. */ +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) + +/*! @name CAPCLR - Capture clear register. */ +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) + +/*! @name CAP - Capture register . */ +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000E000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) + +/*! @name WINDOW - Watchdog Window compare value. */ +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT base address */ +#define WWDT_BASE (0x4000C000u) +/** Peripheral WWDT base pointer */ +#define WWDT ((WWDT_Type *)WWDT_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT } +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** EMC CS base address */ +#define EMC_CS0_BASE (0x80000000u) +#define EMC_CS1_BASE (0x90000000u) +#define EMC_CS2_BASE (0x98000000u) +#define EMC_CS3_BASE (0x9C000000u) +#define EMC_DYCS0_BASE (0xA0000000u) +#define EMC_DYCS1_BASE (0xB0000000u) +#define EMC_DYCS2_BASE (0xC0000000u) +#define EMC_DYCS3_BASE (0xD0000000u) +#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE} +#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE} + +/** OTP API */ +typedef struct { + uint32_t (*otpInit)(void); /** Initializes OTP controller */ + uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */ + uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */ + uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, + uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */ + uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, + uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */ + uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */ + uint32_t RESERVED_0[5]; + uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */ + uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */ +} OTP_API_Type; + +/** ROM API */ +typedef struct { + __I uint32_t usbdApiBase; /** USB API Base */ + uint32_t RESERVED_0[13]; + __I OTP_API_Type *otpApiBase; /** OTP API Base */ + __I uint32_t aesApiBase; /** AES API Base */ + __I uint32_t secureApiBase; /** Secure API Base */ +} ROM_API_Type; + +/** ROM API base address */ +#define ROM_API_BASE (0x03000200u) +/** ROM API base pointer */ +#define ROM_API (*(ROM_API_Type**) ROM_API_BASE) +/** OTP API base pointer */ +#define OTP_API (ROM_API->otpApiBase) + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC54628_H_ */ + diff --git a/fnet_demos/common/startup/LPC54628/LPC54628_features.h b/fnet_demos/common/startup/LPC54628/LPC54628_features.h new file mode 100644 index 00000000..47e7aa8a --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/LPC54628_features.h @@ -0,0 +1,653 @@ +/* +** ################################################################### +** Version: rev. 1.2, 2017-06-08 +** Build: b170609 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-08-12) +** Initial version. +** - rev. 1.1 (2016-11-25) +** Update CANFD and Classic CAN register. +** Add MAC TIMERSTAMP registers. +** - rev. 1.2 (2017-06-08) +** Remove RTC_CTRL_RTC_OSC_BYPASS. +** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. +** Remove RESET and HALT from SYSCON_AHBCLKDIV. +** +** ################################################################### +*/ + +#ifndef _LPC54628_FEATURES_H_ +#define _LPC54628_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (0) +/* @brief ADC_5HC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0) +/* @brief AES availability on the SoC. */ +#define FSL_FEATURE_SOC_AES_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AGC availability on the SoC. */ +#define FSL_FEATURE_SOC_AGC_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AIPSTZ availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPSTZ_COUNT (0) +/* @brief ANATOP availability on the SoC. */ +#define FSL_FEATURE_SOC_ANATOP_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief APBH availability on the SoC. */ +#define FSL_FEATURE_SOC_APBH_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief ASRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASRC_COUNT (0) +/* @brief ASYNC_SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) +/* @brief ATX availability on the SoC. */ +#define FSL_FEATURE_SOC_ATX_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief BCH availability on the SoC. */ +#define FSL_FEATURE_SOC_BCH_COUNT (0) +/* @brief BLEDP availability on the SoC. */ +#define FSL_FEATURE_SOC_BLEDP_COUNT (0) +/* @brief BOD availability on the SoC. */ +#define FSL_FEATURE_SOC_BOD_COUNT (0) +/* @brief CAAM availability on the SoC. */ +#define FSL_FEATURE_SOC_CAAM_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief CALIB availability on the SoC. */ +#define FSL_FEATURE_SOC_CALIB_COUNT (0) +/* @brief CAN availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_CAN_COUNT (2) +/* @brief CAU availability on the SoC. */ +#define FSL_FEATURE_SOC_CAU_COUNT (0) +/* @brief CAU3 availability on the SoC. */ +#define FSL_FEATURE_SOC_CAU3_COUNT (0) +/* @brief CCM availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_COUNT (0) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (0) +/* @brief CHRG availability on the SoC. */ +#define FSL_FEATURE_SOC_CHRG_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (0) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (0) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief COP availability on the SoC. */ +#define FSL_FEATURE_SOC_COP_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CS availability on the SoC. */ +#define FSL_FEATURE_SOC_CS_COUNT (0) +/* @brief CSI availability on the SoC. */ +#define FSL_FEATURE_SOC_CSI_COUNT (0) +/* @brief CT32B availability on the SoC. */ +#define FSL_FEATURE_SOC_CT32B_COUNT (0) +/* @brief CTI availability on the SoC. */ +#define FSL_FEATURE_SOC_CTI_COUNT (0) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (0) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (0) +/* @brief DCP availability on the SoC. */ +#define FSL_FEATURE_SOC_DCP_COUNT (0) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DDRC availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_COUNT (0) +/* @brief DDRC_MP availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0) +/* @brief DDR_PHY availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (0) +/* @brief DMIC availability on the SoC. */ +#define FSL_FEATURE_SOC_DMIC_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (0) +/* @brief ECSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_ECSPI_COUNT (0) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (0) +/* @brief EEPROM availability on the SoC. */ +#define FSL_FEATURE_SOC_EEPROM_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (0) +/* @brief EMC availability on the SoC. */ +#define FSL_FEATURE_SOC_EMC_COUNT (1) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_ENET_COUNT (1) +/* @brief EPDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EPDC_COUNT (0) +/* @brief EPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_EPIT_COUNT (0) +/* @brief ESAI availability on the SoC. */ +#define FSL_FEATURE_SOC_ESAI_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (0) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FLEXRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXRAM_COUNT (0) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FSP availability on the SoC. */ +#define FSL_FEATURE_SOC_FSP_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (0) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_COUNT (0) +/* @brief GPC_PGC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief GPMI availability on the SoC. */ +#define FSL_FEATURE_SOC_GPMI_COUNT (0) +/* @brief GPT availability on the SoC. */ +#define FSL_FEATURE_SOC_GPT_COUNT (0) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (10) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief IEE availability on the SoC. */ +#define FSL_FEATURE_SOC_IEE_COUNT (0) +/* @brief IEER availability on the SoC. */ +#define FSL_FEATURE_SOC_IEER_COUNT (0) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (0) +/* @brief II2C availability on the SoC. */ +#define FSL_FEATURE_SOC_II2C_COUNT (0) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief IOMUXC availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_COUNT (0) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (0) +/* @brief IOMUXC_LPSR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0) +/* @brief IOMUXC_LPSR_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0) +/* @brief IOMUXC_SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (0) +/* @brief IPWM availability on the SoC. */ +#define FSL_FEATURE_SOC_IPWM_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief IUART availability on the SoC. */ +#define FSL_FEATURE_SOC_IUART_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief KPP availability on the SoC. */ +#define FSL_FEATURE_SOC_KPP_COUNT (0) +/* @brief L2CACHEC availability on the SoC. */ +#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0) +/* @brief LCD availability on the SoC. */ +#define FSL_FEATURE_SOC_LCD_COUNT (1) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LCDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDIF_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (0) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (0) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (0) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (0) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (0) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (0) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (0) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (0) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (0) +/* @brief MIPI_CSI2 availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0) +/* @brief MIPI_DSI availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0) +/* @brief MIPI_DSI_HOST availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief MMDC availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDC_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (0) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (0) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (0) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OCOTP availability on the SoC. */ +#define FSL_FEATURE_SOC_OCOTP_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PCIE_PHY_CMN availability on the SoC. */ +#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0) +/* @brief PCIE_PHY_TRSV availability on the SoC. */ +#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (0) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (0) +/* @brief PMU availability on the SoC. */ +#define FSL_FEATURE_SOC_PMU_COUNT (0) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (0) +/* @brief PROP availability on the SoC. */ +#define FSL_FEATURE_SOC_PROP_COUNT (0) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief PXP availability on the SoC. */ +#define FSL_FEATURE_SOC_PXP_COUNT (0) +/* @brief QDEC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDEC_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (0) +/* @brief RDC availability on the SoC. */ +#define FSL_FEATURE_SOC_RDC_COUNT (0) +/* @brief RDC_SEMAPHORE availability on the SoC. */ +#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (0) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RIT availability on the SoC. */ +#define FSL_FEATURE_SOC_RIT_COUNT (1) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (0) +/* @brief ROMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ROMC_COUNT (0) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (0) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (1) +/* @brief SDIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIO_COUNT (0) +/* @brief SDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMA_COUNT (0) +/* @brief SDMAARM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMAARM_COUNT (0) +/* @brief SDMABP availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMABP_COUNT (0) +/* @brief SDMACORE availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMACORE_COUNT (0) +/* @brief SDMCORE availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMCORE_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA4 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA4_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SHA availability on the SoC. */ +#define FSL_FEATURE_SOC_SHA_COUNT (1) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (0) +/* @brief SJC availability on the SoC. */ +#define FSL_FEATURE_SOC_SJC_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief SMARTCARD availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (0) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (0) +/* @brief SPBA availability on the SoC. */ +#define FSL_FEATURE_SOC_SPBA_COUNT (0) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (0) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (10) +/* @brief SPIFI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPIFI_COUNT (1) +/* @brief SPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SPM_COUNT (0) +/* @brief SRC availability on the SoC. */ +#define FSL_FEATURE_SOC_SRC_COUNT (0) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief TEMPMON availability on the SoC. */ +#define FSL_FEATURE_SOC_TEMPMON_COUNT (0) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (0) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (0) +/* @brief TSC availability on the SoC. */ +#define FSL_FEATURE_SOC_TSC_COUNT (0) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (0) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (10) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (0) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (1) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief USB_HSIC availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0) +/* @brief USB_OTG availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_OTG_COUNT (0) +/* @brief USBVREG availability on the SoC. */ +#define FSL_FEATURE_SOC_USBVREG_COUNT (0) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (0) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VIU availability on the SoC. */ +#define FSL_FEATURE_SOC_VIU_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (0) +/* @brief VFIFO availability on the SoC. */ +#define FSL_FEATURE_SOC_VFIFO_COUNT (0) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (0) +/* @brief WKPU availability on the SoC. */ +#define FSL_FEATURE_SOC_WKPU_COUNT (0) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (0) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief XTALOSC availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC_COUNT (0) +/* @brief XTALOSC24M availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (0) + +/* CAN module features */ + +/* @brief Support CANFD or not */ +#define FSL_FEATURE_CAN_SUPPORT_CANFD (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) + +/* EEPROM module features */ + +/* @brief Size of the EEPROM */ +#define FSL_FEATURE_EEPROM_SIZE (0x00004000) +/* @brief Base address of the EEPROM */ +#define FSL_FEATURE_EEPROM_BASE_ADDRESS (0x40108000) +/* @brief Page count of the EEPROM */ +#define FSL_FEATURE_EEPROM_PAGE_COUNT (128) +/* @brief Command number for eeprom program */ +#define FSL_FEATURE_EEPROM_PROGRAM_CMD (6) +/* @brief EEPROM internal clock freqency */ +#define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) + +/* SDIF module features */ + +/* @brief FIFO depth, every location is a WORD */ +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +/* @brief Max DMA buffer size */ +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +/* @brief Max source clock in HZ */ +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) + +/* SPIFI module features */ + +/* @brief SPIFI start address */ +#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000) +/* @brief SPIFI end address */ +#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF) + +/* SYSCON module features */ + +/* @brief Pointer to ROM IAP entry functions */ +#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) + +/* USB module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (0x00002000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) + +/* USBFSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) + +/* USBHSD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) + +/* USBHSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) + +#endif /* _LPC54628_FEATURES_H_ */ + diff --git a/fnet_demos/common/startup/LPC54628/board.c b/fnet_demos/common/startup/LPC54628/board.c new file mode 100644 index 00000000..a4c060fd --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/board.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if 1 //DM + +#include "board.h" +#include +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_emc.h" +#include "pin_mux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* The SDRAM timing. */ +#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */ +#define SDRAM_TRP_NS (18u) +#define SDRAM_TRAS_NS (42u) +#define SDRAM_TSREX_NS (67u) +#define SDRAM_TAPR_NS (18u) +#define SDRAM_TWRDELT_NS (6u) +#define SDRAM_TRC_NS (60u) +#define SDRAM_RFC_NS (60u) +#define SDRAM_XSR_NS (67u) +#define SDRAM_RRD_NS (12u) +#define SDRAM_MRD_NCLK (2u) +#define SDRAM_RAS_NCLK (2u) +#define SDRAM_MODEREG_VALUE (0x23u) +#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Clock rate on the CLKIN pin */ +const uint32_t ExtClockIn = BOARD_EXTCLKINRATE; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize the external memory. */ +void BOARD_InitSDRAM(void) +{ + emc_basic_config_t basicConfig; + emc_dynamic_timing_config_t dynTiming; + emc_dynamic_chip_config_t dynChipConfig; + + /* Basic configuration. */ + basicConfig.endian = kEMC_LittleEndian; + basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk; + /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M. + * If you change the divide to 0 and EMC clock is larger than 100M + * please take refer to emc.dox to adjust EMC clock delay. + */ + basicConfig.emcClkDiv = 1; + /* Dynamic memory timing configuration. */ + dynTiming.readConfig = kEMC_Cmddelay; + dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS; + dynTiming.tRp_Ns = SDRAM_TRP_NS; + dynTiming.tRas_Ns = SDRAM_TRAS_NS; + dynTiming.tSrex_Ns = SDRAM_TSREX_NS; + dynTiming.tApr_Ns = SDRAM_TAPR_NS; + dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */ + dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns; + dynTiming.tRc_Ns = SDRAM_TRC_NS; + dynTiming.tRfc_Ns = SDRAM_RFC_NS; + dynTiming.tXsr_Ns = SDRAM_XSR_NS; + dynTiming.tRrd_Ns = SDRAM_RRD_NS; + dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK; + /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */ + dynChipConfig.chipIndex = 0; + dynChipConfig.dynamicDevice = kEMC_Sdram; + dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK; + dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE; + dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */ + dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP; + /* EMC Basic configuration. */ + EMC_Init(EMC, &basicConfig); + /* EMC Dynamc memory configuration. */ + EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1); +} + +void BOARD_InitHardware(void) +{ + CLOCK_EnableClock(kCLOCK_InputMux); + + BOARD_BootClockPLL220M(); +} + +#endif \ No newline at end of file diff --git a/fnet_demos/common/startup/LPC54628/board.h b/fnet_demos/common/startup/LPC54628/board.h new file mode 100644 index 00000000..8a1619c9 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/board.h @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if 1 //DM +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "LPCXPRESSO54628" + +#define BOARD_EXTCLKINRATE (0) + +/*! @brief The UART to use for debug messages. */ +/* TODO: rename UART to USART */ +#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0 +#define BOARD_DEBUG_UART_INSTANCE 0U +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFreq(kCLOCK_Flexcomm0) +#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0 +#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn +#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Flexcomm0 +#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler +#define BOARD_UART_IRQ FLEXCOMM0_IRQn +/* TODO: obsolete */ +#define BOARD_DEBUG_SPI_CLK_FREQ 12000000 + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE 115200 +#endif /* BOARD_DEBUG_UART_BAUDRATE */ + +/*! @brief The ENET PHY address. */ +#define BOARD_ENET0_PHY_ADDRESS (0x00U) /* Phy address of enet port 0. */ + +#ifndef BOARD_LED1_GPIO +#define BOARD_LED1_GPIO GPIO +#endif +#define BOARD_LED1_GPIO_PORT 3U +#ifndef BOARD_LED1_GPIO_PIN +#define BOARD_LED1_GPIO_PIN 14U +#endif +#ifndef BOARD_LED2_GPIO +#define BOARD_LED2_GPIO GPIO +#endif +#define BOARD_LED2_GPIO_PORT 3U +#ifndef BOARD_LED2_GPIO_PIN +#define BOARD_LED2_GPIO_PIN 3U +#endif +#ifndef BOARD_LED3_GPIO +#define BOARD_LED3_GPIO GPIO +#endif +#define BOARD_LED3_GPIO_PORT 2U +#ifndef BOARD_LED3_GPIO_PIN +#define BOARD_LED3_GPIO_PIN 2U +#endif + +#ifndef BOARD_SW1_GPIO +#define BOARD_SW1_GPIO GPIO +#endif +#define BOARD_SW1_GPIO_PORT 0U +#ifndef BOARD_SW1_GPIO_PIN +#define BOARD_SW1_GPIO_PIN 4U +#endif +#define BOARD_SW1_NAME "SW1" +#define BOARD_SW3_IRQ PIN_INT0_IRQn +#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler + +#ifndef BOARD_SW2_GPIO +#define BOARD_SW2_GPIO GPIO +#endif +#define BOARD_SW2_GPIO_PORT 0U +#ifndef BOARD_SW2_GPIO_PIN +#define BOARD_SW2_GPIO_PIN 6U +#endif +#define BOARD_SW2_NAME "SW2" +#define BOARD_SW2_IRQ PIN_INT0_IRQn +#define BOARD_SW2_IRQ_HANDLER PIN_INT0_IRQHandler + +#ifndef BOARD_SW3_GPIO +#define BOARD_SW3_GPIO GPIO +#endif +#define BOARD_SW3_GPIO_PORT 0U +#ifndef BOARD_SW3_GPIO_PIN +#define BOARD_SW3_GPIO_PIN 5U +#endif +#define BOARD_SW3_NAME "SW3" +#define BOARD_SW3_IRQ PIN_INT0_IRQn +#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler +#define BOARD_SW3_GPIO_PININT_INDEX 0 + +#ifndef BOARD_SW4_GPIO +#define BOARD_SW4_GPIO GPIO +#endif +#ifndef BOARD_SW4_GPIO_PORT +#define BOARD_SW4_GPIO_PORT 0U +#endif +#ifndef BOARD_SW4_GPIO_PIN +#define BOARD_SW4_GPIO_PIN 4U +#endif +#define BOARD_SW4_NAME "SW4" +#define BOARD_SW4_IRQ PIN_INT0_IRQn +#define BOARD_SW4_IRQ_HANDLER PIN_INT0_IRQHandler +#define BOARD_SW4_GPIO_PININT_INDEX 0 + +#ifndef BOARD_SW5_GPIO +#define BOARD_SW5_GPIO GPIO +#endif +#ifndef BOARD_SW5_GPIO_PORT +#define BOARD_SW5_GPIO_PORT 1U +#endif +#ifndef BOARD_SW5_GPIO_PIN +#define BOARD_SW5_GPIO_PIN 1U +#endif +#define BOARD_SW5_NAME "SW5" +#define BOARD_SW5_IRQ PIN_INT1_IRQn +#define BOARD_SW5_IRQ_HANDLER PIN_INT1_IRQHandler +#define BOARD_SW5_GPIO_PININT_INDEX 0 + +#define BOARD_SDIF_BASEADDR SDIF +#define BOARD_SDIF_CLKSRC kCLOCK_SDio +#define BOARD_SDIF_CLK_FREQ CLOCK_GetFreq(kCLOCK_SDio) +#define BOARD_SDIF_CLK_ATTACH kMCLK_to_SDIO_CLK +#define BOARD_SDIF_IRQ SDIO_IRQn +#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360 +#define BOARD_SD_CARD_DETECT_PIN 10 +#define BOARD_SD_CARD_DETECT_PORT 2 +#define BOARD_SD_CARD_DETECT_GPIO GPIO +#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD + +#define BOARD_SDIF_CD_GPIO_INIT() \ + { \ + CLOCK_EnableClock(kCLOCK_Gpio2); \ + GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \ + } +#define BOARD_SDIF_CD_STATUS() \ + GPIO_ReadPinInput(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN) + +#define BOARD_ARDUINO_INT_IRQ (GINT0_IRQn) +#define BOARD_ARDUINO_I2C_IRQ (FLEXCOMM2_IRQn) +#define BOARD_ARDUINO_I2C_INDEX (2) + +/* Board led color mapping */ +#define LOGIC_LED_ON 0U +#define LOGIC_LED_OFF 1U + +#define LED1_INIT(output) \ + GPIO_PinInit(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, BOARD_LED1_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */ +#define LED1_ON() \ + GPIO_PortClear(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Turn on target LED1 */ +#define LED1_OFF() \ + GPIO_PortSet(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Turn off target LED1 */ +#define LED1_TOGGLE() \ + GPIO_PortToggle(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, \ + 1U << BOARD_LED1_GPIO_PIN) /*!< Toggle on target LED1 */ +#define LED2_INIT(output) \ + GPIO_PinInit(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, BOARD_LED2_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED2 */ +#define LED2_ON() \ + GPIO_PortClear(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Turn on target LED2 */ +#define LED2_OFF() \ + GPIO_PortSet(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Turn off target LED2 */ +#define LED2_TOGGLE() \ + GPIO_PortToggle(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, \ + 1U << BOARD_LED2_GPIO_PIN) /*!< Toggle on target LED2 */ + +#define LED3_INIT(output) \ + GPIO_PinInit(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, BOARD_LED3_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED3 */ +#define LED3_ON() \ + GPIO_PortClear(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Turn on target LED3 */ +#define LED3_OFF() \ + GPIO_PortSet(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Turn off target LED3 */ +#define LED3_TOGGLE() \ + GPIO_PortToggle(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, \ + 1U << BOARD_LED3_GPIO_PIN) /*!< Toggle on target LED3 */ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +status_t BOARD_InitDebugConsole(void); +void BOARD_InitSDRAM(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ + +#endif \ No newline at end of file diff --git a/fnet_demos/common/startup/LPC54628/clock_config.c b/fnet_demos/common/startup/LPC54628/clock_config.c new file mode 100644 index 00000000..967aeaa9 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/clock_config.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Setup voltage for the fastest of the clock outputs + * + * 3. Set up wait states of the flash. + * + * 4. Set up all dividers. + * + * 5. Set up all selectors to provide selected clocks. + */ + +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!ClocksProfile +product: Clocks v1.0 +processor: LPC54628J512 +package_id: LPC54628J512ET180 +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: LPCXpresso54628 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} +settings: +- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF48M +outputs: +- {id: System_clock.outFreq, value: 48 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF48M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} +sources: +- {id: SYSCON.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockPLL180M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockPLL180M +outputs: +- {id: FRO12M_clock.outFreq, value: 12 MHz} +- {id: FROHF_clock.outFreq, value: 48 MHz} +- {id: SYSPLL_clock.outFreq, value: 180 MHz} +- {id: System_clock.outFreq, value: 180 MHz} +settings: +- {id: SYSCON.M_MULT.scale, value: '30', locked: true} +- {id: SYSCON.N_DIV.scale, value: '1', locked: true} +- {id: SYSCON.PDEC.scale, value: '2', locked: true} +- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up} +sources: +- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +void BOARD_BootClockPLL180M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up SYS PLL */ + const pll_setup_t pllSetup = { + .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U), + .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)), + .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)), + .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)), + .pllRate = 180000000U, + .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP}; + CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source from external crystal */ + CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */ + POWER_SetVoltageForFreq( + 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */ + CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */ + + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK; +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL220M ********************* + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL220M +called_from_default_init: true +outputs: +- {id: FRO12M_clock.outFreq, value: 12 MHz} +- {id: FROHF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 220 MHz} +- {id: SYSPLL_clock.outFreq, value: 220 MHz} +- {id: System_clock.outFreq, value: 220 MHz} +settings: +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS} +- {id: SYSCON.M_MULT.scale, value: '110', locked: true} +- {id: SYSCON.N_DIV.scale, value: '3', locked: true} +- {id: SYSCON.PDEC.scale, value: '2', locked: true} +- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL220M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL220M configuration + ******************************************************************************/ +void BOARD_BootClockPLL220M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq(220000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(220000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up SYS PLL */ + const pll_setup_t pllSetup = { + .pllctrl = SYSCON_SYSPLLCTRL_SELI(34U) | SYSCON_SYSPLLCTRL_SELP(31U) | SYSCON_SYSPLLCTRL_SELR(0U), + .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(13243U)), + .pllndec = (SYSCON_SYSPLLNDEC_NDEC(1U)), + .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)), + .pllRate = 220000000U, + .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP + }; + CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/ + CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */ + SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */ + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL220M_CORE_CLOCK; +} + diff --git a/fnet_demos/common/startup/LPC54628/clock_config.h b/fnet_demos/common/startup/LPC54628/clock_config.h new file mode 100644 index 00000000..fd69d085 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/clock_config.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ +#define BOARD_BootClockRUN BOARD_BootClockFROHF48M + + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency:12000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency:48000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency:96000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockPLL180M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL180M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL220M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL220M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL220M_CORE_CLOCK 220000000U /*!< Core clock frequency:220000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockPLL220M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL220M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_clock.c b/fnet_demos/common/startup/LPC54628/fsl_clock.c new file mode 100644 index 00000000..b54c6c5b --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_clock.c @@ -0,0 +1,2292 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_clock.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x8000U) + +#define USB_NVALMAX (0x4U) +#define USB_PVALMAX (0x8U) +#define USB_MVALMAX (0x100U) + +#define PLL_MAX_N_DIV 0x100U +#define USB_PLL_MAX_N_DIV 0x100U + +#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000448U) +#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x0100044CU) +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_MDEC_VAL_P (0U) /*!< MDEC is in bits 16 downto 0 */ +#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P) /*!< NDEC is in bits 9 downto 0 */ +#define PLL_NDEC_VAL_P (0U) /*!< NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */ +#define PLL_MIN_IN_SSMODE (2000000U) +#define PLL_MAX_IN_SSMODE (4000000U) + +/*!< Middle of the range values for spread-spectrum */ +#define PLL_SSCG_MF_FREQ_VALUE 4U +#define PLL_SSCG_MC_COMP_VALUE 2U +#define PLL_SSCG_MR_DEPTH_VALUE 4U +#define PLL_SSCG_DITHER_VALUE 0U + +/*!< USB PLL CCO MAX AND MIN FREQ */ +#define USB_PLL_MIN_CCO_FREQ_MHZ (156000000U) +#define USB_PLL_MAX_CCO_FREQ_MHZ (320000000U) +#define USB_PLL_LOWER_IN_LIMIT (1000000U) /*!< Minimum PLL input rate */ + +#define USB_PLL_MSEL_VAL_P (0U) /*!< MSEL is in bits 7 downto 0 */ +#define USB_PLL_MSEL_VAL_M (0xFFU) +#define USB_PLL_PSEL_VAL_P (8U) /*!< PDEC is in bits 9:8 */ +#define USB_PLL_PSEL_VAL_M (0x3U) +#define USB_PLL_NSEL_VAL_P (10U) /*!< NDEC is in bits 11:10 */ +#define USB_PLL_NSEL_VAL_M (0x3U) + +/*!< SWITCH USB POSTDIVIDER FOR REGITSER WRITING */ +#define SWITCH_USB_PSEL(x) ((x==0x0U) ? 0x1U : (x==0x1U) ? 0x02U : (x==0x2U) ? 0x4U : (x==3U) ? 0x8U : 0U) + +/*!< SYS PLL NDEC reg */ +#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) +/*!< SYS PLL PDEC reg */ +#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) +/*!< SYS PLL MDEC reg */ +#define PLL_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_MDEC_VAL_P) & PLL_MDEC_VAL_M) + +/*!< SYS PLL NSEL reg */ +#define USB_PLL_NSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_NSEL_VAL_M) << USB_PLL_NSEL_VAL_P) +/*!< SYS PLL PSEL reg */ +#define USB_PLL_PSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_PSEL_VAL_M) << USB_PLL_PSEL_VAL_P) +/*!< SYS PLL MSEL reg */ +#define USB_PLL_MSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_MSEL_VAL_M) << USB_PLL_MSEL_VAL_P) + +/*!< FRAC control */ +#define AUDIO_PLL_FRACT_MD_P (0U) +#define AUDIO_PLL_FRACT_MD_INT_P (15U) +#define AUDIO_PLL_FRACT_MD_M (0x7FFFUL << AUDIO_PLL_FRACT_MD_P) +#define AUDIO_PLL_FRACT_MD_INT_M (0x7FUL << AUDIO_PLL_FRACT_MD_INT_P) + +#define AUDIO_PLL_MD_FRACT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_P) & PLL_FRAC_MD_FRACT_M) +#define AUDIO_PLL_MD_INT_SET(value) (((unsigned long)(value) << AUDIO_PLL_FRACT_MD_INT_P) & AUDIO_PLL_FRACT_MD_INT_M) + +/* Saved value of PLL output rate, computed whenever needed to save run-time + computation on each call to retrive the PLL rate. */ +static uint32_t s_Pll_Freq; +static uint32_t s_Usb_Pll_Freq; +static uint32_t s_Audio_Pll_Freq; + + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +const uint32_t g_I2S_Mclk_Freq = 0U; +const uint32_t g_Ext_Clk_Freq = 12000000U; +const uint32_t g_Lcd_Clk_In_Freq = 0U; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Find encoded NDEC value for raw N value, max N = NVALMAX */ +static uint32_t pllEncodeN(uint32_t N); +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC); +/* Find encoded PDEC value for raw P value, max P = PVALMAX */ +static uint32_t pllEncodeP(uint32_t P); +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC); +/* Find encoded MDEC value for raw M value, max M = MVALMAX */ +static uint32_t pllEncodeM(uint32_t M); +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC); +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL NDEC setting */ +static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg); +/* Get postdivider (P) from PLL PDEC setting */ +static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg); +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg); +/* Convert the binary to fractional part */ +static double Binary2Fractional(uint32_t binaryPart); +/* Calculate the powerTimes' power of 2 */ +static uint32_t power2Cal(uint32_t powerTimes); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfig( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup); + +/* Update local PLL rate variable */ +static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup); +static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup); + +static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, + 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Clock Selection for IP */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + bool final_descriptor = false; + uint8_t mux; + uint8_t pos; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->MAINCLKSELA); + + for (i = 0U; (i <= 2U) && (!final_descriptor); i++) + { + connection = (clock_attach_id_t)(connection >> (i * 12U)); /*!< pick up next descriptor */ + mux = (uint8_t)connection; + if (connection) + { + pos = ((connection & 0xf00U) >> 8U) - 1U; + if (mux == CM_ASYNCAPB) + { + SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1); + ASYNC_SYSCON->ASYNCAPBCLKSELA = pos; + } + else + { + pClkSel[mux] = pos; + } + } + else + { + final_descriptor = true; + } + } +} + +/* Set IP Clock Divider */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV); + if (reset) + { + pClkDiv[div_name] = 1U << 29U; + } + if (divided_by_value == 0U) /*!< halt */ + { + pClkDiv[div_name] = 1U << 30U; + } + else + { + pClkDiv[div_name] = (divided_by_value - 1U); + } +} + +/* Set FRO Clocking */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq) +{ + uint32_t usb_adj; + if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) + { + return kStatus_Fail; + } + /* Power up the FRO and set this as the base clock */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); + /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */ + usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT; + if (iFreq > 12000000U) + { + if (iFreq == 96000000U) + { + SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) | + SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | + SYSCON_FROCTRL_HSPDCLK(1); + } + else + { + SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) | + SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | + SYSCON_FROCTRL_HSPDCLK(1); + } + } + else + { + SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK(1); + } + + return 0U; +} + +/* Get CLOCK OUT Clk */ +uint32_t CLOCK_GetClockOutClkFreq(void) +{ + return (SYSCON->CLKOUTSELA == 0U) ? CLOCK_GetCoreSysClkFreq(): + (SYSCON->CLKOUTSELA == 1U) ? CLOCK_GetExtClkFreq(): + (SYSCON->CLKOUTSELA == 2U) ? CLOCK_GetWdtOscFreq(): + (SYSCON->CLKOUTSELA == 3U) ? CLOCK_GetFroHfFreq(): + (SYSCON->CLKOUTSELA == 4U) ? CLOCK_GetPllOutFreq(): + (SYSCON->CLKOUTSELA == 5U) ? CLOCK_GetUsbPllOutFreq(): + (SYSCON->CLKOUTSELA == 6U) ? CLOCK_GetAudioPllOutFreq(): + (SYSCON->CLKOUTSELA == 7U) ? CLOCK_GetOsc32KFreq():0U; +} + +/* Get SPIFI Clk */ +uint32_t CLOCK_GetSpifiClkFreq(void) +{ + return (SYSCON->SPIFICLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): + (SYSCON->SPIFICLKSEL == 1U) ? CLOCK_GetPllOutFreq(): + (SYSCON->SPIFICLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): + (SYSCON->SPIFICLKSEL == 3U) ? CLOCK_GetFroHfFreq(): + (SYSCON->SPIFICLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq(): + (SYSCON->SPIFICLKSEL == 7U) ? 0U:0U; +} + +/* Get ADC Clk */ +uint32_t CLOCK_GetAdcClkFreq(void) +{ + return (SYSCON->ADCCLKSEL == 0U) ? CLOCK_GetFroHfFreq(): + (SYSCON->ADCCLKSEL == 1U) ? CLOCK_GetPllOutFreq(): + (SYSCON->ADCCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): + (SYSCON->ADCCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq(): + (SYSCON->ADCCLKSEL == 7U) ? 0U:0U; +} + +/* Get USB0 Clk */ +uint32_t CLOCK_GetUsb0ClkFreq(void) +{ + return (SYSCON->USB0CLKSEL == 0U) ? CLOCK_GetFroHfFreq(): + (SYSCON->USB0CLKSEL == 1U) ? CLOCK_GetPllOutFreq(): + (SYSCON->USB0CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): + (SYSCON->USB0CLKSEL == 7U) ? 0U:0U; +} + +/* Get USB1 Clk */ +uint32_t CLOCK_GetUsb1ClkFreq(void) +{ + + return (SYSCON->USB1CLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): + (SYSCON->USB1CLKSEL == 1U) ? CLOCK_GetPllOutFreq(): + (SYSCON->USB1CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): + (SYSCON->USB1CLKSEL == 7U) ? 0U:0U; +} + +/* Get MCLK Clk */ +uint32_t CLOCK_GetMclkClkFreq(void) +{ + return (SYSCON->MCLKCLKSEL == 0U) ? CLOCK_GetFroHfFreq() / ((SYSCON->FROHFCLKDIV & 0xffu) + 1U): + (SYSCON->MCLKCLKSEL == 1U) ? CLOCK_GetAudioPllOutFreq(): + (SYSCON->MCLKCLKSEL == 7U) ? 0U:0U; +} + +/* Get SCTIMER Clk */ +uint32_t CLOCK_GetSctClkFreq(void) +{ + return (SYSCON->SCTCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): + (SYSCON->SCTCLKSEL == 1U) ? CLOCK_GetPllOutFreq(): + (SYSCON->SCTCLKSEL == 2U) ? CLOCK_GetFroHfFreq(): + (SYSCON->SCTCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq(): + (SYSCON->SCTCLKSEL == 7U) ? 0U:0U; +} + +/* Get SDIO Clk */ +uint32_t CLOCK_GetSdioClkFreq(void) +{ + return (SYSCON->SDIOCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): + (SYSCON->SDIOCLKSEL == 1U) ? CLOCK_GetPllOutFreq(): + (SYSCON->SDIOCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): + (SYSCON->SDIOCLKSEL == 3U) ? CLOCK_GetFroHfFreq(): + (SYSCON->SDIOCLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq(): + (SYSCON->SDIOCLKSEL == 7U) ? 0U:0U; +} + +/* Get LCD Clk */ +uint32_t CLOCK_GetLcdClkFreq(void) +{ + return (SYSCON->LCDCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): + (SYSCON->LCDCLKSEL == 1U) ? CLOCK_GetLcdClkIn(): + (SYSCON->LCDCLKSEL == 2U) ? CLOCK_GetFroHfFreq(): + (SYSCON->LCDCLKSEL == 3U) ? 0U:0U; +} + +/* Get LCD CLK IN Clk */ +uint32_t CLOCK_GetLcdClkIn(void) +{ + return g_Lcd_Clk_In_Freq; +} + +/* Get FRO 12M Clk */ +uint32_t CLOCK_GetFro12MFreq(void) +{ + return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U; +} + +/* Get EXT OSC Clk */ +uint32_t CLOCK_GetExtClkFreq(void) +{ + return g_Ext_Clk_Freq; +} + +/* Get WATCH DOG Clk */ +uint32_t CLOCK_GetWdtOscFreq(void) +{ + uint8_t freq_sel, div_sel; + if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) + { + return 0U; + } + else + { + div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1; + freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; + return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); + } +} + +/* Get HF FRO Clk */ +uint32_t CLOCK_GetFroHfFreq(void) +{ + return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0 : + !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? 0 : + (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? 96000000U : 48000000U; +} + +/* Get SYSTEM PLL Clk */ +uint32_t CLOCK_GetPllOutFreq(void) +{ + return s_Pll_Freq; +} + +/* Get AUDIO PLL Clk */ +uint32_t CLOCK_GetAudioPllOutFreq(void) +{ + return s_Audio_Pll_Freq; +} + +/* Get USB PLL Clk */ +uint32_t CLOCK_GetUsbPllOutFreq(void) +{ + return s_Usb_Pll_Freq; +} + +/* Get RTC OSC Clk */ +uint32_t CLOCK_GetOsc32KFreq(void) +{ + return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */ +} + +/* Get MAIN Clk */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ? CLOCK_GetFro12MFreq() : + ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ? CLOCK_GetExtClkFreq() : + ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ? CLOCK_GetWdtOscFreq() : + ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ? CLOCK_GetFroHfFreq() : + (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() : + (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U; +} + +/* Get I2S MCLK Clk */ +uint32_t CLOCK_GetI2SMClkFreq(void) +{ + return g_I2S_Mclk_Freq; +} + +/* Get ASYNC APB Clk */ +uint32_t CLOCK_GetAsyncApbClkFreq(void) +{ + async_clock_src_t clkSrc; + uint32_t clkRate; + + clkSrc = CLOCK_GetAsyncApbClkSrc(); + + switch (clkSrc) + { + case kCLOCK_AsyncMainClk: + clkRate = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_AsyncFro12Mhz: + clkRate = CLK_FRO_12MHZ; + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Get FLEXCOMM Clk */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) +{ + return (SYSCON->FCLKSEL[id] == 0U) ? CLOCK_GetFro12MFreq() : + (SYSCON->FCLKSEL[id] == 1U) ? CLOCK_GetFroHfFreq() : + (SYSCON->FCLKSEL[id] == 2U) ? CLOCK_GetPllOutFreq() : + (SYSCON->FCLKSEL[id] == 3U) ? CLOCK_GetI2SMClkFreq() : + (SYSCON->FCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U; +} + +/* Get FRG Clk */ +uint32_t CLOCK_GetFRGInputClock(void) +{ + return (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : + (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() : + (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : + (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U; +} + +/* Set FRG Clk */ +uint32_t CLOCK_SetFRGClock(uint32_t freq) +{ + uint32_t input = CLOCK_GetFRGInputClock(); + uint32_t mul; + + if ((freq > 48000000) || (freq > input) || (input / freq >= 2)) + { + /* FRG output frequency should be less than equal to 48MHz */ + return 0; + } + else + { + mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); + SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK; + return 1; + } +} + +/* Set IP Clk */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_ClockOut: + freq = CLOCK_GetClockOutClkFreq() / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); + break; + case kCLOCK_SpiFi: + freq = CLOCK_GetSpifiClkFreq() / ((SYSCON->SPIFICLKDIV & 0xffU) + 1U ); + break; + case kCLOCK_Adc: + freq = CLOCK_GetAdcClkFreq() / ((SYSCON->ADCCLKDIV & 0xffU) + 1U ); + break; + case kCLOCK_Usb0: + freq = CLOCK_GetUsb0ClkFreq() / ((SYSCON->USB0CLKDIV & 0xffU) + 1U ); + break; + case kCLOCK_Usb1: + freq = CLOCK_GetUsb1ClkFreq() / ((SYSCON->USB1CLKDIV & 0xffU) + 1U ); + break; + case kCLOCK_Mclk: + freq = CLOCK_GetMclkClkFreq() / ((SYSCON->MCLKDIV & 0xffU) + 1U ); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_ExtClk: + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_PllOut: + freq = CLOCK_GetPllOutFreq(); + break; + case kClock_WdtOsc: + freq = CLOCK_GetWdtOscFreq(); + break; + case kCLOCK_Frg: + freq = (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : + (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() : + (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : + (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U; + break; + case kCLOCK_Dmic: + freq = (SYSCON->DMICCLKSEL == 0U) ? CLOCK_GetFro12MFreq() : + (SYSCON->DMICCLKSEL == 1U) ? CLOCK_GetFroHfFreq() : + (SYSCON->DMICCLKSEL == 2U) ? CLOCK_GetPllOutFreq() : + (SYSCON->DMICCLKSEL == 3U) ? CLOCK_GetI2SMClkFreq() : + (SYSCON->DMICCLKSEL == 4U) ? CLOCK_GetCoreSysClkFreq() : + (SYSCON->DMICCLKSEL == 5U) ? CLOCK_GetWdtOscFreq() : 0U; + freq = freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U); + break; + + case kCLOCK_AsyncApbClk: + freq = CLOCK_GetAsyncApbClkFreq(); + break; + case kCLOCK_Sct: + freq = CLOCK_GetSctClkFreq() / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_SDio: + freq = CLOCK_GetSdioClkFreq() / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_EMC: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U) / ((SYSCON->EMCCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_LCD: + freq = CLOCK_GetLcdClkFreq() / ((SYSCON->LCDCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_MCAN0: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN0CLKDIV & 0xffU) + 1U); + break; + case kCLOCK_MCAN1: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN1CLKDIV & 0xffU) + 1U); + break; + case kCLOCK_FlexI2S: + freq = CLOCK_GetI2SMClkFreq(); + break; + case kCLOCK_Flexcomm0: + freq = CLOCK_GetFlexCommClkFreq(0U); + break; + case kCLOCK_Flexcomm1: + freq = CLOCK_GetFlexCommClkFreq(1U); + break; + case kCLOCK_Flexcomm2: + freq = CLOCK_GetFlexCommClkFreq(2U); + break; + case kCLOCK_Flexcomm3: + freq = CLOCK_GetFlexCommClkFreq(3U); + break; + case kCLOCK_Flexcomm4: + freq = CLOCK_GetFlexCommClkFreq(4U); + break; + case kCLOCK_Flexcomm5: + freq = CLOCK_GetFlexCommClkFreq(5U); + break; + case kCLOCK_Flexcomm6: + freq = CLOCK_GetFlexCommClkFreq(6U); + break; + case kCLOCK_Flexcomm7: + freq = CLOCK_GetFlexCommClkFreq(7U); + break; + case kCLOCK_Flexcomm8: + freq = CLOCK_GetFlexCommClkFreq(8U); + break; + case kCLOCK_Flexcomm9: + freq = CLOCK_GetFlexCommClkFreq(9U); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Set the FLASH wait states for the passed frequency */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) +{ + if (iFreq <= 12000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle); + } + else if (iFreq <= 24000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle); + } + else if (iFreq <= 36000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle); + } + else if (iFreq <= 60000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle); + } + else if (iFreq <= 96000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle); + } + else if (iFreq <= 120000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash6Cycle); + } + else if (iFreq <= 144000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash7Cycle); + } + else if (iFreq <= 168000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash8Cycle); + } + else + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash9Cycle); + } +} + +/* Find encoded NDEC value for raw N value, max N = NVALMAX */ +static uint32_t pllEncodeN(uint32_t N) +{ + uint32_t x, i; + + /* Find NDec */ + switch (N) + { + case 0U: + x = 0x3FFU; + break; + + case 1U: + x = 0x302U; + break; + + case 2U: + x = 0x202U; + break; + + default: + x = 0x080U; + for (i = N; i <= NVALMAX; i++) + { + x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); + } + break; + } + + return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P); +} + +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC) +{ + uint32_t n, x, i; + + /* Find NDec */ + switch (NDEC) + { + case 0x3FFU: + n = 0U; + break; + + case 0x302U: + n = 1U; + break; + + case 0x202U: + n = 2U; + break; + + default: + x = 0x080U; + n = 0xFFFFFFFFU; + for (i = NVALMAX; ((i >= 3U) && (n == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); + if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) + { + /* Decoded value of NDEC */ + n = i; + } + } + break; + } + + return n; +} + +/* Find encoded PDEC value for raw P value, max P = PVALMAX */ +static uint32_t pllEncodeP(uint32_t P) +{ + uint32_t x, i; + + /* Find PDec */ + switch (P) + { + case 0U: + x = 0x7FU; + break; + + case 1U: + x = 0x62U; + break; + + case 2U: + x = 0x42U; + break; + + default: + x = 0x10U; + for (i = P; i <= PVALMAX; i++) + { + x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); + } + break; + } + + return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P); +} + +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC) +{ + uint32_t p, x, i; + + /* Find PDec */ + switch (PDEC) + { + case 0x7FU: + p = 0U; + break; + + case 0x62U: + p = 1U; + break; + + case 0x42U: + p = 2U; + break; + + default: + x = 0x10U; + p = 0xFFFFFFFFU; + for (i = PVALMAX; ((i >= 3U) && (p == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); + if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) + { + /* Decoded value of PDEC */ + p = i; + } + } + break; + } + + return p; +} + +/* Find encoded MDEC value for raw M value, max M = MVALMAX */ +static uint32_t pllEncodeM(uint32_t M) +{ + uint32_t i, x; + + /* Find MDec */ + switch (M) + { + case 0U: + x = 0x1FFFFU; + break; + + case 1U: + x = 0x18003U; + break; + + case 2U: + x = 0x10003U; + break; + + default: + x = 0x04000U; + for (i = M; i <= MVALMAX; i++) + { + x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU); + } + break; + } + + return x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P); +} + +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC) +{ + uint32_t m, i, x; + + /* Find MDec */ + switch (MDEC) + { + case 0x1FFFFU: + m = 0U; + break; + + case 0x18003U: + m = 1U; + break; + + case 0x10003U: + m = 2U; + break; + + default: + x = 0x04000U; + m = 0xFFFFFFFFU; + for (i = MVALMAX; ((i >= 3U) && (m == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 1U)) & 1) << 14U) | ((x >> 1U) & 0x3FFFU); + if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC) + { + /* Decoded value of MDEC */ + m = i; + } + } + break; + } + + return m; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + /* bandwidth: compute selP from Multiplier */ + if (M < 60U) + { + *pSelP = (M >> 1U) + 1U; + } + else + { + *pSelP = PVALMAX - 1U; + } + + /* bandwidth: compute selI from Multiplier */ + if (M > 16384U) + { + *pSelI = 1U; + } + else if (M > 8192U) + { + *pSelI = 2U; + } + else if (M > 2048U) + { + *pSelI = 4U; + } + else if (M >= 501U) + { + *pSelI = 8U; + } + else if (M >= 60U) + { + *pSelI = 4U * (1024U / (M + 9U)); + } + else + { + *pSelI = (M & 0x3CU) + 4U; + } + + if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT)) + { + *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT); + } + + *pSelR = 0U; +} + +/* Get predivider (N) from PLL NDEC setting */ +static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U) + { + /* Decode NDEC value to get (N) pre divider */ + preDiv = pllDecodeN(nDecReg & 0x3FFU); + if (preDiv == 0U) + { + preDiv = 1U; + } + } + + /* Adjusted by 1, directi is used to bypass */ + return preDiv; +} + +/* Get postdivider (P) from PLL PDEC setting */ +static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) +{ + uint32_t postDiv = 1U; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U) + { + /* Decode PDEC value to get (P) post divider */ + postDiv = 2U * pllDecodeP(pDecReg & 0x7FU); + if (postDiv == 0U) + { + postDiv = 2U; + } + } + + /* Adjusted by 1, directo is used to bypass */ + return postDiv; +} + +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) +{ + uint32_t mMult = 1U; + + /* Decode MDEC value to get (M) multiplier */ + mMult = pllDecodeM(mDecReg & 0x1FFFFU); + + if (mMult == 0U) + { + mMult = 1U; + } + + return mMult; +} + +/* Calculate the powerTimes' power of 2 */ +static uint32_t power2Cal(uint32_t powerTimes) +{ + if (powerTimes == 0) + return 1; + return 2 * power2Cal(powerTimes - 1); +} + +/* Convert the binary to fractional part */ +static double Binary2Fractional(uint32_t binaryPart) +{ + double fractional = 0; + for (uint32_t i = 0; i <= 14; i++) + { + fractional += (double)((binaryPart >> i) & 0x1U) / (double)power2Cal(15 - i); + } + return fractional; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +/* + * Set PLL output based on desired output rate. + * In this function, the it calculates the PLL setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPllConfigInternal( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup) +{ + uint32_t nDivOutHz, fccoHz, multFccoDiv; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 0U; /* 0 implies post-divider will be disabled */ + pllDirectOutput = 1U; + multFccoDiv = 2U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz)); + + if (a > 20000U) + { + a = (multFccoDiv * finHz) / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv; + + /* Find optimal values for filter */ + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllmdec = + PLL_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) ; + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider)); + pSetup->pllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider)); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) | /* Filter coefficient */ + (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) | /* PLL bypass mode disabled */ + (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */ + + return kStatus_PLL_Success; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +uint32_t gPllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPllConfig( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ( (finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]) ) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = gPllSetupCacheStruct[i].pllctrl; + pSetup->pllndec = gPllSetupCacheStruct[i].pllndec; + pSetup->pllpdec = gPllSetupCacheStruct[i].pllpdec; + pSetup->pllmdec = gPllSetupCacheStruct[i].pllmdec; + retErr = kStatus_PLL_Success; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + /* No cache or did not hit the cache. */ + retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + if (kStatus_PLL_Success == retErr) + { + /* Cache the most recent calulation result into buffer. */ + gFinHzCache[gPllSetupCacheIdx] = finHz; + gFoutHzCache[gPllSetupCacheIdx] = foutHz; + + gPllSetupCacheStruct[gPllSetupCacheIdx].pllctrl = pSetup->pllctrl; + gPllSetupCacheStruct[gPllSetupCacheIdx].pllndec = pSetup->pllndec; + gPllSetupCacheStruct[gPllSetupCacheIdx].pllpdec = pSetup->pllpdec; + gPllSetupCacheStruct[gPllSetupCacheIdx].pllmdec = pSetup->pllmdec; + /* Update the index for next available buffer. */ + gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* Update SYSTEM PLL rate variable */ +static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup); +} + +/* Update AUDIO PLL rate variable */ +static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromSetup(pSetup); +} + +/* Update AUDIO Fractional PLL rate variable */ +static void CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pll_setup_t *pSetup) +{ + s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromFractSetup(pSetup); +} + +/* Update USB PLL rate variable */ +static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup) +{ + s_Usb_Pll_Freq = CLOCK_GetUsbPLLOutFromSetup(pSetup); +} + +/* Return System PLL input clock rate */ +uint32_t CLOCK_GetSystemPLLInClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetWdtOscFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return Audio PLL input clock rate */ +uint32_t CLOCK_GetAudioPLLInClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return System PLL output clock rate from setup structure */ +uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) +{ + uint32_t prediv, postdiv, mMult, inPllRate; + uint64_t workRate; + + inPllRate = CLOCK_GetSystemPLLInClockRate(); + /* If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock*/ + if ((pSetup->pllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U) + { + /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ + /* + * 1. Pre-divider + * Pre-divider is only available when the DIRECTI is disabled. + */ + if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK)) + { + prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec); + } + else + { + prediv = 1U; /* The pre-divider is bypassed. */ + } + /* + * 2. Post-divider + * Post-divider is only available when the DIRECTO is disabled. + */ + if (0U == (pSetup->pllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK)) + { + postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec); + } + else + { + postdiv = 1U; /* The post-divider is bypassed. */ + } + /* Adjust input clock */ + inPllRate = inPllRate / prediv; + + /* MDEC used for rate */ + mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec); + workRate = (uint64_t)inPllRate * (uint64_t)mMult; + + workRate = workRate / ((uint64_t)postdiv); + workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/ + + } + else + { + /* In bypass mode */ + workRate = (uint64_t)inPllRate; + } + + return (uint32_t)workRate; +} + +/* Return Usb PLL output clock rate from setup structure */ +uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup) +{ + uint32_t nsel, psel, msel, inPllRate; + uint64_t workRate; + inPllRate = CLOCK_GetExtClkFreq(); + msel = pSetup->msel; + psel = pSetup->psel; + nsel = pSetup->nsel; + + if (pSetup->fbsel == 1U) + { + /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */ + workRate = (inPllRate) * (msel + 1U) / (nsel + 1U); + } + else + { + /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */ + workRate = (inPllRate / (nsel + 1U)) * (msel + 1U) / (2U * SWITCH_USB_PSEL(psel)); + } + + return (uint32_t)workRate; +} + +/* Return Audio PLL output clock rate from setup structure */ +uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup) +{ + uint32_t prediv, postdiv, mMult, inPllRate; + uint64_t workRate; + + inPllRate = CLOCK_GetAudioPLLInClockRate(); + if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U) + { + /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ + /* + * 1. Pre-divider + * Pre-divider is only available when the DIRECTI is disabled. + */ + if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK)) + { + prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec); + } + else + { + prediv = 1U; /* The pre-divider is bypassed. */ + } + /* + * 2. Post-divider + * Post-divider is only available when the DIRECTO is disabled. + */ + if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK)) + { + postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec); + } + else + { + postdiv = 1U; /* The post-divider is bypassed. */ + } + /* Adjust input clock */ + inPllRate = inPllRate / prediv; + + /* MDEC used for rate */ + mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec); + workRate = (uint64_t)inPllRate * (uint64_t)mMult; + + workRate = workRate / ((uint64_t)postdiv); + workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/ + } + else + { + /* In bypass mode */ + workRate = (uint64_t)inPllRate; + } + + return (uint32_t)workRate; +} + +/* Return Audio PLL output clock rate from audio fractioanl setup structure */ +uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup) +{ + uint32_t prediv, postdiv, inPllRate; + double workRate, mMultFactional; + + inPllRate = CLOCK_GetAudioPLLInClockRate(); + if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U) + { + /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ + /* + * 1. Pre-divider + * Pre-divider is only available when the DIRECTI is disabled. + */ + if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK)) + { + prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec); + } + else + { + prediv = 1U; /* The pre-divider is bypassed. */ + } + /* + * 2. Post-divider + * Post-divider is only available when the DIRECTO is disabled. + */ + if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK)) + { + postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec); + } + else + { + postdiv = 1U; /* The post-divider is bypassed. */ + } + /* Adjust input clock */ + inPllRate = inPllRate / prediv; + + mMultFactional = (double)(pSetup->audpllfrac >> 15) + (double)Binary2Fractional(pSetup->audpllfrac & 0x7FFFU); + workRate = (double)inPllRate * (double)mMultFactional; + + workRate = workRate / ((double)postdiv); + workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/ + } + else + { + /* In bypass mode */ + workRate = (uint64_t)inPllRate; + } + + return (uint32_t)workRate; +} + +/* Set the current PLL Rate */ +void CLOCK_SetStoredPLLClockRate(uint32_t rate) +{ + s_Pll_Freq = rate; +} + +/* Set the current Audio PLL Rate */ +void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate) +{ + s_Audio_Pll_Freq = rate; +} + +/* Set the current Usb PLL Rate */ +void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate) +{ + s_Usb_Pll_Freq = rate; +} + +/* Return System PLL output clock rate */ +uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll_Freq == 0U)) + { + Setup.pllctrl = SYSCON->SYSPLLCTRL; + Setup.pllndec = SYSCON->SYSPLLNDEC; + Setup.pllpdec = SYSCON->SYSPLLPDEC; + Setup.pllmdec = SYSCON->SYSPLLMDEC; + + CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup); + } + + rate = s_Pll_Freq; + + return rate; +} + +/* Return AUDIO PLL output clock rate */ +uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Audio_Pll_Freq == 0U)) + { + Setup.pllctrl = SYSCON->AUDPLLCTRL; + Setup.pllndec = SYSCON->AUDPLLNDEC; + Setup.pllpdec = SYSCON->AUDPLLPDEC; + Setup.pllmdec = SYSCON->AUDPLLMDEC; + + CLOCK_GetAudioPLLOutFromSetupUpdate(&Setup); + } + + rate = s_Audio_Pll_Freq; + return rate; +} + +/* Return USB PLL output clock rate */ +uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute) +{ + usb_pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Usb_Pll_Freq == 0U)) + { + Setup.msel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_MSEL_SHIFT) & SYSCON_USBPLLCTRL_MSEL_MASK; + Setup.psel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_PSEL_SHIFT) & SYSCON_USBPLLCTRL_PSEL_MASK; + Setup.nsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_NSEL_SHIFT) & SYSCON_USBPLLCTRL_NSEL_MASK; + Setup.fbsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_FBSEL_SHIFT) & SYSCON_USBPLLCTRL_FBSEL_MASK; + Setup.bypass = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_BYPASS_SHIFT) & SYSCON_USBPLLCTRL_BYPASS_MASK; + Setup.direct = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_DIRECT_SHIFT) & SYSCON_USBPLLCTRL_DIRECT_MASK; + CLOCK_GetUsbPLLOutFromSetupUpdate(&Setup); + } + + rate = s_Usb_Pll_Freq; + return rate; +} + +/* Set PLL output based on the passed PLL setup data */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + pll_error_t pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) + { + inRate = pControl->inputRate; + } + else + { + inRate = CLOCK_GetSystemPLLInClockRate(); + } + + /* PLL flag options */ + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup); + pSetup->pllRate = pControl->desiredRate; + return pllError; +} + +/* Set PLL output from PLL setup structure */ +pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) +{ + if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U) + { + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); + } + /* Enable power for PLLs */ + POWER_SetPLL(); + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); + /*!< Set FLASH waitstates for core */ + CLOCK_SetFLASHAccessCyclesForFreq(pSetup->pllRate); + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->SYSPLLCTRL = pSetup->pllctrl; + SYSCON->SYSPLLNDEC = pSetup->pllndec; + SYSCON->SYSPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->SYSPLLPDEC = pSetup->pllpdec; + SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->SYSPLLMDEC = pSetup->pllmdec; + SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */ + + /* Flags for lock or power on */ + if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U) + { + /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ + volatile uint32_t delayX; + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U); + + /* Initialize and power up PLL */ + SYSCON->SYSPLLMDEC = maxCCO; + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + + /* Set mreq to activate */ + SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U); + + /* Delay for 72 uSec @ 12Mhz */ + for (delayX = 0U; delayX < 172U; ++delayX) + { + } + + /* clear mreq to prepare for restoring mreq */ + SYSCON->SYSPLLMDEC = curSSCTRL; + + /* set original value back and activate */ + SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U); + + /* Enable peripheral states by setting low */ + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + } + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + while (CLOCK_IsSystemPLLLocked() == false) + { + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup); + + /* System voltage adjustment, occurs prior to setting main system clock */ + if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) + { + POWER_SetVoltageForFreq(s_Pll_Freq); + } + + return kStatus_PLL_Success; +} + + +/* Set AUDIO PLL output from AUDIO PLL setup structure */ +pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) +{ + if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U) + { + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); + } + /* Enable power VD3 for PLLs */ + POWER_SetPLL(); + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->AUDPLLCTRL = pSetup->pllctrl; + SYSCON->AUDPLLNDEC = pSetup->pllndec; + SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->AUDPLLPDEC = pSetup->pllpdec; + SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->AUDPLLMDEC = pSetup->pllmdec; + SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */ + SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */ + + /* Flags for lock or power on */ + if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U) + { + /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ + volatile uint32_t delayX; + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t curSSCTRL = SYSCON->AUDPLLMDEC & ~(1U << 17U); + + /* Initialize and power up PLL */ + SYSCON->AUDPLLMDEC = maxCCO; + POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL); + + /* Set mreq to activate */ + SYSCON->AUDPLLMDEC = maxCCO | (1U << 17U); + + /* Delay for 72 uSec @ 12Mhz */ + for (delayX = 0U; delayX < 172U; ++delayX) + { + } + + /* clear mreq to prepare for restoring mreq */ + SYSCON->AUDPLLMDEC = curSSCTRL; + + /* set original value back and activate */ + SYSCON->AUDPLLMDEC = curSSCTRL | (1U << 17U); + + /* Enable peripheral states by setting low */ + POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL); + } + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + while (CLOCK_IsAudioPLLLocked() == false) + { + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetAudioPLLOutFromSetupUpdate(pSetup); + + return kStatus_PLL_Success; +} + +/* Set AUDIO PLL output from AUDIO PLL fractional setup structure */ +pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg) +{ + if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U) + { + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); + } + /* Enable power VD3 for PLLs */ + POWER_SetPLL(); + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->AUDPLLCTRL = pSetup->pllctrl; + SYSCON->AUDPLLNDEC = pSetup->pllndec; + SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->AUDPLLPDEC = pSetup->pllpdec; + SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->AUDPLLMDEC = pSetup->pllmdec; + SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(0); /* enable fractional function */ + SYSCON->AUDPLLFRAC = pSetup->audpllfrac; + SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1U << SYSCON_AUDPLLFRAC_REQ_SHIFT); + + /* Enable peripheral states by setting low */ + POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL); + + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + while (CLOCK_IsAudioPLLLocked() == false) + { + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pSetup); + + return kStatus_PLL_Success; +} + +/* Set Audio PLL output based on the passed Audio PLL setup data */ +pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + pll_error_t pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) + { + inRate = pControl->inputRate; + } + else + { + inRate = CLOCK_GetAudioPLLInClockRate(); + } + + /* PLL flag options */ + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup); + pSetup->pllRate = pControl->desiredRate; + return pllError; +} + + + +/* Setup PLL Frequency from pre-calculated value */ +pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) +{ + if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U) + { + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); + } + /* Enable power VD3 for PLLs */ + POWER_SetPLL(); + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); + + /* Write PLL setup data */ + SYSCON->SYSPLLCTRL = pSetup->pllctrl; + SYSCON->SYSPLLNDEC = pSetup->pllndec; + SYSCON->SYSPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->SYSPLLPDEC = pSetup->pllpdec; + SYSCON->SYSPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->SYSPLLMDEC = pSetup->pllmdec; + SYSCON->SYSPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */ + + /* Flags for lock or power on */ + if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) + { + /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ + volatile uint32_t delayX; + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U); + + /* Initialize and power up PLL */ + SYSCON->SYSPLLMDEC = maxCCO; + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + + /* Set mreq to activate */ + SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U); + + /* Delay for 72 uSec @ 12Mhz */ + for (delayX = 0U; delayX < 172U; ++delayX) + { + } + + /* clear mreq to prepare for restoring mreq */ + SYSCON->SYSPLLMDEC = curSSCTRL; + + /* set original value back and activate */ + SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U); + + /* Enable peripheral states by setting low */ + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + } + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + while (CLOCK_IsSystemPLLLocked() == false) + { + } + } + + /* Update current programmed PLL rate var */ + s_Pll_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Setup Audio PLL Frequency from pre-calculated value */ +pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup) +{ + if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U) + { + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); + } + /* Enable power VD3 for PLLs */ + POWER_SetPLL(); + /* Power off Audio PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL); + + /* Write Audio PLL setup data */ + SYSCON->AUDPLLCTRL = pSetup->pllctrl; + SYSCON->AUDPLLFRAC = pSetup->audpllfrac; + SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1U << SYSCON_AUDPLLFRAC_REQ_SHIFT); /* latch */ + SYSCON->AUDPLLNDEC = pSetup->pllndec; + SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_AUDPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->AUDPLLPDEC = pSetup->pllpdec; + SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_AUDPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->AUDPLLMDEC = pSetup->pllmdec; + SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_AUDPLLMDEC_MREQ_SHIFT); /* latch */ + SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */ + + /* Flags for lock or power on */ + if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) + { + /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ + volatile uint32_t delayX; + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U); + + /* Initialize and power up PLL */ + SYSCON->SYSPLLMDEC = maxCCO; + POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL); + + /* Set mreq to activate */ + SYSCON->SYSPLLMDEC = maxCCO | (1U << 17U); + + /* Delay for 72 uSec @ 12Mhz */ + for (delayX = 0U; delayX < 172U; ++delayX) + { + } + + /* clear mreq to prepare for restoring mreq */ + SYSCON->SYSPLLMDEC = curSSCTRL; + + /* set original value back and activate */ + SYSCON->SYSPLLMDEC = curSSCTRL | (1U << 17U); + + /* Enable peripheral states by setting low */ + POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL); + } + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + while (CLOCK_IsAudioPLLLocked() == false) + { + } + } + + /* Update current programmed PLL rate var */ + s_Audio_Pll_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Setup USB PLL Frequency from pre-calculated value */ +pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup) +{ + uint32_t usbpllctrl, fccoHz; + uint8_t msel, psel, nsel; + bool pllDirectInput, pllDirectOutput, pllfbsel; + volatile uint32_t delayX; + + msel = pSetup->msel; + psel = pSetup->psel; + nsel = pSetup->nsel; + pllDirectInput = pSetup->direct; + pllDirectOutput = pSetup->bypass; + pllfbsel = pSetup->fbsel; + + /* Input clock into the PLL cannot be lower than this */ + if (pSetup->inputRate < USB_PLL_LOWER_IN_LIMIT ) + { + return kStatus_PLL_InputTooLow; + } + + if (pllfbsel == 1U) + { + /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */ + fccoHz = (pSetup->inputRate / (nsel + 1U)) * 2 * (msel + 1U) * SWITCH_USB_PSEL(psel) ; + + /* USB PLL CCO out rate cannot be lower than this */ + if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ) + { + return kStatus_PLL_CCOTooLow; + } + /* USB PLL CCO out rate cannot be Higher than this */ + if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ) + { + return kStatus_PLL_CCOTooHigh; + } + } + else + { + /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */ + fccoHz = pSetup->inputRate / (nsel + 1U) * (msel + 1U); + + /* USB PLL CCO out rate cannot be lower than this */ + if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ) + { + return kStatus_PLL_CCOTooLow; + } + /* USB PLL CCO out rate cannot be Higher than this */ + if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ) + { + return kStatus_PLL_CCOTooHigh; + } + } + + /* If configure the USB HOST clock, VD5 power for USB PHY should be enable + before the PLL is working */ + /* Turn on the ext clock for usb pll input */ + CLOCK_Enable_SysOsc(true); + + /* Enable power VD3 for PLLs */ + POWER_SetPLL(); + + /* Power on the VD5 for USB PHY */ + POWER_SetUsbPhy(); + + /* Power off USB PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_USB_PLL); + + /* Write USB PLL setup data */ + usbpllctrl = USB_PLL_NSEL_VAL_SET(nsel) | /* NSEL VALUE */ + USB_PLL_PSEL_VAL_SET(psel) | /* PSEL VALUE */ + USB_PLL_MSEL_VAL_SET(msel) | /* MSEL VALUE */ + (uint32_t)pllDirectInput << SYSCON_USBPLLCTRL_BYPASS_SHIFT | /* BYPASS DISABLE */ + (uint32_t)pllDirectOutput << SYSCON_USBPLLCTRL_DIRECT_SHIFT | /* DIRECTO DISABLE */ + (uint32_t)pllfbsel << SYSCON_USBPLLCTRL_FBSEL_SHIFT; /* FBSEL SELECT */ + + SYSCON->USBPLLCTRL = usbpllctrl; + + POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); + + /* Delay for 72 uSec @ 12Mhz for the usb pll to lock */ + for (delayX = 0U; delayX < 172U; ++delayX) + { + } + + while (CLOCK_IsUsbPLLLocked() == false) + { + } + CLOCK_GetUsbPLLOutFromSetupUpdate(pSetup); + return kStatus_PLL_Success; +} + +/* Set System PLL clock based on the input frequency and multiplier */ +void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) +{ + uint32_t cco_freq = input_freq * multiply_by; + uint32_t pdec = 1U; + uint32_t selr; + uint32_t seli; + uint32_t selp; + uint32_t mdec, ndec; + + uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1); + + while (cco_freq < 275000000U) + { + multiply_by <<= 1U; /* double value in each iteration */ + pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ + cco_freq = input_freq * multiply_by; + } + selr = 0U; + if (multiply_by < 60U) + { + seli = (multiply_by & 0x3cU) + 4U; + selp = (multiply_by >> 1U) + 1U; + } + else + { + selp = 31U; + if (multiply_by > 16384U) + { + seli = 1U; + } + else if (multiply_by > 8192U) + { + seli = 2U; + } + else if (multiply_by > 2048U) + { + seli = 4U; + } + else if (multiply_by >= 501U) + { + seli = 8U; + } + else + { + seli = 4U * (1024U / (multiply_by + 9U)); + } + } + + if (pdec > 1U) + { + directo = 0U; /* use post divider */ + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ + switch (pdec) + { + case 1U: + pdec = 0x62U; /* 1 * 2 */ + break; + case 2U: + pdec = 0x42U; /* 2 * 2 */ + break; + case 4U: + pdec = 0x02U; /* 4 * 2 */ + break; + case 8U: + pdec = 0x0bU; /* 8 * 2 */ + break; + case 16U: + pdec = 0x11U; /* 16 * 2 */ + break; + case 32U: + pdec = 0x08U; /* 32 * 2 */ + break; + default: + pdec = 0x08U; + break; + } + } + + mdec = PLL_MDEC_VAL_SET(pllEncodeM(multiply_by)); + ndec = 0x302U; /* pre divide by 1 (hardcoded) */ + + SYSCON->SYSPLLCTRL = directo | + (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) | + (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT); + SYSCON->SYSPLLPDEC = pdec | (1U << 7U); /* set Pdec value and assert preq */ + SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */ + SYSCON->SYSPLLMDEC = (1U << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */ +} + +/* Enable USB DEVICE FULL SPEED clock */ +bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbd0); + + if (kCLOCK_UsbSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + case 48000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ + SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | + SYSCON_FROCTRL_USBCLKADJ_MASK; + /* Select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*Set the USB PLL as the Usb0 CLK*/ + POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); + + usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; + + CLOCK_SetUsbPLLFreq(&pll_setup); + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false); + CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK); + uint32_t delay = 100000; + while (delay --) + { + __asm("nop"); + } + } + CLOCK_EnableClock(kCLOCK_Usbd0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB HOST FULL SPEED clock */ +bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbhmr0); + CLOCK_DisableClock(kCLOCK_Usbhsl0); + + if (kCLOCK_UsbSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + case 48000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ + SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | + SYSCON_FROCTRL_USBCLKADJ_MASK; + /* Select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); + } + else + { + /*Set the USB PLL as the Usb0 CLK*/ + POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); + + usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; + + CLOCK_SetUsbPLLFreq(&pll_setup); + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false); + CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK); + uint32_t delay = 100000; + while (delay --) + { + __asm("nop"); + } + } + CLOCK_EnableClock(kCLOCK_Usbhmr0); + CLOCK_EnableClock(kCLOCK_Usbhsl0); + CLOCK_EnableClock(kCLOCK_UsbRam1); + + return ret; +} + +/* Enable USB DEVICE HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq) +{ + bool ret = true; + uint32_t delay; + CLOCK_DisableClock(kCLOCK_Usbd1); + /* Power on the VD5 for USB PHY */ + POWER_SetUsbPhy(); + if (kCLOCK_UsbSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + case 48000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ + SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | + SYSCON_FROCTRL_USBCLKADJ_MASK; + /* Select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB1_CLK); + } + else + { + delay = 100000; + while (delay --) + { + __asm("nop"); + } + usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; + + CLOCK_SetUsbPLLFreq(&pll_setup); + + /* Select USB PLL output as USB clock src */ + CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false); + CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK); + } + + delay = 100000; + while (delay --) + { + __asm("nop"); + } + /* Enable USB1D and USB1RAM */ + CLOCK_EnableClock(kCLOCK_Usbd1); + CLOCK_EnableClock(kCLOCK_UsbRam1); + POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */ + return ret; +} + + +/* Enable USB HOST HIGH SPEED clock */ +bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq) +{ + bool ret = true; + uint32_t delay; + CLOCK_DisableClock(kCLOCK_Usbh1); + /* Power on the VD5 for USB PHY */ + POWER_SetUsbPhy(); + if (kCLOCK_UsbSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + + case 48000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ + break; + + default: + ret = false; + break; + } + /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ + SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | + SYSCON_FROCTRL_USBCLKADJ_MASK; + /* Select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB1_CLK); + } + else + { + delay = 100000; + while (delay --) + { + __asm("nop"); + } + usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; + + CLOCK_SetUsbPLLFreq(&pll_setup); + + /* Select USB PLL output as USB clock src */ + CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false); + CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK); + } + + delay = 100000; + while (delay --) + { + __asm("nop"); + } + /* Enable USBh1 and USB1RAM */ + CLOCK_EnableClock(kCLOCK_Usbh1); + CLOCK_EnableClock(kCLOCK_UsbRam1); + POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */ + return ret; +} diff --git a/fnet_demos/common/startup/LPC54628/fsl_clock.h b/fnet_demos/common/startup/LPC54628/fsl_clock.h new file mode 100644 index 00000000..ef0e11c3 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_clock.h @@ -0,0 +1,1301 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name ofcopyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_device_registers.h" +#include +#include +#include + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.0.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could contol the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/*! @brief Clock ip name array for ROM. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_Adc0 \ + } +/*! @brief Clock ip name array for ROM. */ +#define ROM_CLOCKS \ + { \ + kCLOCK_Rom \ + } +/*! @brief Clock ip name array for SRAM. */ +#define SRAM_CLOCKS \ + { \ + kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \ + } +/*! @brief Clock ip name array for FLASH. */ +#define FLASH_CLOCKS \ + { \ + kCLOCK_Flash \ + } +/*! @brief Clock ip name array for FMC. */ +#define FMC_CLOCKS \ + { \ + kCLOCK_Fmc \ + } +/*! @brief Clock ip name array for EEPROM. */ +#define EEPROM_CLOCKS \ + { \ + kCLOCK_Eeprom \ + } +/*! @brief Clock ip name array for SPIFI. */ +#define SPIFI_CLOCKS \ + { \ + kCLOCK_Spifi \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux \ + } +/*! @brief Clock ip name array for IOCON. */ +#define IOCON_CLOCKS \ + { \ + kCLOCK_Iocon \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0,kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + } +/*! @brief Clock ip name array for PINT. */ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ + } +/*! @brief Clock ip name array for GINT. */ +#define GINT_CLOCKS \ + { \ + kCLOCK_Gint, kCLOCK_Gint \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc \ + } +/*! @brief Clock ip name array for ADC0. */ +#define ADC0_CLOCKS \ + { \ + kCLOCK_Adc0 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for RIT. */ +#define RIT_CLOCKS \ + { \ + kCLOCK_Rit \ + } +/*! @brief Clock ip name array for SCT0. */ +#define SCT_CLOCKS \ + { \ + kCLOCK_Sct0 \ + } +/*! @brief Clock ip name array for MCAN. */ +#define MCAN_CLOCKS \ + { \ + kCLOCK_Mcan0, kCLOCK_Mcan1 \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick \ + } +/*! @brief Clock ip name array for FLEXCOMM. */ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, \ + kCLOCK_FlexComm4, kCLOCK_FlexComm5, kCLOCK_FlexComm6, kCLOCK_FlexComm7, \ + kCLOCK_FlexComm8, kCLOCK_FlexComm9 \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ + kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8,kCLOCK_MinUart9 \ + } + +/*! @brief Clock ip name array for BI2C. */ +#define BI2C_CLOCKS \ + { \ + kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7, \ + kCLOCK_BI2c8, kCLOCK_BI2c9 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSI_CLOCKS \ + { \ + kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7, \ + kCLOCK_LSpi8, kCLOCK_LSpi9 \ + } +/*! @brief Clock ip name array for FLEXI2S. */ +#define FLEXI2S_CLOCKS \ + { \ + kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ + kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \ + } +/*! @brief Clock ip name array for DMIC. */ +#define DMIC_CLOCKS \ + { \ + kCLOCK_DMic \ + } +/*! @brief Clock ip name array for CT32B. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \ + } +/*! @brief Clock ip name array for LCD. */ +#define LCD_CLOCKS \ + { \ + kCLOCK_Lcd \ + } +/*! @brief Clock ip name array for SDIO. */ +#define SDIO_CLOCKS \ + { \ + kCLOCK_Sdio \ + } +/*! @brief Clock ip name array for USBRAM. */ +#define USBRAM_CLOCKS \ + { \ + kCLOCK_UsbRam1 \ + } +/*! @brief Clock ip name array for EMC. */ +#define EMC_CLOCKS \ + { \ + kCLOCK_Emc \ + } +/*! @brief Clock ip name array for ETH. */ +#define ETH_CLOCKS \ + { \ + kCLOCK_Eth \ + } +/*! @brief Clock ip name array for AES. */ +#define AES_CLOCKS \ + { \ + kCLOCK_Aes \ + } +/*! @brief Clock ip name array for OTP. */ +#define OTP_CLOCKS \ + { \ + kCLOCK_Otp \ + } +/*! @brief Clock ip name array for RNG. */ +#define RNG_CLOCKS \ + { \ + kCLOCK_Rng \ + } +/*! @brief Clock ip name array for USBHMR0. */ +#define USBHMR0_CLOCKS \ + { \ + kCLOCK_Usbhmr0 \ + } +/*! @brief Clock ip name array for USBHSL0. */ +#define USBHSL0_CLOCKS \ + { \ + kCLOCK_Usbhsl0 \ + } +/*! @brief Clock ip name array for SHA0. */ +#define SHA0_CLOCKS \ + { \ + kCLOCK_Sha0 \ + } +/*! @brief Clock ip name array for SMARTCARD. */ +#define SMARTCARD_CLOCKS \ + { \ + kCLOCK_SmartCard0, kCLOCK_SmartCard1 \ + } +/*! @brief Clock ip name array for USBD. */ +#define USBD_CLOCKS \ + { \ + kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ + } +/*! @brief Clock ip name array for USBH. */ +#define USBH_CLOCKS \ + { \ + kCLOCK_Usbh1 \ + } +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 +#define ASYNC_CLK_CTRL0 3 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), + kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), + kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), + kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), + kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), + kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), + kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8), + kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), + kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), + kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), + kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), + kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), + kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), + kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), + kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), + kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), + kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), + kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), + kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), + kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2,8), + kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9), + kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10), + kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), + kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12), + kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), + kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), + kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), + kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), + kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), + kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), + + kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13), + kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14) +} clock_ip_name_t; + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_ClockOut, /*!< CLOCKOUT */ + kCLOCK_FroHf, /*!< FRO48/96 */ + kCLOCK_SpiFi, /*!< SPIFI */ + kCLOCK_Adc, /*!< ADC */ + kCLOCK_Usb0, /*!< USB0 */ + kCLOCK_Usb1, /*!< USB1 */ + kCLOCK_UsbPll, /*!< USB1 PLL */ + kCLOCK_Mclk, /*!< MCLK */ + kCLOCK_Sct, /*!< SCT */ + kCLOCK_SDio, /*!< SDIO */ + kCLOCK_EMC, /*!< EMC */ + kCLOCK_LCD, /*!< LCD */ + kCLOCK_MCAN0, /*!< MCAN0 */ + kCLOCK_MCAN1, /*!< MCAN1 */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_PllOut, /*!< PLL Output */ + kCLOCK_UsbClk, /*!< USB input */ + kClock_WdtOsc, /*!< Watchdog Oscillator */ + kCLOCK_Frg, /*!< Frg Clock */ + kCLOCK_Dmic, /*!< Digital Mic clock */ + kCLOCK_AsyncApbClk, /*!< Async APB clock */ + kCLOCK_FlexI2S, /*!< FlexI2S clock */ + kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */ + kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */ + kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */ + kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */ + kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */ + kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */ + kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */ + kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */ + kCLOCK_Flexcomm8, /*!< Flexcomm8Clock */ + kCLOCK_Flexcomm9, /*!< Flexcomm9Clock */ + +} clock_name_t; + +/** + * Clock source selections for the asynchronous APB clock + */ +typedef enum _async_clock_src +{ + kCLOCK_AsyncMainClk = 0, /*!< Main System clock */ + kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */ + kCLOCK_AsyncAudioPllClk, + kCLOCK_AsyncI2cClkFc6, + +} async_clock_src_t; + +/*! @brief Clock Mux Switches +* The encoding is as follows each connection identified is 64bits wide +* starting from LSB upwards +* +* [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]* +* +*/ + +#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8)) +#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20)) +#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32)) +#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44)) +#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56)) + +#define CM_MAINCLKSELA 0 +#define CM_MAINCLKSELB 1 +#define CM_CLKOUTCLKSELA 2 +#define CM_SYSPLLCLKSEL 4 +#define CM_AUDPLLCLKSEL 6 +#define CM_SPIFICLKSEL 8 +#define CM_ADCASYNCCLKSEL 9 +#define CM_USB0CLKSEL 10 +#define CM_USB1CLKSEL 11 +#define CM_FXCOMCLKSEL0 12 +#define CM_FXCOMCLKSEL1 13 +#define CM_FXCOMCLKSEL2 14 +#define CM_FXCOMCLKSEL3 15 +#define CM_FXCOMCLKSEL4 16 +#define CM_FXCOMCLKSEL5 17 +#define CM_FXCOMCLKSEL6 18 +#define CM_FXCOMCLKSEL7 19 +#define CM_FXCOMCLKSEL8 20 +#define CM_FXCOMCLKSEL9 21 +#define CM_MCLKCLKSEL 24 +#define CM_FRGCLKSEL 26 +#define CM_DMICCLKSEL 27 +#define CM_SCTCLKSEL 28 +#define CM_LCDCLKSEL 29 +#define CM_SDIOCLKSEL 30 + +#define CM_ASYNCAPB 31 + +typedef enum _clock_attach_id +{ + + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0), + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0), + kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0), + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0), + kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2), + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3), + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), + kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), + kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), + kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), + kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), + kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), + + kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), + kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), + kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), + kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), + kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), + + kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0), + kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1), + kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7), + + kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0), + kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), + kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2), + kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), + kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4), + kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), + + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), + kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), + kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), + kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), + + kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), + kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), + kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2), + kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), + + kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0), + kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1), + kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2), + kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7), + + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), + kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), + kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), + kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), + + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), + kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), + kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), + kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), + + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), + kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), + kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), + kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), + + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), + kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), + kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), + kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), + + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), + kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), + kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), + kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), + + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), + kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), + kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), + kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), + + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), + kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), + kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), + kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), + + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), + kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), + kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), + kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), + + kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0), + kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1), + kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2), + kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3), + kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4), + kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7), + + kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0), + kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1), + kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2), + kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3), + kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4), + kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7), + + kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), + kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), + kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), + + kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), + kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), + kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), + kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), + kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), + + kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), + kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1), + kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), + kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), + kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), + + kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), + kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), + kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), + kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), + kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), + + kMCLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), + kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), + kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2), + kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), + kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4), + kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), + + kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0), + kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1), + kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2), + kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3), + + kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), + kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), + kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2), + kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3), + kNONE_to_NONE = 0x80000000U, +} clock_attach_id_t; + +/* Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk = 0, + kCLOCK_DivArmTrClkDiv = 1, + kCLOCK_DivCan0Clk = 2, + kCLOCK_DivCan1Clk = 3, + kCLOCK_DivSmartCard0Clk = 4, + kCLOCK_DivSmartCard1Clk = 5, + kCLOCK_DivAhbClk = 32, + kCLOCK_DivClkOut = 33, + kCLOCK_DivFrohfClk = 34, + kCLOCK_DivSpifiClk = 36, + kCLOCK_DivAdcAsyncClk = 37, + kCLOCK_DivUsb0Clk = 38, + kCLOCK_DivUsb1Clk = 39, + kCLOCK_DivFrg = 40, + kCLOCK_DivDmicClk = 42, + kCLOCK_DivMClk = 43, + kCLOCK_DivLcdClk = 44, + kCLOCK_DivSctClk = 45, + kCLOCK_DivEmcClk = 46, + kCLOCK_DivSdioClk = 47 +} clock_div_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + if (index < 3) + { + SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } + else + { + SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1); + ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } +} + +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + if (index < 3) + { + SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } + else + { + ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0); + + } +} +/** + * @brief FLASH Access time definitions + */ +typedef enum _clock_flashtim +{ + kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clocks */ + kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */ + kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */ + kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */ + kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */ + kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */ + kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */ + kCLOCK_Flash8Cycle, /*!< Flash accesses use 8 CPU clocks */ + kCLOCK_Flash9Cycle /*!< Flash accesses use 9 CPU clocks */ +} clock_flashtim_t; + +/** + * @brief Set FLASH memory access time in clocks + * @param clks : Clock cycles for FLASH access + * @return Nothing + */ +static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks) +{ + uint32_t tmp; + + tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK); + + /* Don't alter lower bits */ + SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT); +} + +/** + * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq); +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @param reset : Whether to reset the divider counter. + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); +/** + * @brief Set the flash wait states for the input freuqency. + * @param iFreq : Input frequency + * @return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); +/*! @brief Return Frequency of FRO 12MHz + * @return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void); +/*! @brief Return Frequency of ClockOut + * @return Frequency of ClockOut + */ +uint32_t CLOCK_GetClockOutClkFreq(void); +/*! @brief Return Frequency of Spifi Clock + * @return Frequency of Spifi. + */ +uint32_t CLOCK_GetSpifiClkFreq(void); +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc Clock. + */ +uint32_t CLOCK_GetAdcClkFreq(void); +/*! @brief Return Frequency of Usb0 Clock + * @return Frequency of Usb0 Clock. + */ +uint32_t CLOCK_GetUsb0ClkFreq(void); +/*! @brief Return Frequency of Usb1 Clock + * @return Frequency of Usb1 Clock. + */ +uint32_t CLOCK_GetUsb1ClkFreq(void); +/*! @brief Return Frequency of MClk Clock + * @return Frequency of MClk Clock. + */ +uint32_t CLOCK_GetMclkClkFreq(void); +/*! @brief Return Frequency of SCTimer Clock + * @return Frequency of SCTimer Clock. + */ +uint32_t CLOCK_GetSctClkFreq(void); +/*! @brief Return Frequency of SDIO Clock + * @return Frequency of SDIO Clock. + */ +uint32_t CLOCK_GetSdioClkFreq(void); +/*! @brief Return Frequency of LCD Clock + * @return Frequency of LCD Clock. + */ +uint32_t CLOCK_GetLcdClkFreq(void); +/*! @brief Return Frequency of LCD CLKIN Clock + * @return Frequency of LCD CLKIN Clock. + */ +uint32_t CLOCK_GetLcdClkIn(void); +/*! @brief Return Frequency of External Clock + * @return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void); +/*! @brief Return Frequency of Watchdog Oscillator + * @return Frequency of Watchdog Oscillator + */ +uint32_t CLOCK_GetWdtOscFreq(void); +/*! @brief Return Frequency of High-Freq output of FRO + * @return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPllOutFreq(void); +/*! @brief Return Frequency of USB PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetUsbPllOutFreq(void); +/*! @brief Return Frequency of AUDIO PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetAudioPllOutFreq(void); +/*! @brief Return Frequency of 32kHz osc + * @return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void); +/*! @brief Return Frequency of Core System + * @return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); +/*! @brief Return Frequency of I2S MCLK Clock + * @return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void); +/*! @brief Return Frequency of Flexcomm functional Clock + * @return Frequency of Flexcomm functional Clock + */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); +/*! @brief Return Asynchronous APB Clock source + * @return Asynchronous APB CLock source + */ +__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void) +{ + return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3); +} +/*! @brief Return Frequency of Asynchronous APB Clock + * @return Frequency of Asynchronous APB Clock Clock + */ +uint32_t CLOCK_GetAsyncApbClkFreq(void); +/*! @brief Return Audio PLL input clock rate + * @return Audio PLL input clock rate + */ +uint32_t CLOCK_GetAudioPLLInClockRate(void); +/*! @brief Return System PLL input clock rate + * @return System PLL input clock rate + */ +uint32_t CLOCK_GetSystemPLLInClockRate(void); + +/*! @brief Return System PLL output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return System PLL output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute); + +/*! @brief Return System AUDIO PLL output clock rate + * @param recompute : Forces a AUDIO PLL rate recomputation if true + * @return System AUDIO PLL output clock rate + * @note The AUDIO PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute); + +/*! @brief Return System USB PLL output clock rate + * @param recompute : Forces a USB PLL rate recomputation if true + * @return System USB PLL output clock rate + * @note The USB PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetUSbPLLOutClockRate(bool recompute); + +/*! @brief Enables and disables PLL bypass mode + * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass + * @return System PLL output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass) +{ + if (bypass) + { + SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); + } + else + { + SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); + } +} + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void) +{ + return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0); +} + +/*! @brief Check if USB PLL is locked or not + * @return true if the USB PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void) +{ + return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0); +} + +/*! @brief Check if AUDIO PLL is locked or not + * @return true if the AUDIO PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void) +{ + return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0); +} + +/*! @brief Enables and disables SYS OSC + * @brief enable : true to enable SYS OSC, false to disable SYS OSC +*/ +__STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable) +{ + if(enable) + { + SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK; + SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK; + } + + else + { + SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK; + SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK; + + } +} + +/*! @brief Store the current PLL rate + * @param rate: Current rate of the PLL + * @return Nothing + **/ +void CLOCK_SetStoredPLLClockRate(uint32_t rate); + +/*! @brief Store the current AUDIO PLL rate + * @param rate: Current rate of the PLL + * @return Nothing + **/ +void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate); + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the + * configuration structure must be assigned with the expected PLL frequency. If the + * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration + * function and the driver will determine the PLL rate from the currently selected + * PLL source. This flag might be used to configure the PLL input clock more accurately + * when using the WDT oscillator or a more dyanmic CLKIN source.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT \ + (1 \ + << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \ + \ \ \ \ + \ \ \ \ \ \ + \ \ \ \ \ \ \ \ + hardware */ + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ +} pll_config_t; + +/*! @brief PLL setup structure flags for 'flags' field +* These flags control how the PLL setup function sets up the PLL +*/ +#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ + +/*! @brief PLL setup structure +* This structure can be used to pre-build a PLL setup configuration +* at run-time and quickly set the PLL to the configuration. It can be +* populated with the PLL setup function. If powering up or waiting +* for PLL lock, the PLL input clock source should be configured prior +* to PLL setup. +*/ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */ + uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */ + uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */ + uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */ + uint32_t pllRate; /*!< Acutal PLL rate */ + uint32_t audpllfrac; /*!< only aduio PLL has this function*/ + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */ + kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */ + kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ + kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */ + + kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(7) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */ +} clock_usb_src_t; + +/*! @brief USB PDEL Divider. */ +typedef enum _usb_pll_psel +{ + pSel_Divide_1 = 0U, + pSel_Divide_2, + pSel_Divide_4, + pSel_Divide_8 +}usb_pll_psel; + +/*! @brief PLL setup structure +* This structure can be used to pre-build a USB PLL setup configuration +* at run-time and quickly set the usb PLL to the configuration. It can be +* populated with the USB PLL setup function. If powering up or waiting +* for USB PLL lock, the PLL input clock source should be configured prior +* to USB PLL setup. +*/ +typedef struct _usb_pll_setup +{ + uint8_t msel; /*!< USB PLL control register msel:1U-256U */ + uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */ + uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */ + bool direct; /*!< USB PLL CCO output control */ + bool bypass; /*!< USB PLL inout clock bypass control */ + bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/ + uint32_t inputRate; /*!< USB PLL input rate */ +} usb_pll_setup_t; + +/*! @brief Return System PLL output clock rate from setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup); + +/*! @brief Return System AUDIO PLL output clock rate from setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup); + +/*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup); + +/*! @brief Return System USB PLL output clock rate from setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup); + +/*! @brief Set PLL output based on the passed PLL setup data + * @param pControl : Pointer to populated PLL control structure to generate setup with + * @param pSetup : Pointer to PLL setup structure to be filled + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); + +/*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data + * @param pControl : Pointer to populated PLL control structure to generate setup with + * @param pSetup : Pointer to PLL setup structure to be filled + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup); + +/*! @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure +* @param flagcfg : Flag configuration for PLL config structure + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); + +/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure +* @param flagcfg : Flag configuration for PLL config structure + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock, + * and adjust system voltages to the new AUDIOPLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); + +/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise frequency) + * @param pSetup : Pointer to populated PLL setup structure +* @param flagcfg : Flag configuration for PLL config structure + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock, + * and adjust system voltages to the new AUDIOPLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup); + +/** + * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or Audio PLL setup error code + * @note This function will power off the PLL, setup the Audio PLL with the + * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the Audio PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup); + +/** + * @brief Set USB PLL output from USB PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated USB PLL setup structure + * @return kStatus_PLL_Success on success, or USB PLL setup error code + * @note This function will power off the USB PLL, setup the PLL with the + * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock, + * and adjust system voltages to the new USB PLL rate. The function will not + * alter any source clocks (ie, usb pll clock) that may use the USB PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup); + +/*! @brief Set PLL output based on the multiplier and input frequency + * @param multiply_by : multiplier + * @param input_freq : Clock input frequency of the PLL + * @return Nothing + * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq); + +/*! @brief Disable USB clock. + * + * Disable USB clock. + */ +static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk) +{ + CLOCK_DisableClock(clk); +} + +/*! @brief Enable USB Device FS clock. + * @param src : clock source + * @param freq: clock frequency + * Enable USB Device Full Speed clock. + */ +bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HOST FS clock. + * @param src : clock source + * @param freq: clock frequency + * Enable USB HOST Full Speed clock. + */ +bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB Device HS clock. + * @param src : clock source + * @param freq: clock frequency + * Enable USB Device High Speed clock. + */ +bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HOST HS clock. + * @param src : clock source + * @param freq: clock frequency + * Enable USB HOST High Speed clock. + */ +bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_common.h b/fnet_demos/common/startup/LPC54628/fsl_common.h new file mode 100644 index 00000000..046311d3 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_common.h @@ -0,0 +1,512 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version 2.0.0. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http://supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__ARMCC_VERSION)) +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __align(alignbytes) var +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var +#endif +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif + } + + /*! + * @brief Enaable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_ctimer.c b/fnet_demos/common/startup/LPC54628/fsl_ctimer.c new file mode 100644 index 00000000..7323f510 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_ctimer.c @@ -0,0 +1,386 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ctimer.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to Timer resets for each instance. */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; + +/*! @brief Pointers real ISRs installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (s_ctimerBases[instance] == base) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module */ + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); + + /* Setup the cimer mode and count select */ + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); + + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + DisableIRQ(s_ctimerIRQ[index]); +} + +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +status_t CTIMER_SetupPwm(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0); + + uint32_t reg; + uint32_t period, pulsePeriod = 0; + uint32_t timerClock = srcClock_Hz / (base->PR + 1); + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == kCTIMER_Match_3) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1U << matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = (timerClock / pwmFreq_Hz) - 1; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0) + { + pulsePeriod = period + 1; + } + else + { + pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; + } + + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = period; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) +{ + uint32_t pulsePeriod = 0, period; + + /* Match channel 3 defines the PWM period */ + period = base->MR[kCTIMER_Match_3]; + + /* Calculate pulse width match value */ + pulsePeriod = (period * dutyCyclePercent) / 100; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0) + { + pulsePeriod = period + 1; + } + else + { + pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; + } + + /* Update dutycycle */ + base->MR[matchChannel] = pulsePeriod; +} + +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3))); + reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3))); + reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2)); + reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel); + reg |= (uint32_t)config->outPinInitState << matchChannel; + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + EnableIRQ(s_ctimerIRQ[index]); + } +} + +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3)); + reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3); + EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} + +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0]) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ + { + mask = 0x01 << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if ((int_stat & mask) && (s_ctimerCallback[index][i])) + { + s_ctimerCallback[index][i](int_stat); + } + } + } + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#endif diff --git a/fnet_demos/common/startup/LPC54628/fsl_ctimer.h b/fnet_demos/common/startup/LPC54628/fsl_ctimer.h new file mode 100644 index 00000000..118fc4c8 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_ctimer.h @@ -0,0 +1,451 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_CTIMER_H_ +#define _FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Register callback. + * + * @param base Ctimer peripheral base address + * @param cb_func callback function + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + + /* Enable capture interrupts */ + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + + /* Disable capture interrupts */ + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + + /* Get all the capture interrupts enabled */ + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CTIMER_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_device_registers.h b/fnet_demos/common/startup/LPC54628/fsl_device_registers.h new file mode 100644 index 00000000..482ad256 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_device_registers.h @@ -0,0 +1,56 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_LPC54628J512ET180)) + +#define LPC54628_SERIES + +/* CMSIS-style register definitions */ +#include "LPC54628.h" +/* CPU specific feature definitions */ +#include "LPC54628_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/fnet_demos/common/startup/LPC54628/fsl_dma.c b/fnet_demos/common/startup/LPC54628/fsl_dma.c new file mode 100644 index 00000000..25ff1926 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_dma.c @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMA. + * + * @param base DMA peripheral base address. + */ +static int32_t DMA_GetInstance(DMA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMA instance number to base pointer. */ +static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map DMA instance number to clock name. */ +static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Array to map DMA instance number to IRQ number. */ +static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; + +/*! @brief Pointers to transfer handle for each DMA channel. */ +static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS]; + +/*! @brief Static table of descriptors */ +#if defined(__ICCARM__) +#pragma data_alignment = 512 +dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0}; +#elif defined(__CC_ARM) +__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0}; +#elif defined(__GNUC__) +__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0}; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static int32_t DMA_GetInstance(DMA_Type *base) +{ + int32_t instance; + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) + { + if (s_dmaBases[instance] == base) + { + break; + } + } + assert(instance < ARRAY_SIZE(s_dmaBases)); + return instance < ARRAY_SIZE(s_dmaBases) ? instance : -1; +} + +void DMA_Init(DMA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable dma clock gate */ + CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* set descriptor table */ + base->SRAMBASE = (uint32_t)s_dma_descriptor_table; + /* enable dma peripheral */ + base->CTRL |= DMA_CTRL_ENABLE_MASK; +} + +void DMA_Deinit(DMA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Disable DMA peripheral */ + base->CTRL &= ~(DMA_CTRL_ENABLE_MASK); +} + +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) +{ + assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS) && (NULL != trigger)); + + uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | + DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); + tmp = base->CHANNEL[channel].CFG & (~tmp); + tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + base->CHANNEL[channel].CFG = tmp; +} + +/*! + * @brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + + /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes + * impossible to distinguish between: + * - transfer finishes (represented by value '0x3FF') + * - and remaining 1024 bytes to transfer (value 0x3FF) + * for all descriptor in chain, except the last one. + * If you decide to use this function, please use 1023 transfers as maximal value */ + + /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ + if ((!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) && + (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) + { + return 0; + } + + return base->CHANNEL[channel].XFERCFG + 1; +} + +static void DMA_SetupDescriptor( + dma_descriptor_t *desc, uint32_t xfercfg, void *srcEndAddr, void *dstEndAddr, void *nextDesc) +{ + desc->xfercfg = xfercfg; + desc->srcEndAddr = srcEndAddr; + desc->dstEndAddr = dstEndAddr; + desc->linkToNextDesc = nextDesc; +} + +/* Verify and convert dma_xfercfg_t to XFERCFG register */ +static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) +{ + assert(xfercfg != NULL); + /* check source increment */ + assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4)); + /* check destination increment */ + assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4)); + /* check data width */ + assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4)); + /* check transfer count */ + assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); + + uint32_t xfer = 0, tmp; + /* set valid flag - descriptor is ready now */ + xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0); + /* set reload - allow link to next descriptor */ + xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0); + /* set swtrig flag - start transfer */ + xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig ? 1 : 0); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig ? 1 : 0); + /* set INTA */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0); + /* set INTB */ + xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0); + /* set data width */ + tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1; + xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp); + /* set source increment value */ + tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc; + xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp); + /* set destination increment value */ + tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc; + xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp); + /* set transfer count */ + xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1); + + /* store xferCFG */ + *xfercfg_addr = xfer; +} + +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) +{ + uint32_t xfercfg_reg = 0; + + assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg)); + assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth)); + assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth)); + assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16)); + + /* Setup channel configuration */ + DMA_SetupXferCFG(xfercfg, &xfercfg_reg); + + /* Set descriptor structure */ + DMA_SetupDescriptor( + desc, xfercfg_reg, (uint8_t *)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), + (uint8_t *)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), nextDesc); +} + +void DMA_AbortTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + + DMA_DisableChannel(handle->base, handle->channel); + while (handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].BUSY & (1U << DMA_CHANNEL_INDEX(handle->channel))) + { + } + handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].ABORT |= 1U << DMA_CHANNEL_INDEX(handle->channel); + DMA_EnableChannel(handle->base, handle->channel); +} + +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + int32_t dmaInstance; + assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS)); + + /* base address is invalid DMA instance */ + dmaInstance = DMA_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + handle->base = base; + handle->channel = channel; + s_DMAHandle[channel] = handle; + /* Enable NVIC interrupt */ + EnableIRQ(s_dmaIRQNumber[dmaInstance]); +} + +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc) +{ + uint32_t xfer_count; + assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); + assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4)); + + /* check max */ + xfer_count = transferBytes / byteWidth; + assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth)); + + memset(config, 0, sizeof(*config)); + switch (type) + { + case kDMA_MemoryToMemory: + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 1; + config->isPeriph = false; + break; + case kDMA_PeripheralToMemory: + /* Peripheral register - source doesn't increment */ + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 1; + config->isPeriph = true; + break; + case kDMA_MemoryToPeripheral: + /* Peripheral register - destination doesn't increment */ + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + break; + case kDMA_StaticToStatic: + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + break; + default: + return; + } + + config->dstAddr = (uint8_t *)dstAddr; + config->srcAddr = (uint8_t *)srcAddr; + config->nextDesc = (uint8_t *)nextDesc; + config->xfercfg.transferCount = xfer_count; + config->xfercfg.byteWidth = byteWidth; + config->xfercfg.intA = true; + config->xfercfg.reload = nextDesc != NULL; + config->xfercfg.valid = true; +} + +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) +{ + assert((NULL != handle) && (NULL != config)); + + /* Previous transfer has not finished */ + if (DMA_ChannelIsActive(handle->base, handle->channel)) + { + return kStatus_DMA_Busy; + } + + /* enable/disable peripheral request */ + if (config->isPeriph) + { + DMA_EnableChannelPeriphRq(handle->base, handle->channel); + } + else + { + DMA_DisableChannelPeriphRq(handle->base, handle->channel); + } + + DMA_CreateDescriptor(&s_dma_descriptor_table[handle->channel], &config->xfercfg, config->srcAddr, config->dstAddr, + config->nextDesc); + + return kStatus_Success; +} + +void DMA_StartTransfer(dma_handle_t *handle) +{ + assert(NULL != handle); + + /* Enable channel interrupt */ + handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(handle->channel); + + /* If HW trigger is enabled - disable SW trigger */ + if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) + { + s_dma_descriptor_table[handle->channel].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK); + } + /* Otherwise enable SW trigger */ + else + { + s_dma_descriptor_table[handle->channel].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK; + } + + /* Set channel XFERCFG register according first channel descriptor. */ + handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[handle->channel].xfercfg; + /* At this moment, the channel ACTIVE bit is set and application cannot modify + * or start another transfer using this channel. Channel ACTIVE bit is cleared by + * 'AbortTransfer' function or when the transfer finishes */ +} + +void DMA0_DriverIRQHandler(void) +{ + dma_handle_t *handle; + int32_t channel_group; + int32_t channel_index; + + /* Find channels that have completed transfer */ + for (int i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS; i++) + { + handle = s_DMAHandle[i]; + /* Handle is not present */ + if (NULL == handle) + { + continue; + } + channel_group = DMA_CHANNEL_GROUP(handle->channel); + channel_index = DMA_CHANNEL_INDEX(handle->channel); + /* Channel uses INTA flag */ + if (handle->base->COMMON[channel_group].INTA & (1U << channel_index)) + { + /* Clear INTA flag */ + handle->base->COMMON[channel_group].INTA = 1U << channel_index; + if (handle->callback) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntA); + } + } + /* Channel uses INTB flag */ + if (handle->base->COMMON[channel_group].INTB & (1U << channel_index)) + { + /* Clear INTB flag */ + handle->base->COMMON[channel_group].INTB = 1U << channel_index; + if (handle->callback) + { + (handle->callback)(handle, handle->userData, true, kDMA_IntB); + } + } + /* Error flag */ + if (handle->base->COMMON[channel_group].ERRINT & (1U << channel_index)) + { + /* Clear error flag */ + handle->base->COMMON[channel_group].ERRINT = 1U << channel_index; + if (handle->callback) + { + (handle->callback)(handle, handle->userData, false, kDMA_IntError); + } + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} diff --git a/fnet_demos/common/startup/LPC54628/fsl_dma.h b/fnet_demos/common/startup/LPC54628/fsl_dma.h new file mode 100644 index 00000000..44f86e9a --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_dma.h @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMA_H_ +#define _FSL_DMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dma + * @{ + */ + +/*! @file */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMA driver version */ +#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +#define DMA_MAX_TRANSFER_COUNT 0x400 + +/* Channel group consists of 32 channels. channel_group = (channel / 32) */ +#define DMA_CHANNEL_GROUP(channel) (((uint8_t)channel) >> 5U) +/* Channel index in channel group. channel_index = (channel % 32) */ +#define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F) + +/*! @brief DMA descriptor structure */ +typedef struct _dma_descriptor +{ + uint32_t xfercfg; /*!< Transfer configuration */ + void *srcEndAddr; /*!< Last source address of DMA transfer */ + void *dstEndAddr; /*!< Last destination address of DMA transfer */ + void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */ +} dma_descriptor_t; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_xfercfg +{ + bool valid; /*!< Descriptor is ready to transfer */ + bool reload; /*!< Reload channel configuration register after + current descriptor is exhausted */ + bool swtrig; /*!< Perform software trigger. Transfer if fired + when 'valid' is set */ + bool clrtrig; /*!< Clear trigger */ + bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */ + bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */ + uint8_t byteWidth; /*!< Byte width of data to transfer */ + uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */ + uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */ + uint16_t transferCount; /*!< Number of transfers */ +} dma_xfercfg_t; + +/*! @brief DMA channel priority */ +typedef enum _dma_priority +{ + kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */ + kDMA_ChannelPriority1, /*!< Channel priority 1 */ + kDMA_ChannelPriority2, /*!< Channel priority 2 */ + kDMA_ChannelPriority3, /*!< Channel priority 3 */ + kDMA_ChannelPriority4, /*!< Channel priority 4 */ + kDMA_ChannelPriority5, /*!< Channel priority 5 */ + kDMA_ChannelPriority6, /*!< Channel priority 6 */ + kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */ +} dma_priority_t; + +/*! @brief DMA interrupt flags */ +typedef enum _dma_int +{ + kDMA_IntA, /*!< DMA interrupt flag A */ + kDMA_IntB, /*!< DMA interrupt flag B */ + kDMA_IntError, /*!< DMA interrupt flag error */ +} dma_irq_t; + +/*! @brief DMA trigger type*/ +typedef enum _dma_trigger_type +{ + kDMA_NoTrigger = 0, /*!< Trigger is disabled */ + kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */ + kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | + DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */ + kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */ + kDMA_RisingEdgeTrigger = + DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ +} dma_trigger_type_t; + +/*! @brief DMA trigger burst */ +typedef enum _dma_trigger_burst +{ + kDMA_SingleTransfer = 0, /*!< Single transfer */ + kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */ + kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */ + kDMA_EdgeBurstTransfer2 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */ + kDMA_EdgeBurstTransfer4 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */ + kDMA_EdgeBurstTransfer8 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */ + kDMA_EdgeBurstTransfer16 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */ + kDMA_EdgeBurstTransfer32 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */ + kDMA_EdgeBurstTransfer64 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */ + kDMA_EdgeBurstTransfer128 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */ + kDMA_EdgeBurstTransfer256 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */ + kDMA_EdgeBurstTransfer512 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */ + kDMA_EdgeBurstTransfer1024 = + DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */ +} dma_trigger_burst_t; + +/*! @brief DMA burst wrapping */ +typedef enum _dma_burst_wrap +{ + kDMA_NoWrap = 0, /*!< Wrapping is disabled */ + kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */ + kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */ + kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | + DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */ +} dma_burst_wrap_t; + +/*! @brief DMA transfer type */ +typedef enum _dma_transfer_type +{ + kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */ + kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */ + kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/ + kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */ +} dma_transfer_type_t; + +/*! @brief DMA channel trigger */ +typedef struct _dma_channel_trigger +{ + dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */ + dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */ + dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ +} dma_channel_trigger_t; + +/*! @brief DMA transfer status */ +enum _dma_transfer_status +{ + kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief DMA transfer configuration */ +typedef struct _dma_transfer_config +{ + uint8_t *srcAddr; /*!< Source data address */ + uint8_t *dstAddr; /*!< Destination data address */ + uint8_t *nextDesc; /*!< Chain custom descriptor */ + dma_xfercfg_t xfercfg; /*!< Transfer options */ + bool isPeriph; /*!< DMA transfer is driven by peripheral */ +} dma_transfer_config_t; + +/*! @brief Callback for DMA */ +struct _dma_handle; + +/*! @brief Define Callback function for DMA. */ +typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode); + +/*! @brief DMA transfer handle structure */ +typedef struct _dma_handle +{ + dma_callback callback; /*!< Callback function. Invoked when transfer + of descriptor with interrupt flag finishes */ + void *userData; /*!< Callback function parameter */ + DMA_Type *base; /*!< DMA peripheral base address */ + uint8_t channel; /*!< DMA channel number */ +} dma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMA initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes DMA peripheral. + * + * This function enable the DMA clock, set descriptor table and + * enable DMA peripheral. + * + * @param base DMA peripheral base address. + */ +void DMA_Init(DMA_Type *base); + +/*! + * @brief Deinitializes DMA peripheral. + * + * This function gates the DMA clock. + * + * @param base DMA peripheral base address. + */ +void DMA_Deinit(DMA_Type *base); + +/* @} */ +/*! + * @name DMA Channel Operation + * @{ + */ + +/*! +* @brief Return whether DMA channel is processing transfer +* +* @param base DMA peripheral base address. +* @param channel DMA channel number. +* @return True for active state, false otherwise. +*/ +static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + return (base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false; +} + +/*! + * @brief Enables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Disables the interrupt source for the DMA transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENCLR |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Enable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLESET |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Disable DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLECLR |= 1U << DMA_CHANNEL_INDEX(channel); +} + +/*! + * @brief Set PERIPHREQEN of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Get PERIPHREQEN value of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for enabled PeriphRq, false for disabled. + */ +static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; +} + +/*! + * @brief Set trigger settings of DMA channel. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param trigger trigger configuration. + */ +void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); + +/*! + * @brief Gets the remaining bytes of the current DMA descriptor transfer. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return The number of bytes which have not been transferred yet. + */ +uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); + +/*! + * @brief Set priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @param priority Channel priority value. + */ +static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CFG = + (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); +} + +/*! + * @brief Get priority of channel configuration register. + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return Channel priority value. + */ +static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS); + return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> + DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); +} + +/*! + * @brief Create application specific DMA descriptor + * to be used in a chain in transfer + * + * @param desc DMA descriptor address. + * @param xfercfg Transfer configuration for DMA descriptor. + * @param srcAddr Address of last item to transmit + * @param dstAddr Address of last item to receive. + * @param nextDesc Address of next descriptor in chain. + */ +void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); + +/* @} */ + +/*! + * @name DMA Transactional Operation + * @{ + */ + +/*! + * @brief Abort running transfer by handle. + * + * This function aborts DMA transfer specified by handle. + * + * @param handle DMA handle pointer. + */ +void DMA_AbortTransfer(dma_handle_t *handle); + +/*! + * @brief Creates the DMA handle. + * + * This function is called if using transaction API for DMA. This function + * initializes the internal state of DMA handle. + * + * @param handle DMA handle pointer. The DMA handle stores callback function and + * parameters. + * @param base DMA peripheral base address. + * @param channel DMA channel number. + */ +void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs a callback function for the DMA transfer. + * + * This callback is called in DMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * @param handle DMA handle pointer. + * @param callback DMA callback function pointer. + * @param userData Parameter for callback function. + */ +void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData); + +/*! + * @brief Prepares the DMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type dma_transfer_t. + * @param srcAddr DMA transfer source address. + * @param dstAddr DMA transfer destination address. + * @param byteWidth DMA transfer destination address width(bytes). + * @param transferBytes DMA transfer bytes to be transferred. + * @param type DMA transfer type. + * @param nextDesc Chain custom descriptor to transfer. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in + * source address error(SAE). + */ +void DMA_PrepareTransfer(dma_transfer_config_t *config, + void *srcAddr, + void *dstAddr, + uint32_t byteWidth, + uint32_t transferBytes, + dma_transfer_type_t type, + void *nextDesc); + +/*! + * @brief Submits the DMA transfer request. + * + * This function submits the DMA transfer request according to the transfer configuration structure. + * If the user submits the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * @param handle DMA handle pointer. + * @param config Pointer to DMA transfer configuration structure. + * @retval kStatus_DMA_Success It means submit transfer request succeed. + * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); + +/*! + * @brief DMA start transfer. + * + * This function enables the channel request. User can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * @param handle DMA handle pointer. + */ +void DMA_StartTransfer(dma_handle_t *handle); + +/*! + * @brief DMA IRQ handler for descriptor transfer complete. + * + * This function clears the channel major interrupt flag and call + * the callback function if it is not NULL. + */ +void DMA_HandleIRQ(void); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_DMA_H_*/ diff --git a/fnet_demos/common/startup/LPC54628/fsl_emc.c b/fnet_demos/common/startup/LPC54628/fsl_emc.c new file mode 100644 index 00000000..dcc87c4e --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_emc.c @@ -0,0 +1,380 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_emc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Define macros for EMC driver. */ +#define EMC_REFRESH_CLOCK_PARAM (16U) +#define EMC_SDRAM_WAIT_CYCLES (2000U) +#define EMC_DYNCTL_COLUMNBASE_OFFSET (0U) +#define EMC_DYNCTL_COLUMNBASE_MASK (0x3U) +#define EMC_DYNCTL_COLUMNPLUS_OFFSET (3U) +#define EMC_DYNCTL_COLUMNPLUS_MASK (0x18U) +#define EMC_DYNCTL_BUSWIDTH_MASK (0x80U) +#define EMC_DYNCTL_BUSADDRMAP_MASK (0x20U) +#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1cU) +#define EMC_SDRAM_BANKCS_BA0_MASK (uint32_t)(0x2000) +#define EMC_SDRAM_BANKCS_BA1_MASK (uint32_t)(0x4000) +#define EMC_SDRAM_BANKCS_BA_MASK (EMC_SDRAM_BANKCS_BA0_MASK|EMC_SDRAM_BANKCS_BA1_MASK) +#define EMC_DIV_ROUND_UP(n, m) ((n + m -1)/m) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for EMC module. + * + * @param base EMC peripheral base address + */ +static uint32_t EMC_GetInstance(EMC_Type *base); + +/*! + * @brief Get the clock cycles of EMC clock. + * The function is used to calculate the multiple of the + * 16 EMCCLKs between the timer_Ns period. + * + * @param base EMC peripheral base address + * @param timer_Ns The timer/period in unit of nanosecond + * @param plus The plus added to the register settings to reach the calculated cycles. + * @return The calculated cycles. + */ +static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus); + +/*! + * @brief Get the shift value to shift the mode register content by. + * + * @param addrMap EMC address map for the dynamic memory configuration. + * It is the bit 14 ~ bit 7 of the EMC_DYNAMICCONFIG. + * @return The offset value to shift the mode register content by. + */ +static uint32_t EMC_ModeOffset(uint32_t addrMap); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to EMC clocks for each instance. */ +static const clock_ip_name_t s_EMCClock[FSL_FEATURE_SOC_EMC_COUNT] = EMC_CLOCKS; + +/*! @brief Pointers to EMC bases for each instance. */ +static const EMC_Type *const s_EMCBases[] = EMC_BASE_PTRS; + +/*! @brief Define the the start address for each chip controlled by EMC. */ +static const uint32_t s_EMCDYCSBases[] = EMC_DYCS_ADDRESS; +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t EMC_GetInstance(EMC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_EMCBases); instance++) + { + if (s_EMCBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_EMCBases)); + + return instance; +} + +static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus) +{ + uint32_t cycles; + + cycles = CLOCK_GetFreq(kCLOCK_EMC) / EMC_HZ_ONEMHZ * timer_Ns; + cycles = EMC_DIV_ROUND_UP(cycles, EMC_MILLISECS_ONESEC); /* Round up. */ + + /* Decrese according to the plus. */ + if (cycles >= plus) + { + cycles = cycles - plus; + } + else + { + cycles = 0; + } + + return cycles; +} + +static uint32_t EMC_ModeOffset(uint32_t addrMap) +{ + uint8_t offset = 0; + uint32_t columbase = addrMap & EMC_DYNCTL_COLUMNBASE_MASK; + + /* First calculate the column length. */ + if (columbase == 0x10) + { + offset = 8; + } + else + { + if (!columbase) + { + offset = 9; + } + else + { + offset = 8; + } + /* Add column length increase check. */ + if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 1) + { + offset += 1; + } + else if (((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET) == 2) + { + offset += 2; + } + else + { + /* To avoid MISRA rule 14.10 error. */ + } + } + + /* Add Buswidth/16. */ + if (addrMap & EMC_DYNCTL_BUSWIDTH_MASK) + { + offset += 2; + } + else + { + offset += 1; + } + + /* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */ + if (!(addrMap & EMC_DYNCTL_BUSADDRMAP_MASK)) + { + if (!(addrMap & EMC_DYNCTL_DEVBANKS_BITS_MASK)) + { + offset += 1; + } + else + { + offset += 2; + } + } + + return offset; +} + +void EMC_Init(EMC_Type *base, emc_basic_config_t *config) +{ + /* Enable EMC clock. */ + CLOCK_EnableClock((s_EMCClock[EMC_GetInstance(base)])); + + /* Reset the EMC. */ + SYSCON->PRESETCTRL[2] |= SYSCON_PRESETCTRL_EMC_RESET_MASK; + SYSCON->PRESETCTRL[2] &= ~ SYSCON_PRESETCTRL_EMC_RESET_MASK; + + /* Set the EMC sytem configure. */ + SYSCON->EMCCLKDIV = SYSCON_EMCCLKDIV_DIV(config->emcClkDiv); + + SYSCON->EMCSYSCTRL = SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(config->fbClkSrc); + + /* Set the endian mode. */ + base->CONFIG = config->endian; + /* Enable the EMC module with normal memory map mode and normal work mode. */ + base->CONTROL = EMC_CONTROL_E_MASK; +} + +void EMC_DynamicMemInit(EMC_Type *base, emc_dynamic_timing_config_t *timing, + emc_dynamic_chip_config_t *config, uint32_t totalChips) +{ + assert(config); + assert(timing); + assert(totalChips <= EMC_DYNAMIC_MEMDEV_NUM); + + uint32_t count; + uint8_t casLatency; + uint32_t addr; + uint32_t offset; + uint32_t data; + emc_dynamic_chip_config_t *dynamicConfig = config; + + /* Setting for dynamic memory controller chip independent configuration. */ + for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++) + { + base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG = EMC_DYNAMIC_DYNAMICCONFIG_MD(dynamicConfig->dynamicDevice) | + EMC_ADDRMAP(dynamicConfig->devAddrMap); + /* Abstract CAS latency from the sdram mode reigster setting values. */ + casLatency = (dynamicConfig->sdramModeReg & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT; + base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICRASCAS = EMC_DYNAMIC_DYNAMICRASCAS_RAS(dynamicConfig->rAS_Nclk) | + EMC_DYNAMIC_DYNAMICRASCAS_CAS(casLatency); + + dynamicConfig ++; + } + + /* Configure the Dynamic Memory controller timing/latency for all chips. */ + base->DYNAMICREADCONFIG = EMC_DYNAMICREADCONFIG_RD(timing->readConfig); + base->DYNAMICRP = EMC_CalculateTimerCycles(base, timing->tRp_Ns, 1) & EMC_DYNAMICRP_TRP_MASK; + base->DYNAMICRAS = EMC_CalculateTimerCycles(base, timing->tRas_Ns, 1) & EMC_DYNAMICRAS_TRAS_MASK; + base->DYNAMICSREX = EMC_CalculateTimerCycles(base, timing->tSrex_Ns, 1) & EMC_DYNAMICSREX_TSREX_MASK; + base->DYNAMICAPR = EMC_CalculateTimerCycles(base, timing->tApr_Ns, 1) & EMC_DYNAMICAPR_TAPR_MASK; + base->DYNAMICDAL = EMC_CalculateTimerCycles(base, timing->tDal_Ns, 0) & EMC_DYNAMICDAL_TDAL_MASK; + base->DYNAMICWR = EMC_CalculateTimerCycles(base, timing->tWr_Ns, 1) & EMC_DYNAMICWR_TWR_MASK; + base->DYNAMICRC = EMC_CalculateTimerCycles(base, timing->tRc_Ns, 1) & EMC_DYNAMICRC_TRC_MASK; + base->DYNAMICRFC = EMC_CalculateTimerCycles(base, timing->tRfc_Ns, 1) &EMC_DYNAMICRFC_TRFC_MASK; + base->DYNAMICXSR = EMC_CalculateTimerCycles(base, timing->tXsr_Ns, 1) & EMC_DYNAMICXSR_TXSR_MASK; + base->DYNAMICRRD = EMC_CalculateTimerCycles(base, timing->tRrd_Ns, 1) & EMC_DYNAMICRRD_TRRD_MASK; + base->DYNAMICMRD = EMC_DYNAMICMRD_TMRD((timing->tMrd_Nclk > 0)?timing->tMrd_Nclk - 1:0); + + /* Initialize the SDRAM.*/ + for (count = 0; count < EMC_SDRAM_WAIT_CYCLES; count ++) + { + } + /* Step 2. issue nop command. */ + base->DYNAMICCONTROL = 0x00000183; + for (count = 0; count < EMC_SDRAM_WAIT_CYCLES; count ++) + { + } + /* Step 3. issue precharge all command. */ + base->DYNAMICCONTROL = 0x00000103; + + /* Step 4. issue two auto-refresh command. */ + base->DYNAMICREFRESH = 2; + for (count = 0; count < EMC_SDRAM_WAIT_CYCLES/2; count ++) + { + } + + base->DYNAMICREFRESH = EMC_CalculateTimerCycles(base, timing->refreshPeriod_Nanosec, 0)/EMC_REFRESH_CLOCK_PARAM; + + /* Step 5. issue a mode command and set the mode value. */ + base->DYNAMICCONTROL = 0x00000083; + + /* Calculate the mode settings here and to reach the 8 auto-refresh time requirement. */ + dynamicConfig = config; + for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++) + { + /* Get the shift value first. */ + offset = EMC_ModeOffset(dynamicConfig->devAddrMap); + addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] | + ((uint32_t)(dynamicConfig->sdramModeReg & ~EMC_SDRAM_BANKCS_BA_MASK ) << offset)); + /* Set the right mode setting value. */ + data = *(volatile uint32_t *)addr; + data = data; + dynamicConfig ++; + } + + if (config->dynamicDevice) + { + /* Add extended mode register if the low-power sdram is used. */ + base->DYNAMICCONTROL = 0x00000083; + /* Calculate the mode settings for extended mode register. */ + dynamicConfig = config; + for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++) + { + /* Get the shift value first. */ + offset = EMC_ModeOffset(dynamicConfig->devAddrMap); + addr = (s_EMCDYCSBases[dynamicConfig->chipIndex] | (((uint32_t)(dynamicConfig->sdramExtModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) | + EMC_SDRAM_BANKCS_BA1_MASK) << offset)); + /* Set the right mode setting value. */ + data = *(volatile uint32_t *)addr; + data = data; + dynamicConfig ++; + } + } + + /* Step 6. issue normal operation command. */ + base->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */ + + /* The buffer shall be disabled when do the sdram initialization and + * enabled after the initialization during normal opeation. + */ + dynamicConfig = config; + for (count = 0; (count < totalChips) && (dynamicConfig != NULL); count ++) + { + base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG |= EMC_DYNAMIC_DYNAMICCONFIG_B_MASK; + dynamicConfig ++; + } +} + +void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, + emc_static_chip_config_t *config, uint32_t totalChips) +{ + assert(config); + + uint32_t count; + emc_static_chip_config_t *staticConfig = config; + + /* Initialize extended wait. */ + if (extWait_Ns) + { + for (count = 0; (count < totalChips) && (staticConfig != NULL); count ++) + { + assert(staticConfig->specailConfig & kEMC_AsynchronosPageEnable); + } + + base->STATICEXTENDEDWAIT = EMC_CalculateTimerCycles(base, *extWait_Ns, 1); + staticConfig ++; + } + + /* Initialize the static memory chip specific configure. */ + staticConfig = config; + for (count = 0; (count < totalChips) && (staticConfig != NULL); count ++) + { + + base->STATIC[staticConfig->chipIndex].STATICCONFIG = + (staticConfig->specailConfig | staticConfig->memWidth); + base->STATIC[staticConfig->chipIndex].STATICWAITWEN = + EMC_CalculateTimerCycles(base, staticConfig->tWaitWriteEn_Ns, 1); + base->STATIC[staticConfig->chipIndex].STATICWAITOEN = + EMC_CalculateTimerCycles(base, staticConfig->tWaitOutEn_Ns, 0); + base->STATIC[staticConfig->chipIndex].STATICWAITRD = + EMC_CalculateTimerCycles(base, staticConfig->tWaitReadNoPage_Ns, 1); + base->STATIC[staticConfig->chipIndex].STATICWAITPAGE = + EMC_CalculateTimerCycles(base, staticConfig->tWaitReadPage_Ns, 1); + base->STATIC[staticConfig->chipIndex].STATICWAITWR = + EMC_CalculateTimerCycles(base, staticConfig->tWaitWrite_Ns, 2); + base->STATIC[staticConfig->chipIndex].STATICWAITTURN = + EMC_CalculateTimerCycles(base, staticConfig->tWaitTurn_Ns, 1); + + staticConfig ++; + } +} + +void EMC_Deinit(EMC_Type *base) +{ + /* Deinit the EMC. */ + base->CONTROL &= ~EMC_CONTROL_E_MASK; + + /* Disable EMC clock. */ + CLOCK_DisableClock(s_EMCClock[EMC_GetInstance(base)]); +} diff --git a/fnet_demos/common/startup/LPC54628/fsl_emc.h b/fnet_demos/common/startup/LPC54628/fsl_emc.h new file mode 100644 index 00000000..1afce0b6 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_emc.h @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_EMC_H_ +#define _FSL_EMC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup emc + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief EMC driver version 2.0.0. */ +#define FSL_EMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Define the chip numbers for dynamic and static memory devices. */ +#define EMC_STATIC_MEMDEV_NUM (4U) +#define EMC_DYNAMIC_MEMDEV_NUM (4U) +#define EMC_ADDRMAP_SHIFT EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT +#define EMC_ADDRMAP_MASK (EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK |EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK) +#define EMC_ADDRMAP(x) (((uint32_t)(((uint32_t)(x)) << EMC_ADDRMAP_SHIFT)) & EMC_ADDRMAP_MASK) +#define EMC_HZ_ONEMHZ (1000000U) +#define EMC_MILLISECS_ONESEC (1000U) +#define EMC_SDRAM_MODE_CL_SHIFT (4U) +#define EMC_SDRAM_MODE_CL_MASK (0x70U) + +/*! + * @brief Define EMC memory width for static memory device. + */ +typedef enum _emc_static_memwidth +{ + kEMC_8BitWidth = 0x0U, /*!< 8 bit memory width. */ + kEMC_16BitWidth, /*!< 16 bit memory width. */ + kEMC_32BitWidth /*!< 32 bit memory width. */ +} emc_static_memwidth_t; + +/*! + * @brief Define EMC static configuration. + */ +typedef enum _emc_static_special_config +{ + kEMC_AsynchronosPageEnable = 0x0008U,/*!< Enable the asynchronous page mode. page length four. */ + kEMC_ActiveHighChipSelect = 0x0040U, /*!< Chip select active high. */ + kEMC_ByteLaneStateAllLow = 0x0080U, /*!< Reads/writes the respective valuie bits in BLS3:0 are low. */ + kEMC_ExtWaitEnable = 0x0100U, /*!< Extended wait enable. */ + kEMC_BufferEnable = 0x80000U /*!< Buffer enable. */ +} emc_static_special_config_t; + +/*! @brief EMC dynamic memory device. */ +typedef enum _emc_dynamic_device +{ + kEMC_Sdram = 0x0U, /*!< Dynamic memory device: SDRAM. */ + kEMC_Lpsdram, /*!< Dynamic memory device: Low-power SDRAM. */ +} emc_dynamic_device_t; + +/*! @brief EMC dynamic read strategy. */ +typedef enum _emc_dynamic_read +{ + kEMC_NoDelay = 0x0U, /*!< No delay. */ + kEMC_Cmddelay, /*!< Command delayed strategy, using EMCCLKDELAY. */ + kEMC_CmdDelayPulseOneclk, /*!< Command delayed strategy pluse one clock cycle using EMCCLKDELAY. */ + kEMC_CmddelayPulsetwoclk, /*!< Command delayed strategy pulse two clock cycle using EMCCLKDELAY. */ +} emc_dynamic_read_t; + +/*! @brief EMC endian mode. */ +typedef enum _emc_endian_mode +{ + kEMC_LittleEndian = 0x0U, /*!< Little endian mode. */ + kEMC_BigEndian, /*!< Big endian mode. */ +} emc_endian_mode_t; + +/*! @brief EMC Feedback clock input source select. */ +typedef enum _emc_fbclk_src +{ + kEMC_IntloopbackEmcclk = 0U, /*!< Use the internal loop back from EMC_CLK output. */ + kEMC_EMCFbclkInput /*!< Use the external EMC_FBCLK input. */ +} emc_fbclk_src_t; + +/*! @brief EMC dynamic timing/delay configure structure. */ +typedef struct _emc_dynamic_timing_config +{ + emc_dynamic_read_t readConfig; /* Dynamic read strategy. */ + uint32_t refreshPeriod_Nanosec; /*!< The refresh period in unit of nanosecond. */ + uint32_t tRp_Ns; /*!< Precharge command period in unit of nanosecond. */ + uint32_t tRas_Ns; /*!< Active to precharge command period in unit of nanosecond. */ + uint32_t tSrex_Ns; /*!< Self-refresh exit time in unit of nanosecond. */ + uint32_t tApr_Ns; /*!< Last data out to active command time in unit of nanosecond. */ + uint32_t tDal_Ns; /*!< Data-in to active command in unit of nanosecond. */ + uint32_t tWr_Ns; /*!< Write recovery time in unit of nanosecond. */ + uint32_t tRc_Ns; /*!< Active to active command period in unit of nanosecond. */ + uint32_t tRfc_Ns; /*!< Auto-refresh period and auto-refresh to active command period in unit of nanosecond. */ + uint32_t tXsr_Ns; /*!< Exit self-refresh to active command time in unit of nanosecond. */ + uint32_t tRrd_Ns; /*!< Active bank A to active bank B latency in unit of nanosecond. */ + uint8_t tMrd_Nclk; /*!< Load mode register to active command time in unit of EMCCLK cycles.*/ +} emc_dynamic_timing_config_t; + +/*! + * @brief EMC dynamic memory controller independent chip configuration structure. + * Please take refer to the address mapping table in the RM in EMC chapter when you + * set the "devAddrMap". Choose the right Bit 14 Bit12 ~ Bit 7 group in the table + * according to the bus width/banks/row/colum length for you device. + * Set devAddrMap with the value make up with the seven bits (bit14 bit12 ~ bit 7) + * and inset the bit 13 with 0. + * for example, if the bit 14 and bit12 ~ bit7 is 1000001 is choosen according to the + * 32bit high-performance bus width with 2 banks, 11 row lwngth, 8 column length. + * Set devAddrMap with 0x81. + */ +typedef struct _emc_dynamic_chip_config +{ + uint8_t chipIndex; /*!< Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1. */ + emc_dynamic_device_t dynamicDevice; /*!< All chips shall use the same device setting. mixed use are not supported. */ + uint8_t rAS_Nclk; /*!< Active to read/write delay tRCD. */ + uint16_t sdramModeReg; /*!< Sdram mode register setting. */ + uint16_t sdramExtModeReg; /*!< Used for low-power sdram device. The extended mode register. */ + uint8_t devAddrMap; /*!< dynamic device address mapping, choose the address mapping for your specific device. */ +} emc_dynamic_chip_config_t; + +/*! + * @brief EMC static memory controller independent chip configuration structure. + */ +typedef struct _emc_static_chip_config +{ + uint8_t chipIndex; + emc_static_memwidth_t memWidth; /*!< Memory width. */ + uint32_t specailConfig; /*!< Static configuration,a logical OR of "emc_static_special_config_t". */ + uint32_t tWaitWriteEn_Ns;/*!< The delay form chip select to write enable in unit of nanosecond. */ + uint32_t tWaitOutEn_Ns; /*!< The delay from chip selcet to output enable in unit of nanosecond. */ + uint32_t tWaitReadNoPage_Ns;/*!< In No-page mode, the delay from chip select to read access in unit of nanosecond. */ + uint32_t tWaitReadPage_Ns; /*!< In page mode, the read after the first read wait states in unit of nanosecond. */ + uint32_t tWaitWrite_Ns; /*!< The delay from chip select to write access in unit of nanosecond. */ + uint32_t tWaitTurn_Ns; /*!< The Bus turn-around time in unit of nanosecond. */ +} emc_static_chip_config_t; + +/*! + * @brief EMC module basic configuration structure. + * + * Defines the static memory controller configure structure and + * uses the EMC_Init() function to make necessary initializations. + * + */ +typedef struct _emc_basic_config +{ + emc_endian_mode_t endian; /*!< Endian mode . */ + emc_fbclk_src_t fbClkSrc; /*!< The feedback clock source. */ + uint8_t emcClkDiv; /*!< EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */ +} emc_basic_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name EMC Initialize and de-initialize opeartion + * @{ + */ +/*! + * @brief Initializes the basic for EMC. + * This function ungates the EMC clock, initializes the emc system configure + * and enable the EMC module. This function must be called in the first step to initialize + * the external memory. + * + * @param base EMC peripheral base address. + * @param config The EMC basic configuration. + */ +void EMC_Init(EMC_Type *base, emc_basic_config_t *config); + +/*! + * @brief Initializes the dynamic memory controller. + * This function initializes the dynamic memory controller in external memory controller. + * This function must be called after EMC_Init and before accessing the external dynamic memory. + * + * @param base EMC peripheral base address. + * @param timing The timing and latency for dynamica memory controller setting. It shall + * be used for all dynamica memory chips, threfore the worst timing value for all + * used chips must be given. + * @param configure The EMC dynamic memory controller chip independent configuration pointer. + * This configuration pointer is actually pointer to a configration array. the array number + * depends on the "totalChips". + * @param totalChips The total dynamic memory chip numbers been used or the length of the + * "emc_dynamic_chip_config_t" type memory. + */ +void EMC_DynamicMemInit(EMC_Type *base, emc_dynamic_timing_config_t *timing, + emc_dynamic_chip_config_t *config, uint32_t totalChips); + +/*! + * @brief Initializes the static memory controller. + * This function initializes the static memory controller in external memory controller. + * This function must be called after EMC_Init and before accessing the external static memory. + * + * @param base EMC peripheral base address. + * @param extWait_Ns The extended wait timeout or the read/write transfer time. + * This is common for all static memory chips and set with NULL if not required. + * @param configure The EMC static memory controller chip independent configuration pointer. + * This configuration pointer is actually pointer to a configration array. the array number + * depends on the "totalChips". + * @param totalChips The total static memory chip numbers been used or the length of the + * "emc_static_chip_config_t" type memory. + */ +void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips); + +/*! + * @brief Deinitializes the EMC module and gates the clock. + * This function gates the EMC controller clock. As a result, the EMC + * module doesn't work after calling this function. + * + * @param base EMC peripheral base address. + */ +void EMC_Deinit(EMC_Type *base); + +/* @} */ + +/*! + * @name EMC Basic Operation + * @{ + */ + +/*! + * @brief Enables/disables the EMC module. + * + * @param base EMC peripheral base address. + * @param enable True enable EMC module, false disable. + */ +static inline void EMC_Enable(EMC_Type *base, bool enable) +{ + if (enable) + { + base->CONTROL |= EMC_CONTROL_E_MASK; + } + else + { + base->CONTROL &= ~EMC_CONTROL_E_MASK; + } +} + +/*! + * @brief Enables/disables the EMC Dynaimc memory controller. + * + * @param base EMC peripheral base address. + * @param enable True enable EMC dynamic memory controller, false disable. + */ +static inline void EMC_EnableDynamicMemControl(EMC_Type *base, bool enable) +{ + if (enable) + { + base->DYNAMICCONTROL |= (EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK); + } + else + { + base->DYNAMICCONTROL &= ~(EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK); + } +} + +/*! + * @brief Enables/disables the EMC address mirror. + * Enable the address mirror the EMC_CS1is mirrored to both EMC_CS0 + * and EMC_DYCS0 memory areas. Disable the address mirror enables + * EMC_cS0 and EMC_DYCS0 memory to be accessed. + * + * @param base EMC peripheral base address. + * @param enable True enable the address mirror, false disable the address mirror. + */ +static inline void EMC_MirrorChipAddr(EMC_Type *base, bool enable) +{ + if (enable) + { + base->CONTROL |= EMC_CONTROL_M_MASK; + } + else + { + base->CONTROL &= ~EMC_CONTROL_M_MASK; + } +} + +/*! + * @brief Enter the self-refresh mode for dynamic memory controller. + * This function provided self-refresh mode enter or exit for application. + * + * @param base EMC peripheral base address. + * @param enable True enter the self-refresh mode, false to exit self-refresh + * and enter the normal mode. + */ +static inline void EMC_EnterSelfRefreshCommand(EMC_Type *base, bool enable) +{ + if (enable) + { + base->DYNAMICCONTROL |= EMC_DYNAMICCONTROL_SR_MASK; + } + else + { + base->DYNAMICCONTROL &= ~EMC_DYNAMICCONTROL_SR_MASK; + } +} + +/*! + * @brief Get the operating mode of the EMC. + * This function can be used to get the operating mode of the EMC. + * + * @param base EMC peripheral base address. + * @return The EMC in self-refresh mode if true, else in normal mode. + */ +static inline bool EMC_IsInSelfrefreshMode(EMC_Type *base) +{ + return ((base->STATUS & EMC_STATUS_SA_MASK) ? true : false); +} + +/*! + * @brief Enter/exit the low-power mode. + * + * @param base EMC peripheral base address. + * @param enable True Enter the low-power mode, false exit low-power mode + * and return to normal mode. + */ +static inline void EMC_EnterLowPowerMode(EMC_Type *base, bool enable) +{ + if (enable) + { + base->CONTROL |= EMC_CONTROL_L_MASK; + } + else + { + base->CONTROL &= ~ EMC_CONTROL_L_MASK; + } +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_EMC_H_*/ diff --git a/fnet_demos/common/startup/LPC54628/fsl_enet.c b/fnet_demos/common/startup/LPC54628/fsl_enet.c new file mode 100644 index 00000000..4e39452f --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_enet.c @@ -0,0 +1,1820 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_enet.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief IPv4 PTP message IP version offset. */ +#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU +/*! @brief IPv4 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U +/*! @brief IPv4 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U +/*! @brief IPv4 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU +/*! @brief IPv4 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU +/*! @brief IPv4 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU +/*! @brief IPv4 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U +/*! @brief IPv4 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU +/*! @brief IPv6 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U +/*! @brief IPv6 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U +/*! @brief IPv6 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU +/*! @brief IPv6 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU +/*! @brief IPv6 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U +/*! @brief IPv6 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU +/*! @brief IPv6 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU +/*! @brief PTPv2 message Ethernet packet type offset. */ +#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU +/*! @brief PTPv2 message Ethernet message type offset. */ +#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU +/*! @brief PTPv2 message Ethernet version type offset. */ +#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU +/*! @brief PTPv2 message Ethernet clock id offset. */ +#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22 +/*! @brief PTPv2 message Ethernet sequence id offset. */ +#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c +/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */ +#define ENET_ETHERNETL2 0x88F7U +/*! @brief Packet type IPv4. */ +#define ENET_IPV4 0x0800U +/*! @brief Packet type IPv6. */ +#define ENET_IPV6 0x86ddU +/*! @brief Packet type VLAN. */ +#define ENET_8021QVLAN 0x8100U +/*! @brief UDP protocol type. */ +#define ENET_UDPVERSION 0x0011U +/*! @brief Packet IP version IPv4. */ +#define ENET_IPV4VERSION 0x0004U +/*! @brief Packet IP version IPv6. */ +#define ENET_IPV6VERSION 0x0006U + +/*! @brief Defines 10^9 nanosecond. */ +#define ENET_NANOSECS_ONESECOND (1000000000U) +/*! @brief Defines 10^6 microsecond.*/ +#define ENET_MICRSECS_ONESECOND (1000000U) + +/*! @brief Rx buffer LSB ignore bits. */ +#define ENET_RXBUFF_IGNORELSB_BITS (2U) +/*! @brief ENET FIFO size unit. */ +#define ENET_FIFOSIZE_UNIT (256U) +/*! @brief ENET half-dulpex default IPG. */ +#define ENET_HALFDUPLEX_DEFAULTIPG (4U) +/*! @breif ENET miminum ring length. */ +#define ENET_MIN_RINGLEN (4U) +/*! @breif ENET wakeup filter numbers. */ +#define ENET_WAKEUPFILTER_NUM (8U) +/*! @breif Requried systime timer frequency. */ +#define ENET_SYSTIME_REQUIRED_CLK_MHZ (50U) +/*! @brief Ethernet VLAN tag length. */ +#define ENET_FRAME_VLAN_TAGLEN 4U + +/*! @brief AVB TYPE */ +#define ENET_AVBTYPE 0x22F0U +#define ENET_HEAD_TYPE_OFFSET (12) +#define ENET_HEAD_AVBTYPE_OFFSET (16) + +/*! @brief Defines the macro for converting constants from host byte order to network byte order. */ +#define ENET_HTONS(n) __REV16(n) +#define ENET_HTONL(n) __REV(n) +#define ENET_NTOHS(n) __REV16(n) +#define ENET_NTOHL(n) __REV(n) + +/* Typedef for interrupt handler. */ +typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +uint32_t ENET_GetInstance(ENET_Type *base); + +/*! + * @brief Increase the index in the ring. + * + * @param index The current index. + * @param max The size. + * @return the increased index. + */ +static uint32_t ENET_IncreaseIndex(uint32_t index, uint32_t max); + +/*! + * @brief Set ENET system configuration. + * This function reset the ethernet module and set the phy selection. + * It should be called before any other ethernet operation. + * + * @param miiMode The MII/RMII mode for interface between the phy and ethernet. + */ +static void ENET_SetSYSControl(enet_mii_mode_t miiMode); + +/*! + * @brief Set ENET DMA controller with the configuration. + * + * @param base ENET peripheral base address. + * @param config ENET Mac configuration. + */ +static void ENET_SetDMAControl(ENET_Type *base, const enet_config_t *config); + +/*! + * @brief Set ENET MAC controller with the configuration. + * + * @param base ENET peripheral base address. + * @param config ENET Mac configuration. + * @param macAddr ENET six-byte mac address. + */ +static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr); +/*! + * @brief Set ENET MTL with the configuration. + * + * @param base ENET peripheral base address. + * @param config ENET Mac configuration. + */ +static void ENET_SetMTL(ENET_Type *base, const enet_config_t *config); + +/*! + * @brief Set ENET DMA transmit buffer descriptors for one channel. + * + * @param base ENET peripheral base address. + * @param bufferConfig ENET buffer configuration. + * @param intTxEnable tx interrupt enable. + * @param channel The channel number, 0 , 1. + */ +static status_t ENET_TxDescriptorsInit(ENET_Type *base, + const enet_buffer_config_t *bufferConfig, + bool intTxEnable, + uint8_t channel); + +/*! + * @brief Set ENET DMA receive buffer descriptors for one channel. + * + * @param base ENET peripheral base address. + * @param bufferConfig ENET buffer configuration. + * @param intRxEnable tx interrupt enable. + * @param channel The channel number, 0 , 1. + * @param doubleBuffEnable Two buffers are enabled. + */ +static status_t ENET_RxDescriptorsInit(ENET_Type *base, + const enet_buffer_config_t *bufferConfig, + bool intRxEnable, + uint8_t channel, + bool doubleBuffEnable); + +/*! + * @brief Set ENET get transmit ring descriptors. + * + * @param data The ENET data to be transfered. + * @param handle ENET handler. + */ +static uint8_t ENET_GetTxRingId(uint8_t *data, enet_handle_t *handle); + +#ifdef ENET_PTP1588FEATURE_REQUIRED +/*! + * @brief Sets the ENET 1588 feature. + * + * Enable the enhacement 1588 buffer descriptor mode and start + * the 1588 timer. + * + * @param base ENET peripheral base address. + * @param config The ENET configuration. + * @param refClk_Hz The reference clock for ptp 1588. + */ +static void ENET_SetPtp1588(ENET_Type *base, const enet_config_t *config, uint32_t refClk_Hz); + +/*! + * @brief Parses the ENET frame for time-stamp process of PTP 1588 frame. + * + * @param data The ENET read data for frame parse. + * @param ptpTsData The ENET PTP message and time-stamp data pointer. + * @param isFastEnabled The fast parse flag. + * - true , Fast processing, only check if this is a PTP message. + * - false, Store the PTP message data after check the PTP message. + */ +static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled); + +/*! + * @brief Updates the new PTP 1588 time-stamp to the time-stamp buffer ring. + * + * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. + * @param ptpTimeData The new PTP 1588 time-stamp data pointer. + */ +static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Search up the right PTP 1588 time-stamp from the time-stamp buffer ring. + * + * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. + * @param ptpTimeData The find out right PTP 1588 time-stamp data pointer with the specific PTP message. + */ +static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata); + +/*! + * @brief Store the receive time-stamp for event PTP frame in the time-stamp buffer ring. + * + * @param base ENET peripheral base address. + * @param handle ENET handler. + * @param rxDesc The ENET receive descriptor pointer. + * @param channel The rx channel. + * @param ptpTimeData The PTP 1588 time-stamp data pointer. + */ +static status_t ENET_StoreRxFrameTime(ENET_Type *base, + enet_handle_t *handle, + enet_rx_bd_struct_t *rxDesc, + uint8_t channel, + enet_ptp_time_data_t *ptpTimeData); +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to enet handles for each instance. */ +static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_LPC_ENET_COUNT] = {NULL}; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to enet clocks for each instance. */ +const clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_LPC_ENET_COUNT] = ETH_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to enet bases for each instance. */ +static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS; + +/*! @brief Pointers to enet IRQ number for each instance. */ +static const IRQn_Type s_enetIrqId[] = ENET_IRQS; + +/* ENET ISR for transactional APIs. */ +static enet_isr_t s_enetIsr; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ENET_IncreaseIndex(uint32_t index, uint32_t max) +{ + /* Increase the index. */ + index++; + if (index >= max) + { + index = 0; + } + return index; +} + +static void ENET_SetSYSControl(enet_mii_mode_t miiMode) +{ + /* Reset first. */ + SYSCON->PRESETCTRL[2] = SYSCON_PRESETCTRL_ETH_RST_MASK; + SYSCON->PRESETCTRL[2] &= ~SYSCON_PRESETCTRL_ETH_RST_MASK; + /* Set MII/RMII before the peripheral ethernet dma reset. */ + SYSCON->ETHPHYSEL = (SYSCON->ETHPHYSEL & ~SYSCON_ETHPHYSEL_PHY_SEL_MASK) | SYSCON_ETHPHYSEL_PHY_SEL(miiMode); +} + +static void ENET_SetDMAControl(ENET_Type *base, const enet_config_t *config) +{ + assert(config); + + uint8_t index; + uint32_t reg; + uint32_t burstLen; + + /* Reset first and wait for the complete + * The reset bit will automatically be cleared after complete. */ + base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK; + while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK) + { + } + + /* Set the burst length. */ + for (index = 0; index < ENET_RING_NUM_MAX; index++) + { + burstLen = kENET_BurstLen1; + if (config->multiqueueCfg) + { + burstLen = config->multiqueueCfg->burstLen; + } + base->DMA_CH[index].DMA_CHX_CTRL = burstLen & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK; + + reg = base->DMA_CH[index].DMA_CHX_TX_CTRL & ~ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK; + base->DMA_CH[index].DMA_CHX_TX_CTRL = reg | ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(burstLen & 0x3F); + + reg = base->DMA_CH[index].DMA_CHX_RX_CTRL & ~ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK; + base->DMA_CH[index].DMA_CHX_RX_CTRL = reg | ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(burstLen & 0x3F); + } +} + +static void ENET_SetMTL(ENET_Type *base, const enet_config_t *config) +{ + assert(config); + + uint32_t txqOpreg = 0; + uint32_t rxqOpReg = 0; + enet_multiqueue_config_t *multiqCfg = config->multiqueueCfg; + uint8_t index; + + /* Set transmit operation mode. */ + if (config->specialControl & kENET_StoreAndForward) + { + txqOpreg = ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK; + rxqOpReg = ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK; + } + txqOpreg |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK | + ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(ENET_MTL_TXFIFOSIZE / ENET_FIFOSIZE_UNIT - 1); + base->MTL_QUEUE[0].MTL_TXQX_OP_MODE = txqOpreg | ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(2); + base->MTL_QUEUE[1].MTL_TXQX_OP_MODE = txqOpreg; + + /* Set receive operation mode. */ + rxqOpReg |= ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK | + ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(ENET_MTL_RXFIFOSIZE / ENET_FIFOSIZE_UNIT - 1); + base->MTL_QUEUE[0].MTL_RXQX_OP_MODE = rxqOpReg; + + /* Set the schedule/arbitration(set for multiple queues). */ + if (multiqCfg) + { + base->MTL_OP_MODE = ENET_MTL_OP_MODE_SCHALG(multiqCfg->mtltxSche) | ENET_MTL_OP_MODE_RAA(multiqCfg->mtlrxSche); + /* Set the rx queue mapping to dma channel. */ + base->MTL_RXQ_DMA_MAP = multiqCfg->mtlrxQuemap; + /* Set the tx/rx queue operation mode for multi-queue. */ + base->MTL_QUEUE[1].MTL_TXQX_OP_MODE |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(2); + base->MTL_QUEUE[1].MTL_RXQX_OP_MODE = rxqOpReg; + + /* Set the tx/rx queue weight. */ + for (index = 0; index < ENET_RING_NUM_MAX; index++) + { + base->MTL_QUEUE[index].MTL_TXQX_QNTM_WGHT = multiqCfg->txqueweight[index]; + base->MTL_QUEUE[index].MTL_RXQX_CTRL = ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(multiqCfg->rxqueweight[index]); + } + } +} + +static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr) +{ + assert(config); + + uint32_t reg = 0; + + /* Set Macaddr */ + /* The dma channel 0 is set as to which the rx packet + * whose DA matches the MAC address content is routed. */ + if (macAddr) + { + ENET_SetMacAddr(base, macAddr); + } + + /* Set the receive filter. */ + reg = ENET_MAC_FRAME_FILTER_PR(!!(config->specialControl & kENET_PromiscuousEnable)) | + ENET_MAC_FRAME_FILTER_DBF(!!(config->specialControl & kENET_BroadCastRxDisable)) | + ENET_MAC_FRAME_FILTER_PM(!!(config->specialControl & kENET_MulticastAllEnable)); + base->MAC_FRAME_FILTER = reg; + /* Flow control. */ + if (config->specialControl & kENET_FlowControlEnable) + { + base->MAC_RX_FLOW_CTRL = ENET_MAC_RX_FLOW_CTRL_RFE_MASK | ENET_MAC_RX_FLOW_CTRL_UP_MASK; + base->MAC_TX_FLOW_CTRL_Q[0] = ENET_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration); + base->MAC_TX_FLOW_CTRL_Q[1] = ENET_MAC_TX_FLOW_CTRL_Q_PT(config->pauseDuration); + } + + /* Set the 1us ticket. */ + reg = CLOCK_GetFreq(kCLOCK_CoreSysClk) / ENET_MICRSECS_ONESECOND - 1; + base->MAC_1US_TIC_COUNTR = ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(reg); + + /* Set the speed and duplex. */ + reg = ENET_MAC_CONFIG_ECRSFD_MASK | ENET_MAC_CONFIG_PS_MASK | ENET_MAC_CONFIG_DM(config->miiDuplex) | + ENET_MAC_CONFIG_FES(config->miiSpeed) | + ENET_MAC_CONFIG_S2KP(!!(config->specialControl & kENET_8023AS2KPacket)); + if (config->miiDuplex == kENET_MiiHalfDuplex) + { + reg |= ENET_MAC_CONFIG_IPG(ENET_HALFDUPLEX_DEFAULTIPG); + } + base->MAC_CONFIG = reg; + + /* Enable channel. */ + base->MAC_RXQ_CTRL[0] = ENET_MAC_RXQ_CTRL_RXQ0EN(1) | ENET_MAC_RXQ_CTRL_RXQ1EN(1); +} + +static status_t ENET_TxDescriptorsInit(ENET_Type *base, + const enet_buffer_config_t *bufferConfig, + bool intTxEnable, + uint8_t channel) +{ + uint16_t j; + enet_tx_bd_struct_t *txbdPtr; + uint32_t control = intTxEnable ? ENET_TXDESCRIP_RD_IOC_MASK : 0; + const enet_buffer_config_t *buffCfg = bufferConfig; + + if (!buffCfg) + { + return kStatus_InvalidArgument; + } + + /* Check the ring length. */ + if (buffCfg->txRingLen < ENET_MIN_RINGLEN) + { + return kStatus_InvalidArgument; + } + /* Set the tx descriptor start/tail pointer, shall be word aligned. */ + base->DMA_CH[channel].DMA_CHX_TXDESC_LIST_ADDR = + (uint32_t)buffCfg->txDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK; + base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = + (uint32_t)buffCfg->txDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK; + /* Set the tx ring length. */ + base->DMA_CH[channel].DMA_CHX_TXDESC_RING_LENGTH = + (uint16_t)(buffCfg->txRingLen - 1) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK; + + /* Init the txbdPtr to the transmit descriptor start address. */ + txbdPtr = (enet_tx_bd_struct_t *)(buffCfg->txDescStartAddrAlign); + for (j = 0; j < buffCfg->txRingLen; j++) + { + txbdPtr->buff1Addr = 0; + txbdPtr->buff2Addr = 0; + txbdPtr->buffLen = control; + txbdPtr->controlStat = 0; + txbdPtr++; + } + + return kStatus_Success; +} + +static status_t ENET_RxDescriptorsInit( + ENET_Type *base, const enet_buffer_config_t *bufferConfig, bool intRxEnable, uint8_t channel, bool doubleBuffEnable) +{ + uint16_t j; + uint32_t reg; + enet_rx_bd_struct_t *rxbdPtr; + uint16_t index; + const enet_buffer_config_t *buffCfg = bufferConfig; + uint32_t control = ENET_RXDESCRIP_WR_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK; + + if (!buffCfg) + { + return kStatus_InvalidArgument; + } + + if (intRxEnable) + { + control |= ENET_RXDESCRIP_RD_IOC_MASK; + } + + if (doubleBuffEnable) + { + control |= ENET_RXDESCRIP_RD_BUFF2VALID_MASK; + } + + /* Check the ring length. */ + if (buffCfg->rxRingLen < ENET_MIN_RINGLEN) + { + return kStatus_InvalidArgument; + } + + /* Set the rx descriptor start/tail pointer, shall be word aligned. */ + base->DMA_CH[channel].DMA_CHX_RXDESC_LIST_ADDR = + (uint32_t)buffCfg->rxDescStartAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK; + base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = + (uint32_t)buffCfg->rxDescTailAddrAlign & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK; + base->DMA_CH[channel].DMA_CHX_RXDESC_RING_LENGTH = + (uint16_t)(buffCfg->rxRingLen - 1) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK; + reg = base->DMA_CH[channel].DMA_CHX_RX_CTRL & ~ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK; + reg |= ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(buffCfg->rxBuffSizeAlign >> ENET_RXBUFF_IGNORELSB_BITS); + base->DMA_CH[channel].DMA_CHX_RX_CTRL = reg; + + /* Init the rxbdPtr to the receive descriptor start address. */ + rxbdPtr = (enet_rx_bd_struct_t *)(buffCfg->rxDescStartAddrAlign); + + for (j = 0; j < buffCfg->rxRingLen; j++) + { + if (doubleBuffEnable) + { + index = 2 * j; + } + else + { + index = j; + } + rxbdPtr->buff1Addr = *(buffCfg->rxBufferStartAddr + index); + /* The second buffer is set with 0 because it is not required for normal case. */ + if (doubleBuffEnable) + { + rxbdPtr->buff2Addr = *(buffCfg->rxBufferStartAddr + index + 1); + } + else + { + rxbdPtr->buff2Addr = 0; + } + + /* Set the valid and DMA own flag.*/ + rxbdPtr->control = control; + rxbdPtr++; + } + + return kStatus_Success; +} + +static uint8_t ENET_GetTxRingId(uint8_t *data, enet_handle_t *handle) +{ + /* Defuault use the queue/ring 0. */ + uint8_t ringId = 0; + + if (handle->multiQueEnable) + { + /* Parse the frame and choose the queue id for different avb frames + * AVB Class frame in queue 1. + * non-AVB frame in queue 0. + */ + if ((*(uint16_t *)(data + ENET_HEAD_TYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN)) && + ((*(uint16_t *)(data + ENET_HEAD_AVBTYPE_OFFSET)) == ENET_HTONS(ENET_AVBTYPE))) + { + /* AVBTP stream data frame. */ + ringId = 1; + } + } + + return ringId; +} + +#ifdef ENET_PTP1588FEATURE_REQUIRED +static void ENET_SetPtp1588(ENET_Type *base, const enet_config_t *config, uint32_t refClk_Hz) +{ + assert(config); + assert(config->ptpConfig); + assert(refClk_Hz); + + uint32_t control; + enet_ptp_config_t *ptpConfig = config->ptpConfig; + + /* Clear the timestamp interrupt first. */ + base->MAC_INTR_EN &= ~ENET_MAC_INTR_EN_TSIE_MASK; + + if (ptpConfig->fineUpdateEnable) + { + base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK; + /* Set the initial added value for the fine update. */ + control = 100000000U / (refClk_Hz / ENET_MICRSECS_ONESECOND / ENET_SYSTIME_REQUIRED_CLK_MHZ); + base->MAC_SYS_TIMESTMP_ADDEND = control; + base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK; + while (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK) + { + } + } + + /* Enable the IEEE 1588 timestamping and snapshot for event message. */ + control = ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK | + ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK | + ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK | ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK | + ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(ptpConfig->tsRollover); + + if (ptpConfig->ptp1588V2Enable) + { + control |= ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK | ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK; + } + + /* Initialize the sub-second increment register. */ + if (ptpConfig->tsRollover) + { + base->MAC_SUB_SCND_INCR = ENET_MAC_SUB_SCND_INCR_SSINC(ENET_NANOSECS_ONESECOND / refClk_Hz); + base->MAC_SYS_TIME_NSCND_UPD = 0; + } + else + { + /* round up. */ + uint32_t data = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK / refClk_Hz; + base->MAC_SUB_SCND_INCR = ENET_MAC_SUB_SCND_INCR_SSINC(data); + base->MAC_SYS_TIME_NSCND_UPD = 0; + } + /* Set the second.*/ + base->MAC_SYS_TIME_SCND_UPD = 0; + base->MAC_SYS_TIME_HWORD_SCND = 0; + + /* Initialize the system timer. */ + base->MAC_TIMESTAMP_CTRL = control | ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK; +} + +static bool ENET_Ptp1588ParseFrame(uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled) +{ + assert(data); + if (!isFastEnabled) + { + assert(ptpTsData); + } + + bool isPtpMsg = false; + uint8_t *buffer = data; + uint16_t ptpType; + + /* Check for VLAN frame. */ + if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN)) + { + buffer += ENET_FRAME_VLAN_TAGLEN; + } + + ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET); + switch (ENET_HTONS(ptpType)) + { /* Ethernet layer 2. */ + case ENET_ETHERNETL2: + if (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) <= kENET_PtpEventMsgType) + { + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a ptpv2 message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], (void *)(buffer + ENET_PTP1588_ETHL2_CLOCKID_OFFSET), + kENET_PtpSrcPortIdLen); + } + } + break; + /* IPV4. */ + case ENET_IPV4: + if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV4VERSION) + { + if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && + (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) + { + /* Set the PTP message flag. */ + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a IPV4 ptp message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = + ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], + (void *)(buffer + ENET_PTP1588_IPV4_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); + } + } + } + break; + /* IPV6. */ + case ENET_IPV6: + if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV6VERSION) + { + if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && + (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) + { + /* Set the PTP message flag. */ + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a IPV6 ptp message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = + ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], + (void *)(buffer + ENET_PTP1588_IPV6_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); + } + } + } + break; + default: + break; + } + return isPtpMsg; +} + +static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData) +{ + assert(ptpTsDataRing); + assert(ptpTsDataRing->ptpTsData); + assert(ptpTimeData); + + uint16_t usedBuffer = 0; + + /* Check if the buffers ring is full. */ + if (ptpTsDataRing->end >= ptpTsDataRing->front) + { + usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; + } + else + { + usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); + } + + if (usedBuffer == ptpTsDataRing->size) + { + return kStatus_ENET_PtpTsRingFull; + } + + /* Copy the new data into the buffer. */ + memcpy((ptpTsDataRing->ptpTsData + ptpTsDataRing->end), ptpTimeData, sizeof(enet_ptp_time_data_t)); + + /* Increase the buffer pointer to the next empty one. */ + ptpTsDataRing->end = (ptpTsDataRing->end + 1) % ptpTsDataRing->size; + + return kStatus_Success; +} + +static status_t ENET_StoreRxFrameTime(ENET_Type *base, + enet_handle_t *handle, + enet_rx_bd_struct_t *rxDesc, + uint8_t channel, + enet_ptp_time_data_t *ptpTimeData) +{ + assert(ptpTimeData); + + uint32_t nanosecond; + uint32_t nanoOverSize = ENET_NANOSECS_ONESECOND; /* Default use the digital rollover. */ + + /* Get transmit time stamp second. */ + nanosecond = rxDesc->reserved | rxDesc->buff1Addr; + if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)) + { + /* Binary rollover. */ + nanoOverSize = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK; + } + ptpTimeData->timeStamp.second = nanosecond / nanoOverSize; + ptpTimeData->timeStamp.nanosecond = nanosecond % nanoOverSize; + + /* Store the timestamp to the receive time stamp ring. */ + /* Check if the buffers ring is full. */ + return ENET_Ptp1588UpdateTimeRing(&handle->rxBdRing[channel].rxPtpTsDataRing, ptpTimeData); +} + +static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata) +{ + assert(ptpTsDataRing); + assert(ptpTsDataRing->ptpTsData); + assert(ptpTimedata); + + uint32_t index; + uint32_t size; + uint16_t usedBuffer = 0; + + /* Check the PTP 1588 timestamp ring. */ + if (ptpTsDataRing->front == ptpTsDataRing->end) + { + return kStatus_ENET_PtpTsRingEmpty; + } + + /* Search the element in the ring buffer */ + index = ptpTsDataRing->front; + size = ptpTsDataRing->size; + while (index != ptpTsDataRing->end) + { + if (((ptpTsDataRing->ptpTsData + index)->sequenceId == ptpTimedata->sequenceId) && + (!memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]), + (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) && + ((ptpTsDataRing->ptpTsData + index)->version == ptpTimedata->version) && + ((ptpTsDataRing->ptpTsData + index)->messageType == ptpTimedata->messageType)) + { + break; + } + + /* Increase the ptp ring index. */ + index = (index + 1) % size; + } + + if (index == ptpTsDataRing->end) + { + /* Check if buffers is full. */ + if (ptpTsDataRing->end >= ptpTsDataRing->front) + { + usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; + } + else + { + usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); + } + + if (usedBuffer == ptpTsDataRing->size) + { /* Drop one in the front. */ + ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size; + } + return kStatus_ENET_PtpTsRingFull; + } + + /* Get the right timestamp of the required ptp messag. */ + ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second; + ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond; + + /* Increase the index. */ + ptpTsDataRing->front = (ptpTsDataRing->front + 1) % size; + + return kStatus_Success; +} +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + +uint32_t ENET_GetInstance(ENET_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < FSL_FEATURE_SOC_LPC_ENET_COUNT; instance++) + { + if (s_enetBases[instance] == base) + { + break; + } + } + + assert(instance < FSL_FEATURE_SOC_LPC_ENET_COUNT); + + return instance; +} + +void ENET_GetDefaultConfig(enet_config_t *config) +{ + /* Checks input parameter. */ + assert(config); + + /* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ + config->miiMode = kENET_RmiiMode; + config->miiSpeed = kENET_MiiSpeed100M; + config->miiDuplex = kENET_MiiFullDuplex; + + /* Sets default configuration for other options. */ + config->specialControl = false; + config->multiqueueCfg = NULL; + config->pauseDuration = 0; + +#ifdef ENET_PTP1588FEATURE_REQUIRED + config->ptpConfig = NULL; +#endif /* ENET_PTP1588FEATURE_REQUIRED */ +} + +void ENET_Init(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr, uint32_t refclkSrc_Hz) +{ + assert(config); + + uint32_t instance = ENET_GetInstance(base); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ENET clock. */ + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* System configure fistly. */ + ENET_SetSYSControl(config->miiMode); + + /* Initializes the ENET DMA with basic function. */ + ENET_SetDMAControl(base, config); + + /* Initializes the ENET MTL with basic function. */ + ENET_SetMTL(base, config); + + /* Initializes the ENET MAC with basic function. */ + ENET_SetMacControl(base, config, macAddr); + +#ifdef ENET_PTP1588FEATURE_REQUIRED + ENET_SetPtp1588(base, config, refclkSrc_Hz); +#endif /* ENET_PTP1588FEATURE_REQUIRED */ +} + +void ENET_Deinit(ENET_Type *base) +{ + /* Reset first and wait for the complete + * The reset bit will automatically be cleared after complete. */ + base->DMA_MODE |= ENET_DMA_MODE_SWR_MASK; + while (base->DMA_MODE & ENET_DMA_MODE_SWR_MASK) + { + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disables the clock source. */ + CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer_config_t *bufferConfig) +{ + assert(config); + assert(bufferConfig); + + bool intTxEnable = false; + bool intRxEnable = false; + bool doubleBuffEnable = (config->specialControl & kENET_DescDoubleBuffer) ? true : false; + uint8_t ringNum = config->multiqueueCfg == NULL ? 1 : 2; + uint8_t channel; + + for (channel = 0; channel < ringNum; channel++) + { + intRxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) ? true : false; + intTxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) ? true : false; + + if (ENET_TxDescriptorsInit(base, bufferConfig, intTxEnable, channel) != kStatus_Success) + { + return kStatus_Fail; + } + + if (ENET_RxDescriptorsInit(base, bufferConfig, intRxEnable, channel, doubleBuffEnable) != kStatus_Success) + { + return kStatus_Fail; + } + + bufferConfig++; + if (!bufferConfig) + { + return kStatus_InvalidArgument; + } + } + return kStatus_Success; +} + +void ENET_StartRxTx(ENET_Type *base, uint8_t txRingNum, uint8_t rxRingNum) +{ + assert(txRingNum); + assert(rxRingNum); + + uint8_t index; + + if (txRingNum > ENET_RING_NUM_MAX) + { + txRingNum = ENET_RING_NUM_MAX; + } + if (rxRingNum > ENET_RING_NUM_MAX) + { + rxRingNum = ENET_RING_NUM_MAX; + } + /* Start/Acive the DMA first. */ + for (index = 0; index < rxRingNum; index++) + { + base->DMA_CH[index].DMA_CHX_RX_CTRL |= ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK; + } + for (index = 0; index < txRingNum; index++) + { + base->DMA_CH[index].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK; + } + + /* Enable the RX/TX then. */ + base->MAC_CONFIG |= ENET_MAC_CONFIG_RE_MASK; + base->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK; +} + +void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) +{ + uint32_t interrupt = mask & 0xFFFFU; + uint8_t index; + + /* For dma interrupt. */ + if (interrupt) + { + for (index = 0; index < ENET_RING_NUM_MAX; index++) + { + /* Set for all abnormal interrupts. */ + if (ENET_ABNORM_INT_MASK & interrupt) + { + interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK; + } + /* Set for all normal interrupts. */ + if (ENET_NORM_INT_MASK & interrupt) + { + interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK; + } + base->DMA_CH[index].DMA_CHX_INT_EN = interrupt; + } + } + interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET; + if (interrupt) + { + /* MAC interrupt */ + base->MAC_INTR_EN |= interrupt; + } +} + +void ENET_ClearMacInterruptStatus(ENET_Type *base, uint32_t mask) +{ + volatile uint32_t dummy; + + if (mask & kENET_MacTimestamp) + { + dummy = base->MAC_SYS_TIMESTMP_STAT; + } + else if (mask & kENET_MacPmt) + { + dummy = base->MAC_PMT_CRTL_STAT; + } + else + { + /* Add for avoid the misra 2004 rule 14.10 */ + } + (void)dummy; +} + +void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) +{ + uint32_t interrupt = mask & 0xFFFFU; + uint8_t index; + + /* For dma interrupt. */ + if (interrupt) + { + for (index = 0; index < ENET_RING_NUM_MAX; index++) + { + /* Set for all abnormal interrupts. */ + if (ENET_ABNORM_INT_MASK & interrupt) + { + interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK; + } + /* Set for all normal interrupts. */ + if (ENET_NORM_INT_MASK & interrupt) + { + interrupt |= ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK; + } + base->DMA_CH[index].DMA_CHX_INT_EN &= ~interrupt; + } + } + interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET; + if (interrupt) + { + /* MAC interrupt */ + base->MAC_INTR_EN &= ~interrupt; + } +} + +void ENET_CreateHandler(ENET_Type *base, + enet_handle_t *handle, + enet_config_t *config, + enet_buffer_config_t *bufferConfig, + enet_callback_t callback, + void *userData) +{ + assert(config); + assert(bufferConfig); + assert(callback); + + uint8_t ringNum = 1; + uint8_t count = 0; + uint8_t rxIntEnable = 0; + enet_buffer_config_t *buffConfig = bufferConfig; + + if (config->multiqueueCfg) + { + ringNum = 2; + handle->multiQueEnable = true; + } + + /* Store transfer parameters in handle pointer. */ + memset(handle, 0, sizeof(enet_handle_t)); + if (config->specialControl & kENET_DescDoubleBuffer) + { + handle->doubleBuffEnable = true; + } + if (config->multiqueueCfg) + { + handle->multiQueEnable = true; + } + for (count = 0; count < ringNum; count++) + { + handle->rxBdRing[count].rxBdBase = buffConfig->rxDescStartAddrAlign; + handle->rxBdRing[count].rxGenIdx = 0; + handle->rxBdRing[count].rxRingLen = buffConfig->rxRingLen; + handle->rxBdRing[count].rxBuffSizeAlign = buffConfig->rxBuffSizeAlign; + + handle->txBdRing[count].txBdBase = buffConfig->txDescStartAddrAlign; + handle->txBdRing[count].txRingLen = buffConfig->txRingLen; + handle->txBdRing[count].txGenIdx = 0; + handle->txBdRing[count].txConsumIdx = 0; + handle->txBdRing[count].txDescUsed = 0; +#ifdef ENET_PTP1588FEATURE_REQUIRED + assert(bufferConfig->rxPtpTsData); + assert(bufferConfig->txPtpTsData); + assert(buffConfig->rxRingLen <= ENET_RXBUFFSTORE_NUM); + + uint32_t index; + + handle->rxBdRing[count].rxPtpTsDataRing.ptpTsData = buffConfig->rxPtpTsData; + handle->rxBdRing[count].rxPtpTsDataRing.front = 0; + handle->rxBdRing[count].rxPtpTsDataRing.end = 0; + handle->rxBdRing[count].rxPtpTsDataRing.size = buffConfig->ptpTsRxBuffNum; + handle->txBdRing[count].txPtpTsDataRing.ptpTsData = buffConfig->txPtpTsData; + handle->txBdRing[count].txPtpTsDataRing.front = 0; + handle->txBdRing[count].txPtpTsDataRing.end = 0; + handle->txBdRing[count].txPtpTsDataRing.size = buffConfig->ptpTsTxBuffNum; + + for (index = 0; index < buffConfig->rxRingLen; index++) + { + handle->rxbuffers[index] = *(buffConfig->rxBufferStartAddr + index); + } +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + /* Enable tx interrupt for use transactional API to do tx buffer free/requeue. */ + base->DMA_CH[count].DMA_CHX_INT_EN |= ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK; + /* Check if the rx interrrupt is enabled. */ + rxIntEnable |= (base->DMA_CH[count].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK); + buffConfig++; + } + + handle->rxintEnable = rxIntEnable ? true : false; + + /* Save the handle pointer in the global variables. */ + s_ENETHandle[ENET_GetInstance(base)] = handle; + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Enable the NVIC for tx. */ + s_enetIsr = ENET_IRQHandler; + EnableIRQ(s_enetIrqId[ENET_GetInstance(base)]); +} + +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + assert(macAddr); + + uint32_t address = base->MAC_ADDR_LOW; + + /* Get from physical address lower register. */ + macAddr[2] = 0xFFU & (address >> 24U); + macAddr[3] = 0xFFU & (address >> 16U); + macAddr[4] = 0xFFU & (address >> 8U); + macAddr[5] = 0xFFU & address; + + /* Get from physical address high register. */ + address = base->MAC_ADDR_HIGH; + macAddr[0] = 0xFFU & (address >> 8U); + macAddr[1] = 0xFFU & address; +} + +void ENET_SetSMI(ENET_Type *base) +{ + uint32_t crDiv; + uint32_t srcClock_Hz = CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000000U; + + if ((srcClock_Hz >= 20U) && (srcClock_Hz < 35)) + { + crDiv = 2; + } + else if ((srcClock_Hz >= 35) && (srcClock_Hz < 60)) + { + crDiv = 3; + } + else if ((srcClock_Hz >= 100) && (srcClock_Hz < 150)) + { + crDiv = 1; + } + else + { + crDiv = 0; + } + + base->MAC_MDIO_ADDR = ENET_MAC_MDIO_ADDR_CR(crDiv); +} + +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t reg = base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_CR_MASK; + + /* Build MII write command. */ + base->MAC_MDIO_ADDR = reg | ENET_MAC_MDIO_ADDR_MOC(kENET_MiiWriteFrame) | ENET_MAC_MDIO_ADDR_PA(phyAddr) | + ENET_MAC_MDIO_ADDR_RDA(phyReg); + base->MAC_MDIO_DATA = data; + base->MAC_MDIO_ADDR |= ENET_MAC_MDIO_ADDR_MB_MASK; +} + +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) +{ + uint32_t reg = base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_CR_MASK; + + /* Build MII read command. */ + base->MAC_MDIO_ADDR = reg | ENET_MAC_MDIO_ADDR_MOC(kENET_MiiReadFrame) | ENET_MAC_MDIO_ADDR_PA(phyAddr) | + ENET_MAC_MDIO_ADDR_RDA(phyReg); + base->MAC_MDIO_ADDR |= ENET_MAC_MDIO_ADDR_MB_MASK; +} + +void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter) +{ + uint8_t index; + uint32_t *reg = wakeFilter; + + /* Disable the tx dma. */ + base->DMA_CH[0].DMA_CHX_TX_CTRL &= ~ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK; + base->DMA_CH[1].DMA_CHX_TX_CTRL &= ~ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK; + + /* Disable the mac tx/rx. */ + base->MAC_CONFIG &= ~(ENET_MAC_CONFIG_RE_MASK | ENET_MAC_CONFIG_TE_MASK); + /* Enable the remote wakeup packet and enable the power down mode. */ + if (wakeFilter) + { + for (index = 0; index < ENET_WAKEUPFILTER_NUM; index++) + { + base->MAC_RWAKE_FRFLT = *reg; + reg++; + } + } + base->MAC_PMT_CRTL_STAT = ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK | ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK | + ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK; + + /* Enable the MAC rx. */ + base->MAC_CONFIG |= ENET_MAC_CONFIG_RE_MASK; +} + +status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *length, uint8_t channel) +{ + assert(handle); + assert(length); + + enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel]; + enet_rx_bd_struct_t *rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; + uint16_t index = rxBdRing->rxGenIdx; + + /* Reset the length to zero. */ + *length = 0; + + if (rxDesc->control & ENET_RXDESCRIP_WR_OWN_MASK) + { + return kStatus_ENET_RxFrameEmpty; + } + else + { + do + { + /* Application owns the buffer descriptor, get the length. */ + if (rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK) + { + if (rxDesc->control & ENET_RXDESCRIP_WR_ERRSUM_MASK) + { + return kStatus_ENET_RxFrameError; + } + *length = rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK; + return kStatus_Success; + } + + index = ENET_IncreaseIndex(index, rxBdRing->rxRingLen); + rxDesc = rxBdRing->rxBdBase + index; + } while (index != rxBdRing->rxGenIdx); + + return kStatus_ENET_RxFrameError; + } +} + +status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel) +{ + assert(handle); + + uint32_t len = 0; + uint32_t offset = 0; + uint32_t control; + bool isLastBuff = false; + enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel]; + enet_rx_bd_struct_t *rxDesc; + status_t result = kStatus_Fail; + uint16_t index = rxBdRing->rxGenIdx; + bool suspend = false; +#ifdef ENET_PTP1588FEATURE_REQUIRED + uint32_t buffer; + uint32_t bufferAdd; +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + + /* Suspend and command for rx. */ + if (base->DMA_CH[channel].DMA_CHX_STAT & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) + { + suspend = true; + } + + /* For data-NULL input, only update the buffer descriptor. */ + if ((!data)) + { + do + { + /* Get the control flag. */ + rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; + rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen); + control = rxDesc->control; + /* Updates the receive buffer descriptors. */ + ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable); + + /* Find the last buffer descriptor for the frame. */ + if (control & ENET_RXDESCRIP_WR_LD_MASK) + { +#ifdef ENET_PTP1588FEATURE_REQUIRED + /* Reinit for the context descritor which has been updated by DMA. */ + rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; + if (rxDesc->control & ENET_RXDESCRIP_WR_CTXT_MASK) + { + if (!handle->doubleBuffEnable) + { + buffer = handle->rxbuffers[rxBdRing->rxGenIdx]; + ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, NULL, handle->rxintEnable, + handle->doubleBuffEnable); + } + else + { + buffer = handle->rxbuffers[2 * rxBdRing->rxGenIdx]; + bufferAdd = handle->rxbuffers[2 * rxBdRing->rxGenIdx + 1]; + ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, (void *)bufferAdd, handle->rxintEnable, + handle->doubleBuffEnable); + } + rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen); + } +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + break; + } + } while (rxBdRing->rxGenIdx != index); + + result = kStatus_Success; + } + else + { +#ifdef ENET_PTP1588FEATURE_REQUIRED + enet_ptp_time_data_t ptpTsData; + bool ptp1588 = false; +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + + while ((!isLastBuff)) + { + /* The last buffer descriptor of a frame. */ + rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; + rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen); +#ifdef ENET_PTP1588FEATURE_REQUIRED + if (rxDesc->control & ENET_RXDESCRIP_WR_FD_MASK) + { + ptp1588 = ENET_Ptp1588ParseFrame((uint8_t *)rxDesc->buff1Addr, &ptpTsData, false); + } +#endif + if (rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK) + { + /* This is a valid frame. */ + isLastBuff = true; + if (length == (rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK)) + { + /* Copy the frame to user's buffer. */ + len = (rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK) - offset; + if (len > rxBdRing->rxBuffSizeAlign) + { + memcpy(data + offset, (void *)rxDesc->buff1Addr, rxBdRing->rxBuffSizeAlign); + offset += rxBdRing->rxBuffSizeAlign; + memcpy(data + offset, (void *)rxDesc->buff2Addr, len - rxBdRing->rxBuffSizeAlign); + } + else + { + memcpy(data + offset, (void *)rxDesc->buff1Addr, len); + } + + result = kStatus_Success; + } + + /* Updates the receive buffer descriptors. */ + ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable); +#ifdef ENET_PTP1588FEATURE_REQUIRED + /* Store the rx timestamp which is in the next buffer descriptor of the last + * descriptor of a frame. */ + rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; + + /* Reinit for the context descritor which has been updated by DMA. */ + if (rxDesc->control & ENET_RXDESCRIP_WR_CTXT_MASK) + { + if (ptp1588) + { + ENET_StoreRxFrameTime(base, handle, rxDesc, channel, &ptpTsData); + } + + if (!handle->doubleBuffEnable) + { + buffer = handle->rxbuffers[rxBdRing->rxGenIdx]; + ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, NULL, handle->rxintEnable, + handle->doubleBuffEnable); + } + else + { + buffer = handle->rxbuffers[2 * rxBdRing->rxGenIdx]; + bufferAdd = handle->rxbuffers[2 * rxBdRing->rxGenIdx + 1]; + ENET_UpdateRxDescriptor(rxDesc, (void *)buffer, (void *)bufferAdd, handle->rxintEnable, + handle->doubleBuffEnable); + } + rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen); + } + base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR; +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + } + else + { + /* Store a frame on several buffer descriptors. */ + isLastBuff = false; + /* Length check. */ + if (offset >= length) + { + /* Updates the receive buffer descriptors. */ + ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable); + break; + } + + memcpy(data + offset, (void *)rxDesc->buff1Addr, rxBdRing->rxBuffSizeAlign); + offset += rxBdRing->rxBuffSizeAlign; + if ((rxDesc->buff2Addr) && (handle->doubleBuffEnable)) + { + memcpy(data + offset, (void *)rxDesc->buff2Addr, rxBdRing->rxBuffSizeAlign); + offset += rxBdRing->rxBuffSizeAlign; + } + + /* Updates the receive buffer descriptors. */ + ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable); + } + } + } + + /* Set command for rx when it is suspend. */ + if (suspend) + { + base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR; + } + + return result; +} + +void ENET_UpdateRxDescriptor( + enet_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable) +{ + assert(rxDesc); + uint32_t control = ENET_RXDESCRIP_RD_OWN_MASK | ENET_RXDESCRIP_RD_BUFF1VALID_MASK; + + if (intEnable) + { + control |= ENET_RXDESCRIP_RD_IOC_MASK; + } + + if (doubleBuffEnable) + { + control |= ENET_RXDESCRIP_RD_BUFF2VALID_MASK; + } + + /* Update the buffer if needed. */ + if (buffer1) + { + rxDesc->buff1Addr = (uint32_t)buffer1; + } + if (buffer2) + { + rxDesc->buff2Addr = (uint32_t)buffer2; + } + else + { + rxDesc->buff2Addr = 0; + } + + rxDesc->reserved = 0; + rxDesc->control = control; +} + +void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc, + void *buffer1, + uint32_t bytes1, + void *buffer2, + uint32_t bytes2, + uint32_t framelen, + bool intEnable, + bool tsEnable, + enet_desc_flag flag, + uint8_t slotNum) +{ + uint32_t control = ENET_TXDESCRIP_RD_BL1(bytes1) | ENET_TXDESCRIP_RD_BL2(bytes2); + + if (tsEnable) + { + control |= ENET_TXDESCRIP_RD_TTSE_MASK; + } + else + { + control &= ~ENET_TXDESCRIP_RD_TTSE_MASK; + } + + if (intEnable) + { + control |= ENET_TXDESCRIP_RD_IOC_MASK; + } + else + { + control &= ~ENET_TXDESCRIP_RD_IOC_MASK; + } + + /* Preare the descriptor for transmit. */ + txDesc->buff1Addr = (uint32_t)buffer1; + txDesc->buff2Addr = (uint32_t)buffer2; + txDesc->buffLen = control; + + control = ENET_TXDESCRIP_RD_FL(framelen) | ENET_TXDESCRIP_RD_LDFD(flag) | ENET_TXDESCRIP_RD_OWN_MASK; + + txDesc->controlStat = control; +} + +void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t channel) +{ + enet_tx_bd_ring_t *txBdRing = &handle->txBdRing[channel]; + enet_tx_bd_struct_t *txDesc = txBdRing->txBdBase + txBdRing->txConsumIdx; + + /* Need to update the first index for transmit buffer free. */ + while ((txBdRing->txDescUsed > 0) && (!(txDesc->controlStat & ENET_TXDESCRIP_RD_OWN_MASK))) + { +#ifdef ENET_PTP1588FEATURE_REQUIRED + uint32_t nanosecond; + uint32_t nanoOverSize = ENET_NANOSECS_ONESECOND; /* Default use the digital rollover. */ + + if (txDesc->controlStat & ENET_TXDESCRIP_RD_LD_MASK) + { + enet_ptp_time_data_t *ptpTsData = txBdRing->txPtpTsDataRing.ptpTsData + txBdRing->txPtpTsDataRing.end; + if (txDesc->controlStat & ENET_TXDESCRIP_WB_TTSS_MASK) + { + /* Get transmit time stamp second. */ + nanosecond = txDesc->buff2Addr | txDesc->buff1Addr; + if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)) + { + /* Binary rollover. */ + nanoOverSize = ENET_MAC_SYS_TIME_NSCND_TSSS_MASK; + } + ptpTsData->timeStamp.second = nanosecond / nanoOverSize; + ptpTsData->timeStamp.nanosecond = nanosecond % nanoOverSize; + + /* Store the timestamp to the transmit timestamp ring. */ + ENET_Ptp1588UpdateTimeRing(&txBdRing->txPtpTsDataRing, ptpTsData); + } + } +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + + /* For tx buffer free or requeue for each descriptor. + * The tx interrupt callback should free/requeue the tx buffer. */ + if (handle->callback) + { + handle->callback(base, handle, kENET_TxIntEvent, channel, handle->userData); + } + + txBdRing->txDescUsed--; + + /* Update the txConsumIdx/txDesc. */ + txBdRing->txConsumIdx = ENET_IncreaseIndex(txBdRing->txConsumIdx, txBdRing->txRingLen); + txDesc = txBdRing->txBdBase + txBdRing->txConsumIdx; + } +} + +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length) +{ + assert(handle); + assert(data); + + enet_tx_bd_ring_t *txBdRing; + enet_tx_bd_struct_t *txDesc; + uint8_t channel = 0; + bool ptp1588 = false; + + if (length > 2 * ENET_TXDESCRIP_RD_BL1_MASK) + { + return kStatus_ENET_TxFrameOverLen; + } + + /* Choose the transit queue. */ + channel = ENET_GetTxRingId(data, handle); + + /* Check if the DMA owns the descriptor. */ + txBdRing = (enet_tx_bd_ring_t *)&handle->txBdRing[channel]; + txDesc = txBdRing->txBdBase + txBdRing->txGenIdx; + if (txBdRing->txRingLen == txBdRing->txDescUsed) + { + return kStatus_ENET_TxFrameBusy; + } + +#ifdef ENET_PTP1588FEATURE_REQUIRED + enet_ptp_time_data_t ptpTsData; + + ptp1588 = ENET_Ptp1588ParseFrame(data, &ptpTsData, true); +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + + /* Fill the descriptor. */ + if (length <= ENET_TXDESCRIP_RD_BL1_MASK) + { + ENET_SetupTxDescriptor(txDesc, data, length, NULL, 0, length, true, ptp1588, kENET_FirstLastFlag, 0); + } + else + { + ENET_SetupTxDescriptor(txDesc, data, ENET_TXDESCRIP_RD_BL1_MASK, data + ENET_TXDESCRIP_RD_BL1_MASK, + (length - ENET_TXDESCRIP_RD_BL1_MASK), length, true, ptp1588, kENET_FirstLastFlag, 0); + } + + /* Increase the index. */ + txBdRing->txGenIdx = ENET_IncreaseIndex(txBdRing->txGenIdx, txBdRing->txRingLen); + /* Disable interrupt first and then enable interrupt to avoid the race condition. */ + DisableIRQ(s_enetIrqId[ENET_GetInstance(base)]); + txBdRing->txDescUsed++; + EnableIRQ(s_enetIrqId[ENET_GetInstance(base)]); + + /* Update the transmit tail address. */ + txDesc = txBdRing->txBdBase + txBdRing->txGenIdx; + if (!txBdRing->txGenIdx) + { + txDesc = txBdRing->txBdBase + txBdRing->txRingLen; + } + base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = (uint32_t)txDesc & ~ENET_ADDR_ALIGNMENT; + + return kStatus_Success; +} + +#ifdef ENET_PTP1588FEATURE_REQUIRED +void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecond) +{ + assert(second); + assert(nanosecond); + + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Get the current PTP time. */ + *second = ((uint64_t)(base->MAC_SYS_TIME_HWORD_SCND & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK) << 32U) | + base->MAC_SYS_TIME_SCND; + *nanosecond = base->MAC_SYS_TIME_NSCND & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK; + if (!(base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)) + { + /* Binary rollover, the unit of the increment is ~ 0.466 ns. */ + *nanosecond = *nanosecond / 1000U * 466U; + } + + /* Enables the interrupt. */ + EnableGlobalIRQ(primask); +} + +void ENET_Ptp1588CorrectTimerInCoarse(ENET_Type *base, enet_systime_op operation, uint32_t second, uint32_t nanosecond) +{ + uint32_t corrSecond = second; + uint32_t corrNanosecond; + + /* Set the system timer. */ + if (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK) + { + if (operation == kENET_SystimeSubtract) + { + /* Set with the complement of the sub-second. */ + corrSecond = ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK - (second - 1); + corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK | + ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(ENET_NANOSECS_ONESECOND - nanosecond); + } + else + { + corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(nanosecond); + } + } + else + { + nanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK / ENET_NANOSECS_ONESECOND * nanosecond; + if (operation == kENET_SystimeSubtract) + { + /* Set with the complement of the sub-second. */ + corrSecond = ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK - (second - 1); + corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK | + ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK + 1 - nanosecond); + } + else + { + corrNanosecond = ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(nanosecond); + } + } + + base->MAC_SYS_TIME_SCND_UPD = corrSecond; + base->MAC_SYS_TIME_NSCND_UPD = corrNanosecond; + + /* Update the timer. */ + base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK; + while (base->MAC_TIMESTAMP_CTRL & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK) + ; +} + +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + uint32_t result = kStatus_Success; + uint8_t count; + uint8_t index = handle->multiQueEnable ? 2 : 1; + + for (count = 0; count < index; count++) + { + result = ENET_Ptp1588SearchTimeRing(&handle->txBdRing[count].txPtpTsDataRing, ptpTimeData); + if (result == kStatus_Success) + { + break; + } + } + + return result; +} + +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + uint32_t result = kStatus_Success; + uint8_t count; + uint8_t index = handle->multiQueEnable ? 2 : 1; + + for (count = 0; count < index; count++) + { + result = ENET_Ptp1588SearchTimeRing(&handle->rxBdRing[count].rxPtpTsDataRing, ptpTimeData); + if (result == kStatus_Success) + { + break; + } + } + + return result; +} + +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + +void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + /* Check for the interrupt source type. */ + /* DMA CHANNEL 0. */ + if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_DC0IS_MASK) + { + uint32_t flag = base->DMA_CH[0].DMA_CHX_STAT; + if (flag & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK) + { + base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK; + if (handle->callback) + { + handle->callback(base, handle, kENET_RxIntEvent, 0, handle->userData); + } + } + if (flag & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK) + { + base->DMA_CH[0].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK; + ENET_ReclaimTxDescriptor(base, handle, 0); + } + } + + /* DMA CHANNEL 1. */ + if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_DC1IS_MASK) + { + uint32_t flag = base->DMA_CH[1].DMA_CHX_STAT; + if (flag & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK) + { + base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_RI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK; + if (handle->callback) + { + handle->callback(base, handle, kENET_RxIntEvent, 1, handle->userData); + } + } + if (flag & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK) + { + base->DMA_CH[1].DMA_CHX_STAT = ENET_DMA_CH_DMA_CHX_STAT_TI_MASK | ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK; + ENET_ReclaimTxDescriptor(base, handle, 1); + } + } + +#ifdef ENET_PTP1588FEATURE_REQUIRED + /* MAC TIMESTAMP. */ + if (base->DMA_INTR_STAT & ENET_DMA_INTR_STAT_MACIS_MASK) + { + if (base->MAC_INTR_STAT & ENET_MAC_INTR_STAT_TSIS_MASK) + { + if (handle->callback) + { + handle->callback(base, handle, kENET_TimeStampIntEvent, 0, handle->userData); + } + } + } +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ETHERNET_DriverIRQHandler(void) +{ + s_enetIsr(ENET, s_ENETHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} diff --git a/fnet_demos/common/startup/LPC54628/fsl_enet.h b/fnet_demos/common/startup/LPC54628/fsl_enet.h new file mode 100644 index 00000000..631fd881 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_enet.h @@ -0,0 +1,1178 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_ENET_H_ +#define _FSL_ENET_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_enet + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines the driver version. */ +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/*! @name Control and status region bit masks of the receive buffer descriptor. */ +/*@{*/ +/*! @brief Defines for read format. */ +#define ENET_RXDESCRIP_RD_BUFF1VALID_MASK (1U << 24) /*!< Buffer1 address valid. */ +#define ENET_RXDESCRIP_RD_BUFF2VALID_MASK (1U << 25) /*!< Buffer2 address valid. */ +#define ENET_RXDESCRIP_RD_IOC_MASK (1U << 30) /*!< Interrupt enable on complete. */ +#define ENET_RXDESCRIP_RD_OWN_MASK (1U << 31) /*!< Own bit. */ + +/*! @brief Defines for write back format. */ +#define ENET_RXDESCRIP_WR_ERR_MASK ((1U << 3) | (1U << 7)) +#define ENET_RXDESCRIP_WR_PYLOAD_MASK (0x7U) +#define ENET_RXDESCRIP_WR_PTPMSGTYPE_MASK (0xF00U) +#define ENET_RXDESCRIP_WR_PTPTYPE_MASK (1U << 12) +#define ENET_RXDESCRIP_WR_PTPVERSION_MASK (1U << 13) +#define ENET_RXDESCRIP_WR_PTPTSA_MASK (1U << 14) +#define ENET_RXDESCRIP_WR_PACKETLEN_MASK (0x7FFFU) +#define ENET_RXDESCRIP_WR_ERRSUM_MASK (1U << 15) +#define ENET_RXDESCRIP_WR_TYPE_MASK (0x30000U) +#define ENET_RXDESCRIP_WR_DE_MASK (1U << 19) +#define ENET_RXDESCRIP_WR_RE_MASK (1U << 20) +#define ENET_RXDESCRIP_WR_OE_MASK (1U << 21) +#define ENET_RXDESCRIP_WR_RS0V_MASK (1U << 25) +#define ENET_RXDESCRIP_WR_RS1V_MASK (1U << 26) +#define ENET_RXDESCRIP_WR_RS2V_MASK (1U << 27) +#define ENET_RXDESCRIP_WR_LD_MASK (1U << 28) +#define ENET_RXDESCRIP_WR_FD_MASK (1U << 29) +#define ENET_RXDESCRIP_WR_CTXT_MASK (1U << 30) +#define ENET_RXDESCRIP_WR_OWN_MASK (1U << 31) +/*@}*/ + +/*! @name Control and status bit masks of the transmit buffer descriptor. */ +/*@{*/ +/*! @brief Defines for read format. */ +#define ENET_TXDESCRIP_RD_BL1_MASK (0x3fffU) +#define ENET_TXDESCRIP_RD_BL2_MASK (ENET_TXDESCRIP_RD_BL1_MASK << 16) +#define ENET_TXDESCRIP_RD_BL1(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) +#define ENET_TXDESCRIP_RD_BL2(n) (((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) << 16) +#define ENET_TXDESCRIP_RD_TTSE_MASK (1U << 30) +#define ENET_TXDESCRIP_RD_IOC_MASK (1U << 31) + +#define ENET_TXDESCRIP_RD_FL_MASK (0x7FFFU) +#define ENET_TXDESCRIP_RD_FL(n) ((uint32_t)(n) & ENET_TXDESCRIP_RD_FL_MASK) +#define ENET_TXDESCRIP_RD_CIC(n) (((uint32_t)(n) & 0x3) << 16) +#define ENET_TXDESCRIP_RD_TSE_MASK (1U << 18) +#define ENET_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n) & 0x0f) << 19) +#define ENET_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n) & 0x07) << 23) +#define ENET_TXDESCRIP_RD_CPC(n) (((uint32_t)(n) & 0x03) << 26) +#define ENET_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n) & 0x03) << 28) +#define ENET_TXDESCRIP_RD_LD_MASK (1U << 28) +#define ENET_TXDESCRIP_RD_FD_MASK (1U << 29) +#define ENET_TXDESCRIP_RD_CTXT_MASK (1U << 30) +#define ENET_TXDESCRIP_RD_OWN_MASK (1UL << 31) + +/*! @brief Defines for write back format. */ +#define ENET_TXDESCRIP_WB_TTSS_MASK (1UL << 17) +/*@}*/ + +/*! @name Bit mask for interrupt enable type. */ +/*@{*/ +#define ENET_ABNORM_INT_MASK \ + (ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK | \ + ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK | \ + ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK) +#define ENET_NORM_INT_MASK \ + (ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK | \ + ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK) +/*@}*/ + +/*! @name Defines some Ethernet parameters. */ +/*@{*/ + +#define ENET_FRAME_MAX_FRAMELEN (1518U)/*!< Default maximum Ethernet frame size. */ +#define ENET_ADDR_ALIGNMENT (0x3U) /*!< Recommended ethernet buffer alignment. */ +#define ENET_BUFF_ALIGNMENT (4U) /*!< Receive buffer alignment shall be 4bytes-aligned. */ +#define ENET_RING_NUM_MAX (2U) /*!< The Maximum number of tx/rx descriptor rings. */ +#define ENET_MTL_RXFIFOSIZE (2048U) /*!< The rx fifo size. */ +#define ENET_MTL_TXFIFOSIZE (2048U) /*!< The tx fifo size. */ +#define ENET_MACINT_ENUM_OFFSET (16U) /*!< The offest for mac interrupt in enum type. */ +/*@}*/ + +#ifdef ENET_PTP1588FEATURE_REQUIRED +/* Define the buffer length to store the rx buffers address. + * because the context descriptor will be updated for store the time + * stamp for rx frame. so we need to reinit the descriptors. + * This macro shall at least equal to the rxRingLen + * assigned in the enet_buffer_config. That means if the rx descriptor + * length is larger than 5, please increse this macro. */ +#define ENET_RXBUFFSTORE_NUM (6) +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + +/*! @brief Defines the status return codes for transaction. */ +enum _enet_status +{ + kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< A frame received but data error happen. */ + kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< Failed to receive a frame. */ + kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< No frame arrive. */ + kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< Transmit descriptors are under process. */ + kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 4U), /*!< Transmit frame fail. */ + kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 5U) /*!< Transmit oversize. */ +#ifdef ENET_PTP1588FEATURE_REQUIRED + , + kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Timestamp ring full. */ + kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 7U) /*!< Timestamp ring empty. */ +#endif /* ENET_PTP1588FEATURE_REQUIRED */ +}; + +/*! @brief Defines the MII/RMII mode for data interface between the MAC and the PHY. */ +typedef enum _enet_mii_mode { + kENET_MiiMode = 0U, /*!< MII mode for data interface. */ + kENET_RmiiMode = 1U /*!< RMII mode for data interface. */ +} enet_mii_mode_t; + +/*! @brief Defines the 10/100 Mbps speed for the MII data interface. */ +typedef enum _enet_mii_speed { + kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ + kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */ +} enet_mii_speed_t; + +/*! @brief Defines the half or full duplex for the MII data interface. */ +typedef enum _enet_mii_duplex { + kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ + kENET_MiiFullDuplex /*!< Full duplex mode. */ +} enet_mii_duplex_t; + +/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */ +typedef enum _enet_mii_normal_opcode { + kENET_MiiWriteFrame = 1U, /*!< Write frame operation for a valid MII management frame. */ + kENET_MiiReadFrame = 3U /*!< Read frame operation for a valid MII management frame. */ +} enet_mii_normal_opcode; + +/*! @brief Define the DMA maximum transmit burst length. */ +typedef enum _enet_dma_burstlen { + kENET_BurstLen1 = 0x00001U, /*!< DMA burst length 1. */ + kENET_BurstLen2 = 0x00002U, /*!< DMA burst length 2. */ + kENET_BurstLen4 = 0x00004U, /*!< DMA burst length 4. */ + kENET_BurstLen8 = 0x00008U, /*!< DMA burst length 8. */ + kENET_BurstLen16 = 0x00010U, /*!< DMA burst length 16. */ + kENET_BurstLen32 = 0x00020U, /*!< DMA burst length 32. */ + kENET_BurstLen64 = 0x10008U, /*!< DMA burst length 64. eight times enabled. */ + kENET_BurstLen128 = 0x10010U, /*!< DMA burst length 128. eight times enabled. */ + kENET_BurstLen256 = 0x10020U, /*!< DMA burst length 256. eight times enabled. */ +} enet_dma_burstlen; + +/*! @brief Define the flag for the descriptor. */ +typedef enum _enet_desc_flag { + kENET_MiddleFlag = 0, /*!< It's a middle descriptor of the frame. */ + kENET_FirstFlagOnly, /*!< It's the first descriptor of the frame. */ + kENET_LastFlagOnly, /*!< It's the last descriptor of the frame. */ + kENET_FirstLastFlag /*!< It's the first and last descriptor of the frame. */ +} enet_desc_flag; + +/*! @brief Define the system time adjust operation control. */ +typedef enum _enet_systime_op { + kENET_SystimeAdd = 0U, /*!< System time add to. */ + kENET_SystimeSubtract = 1U /*!< System time subtract. */ +} enet_systime_op; + +/*! @brief Define the system time rollover control. */ +typedef enum _enet_ts_rollover_type { + kENET_BinaryRollover = 0, /*!< System time binary rollover.*/ + kENET_DigitalRollover = 1 /*!< System time digital rollover.*/ +} enet_ts_rollover_type; + +/*! @brief Defines some special configuration for ENET. + * + * These control flags are provided for special user requirements. + * Normally, these is no need to set this control flags for ENET initialization. + * But if you have some special requirements, set the flags to specialControl + * in the enet_config_t. + * @note "kENET_StoreAndForward" is recommended to be set when the + * ENET_PTP1588FEATURE_REQUIRED is defined or else the timestamp will be mess-up + * when the overflow happens. + */ +typedef enum _enet_special_config { + + /***********************DMA CONFGI**********************************************/ + kENET_DescDoubleBuffer = 0x0001U, /*!< The double buffer is used in the tx/rx descriptor. */ + /**************************MTL************************************/ + kENET_StoreAndForward = 0x0002U, /*!< The rx/tx store and forward enable. */ + /***********************MAC****************************************/ + kENET_PromiscuousEnable = 0x0004U, /*!< The promiscuous enabled. */ + kENET_FlowControlEnable = 0x0008U, /*!< The flow control enabled. */ + kENET_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */ + kENET_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */ + kENET_8023AS2KPacket = 0x0040U /*!< 8023as support for 2K packets. */ +} enet_special_config_t; + +/*! @brief List of DMA interrupts supported by the ENET interrupt. This + * enumeration uses one-bot encoding to allow a logical OR of multiple + * members. + */ +typedef enum _enet_dma_interrupt_enable { + kENET_DmaTx = ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK, /*!< Tx interrupt. */ + kENET_DmaTxStop = ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK, /*!< Tx stop interrupt. */ + kENET_DmaTxBuffUnavail = ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK, /*!< Tx buffer unavailable. */ + kENET_DmaRx = ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK, /*!< Rx interrupt. */ + kENET_DmaRxBuffUnavail = ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK, /*!< Rx buffer unavailable. */ + kENET_DmaRxStop = ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK, /*!< Rx stop. */ + kENET_DmaRxWatchdogTimeout = ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK, /*!< Rx watchdog timeout. */ + kENET_DmaEarlyTx = ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK, /*!< Early transmit. */ + kENET_DmaEarlyRx = ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK, /*!< Early receive. */ + kENET_DmaBusErr = ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK, /*!< Fatal bus error. */ +} enet_dma_interrupt_enable_t; + +/*! @brief List of mac interrupts supported by the ENET interrupt. This + * enumeration uses one-bot encoding to allow a logical OR of multiple + * members. + */ +typedef enum _enet_mac_interrupt_enable { + kENET_MacPmt = (ENET_MAC_INTR_EN_PMTIE_MASK << ENET_MACINT_ENUM_OFFSET), + kENET_MacTimestamp = (ENET_MAC_INTR_EN_TSIE_MASK << ENET_MACINT_ENUM_OFFSET), +} enet_mac_interrupt_enable_t; + +/*! @brief Defines the common interrupt event for callback use. */ +typedef enum _enet_event { + kENET_RxIntEvent, /*!< Receive interrupt event. */ + kENET_TxIntEvent, /*!< Transmit interrupt event. */ + kENET_WakeUpIntEvent, /*!< Wake up interrupt event. */ + kENET_TimeStampIntEvent, /*!< Time stamp interrupt event. */ +} enet_event_t; + +/*! @brief Define the DMA transmit arbitration for multi-queue. */ +typedef enum _enet_dma_tx_sche { + kENET_FixPri = 0, /*!< Fixed priority. channel 0 has lower priority than channel 1. */ + kENET_WeightStrPri, /*!< Weighted(burst length) strict priority. */ + kENET_WeightRoundRobin /*!< Weighted (weight factor) round robin. */ +} enet_dma_tx_sche; + +/*! @brief Define the MTL tx scheduling algorithm for multiple queues/rings. */ +typedef enum _enet_mtl_multiqueue_txsche { + kENET_txWeightRR = 0U, /*!< Tx weight round-robin. */ + kENET_txStrPrio = 3U, /*!< Tx strict priority. */ +} enet_mtl_multiqueue_txsche; + +/*! @brief Define the MTL rx scheduling algorithm for multiple queues/rings. */ +typedef enum _enet_mtl_multiqueue_rxsche { + kENET_rxStrPrio = 0U, /*!< Tx weight round-robin, rx strict priority. */ + kENET_rxWeightStrPrio, /*!< Tx strict priority, rx weight strict priority. */ +} enet_mtl_multiqueue_rxsche; + +/*! @brief Define the MTL rx queue and DMA channel mapping. */ +typedef enum _enet_mtl_rxqueuemap { + kENET_StaticDirctMap = 0x100U, /*!< The received fame in rx Qn(n = 0,1) direclty map to dma channel n. */ + kENET_DynamicMap = + 0x1010U, /*!< The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac. + */ +} enet_mtl_rxqueuemap; + +/*! @brief Defines the ENET PTP message related constant. */ +typedef enum _enet_ptp_event_type { + kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ + kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ + kENET_PtpEventPort = 319U, /*!< PTP event port number. */ + kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ +} enet_ptp_event_type_t; + +/*! @brief Defines the receive descriptor structure + * has the read-format and write-back format structure. They both + * has the same size with different region definition. so + * we define the read-format region as the recive descriptor structure + * Use the read-format region mask bits in the descriptor initialization + * Use the write-back format region mask bits in the receive data process. + */ +typedef struct _enet_rx_bd_struct +{ + __IO uint32_t buff1Addr; /*!< Buffer 1 address */ + __IO uint32_t reserved; /*!< Reserved */ + __IO uint32_t buff2Addr; /*!< Buffer 2 or next descriptor address */ + __IO uint32_t control; /*!< Buffer 1/2 byte counts and control */ +} enet_rx_bd_struct_t; + +/*! @brief Defines the transmit descriptor structure + * has the read-format and write-back format structure. They both + * has the same size with different region definition. so + * we define the read-format region as the transmit descriptor structure + * Use the read-format region mask bits in the descriptor initialization + * Use the write-back format region mask bits in the transmit data process. + */ +typedef struct _enet_tx_bd_struct +{ + __IO uint32_t buff1Addr; /*!< Buffer 1 address */ + __IO uint32_t buff2Addr; /*!< Buffer 2 address */ + __IO uint32_t buffLen; /*!< Buffer 1/2 byte counts */ + __IO uint32_t controlStat; /*!< TDES control and status word */ +} enet_tx_bd_struct_t; + +#ifdef ENET_PTP1588FEATURE_REQUIRED +/*! @brief Defines the ENET PTP time stamp structure. */ +typedef struct _enet_ptp_time +{ + uint64_t second; /*!< Second. */ + uint32_t nanosecond; /*!< Nanosecond. */ +} enet_ptp_time_t; + +/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ +typedef struct _enet_ptp_time_data +{ + uint8_t version; /*!< PTP version. */ + uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ + uint16_t sequenceId; /*!< PTP sequence ID. */ + uint8_t messageType; /*!< PTP message type. */ + enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ +} enet_ptp_time_data_t; + +/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ +typedef struct _enet_ptp_time_data_ring +{ + uint32_t front; /*!< The first index of the ring. */ + uint32_t end; /*!< The end index of the ring. */ + uint32_t size; /*!< The size of the ring. */ + enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */ +} enet_ptp_time_data_ring_t; + +/*! @brief Defines the ENET PTP configuration structure. */ +typedef struct _enet_ptp_config +{ + bool fineUpdateEnable; /*!< Use the fine update. */ + bool ptp1588V2Enable; /*!< ptp 1588 version 2 is used. */ + enet_ts_rollover_type tsRollover; /*!< 1588 time nanosecond rollover. */ +} enet_ptp_config_t; +#endif /* ENET_PTP1588FEATURE_REQUIRED */ + +/*! @brief Defines the buffer descriptor configure structure. + * + * Notes: + * 1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned. + * 2. The recommended minimum tx/rx ring length is 4. + * 3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end + * of the last last descriptor. because only the descriptors between the start address and the + * tail address will be used by DMA. + * 4. The decriptor address is the start address of all used contiguous memory. + * for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memorise + * for rx descriptor ring 0. + * 5. The "*rxBufferstartAddr" is the first element of rxRingLen (2*rxRingLen for double buffers) + * rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor + * the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for + * the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the + * address of a rxRingLen or 2*rxRingLen array. + */ +typedef struct _enet_buffer_config +{ + uint8_t rxRingLen; /*!< The length of receive buffer descriptor ring. */ + uint8_t txRingLen; /*!< The length of transmit buffer descriptor ring. */ + enet_tx_bd_struct_t *txDescStartAddrAlign; /*!< Aligned transmit descriptor start address. */ + enet_tx_bd_struct_t *txDescTailAddrAlign; /*!< Aligned transmit descriptor tail address. */ + enet_rx_bd_struct_t *rxDescStartAddrAlign; /*!< Aligned receive descriptor start address. */ + enet_rx_bd_struct_t *rxDescTailAddrAlign; /*!< Aligned receive descriptor tail address. */ + uint32_t *rxBufferStartAddr; /*!< Start address of the rx buffers. */ + uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ +#ifdef ENET_PTP1588FEATURE_REQUIRED + uint8_t ptpTsRxBuffNum; /*!< Receive 1588 timestamp buffer number*/ + uint8_t ptpTsTxBuffNum; /*!< Transmit 1588 timestamp buffer number*/ + enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */ + enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */ +#endif /* ENET_PTP1588FEATURE_REQUIRED */ +} enet_buffer_config_t; + +/*! @brief Defines the configuration when multi-queue is used. */ +typedef struct enet_multiqueue_config +{ + /***********************DMA block*******************************/ + enet_dma_tx_sche dmaTxSche; /*!< Transmit arbitation. */ + enet_dma_burstlen burstLen; /*!< Burset len for the queue 1. */ + uint8_t txdmaChnWeight[ENET_RING_NUM_MAX]; /*!< Transmit channel weight. */ + /***********************MTL block*******************************/ + enet_mtl_multiqueue_txsche mtltxSche; /*!< Transmit schedule for multi-queue. */ + enet_mtl_multiqueue_rxsche mtlrxSche; /*!< Receive schedule for multi-queue. */ + uint8_t rxqueweight[ENET_RING_NUM_MAX]; /*!< Refer to the MTL RxQ Control register. */ + uint32_t txqueweight[ENET_RING_NUM_MAX]; /*!< Refer to the MTL TxQ Quantum Weight register. */ + uint8_t rxqueuePrio[ENET_RING_NUM_MAX]; /*!< Receive queue priority. */ + uint8_t txqueuePrio[ENET_RING_NUM_MAX]; /*!< Refer to Transmit Queue Priority Mapping register. */ + enet_mtl_rxqueuemap mtlrxQuemap; /*!< Rx queue DMA Channel mapping. */ +} enet_multiqueue_config_t; + +/*! @brief Defines the basic configuration structure for the ENET device. + * + * Note: + * 1. Default the signal queue is used so the "*multiqueueCfg" is set default + * with NULL. Set the pointer with a valid configration pointer if the multiple + * queues are required. If multiple queue is enabled, please make sure the + * buffer configuration for all are prepared also. + */ +typedef struct _enet_config +{ + uint16_t specialControl; /*!< The logicl or of enet_special_config_t */ + enet_multiqueue_config_t *multiqueueCfg; /*!< Use both tx/rx queue(dma channel) 0 and 1. */ + /* -----------------MAC block-------------------------------*/ + enet_mii_mode_t miiMode; /*!< MII mode. */ + enet_mii_speed_t miiSpeed; /*!< MII Speed. */ + enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ + uint16_t pauseDuration; /*!< Used in the tx flow control frame, only valid when kENET_FlowControlEnable is set. */ +/* -----------------Timestamp -------------------------------*/ +#ifdef ENET_PTP1588FEATURE_REQUIRED + enet_ptp_config_t *ptpConfig; /*!< PTP 1588 feature configuration */ +#endif /* ENET_PTP1588FEATURE_REQUIRED */ +} enet_config_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _enet_handle enet_handle_t; + +/*! @brief ENET callback function. */ +typedef void (*enet_callback_t)( + ENET_Type *base, enet_handle_t *handle, enet_event_t event, uint8_t channel, void *userData); + +/*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */ +typedef struct _enet_tx_bd_ring +{ + enet_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */ + uint16_t txGenIdx; /*!< tx generate index. */ + uint16_t txConsumIdx; /*!< tx consum index. */ + volatile uint16_t txDescUsed; /*!< tx descriptor used number. */ + uint16_t txRingLen; /*!< tx ring length. */ +#ifdef ENET_PTP1588FEATURE_REQUIRED + enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */ +#endif /* ENET_PTP1588FEATURE_REQUIRED */ +} enet_tx_bd_ring_t; + +/*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */ +typedef struct _enet_rx_bd_ring +{ + enet_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */ + uint16_t rxGenIdx; /*!< The current available receive buffer descriptor pointer. */ + uint16_t rxRingLen; /*!< Receive ring length. */ + uint32_t rxBuffSizeAlign; /*!< Receive buffer size. */ +#ifdef ENET_PTP1588FEATURE_REQUIRED + enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */ +#endif /* ENET_PTP1588FEATURE_REQUIRED*/ +} enet_rx_bd_ring_t; + +/*! @brief Defines the ENET handler structure. */ +struct _enet_handle +{ + bool multiQueEnable; /*!< Enable multi-queue. */ + bool doubleBuffEnable; /*!< The double buffer is used in the descriptor. */ + bool rxintEnable; /*!< Rx interrup enabled. */ + enet_rx_bd_ring_t rxBdRing[ENET_RING_NUM_MAX]; /*!< Receive buffer descriptor. */ + enet_tx_bd_ring_t txBdRing[ENET_RING_NUM_MAX]; /*!< Transmit buffer descriptor. */ +#ifdef ENET_PTP1588FEATURE_REQUIRED + uint32_t rxbuffers[ENET_RXBUFFSTORE_NUM]; /*!< The Initi-rx buffers will be used for reInitialize. */ +#endif + enet_callback_t callback; /*!< Callback function. */ + void *userData; /*!< Callback function parameter.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET configure + * structure for ENET_Init(). User may use the initialized + * structure unchanged in ENET_Init(), or modify some fields of the + * structure before calling ENET_Init(). + * Example: + @code + enet_config_t config; + ENET_GetDefaultConfig(&config); + @endcode + * @param config The ENET mac controller configuration structure pointer. + */ +void ENET_GetDefaultConfig(enet_config_t *config); + +/*! + * @brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET basic + * configuration. + * + * @param base ENET peripheral base address. + * @param config ENET mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * @param macAddr ENET mac address of Ethernet device. This MAC address should be + * provided. + * @param refclkSrc_Hz ENET input reference clock. + */ +void ENET_Init(ENET_Type *base, const enet_config_t *config, uint8_t *macAddr, uint32_t refclkSrc_Hz); + +/*! + * @brief Deinitializes the ENET module. + + * This function gates the module clock and disables the ENET module. + * + * @param base ENET peripheral base address. + */ +void ENET_Deinit(ENET_Type *base); + +/*! + * @brief Initialize for all ENET descriptors. + * + * @note This function is do all tx/rx descriptors initialization. Because this API + * read all interrupt registers first and then set the interrupt flag for all descriptos, + * if the interrupt register is set. so the descriptor initialization should be called + * after ENET_Init(), ENET_EnableInterrupts() and ENET_CreateHandle()(if transactional APIs + * are used). + * + * @param base ENET peripheral base address. + * @param config The configuration for ENET. + * @param bufferConfig All buffers configuration. + */ +status_t ENET_DescriptorInit(ENET_Type *base, enet_config_t *config, enet_buffer_config_t *bufferConfig); + +/*! + * @brief Starts the ENET rx/tx. + * This function enable the tx/rx and starts the rx/tx DMA. + * This shall be set after ENET initialization and before + * starting to receive the data. + * + * @param base ENET peripheral base address. + * @param rxRingNum The number of the used rx rings. It shall not be + * larger than the ENET_RING_NUM_MAX(2). If the ringNum is set with + * 1, the ring 0 will be used. + * @param txRingNum The number of the used tx rings. It shall not be + * larger than the ENET_RING_NUM_MAX(2). If the ringNum is set with + * 1, the ring 0 will be used. + * + * @note This must be called after all the ENET initilization. + * And should be called when the ENET receive/transmit is required. + */ +void ENET_StartRxTx(ENET_Type *base, uint8_t txRingNum, uint8_t rxRingNum); + +/* @} */ + +/*! + * @name MII interface operation + * @{ + */ + +/*! + * @brief Sets the ENET MII speed and duplex. + * + * This API is provided to dynamically change the speed and dulpex for MAC. + * + * @param base ENET peripheral base address. + * @param speed The speed of the RMII mode. + * @param duplex The duplex of the RMII mode. + */ +static inline void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) +{ + uint32_t reg = base->MAC_CONFIG & ~(ENET_MAC_CONFIG_DM_MASK | ENET_MAC_CONFIG_FES_MASK); + reg |= ENET_MAC_CONFIG_DM(duplex) | ENET_MAC_CONFIG_FES(speed); + + base->MAC_CONFIG = reg; +} + +/*! + * @brief Sets the ENET SMI(serial management interface)- MII management interface. + * + * @param base ENET peripheral base address. + */ +void ENET_SetSMI(ENET_Type *base); + +/*! + * @brief Checks if the SMI is busy. + * + * @param base ENET peripheral base address. + * @return The status of MII Busy status. + */ +static inline bool ENET_IsSMIBusy(ENET_Type *base) +{ + return (base->MAC_MDIO_ADDR & ENET_MAC_MDIO_ADDR_MB_MASK) ? true : false; +} + +/*! + * @brief Reads data from the PHY register through SMI interface. + * + * @param base ENET peripheral base address. + * @return The data read from PHY + */ +static inline uint16_t ENET_ReadSMIData(ENET_Type *base) +{ + return (uint16_t)(base->MAC_MDIO_DATA & ENET_MAC_MDIO_DATA_MD_MASK); +} + +/*! + * @brief Starts an SMI read command. + * support both MDIO IEEE802.3 Clause 22 and clause 45. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + */ +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg); + +/*! + * @brief Starts a SMI write command. + * support both MDIO IEEE802.3 Clause 22 and clause 45. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param data The data written to PHY. + */ +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); +/* @} */ + +/*! + * @name Other basic operation + * @{ + */ + +/*! + * @brief Sets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +static inline void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + assert(macAddr); + + /* Set Macaddr */ + base->MAC_ADDR_LOW = ((uint32_t)macAddr[3] << 24) | ((uint32_t)macAddr[2] << 16) | ((uint32_t)macAddr[1] << 8) | + ((uint32_t)macAddr[0]); + base->MAC_ADDR_HIGH = ((uint32_t)macAddr[5] << 8) | ((uint32_t)macAddr[4]); +} + +/*! + * @brief Gets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Set the MAC to enter into power down mode. + * the remote power wake up frame and magic frame can wake up + * the ENET from the power down mode. + * + * @param base ENET peripheral base address. + * @param wakeFilter The wakeFilter provided to configure the wake up frame fitlter. + * Set the wakeFilter to NULL is not required. But if you have the filter requirement, + * please make sure the wakeFilter pointer shall be eight continous + * 32-bits configuration. + */ +void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter); + +/*! + * @brief Set the MAC to exit power down mode. + * Eixt from the power down mode and recover to noraml work mode. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_ExitPowerDown(ENET_Type *base) +{ + /* Clear and status ans reset the power down. */ + base->MAC_PMT_CRTL_STAT &= ~ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK; + + /* Restore the tx which is disabled when enter power down mode. */ + base->DMA_CH[0].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK; + base->DMA_CH[1].DMA_CHX_TX_CTRL |= ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK; + base->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK; +} + +/* @} */ + +/*! + * @name Interrupts. + * @{ + */ + +/*! + * @brief Enables the ENET DMA and MAC interrupts. + * + * This function enables the ENET interrupt according to the provided mask. The mask + * is a logical OR of enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t. + * For example, to enable the dma and mac interrupt, do the following. + * @code + * ENET_EnableInterrupts(ENET, kENET_DmaRx | kENET_DmaTx | kENET_MacPmt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to enable. This is a logical OR of both + * enumeration :: enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t. + */ +void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask); + +/*! + * @brief Disables the ENET DMA and MAC interrupts. + * + * This function disables the ENET interrupt according to the provided mask. The mask + * is a logical OR of enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t. + * For example, to disable the dma and mac interrupt, do the following. + * @code + * ENET_DisableInterrupts(ENET, kENET_DmaRx | kENET_DmaTx | kENET_MacPmt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to disables. This is a logical OR of both + * enumeration :: enet_dma_interrupt_enable_t and enet_mac_interrupt_enable_t. + */ +void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask); + +/*! + * @brief Gets the ENET DMA interrupt status flag. + * + * @param base ENET peripheral base address. + * @param channel The DMA Channel. Shall not be larger than ENET_RING_NUM_MAX. + * @return The event status of the interrupt source. This is the logical OR of members + * of the enumeration :: enet_dma_interrupt_enable_t. + */ +static inline uint32_t ENET_GetDmaInterruptStatus(ENET_Type *base, uint8_t channel) +{ + return base->DMA_CH[channel].DMA_CHX_STAT; +} + +/*! + * @brief Clear the ENET DMA interrupt status flag. + * + * @param base ENET peripheral base address. + * @param channel The DMA Channel. Shall not be larger than ENET_RING_NUM_MAX. + * @return The event status of the interrupt source. This is the logical OR of members + * of the enumeration :: enet_dma_interrupt_enable_t. + */ +static inline void ENET_ClearDmaInterruptStatus(ENET_Type *base, uint8_t channel, uint32_t mask) +{ + /* Clear the dam interrupt status bit in dma channel interrupt status register. */ + base->DMA_CH[channel].DMA_CHX_STAT = mask; +} + +/*! + * @brief Gets the ENET MAC interrupt status flag. + * + * @param base ENET peripheral base address. + * @return The event status of the interrupt source. + * Use the enum in enet_mac_interrupt_enable_t and right shift + * ENET_MACINT_ENUM_OFFSET to mask the returned value to get the + * exact interrupt status. + */ +static inline uint32_t ENET_GetMacInterruptStatus(ENET_Type *base) +{ + return base->MAC_INTR_STAT; +} + +/*! + * @brief Clears the ENET mac interrupt events status flag. + * + * This function clears enabled ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See the @ref enet_mac_interrupt_enable_t. + * For example, to clear the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_ClearMacInterruptStatus(ENET, kENET_MacPmt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupt source to be cleared. + * This is the logical OR of members of the enumeration :: enet_mac_interrupt_enable_t. + */ +void ENET_ClearMacInterruptStatus(ENET_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Functional operation. + * @{ + */ + +/*! + * @brief Get the tx descriptor DMA Own flag. + * + * @param txDesc The given tx descriptor. + * @retval True the dma own tx descriptor, false application own tx descriptor. + * + */ +static inline bool ENET_IsTxDescriptorDmaOwn(enet_tx_bd_struct_t *txDesc) +{ + return (txDesc->controlStat & ENET_TXDESCRIP_RD_OWN_MASK) ? true : false; +} + +/*! + * @brief Setup a given tx descriptor. + * This function is a low level functional API to setup or prepare + * a given tx descriptor. + * + * @param txDesc The given tx descriptor. + * @param buffer1 The first buffer address in the descriptor. + * @param bytes1 The bytes in the fist buffer. + * @param buffer2 The second buffer address in the descriptor. + * @param bytes1 The bytes in the second buffer. + * @param framelen The length of the frame to be transmitted. + * @param intEnable Interrupt enable flag. + * @param tsEnable The timestamp enable. + * @param flag The flag of this tx desciriptor, see "enet_desc_flag" . + * @param slotNum The slot num used for AV only. + * + * @note This must be called after all the ENET initilization. + * And should be called when the ENET receive/transmit is required. + * Transmit buffers are 'zero-copy' buffers, so the buffer must remain in + * memory until the packet has been fully transmitted. The buffers + * should be free or requeued in the transmit interrupt irq handler. + */ +void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc, + void *buffer1, + uint32_t bytes1, + void *buffer2, + uint32_t bytes2, + uint32_t framelen, + bool intEnable, + bool tsEnable, + enet_desc_flag flag, + uint8_t slotNum); + +/*! + * @brief Update the tx descriptor tail pointer. + * This function is a low level functional API to update the + * the tx descriptor tail. + * This is called after you setup a new tx descriptor to update + * the tail pointer to make the new descritor accessable by DMA. + * + * @param base ENET peripheral base address. + * @param channel The tx DMA channel. + * @param txDescTailAddrAlign The new tx tail pointer address. + * + */ +static inline void ENET_UpdateTxDescriptorTail(ENET_Type *base, uint8_t channel, uint32_t txDescTailAddrAlign) +{ + base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = txDescTailAddrAlign & ~ENET_ADDR_ALIGNMENT; +} + +/*! + * @brief Update the rx descriptor tail pointer. + * This function is a low level functional API to update the + * the rx descriptor tail. + * This is called after you setup a new rx descriptor to update + * the tail pointer to make the new descritor accessable by DMA + * and to anouse the rx poll command for DMA. + * + * @param base ENET peripheral base address. + * @param channel The rx DMA channel. + * @param rxDescTailAddrAlign The new rx tail pointer address. + * + */ +static inline void ENET_UpdateRxDescriptorTail(ENET_Type *base, uint8_t channel, uint32_t rxDescTailAddrAlign) +{ + base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTailAddrAlign & ~ENET_ADDR_ALIGNMENT; +} + +/*! + * @brief Gets the context in the ENET rx descriptor. + * This function is a low level functional API to get the + * the status flag from a given rx descriptor. + * + * @param rxDesc The given rx descriptor. + * @retval The RDES3 regions for write-back format rx buffer descriptor. + * + * @note This must be called after all the ENET initilization. + * And should be called when the ENET receive/transmit is required. + */ +static inline uint32_t ENET_GetRxDescriptor(enet_rx_bd_struct_t *rxDesc) +{ + assert(rxDesc); + + return rxDesc->control; +} +/*! + * @brief Updates the buffers and the own status for a given rx descriptor. + * This function is a low level functional API to Updates the + * buffers and the own status for a given rx descriptor. + * + * @param rxDesc The given rx descriptor. + * @param buffer1 The first buffer address in the descriptor. + * @param buffer2 The second buffer address in the descriptor. + * @param intEnable Interrupt enable flag. + * @param doubleBuffEnable The double buffer enable flag. + * + * @note This must be called after all the ENET initilization. + * And should be called when the ENET receive/transmit is required. + */ +void ENET_UpdateRxDescriptor( + enet_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable); + +/* @} */ + +/*! + * @name Transactional operation + * @{ + */ + +/*! + * @brief Create ENET Handler + * + * This is a transactional API and it's provided to store all datas which are needed + * during the whole transactional process. This API should not be used when you use + * functional APIs to do data tx/rx. This is funtion will store many data/flag for + * transactional use, so all configure API such as ENET_Init(), ENET_DescriptorInit(), + * ENET_EnableInterrupts() etc. + * + * @note as our transactional transmit API use the zero-copy transmit buffer. + * so there are two thing we emphasize here: + * 1. tx buffer free/requeue for application should be done in the tx + * interrupt handler. Please set callback: kENET_TxIntEvent with tx buffer free/requeue + * process APIs. + * 2. the tx interrupt is forced to open. + * + * @param base ENET peripheral base address. + * @param handle ENET handler. + * @param config ENET configuration. + * @param bufferConfig ENET buffer configuration. + * @param callback The callback function. + * @param userData The application data. + */ +void ENET_CreateHandler(ENET_Type *base, + enet_handle_t *handle, + enet_config_t *config, + enet_buffer_config_t *bufferConfig, + enet_callback_t callback, + void *userData); + +/*! +* @brief Gets the size of the read frame. +* This function gets a received frame size from the ENET buffer descriptors. +* @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. +* After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the +* receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". +* +* @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. +* @param length The length of the valid frame received. +* @param channel The DMAC channel for the rx. +* @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. +* @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data +* and NULL length to update the receive buffers. +* @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame +* should be called with the right data buffer and the captured data length input. +*/ +status_t ENET_GetRxFrameSize(ENET_Type *base, enet_handle_t *handle, uint32_t *length, uint8_t channel); + +/*! + * @brief Reads a frame from the ENET device. + * This function reads a frame from the ENET DMA descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * For example use rx dma channel 0: + * @code + * uint32_t length; + * enet_handle_t g_handle; + * //Get the received frame size firstly. + * status = ENET_GetRxFrameSize(&g_handle, &length, 0); + * if (length != 0) + * { + * //Allocate memory here with the size of "length" + * uint8_t *data = memory allocate interface; + * if (!data) + * { + * ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0); + * //Add the console warning log. + * } + * else + * { + * status = ENET_ReadFrame(ENET, &g_handle, data, length, 0); + * //Call stack input API to deliver the data to stack + * } + * } + * else if (status == kStatus_ENET_RxFrameError) + * { + * //Update the received buffer when a error frame is received. + * ENET_ReadFrame(ENET, &g_handle, NULL, 0, 0); + * } + * @endcode + * @param base ENET peripheral base address. + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to store the frame which memory size should be at least "length". + * @param length The size of the data buffer which is still the length of the received frame. + * @param channel The rx DMA channel. shall not be larger than 2. + * @return The execute status, successful or failure. + */ +status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t channel); + +/*! + * @brief Transmits an ENET frame. + * @note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to be send. + * @param length The length of the data to be send. + * @retval kStatus_Success Send frame succeed. + * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length); + +/*! + * @brief Reclaim tx descriptors. + * This function is used to update the tx descriptor status and + * store the tx timestamp when the 1588 feature is enabled. + * This is called by the transmit interupt IRQ handler after the + * complete of a frame transmission. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param channel The tx DMA channnel. + * + */ +void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t channel); + +/*! + * @brief The ENET PMT IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_PMTIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief The ENET IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_IRQHandler(ENET_Type *base, enet_handle_t *handle); + +/* @} */ + +#ifdef ENET_PTP1588FEATURE_REQUIRED +/*! + * @name ENET Enhanced function operation + * @{ + */ + +/*! + * @brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * @param base ENET peripheral base address. + * @param ptpClkSrc The clock source of the PTP timer. + */ +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); + +/*! + * @brief Coreect the ENET PTP 1588 timer in coarse method. + * + * @param base ENET peripheral base address. + * @param operation The system time operation, refer to "enet_systime_op" + * @param second The correction second. + * @param nanosecond The correction nanosecond. + */ +void ENET_Ptp1588CorrectTimerInCoarse(ENET_Type *base, enet_systime_op operation, uint32_t second, uint32_t nanosecond); + +/*! + * @brief Coreect the ENET PTP 1588 timer in fine method. + * + * + * @param base ENET peripheral base address. + * @param addend The addend value to be set in the fine method + * @note Should take refer to the chapter "System time corretion" and + * see the description for the "fine correction method". + */ +static inline void ENET_Ptp1588CorrectTimerInFine(ENET_Type *base, uint32_t addend) +{ + /* Set the freqCompensation value. */ + base->MAC_SYS_TIMESTMP_ADDEND = addend; + base->MAC_TIMESTAMP_CTRL |= ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK; +} + +/*! + * @brief Get the ENET Time stamp current addend value. + * + * @param base ENET peripheral base address. + * @return The addend value. + */ +static inline uint32_t ENET_Ptp1588GetAddend(ENET_Type *base) +{ + return base->MAC_SYS_TIMESTMP_ADDEND; +} + +/*! + * @brief Gets the current ENET time from the PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param second The PTP 1588 system timer second. + * @param nanosecond The PTP 1588 system timer nanosecond. + * For the unit of the nanosecond is 1ns. so the nanosecond is the real nanosecond. + */ +void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecond); + +/*! + * @brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); +#endif /* ENET_PTP1588FEATURE_REQUIRED */ +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_ENET_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_flexcomm.c b/fnet_demos/common/startup/LPC54628/fsl_flexcomm.c new file mode 100644 index 00000000..162f5140 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_flexcomm.c @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; + +/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; + +/*! @brief Array to map FLEXCOMM instance number to base address. */ +static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) +{ + if (periph == FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if ((periph >= FLEXCOMM_PERIPH_USART) && (periph <= FLEXCOMM_PERIPH_I2S_TX)) + { + return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > 0 ? true : false; + } + else if (periph == FLEXCOMM_PERIPH_I2S_RX) + { + return (base->PSELID & (1 << 7)) > 0 ? true : false; + } + else + { + return false; + } +} + +/* Get the index corresponding to the FLEXCOMM */ +uint32_t FLEXCOMM_GetInstance(void *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) + { + if ((uint32_t)base == s_flexcommBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +/* Changes FLEXCOMM mode */ +status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) +{ + /* Check whether peripheral type is present */ + if (!FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock) + { + base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) +{ + int idx = FLEXCOMM_GetInstance(base); + + if (idx < 0) + { + return kStatus_InvalidArgument; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_flexcommClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Set the FLEXCOMM to given peripheral */ + return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); +} + +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(base); + + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_flexcommIrqHandler[instance] = NULL; + s_flexcommHandle[instance] = handle; + s_flexcommIrqHandler[instance] = handler; + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(FLEXCOMM0) +void FLEXCOMM0_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[0]); + s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM1) +void FLEXCOMM1_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[1]); + s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM2) +void FLEXCOMM2_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[2]); + s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM3) +void FLEXCOMM3_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[3]); + s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM4) +void FLEXCOMM4_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[4]); + s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#endif + +#if defined(FLEXCOMM5) +void FLEXCOMM5_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[5]); + s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM6) +void FLEXCOMM6_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[6]); + s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM7) +void FLEXCOMM7_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[7]); + s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM8) +void FLEXCOMM8_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[8]); + s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM9) +void FLEXCOMM9_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[9]); + s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); + /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/fnet_demos/common/startup/LPC54628/fsl_flexcomm.h b/fnet_demos/common/startup/LPC54628/fsl_flexcomm.h new file mode 100644 index 00000000..93a2ec6a --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_flexcomm.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXCOMM_H_ +#define _FSL_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version 2.0.0. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief FLEXCOMM peripheral modes. */ +typedef enum +{ + FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ + FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ + FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ + FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ + FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ +} FLEXCOMM_PERIPH_T; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); + +/*! @brief Array with IRQ number for each FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/*! @brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base); + +/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); + +/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle); + +/*@}*/ + +#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/fnet_demos/common/startup/LPC54628/fsl_gpio.c b/fnet_demos/common/startup/LPC54628/fsl_gpio.c new file mode 100644 index 00000000..9fc38844 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_gpio.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpio.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* +* Prototypes +************ ******************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) +{ + if (config->pinDirection == kGPIO_DigitalInput) + { + base->DIR[port] &= ~(1U << pin); + } + else + { + /* Set default output value */ + if (config->outputLogic == 0U) + { + base->CLR[port] = (1U << pin); + } + else + { + base->SET[port] = (1U << pin); + } + /* Set pin direction */ + base->DIR[port] |= 1U << pin; + } +} diff --git a/fnet_demos/common/startup/LPC54628/fsl_gpio.h b/fnet_demos/common/startup/LPC54628/fsl_gpio.h new file mode 100644 index 00000000..dd68de25 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_gpio.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _LPC_GPIO_H_ +#define _LPC_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPC GPIO driver version 2.1.1. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/*! @brief LPC GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused. + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + +/*! + * @brief Initializes the GPIO peripheral. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortInit. + */ +static inline void GPIO_Init(GPIO_Type *base, uint32_t port) +{ + GPIO_PortInit(base, port); +} + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} +/*@}*/ +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the GPIO PIN. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return (uint32_t)base->B[port][pin]; +} + +/*! + * @brief Reads the current input value of the GPIO PIN. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return GPIO_PinRead(base, port, pin); +} +/*@}*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->SET[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortSet(base, port, mask); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->CLR[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortClear(base, port, mask); +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->NOT[port] = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortToggle. + */ +static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortToggle(base, port, mask); +} +/*@}*/ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + */ +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->PIN[port]; +} + +/*! + * @brief Reads the current input value of the whole GPIO port. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortRead + */ +static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port) +{ + return GPIO_PortRead(base, port); +} + +/*@}*/ +/*! @name GPIO Mask Operations */ +/*@{*/ + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->MASK[port] = mask; +} + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedSet. + */ +static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + GPIO_PortMaskedSet(base, port, mask); +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param output GPIO port output value. + */ +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) +{ + base->MPIN[port] = output; +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedWrite. + */ +static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output) +{ + GPIO_PortMaskedWrite(base, port, output); +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @retval masked GPIO port value + */ +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->MPIN[port]; +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedRead. + */ +static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port) +{ + return GPIO_PortMaskedRead(base, port); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _LPC_GPIO_H_*/ diff --git a/fnet_demos/common/startup/LPC54628/fsl_inputmux.c b/fnet_demos/common/startup/LPC54628/fsl_inputmux.c new file mode 100644 index 00000000..92358517 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_inputmux.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_inputmux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void INPUTMUX_Init(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_InputMux); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) +{ + uint32_t pmux_id; + uint32_t output_id; + + /* extract pmux to be used */ + pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; + /* extract function number */ + output_id = ((uint32_t)(connection)) & 0xffffU; + /* programm signal */ + *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id; +} + +void INPUTMUX_Deinit(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_InputMux); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/fnet_demos/common/startup/LPC54628/fsl_inputmux.h b/fnet_demos/common/startup/LPC54628/fsl_inputmux.h new file mode 100644 index 00000000..3d298558 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_inputmux.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_INPUTMUX_H_ +#define _FSL_INPUTMUX_H_ + +#include "fsl_inputmux_connections.h" +#include "fsl_common.h" + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! @file */ +/*! @file fsl_inputmux_connections.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Group interrupt driver version for SDK */ +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + /*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base); + +/*! + * @brief Attaches a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param index Destination peripheral to attach the signal to. + * @param connection Selects connection. + * + * @retval None. +*/ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); + +/*! + * @brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_INPUTMUX_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_inputmux_connections.h b/fnet_demos/common/startup/LPC54628/fsl_inputmux_connections.h new file mode 100644 index 00000000..3b909ed4 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_inputmux_connections.h @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2017, NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define SCT0_PMUX_ID 0x00U +#define PINTSEL_PMUX_ID 0xC0U +#define DMA_TRIG0_PMUX_ID 0xE0U +#define DMA_OTRIG_PMUX_ID 0x160U +#define FREQMEAS_PMUX_ID 0x180U +#define PMUX_SHIFT 20U + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< SCT INMUX. */ + kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_T0Out0ToSct0 = 8U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_T1Out0ToSct0 = 9U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_T2Out0ToSct0 = 10U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_T3Out0ToSct0 = 11U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_T4Out0ToSct0 = 12U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_AdcThcmpIrqToSct0 = 13U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSct0 = 17U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DebugHaltedToSct0 = 18U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SmartCard0TxActivreToSct0 = 19U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SmartCard0RxActivreToSct0 = 20U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SmartCard1TxActivreToSct0 = 21U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_SmartCard1RxActivreToSct0 = 22U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_I2s6SclkToSct0 = 23U + (SCT0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_I2sS7clkToSct0 = 24U + (SCT0_PMUX_ID << PMUX_SHIFT), + + /*!< Frequency measure. */ + kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Fro96MhzToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_WdtOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_MainClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_a = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_b = 7U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), + + /*!< Pin Interrupt. */ + kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT), + /*!< DMA ITRIG. */ + kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Adc0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), + /*!< DMA OTRIG. */ + kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaChannel9_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm8RxTrigoutToTriginChannels = 20U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm8TxTrigoutToTriginChannels = 21U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm9RxTrigoutToTriginChannels = 22U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaFlexcomm9TxTrigoutToTriginChannels = 23U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaSmartcard0RxTrigoutToTriginChannels = 24U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaSmartcard0TxTrigoutToTriginChannels = 25U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaSmartcard1RxTrigoutToTriginChannels = 26U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), + kINPUTMUX_DmaSmartcard1TxTrigoutToTriginChannels = 27U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), +} inputmux_connection_t; + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_iocon.h b/fnet_demos/common/startup/LPC54628/fsl_iocon.h new file mode 100644 index 00000000..7cf6911f --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_iocon.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_IOCON_H_ +#define _FSL_IOCON_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_iocon + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOCON driver version 2.0.0. */ +#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/** + * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format + */ +typedef struct _iocon_group +{ + uint32_t port : 8; /* Pin port */ + uint32_t pin : 8; /* Pin number */ + uint32_t modefunc : 16; /* Function and mode */ +} iocon_group_t; + +/** + * @brief IOCON function and mode selection definitions + * @note See the User Manual for specific modes and functions supported by the various pins. + */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */ +#define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */ +#define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << 6) /*!< I2C Slew Rate Control */ +#define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */ +#define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */ +#define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */ +#define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */ +#define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */ +#define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */ +#define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */ +#define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */ +#define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */ +#define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */ +#define IOCON_CLKDIV(div) \ + ((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#else +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ +#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ +#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << 5) /*!< I2C Slew Rate Control */ +#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */ +#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ +#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ +#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ +#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ +#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ +#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ +#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */ +#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ +#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ +#define IOCON_CLKDIV(div) \ + ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) +{ + base->PIO[port][pin] = modefunc; +} + +/** + * @brief Set all I/O Control pin muxing + * @param base : The base of IOCON peripheral on the chip + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) +{ + uint32_t i; + + for (i = 0; i < arrayLength; i++) + { + IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); + } +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_IOCON_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_pint.c b/fnet_demos/common/startup/LPC54628/fsl_pint.c new file mode 100644 index 00000000..d641fc35 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_pint.c @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pint.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; + +/*! @brief Callback function array for PINT(s). */ +static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +void PINT_Init(PINT_Type *base) +{ + uint32_t i; + uint32_t pmcfg; + + assert(base); + + pmcfg = 0; + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + + /* Disable all bit slices */ + for (i = 0; i < PINT_PIN_INT_COUNT; i++) + { + pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); + } + + /* Enable the peripheral clock */ + CLOCK_EnableClock(kCLOCK_Pint); + + /* Reset the peripheral */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); + + /* Disable all pattern match bit slices */ + base->PMCFG = pmcfg; +} + +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) +{ + assert(base); + + /* Clear Rise and Fall flags first */ + PINT_PinInterruptClrRiseFlag(base, intr); + PINT_PinInterruptClrFallFlag(base, intr); + + /* select level or edge sensitive */ + base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U); + + /* enable rising or level interrupt */ + if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) + { + base->SIENR = 1U << intr; + } + else + { + base->CIENR = 1U << intr; + } + + /* Enable falling or select high level */ + if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + { + base->SIENF = 1U << intr; + } + else + { + base->CIENF = 1U << intr; + } + + s_pintCallback[intr] = callback; +} + +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) +{ + uint32_t mask; + bool level; + + assert(base); + + *enable = kPINT_PinIntEnableNone; + level = false; + + mask = 1U << pintr; + if (base->ISEL & mask) + { + /* Pin interrupt is level sensitive */ + level = true; + } + + if (base->IENR & mask) + { + if (level) + { + /* Level interrupt is enabled */ + *enable = kPINT_PinIntEnableLowLevel; + } + else + { + /* Rising edge interrupt */ + *enable = kPINT_PinIntEnableRiseEdge; + } + } + + if (base->IENF & mask) + { + if (level) + { + /* Level interrupt is active high */ + *enable = kPINT_PinIntEnableHighLevel; + } + else + { + /* Either falling or both edge */ + if (*enable == kPINT_PinIntEnableRiseEdge) + { + /* Rising and faling edge */ + *enable = kPINT_PinIntEnableBothEdges; + } + else + { + /* Falling edge */ + *enable = kPINT_PinIntEnableFallEdge; + } + } + } + + *callback = s_pintCallback[pintr]; +} + +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t pmcfg; + + assert(base); + + src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U); + cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U); + + /* Input source selection for selected bit slice */ + base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift); + + /* Bit slice configuration */ + pmcfg = base->PMCFG; + pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift); + + /* If end point is true, enable the bits */ + if (bslice != 7U) + { + if (cfg->end_point) + { + pmcfg |= (0x1U << bslice); + } + else + { + pmcfg &= ~(0x1U << bslice); + } + } + + base->PMCFG = pmcfg; + + /* Save callback pointer */ + s_pintCallback[bslice] = cfg->callback; +} + +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + + assert(base); + + src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U); + cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U); + + cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift); + cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift); + + if (bslice == 7U) + { + cfg->end_point = true; + } + else + { + cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice; + } + cfg->callback = s_pintCallback[bslice]; +} + +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) +{ + uint32_t pmctrl; + uint32_t pmstatus; + uint32_t pmsrc; + + pmctrl = PINT->PMCTRL; + pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; + if (pmstatus) + { + /* Reset Pattern match engine detection logic */ + pmsrc = base->PMSRC; + base->PMSRC = pmsrc; + } + return (pmstatus); +} + +void PINT_EnableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + PINT_PinInterruptClrStatusAll(base); + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + EnableIRQ(s_pintIRQ[i]); + } +} + +void PINT_DisableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + DisableIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + } +} + +void PINT_Deinit(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + /* Cleanup */ + PINT_DisableCallback(base); + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + + /* Reset the peripheral */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); + + /* Disable the peripheral clock */ + CLOCK_DisableClock(kCLOCK_Pint); +} + +/* IRQ handler functions overloading weak symbols in the startup */ +void PIN_INT0_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt0] != NULL) + { + s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); + } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +void PIN_INT1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt1] != NULL) + { + s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); + } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) +void PIN_INT2_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt2] != NULL) + { + s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); + } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) +void PIN_INT3_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt3] != NULL) + { + s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); + } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) +void PIN_INT4_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt4] != NULL) + { + s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); + } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) +void PIN_INT5_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt5] != NULL) + { + s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); + } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) +void PIN_INT6_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt6] != NULL) + { + s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); + } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) +void PIN_INT7_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt7] != NULL) + { + s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); + } + /* Clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/fnet_demos/common/startup/LPC54628/fsl_pint.h b/fnet_demos/common/startup/LPC54628/fsl_pint.h new file mode 100644 index 00000000..ae3ce304 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_pint.h @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_PINT_H_ +#define _FSL_PINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/* Number of interrupt line supported by PINT */ +#define PINT_PIN_INT_COUNT 8U + +/* Number of input sources supported by PINT */ +#define PINT_INPUT_COUNT 8U + +/* PININT Bit slice source register bits */ +#define PININT_BITSLICE_SRC_START 8U +#define PININT_BITSLICE_SRC_MASK 7U + +/* PININT Bit slice configuration register bits */ +#define PININT_BITSLICE_CFG_START 8U +#define PININT_BITSLICE_CFG_MASK 7U +#define PININT_BITSLICE_ENDP_MASK 7U + +#define PINT_PIN_INT_LEVEL 0x10U +#define PINT_PIN_INT_EDGE 0x00U +#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U +#define PINT_PIN_INT_RISE 0x01U +#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) +#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) +#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + +/*! @brief PINT Pin Interrupt enable type */ +typedef enum _pint_pin_enable +{ + kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ + kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ + kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ + kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ + kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ + kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ +} pint_pin_enable_t; + +/*! @brief PINT Pin Interrupt type */ +typedef enum _pint_int +{ + kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ +#endif +} pint_pin_int_t; + +/*! @brief PINT Pattern Match bit slice input source type */ +typedef enum _pint_pmatch_input_src +{ + kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ + kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ + kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ + kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ + kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ + kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ + kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ +} pint_pmatch_input_src_t; + +/*! @brief PINT Pattern Match bit slice type */ +typedef enum _pint_pmatch_bslice +{ + kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ +#endif +} pint_pmatch_bslice_t; + +/*! @brief PINT Pattern Match configuration type */ +typedef enum _pint_pmatch_bslice_cfg +{ + kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ + kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ + kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ + kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ + kPINT_PatternMatchHigh = 4U, /*!< High level */ + kPINT_PatternMatchLow = 5U, /*!< Low level */ + kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ + kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ +} pint_pmatch_bslice_cfg_t; + +/*! @brief PINT Callback function. */ +typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); + +typedef struct _pint_pmatch_cfg +{ + pint_pmatch_input_src_t bs_src; + pint_pmatch_bslice_cfg_t bs_cfg; + bool end_point; + pint_cb_t callback; +} pint_pmatch_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Init(PINT_Type *base); + +/*! + * @brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param intr Pin interrupt. + * @param enable Selects detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); + +/*! + * @brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * @param enable Pointer to store the detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); + +/*! + * @brief Clear Selected pin interrupt status. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + base->IST = (1U << pintr); +} + +/*! + * @brief Get Selected pin interrupt status. + + * This function returns the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->IST & (1U << pintr)) ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupts status. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrStatusAll(PINT_Type *base) +{ + base->IST = PINT_IST_PSTAT_MASK; +} + +/*! + * @brief Get all pin interrupts status. + + * This function returns the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the status of corresponding pin interrupt. + * = 0 No pin interrupt request. = 1 Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) +{ + return (base->IST); +} + +/*! + * @brief Clear Selected pin interrupt fall flag. + + * This function clears the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->FALL = (1U << pintr); +} + +/*! + * @brief Get selected pin interrupt fall flag. + + * This function returns the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->FALL & (1U << pintr)) ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt fall flags. + + * This function clears the fall flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) +{ + base->FALL = PINT_FALL_FDET_MASK; +} + +/*! + * @brief Get all pin interrupt fall flags. + + * This function returns the fall flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. + * 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) +{ + return (base->FALL); +} + +/*! + * @brief Clear Selected pin interrupt rise flag. + + * This function clears the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->RISE = (1U << pintr); +} + +/*! + * @brief Get selected pin interrupt rise flag. + + * This function returns the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->RISE & (1U << pintr)) ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt rise flags. + + * This function clears the rise flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) +{ + base->RISE = PINT_RISE_RDET_MASK; +} + +/*! + * @brief Get all pin interrupt rise flags. + + * This function returns the rise flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. + * 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) +{ + return (base->RISE); +} + +/*! + * @brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get pattern match bit slice status. + + * This function returns the status of selected bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * + * @retval status = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) +{ + return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (0x1U << bslice)) >> bslice; +} + +/*! + * @brief Get status of all pattern match bit slices. + + * This function returns the status of all bit slices. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the match status of corresponding bit slice. + * = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) +{ + return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; +} + +/*! + * @brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * @param base Base address of the PINT peripheral. + * + * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); + +/*! + * @brief Enable pattern match function. + + * This function enables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Disable pattern match function. + + * This function disables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Enable RXEV output. + + * This function enables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Disable RXEV output. + + * This function disables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_EnableCallback(PINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void PINT_DisableCallback(PINT_Type *base); + +/*! + * @brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Deinit(PINT_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_PINT_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_power.c b/fnet_demos/common/startup/LPC54628/fsl_power.c new file mode 100644 index 00000000..69b53d1f --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_power.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016, NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_common.h" +#include "fsl_power.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Empty file since implementation is in header file and power library */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_power.h b/fnet_demos/common/startup/LPC54628/fsl_power.h new file mode 100644 index 00000000..fa7d8070 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_power.h @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016, NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_POWER_H_ +#define _FSL_POWER_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 2.0.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot) +#define PDRCFG0 0x0U +#define PDRCFG1 0x1U + +typedef enum pd_bits +{ + kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U), + kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U), + kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U), + kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U), + kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U), + kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U), + kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U), + kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U), + kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U), + kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U), + kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U), + kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U), + kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U), + kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U), + kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U), + kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U), + kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U), + kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U), + kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U), + kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U), + kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U), + kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U), + kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U), + kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U), + + kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U), + kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U), + kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U), + kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U), + kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U), + kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U), + + kPDRUNCFG_ForceUnsigned = 0x80000000U, +} pd_bit_t; + +/* Power mode configuration API parameter */ +typedef enum _power_mode_config +{ + kPmu_Sleep = 0U, + kPmu_Deep_Sleep = 1U, + kPmu_Deep_PowerDown = 2U, +} power_mode_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! +* @name Power Configuration +* @{ +*/ + +/*! + * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral + * + * @param en peripheral for which to enable the PDRUNCFG bit + * @return none + */ +static inline void POWER_EnablePD(pd_bit_t en) +{ + /* PDRUNCFGSET */ + SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU)); +} + +/*! + * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral + * + * @param en peripheral for which to disable the PDRUNCFG bit + * @return none + */ +static inline void POWER_DisablePD(pd_bit_t en) +{ + /* PDRUNCFGCLR */ + SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU)); +} + +/*! + * @brief API to enable deep sleep bit in the ARM Core. + * + * @param none + * @return none + */ +static inline void POWER_EnableDeepSleep(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to disable deep sleep bit in the ARM Core. + * + * @param none + * @return none + */ +static inline void POWER_DisableDeepSleep(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to power down flash controller. + * + * @param none + * @return none + */ +static inline void POWER_PowerDownFlash(void) +{ + /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ + CLOCK_DisableClock(kCLOCK_Flash); + + /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ + CLOCK_DisableClock(kCLOCK_Fmc); +} + +/*! + * @brief API to power up flash controller. + * + * @param none + * @return none + */ +static inline void POWER_PowerUpFlash(void) +{ + /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ + CLOCK_EnableClock(kCLOCK_Fmc); +} + +/*! + * @brief Power Library API to power the PLLs. + * + * @param none + * @return none + */ +void POWER_SetPLL(void); + +/*! + * @brief Power Library API to power the USB PHY. + * + * @param none + * @return none + */ +void POWER_SetUsbPhy(void); + +/*! + * @brief Power Library API to enter different power mode. + * + * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on during power mode selected. + * @return none + */ +void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd); + +/*! + * @brief Power Library API to enter sleep mode. + * + * @return none + */ +void POWER_EnterSleep(void); + +/*! + * @brief Power Library API to enter deep sleep mode. + * + * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be powered on during deep sleep + * @return none + */ +void POWER_EnterDeepSleep(uint64_t exclude_from_pd); + +/*! + * @brief Power Library API to enter deep power down mode. + * + * @param exclude_from_pd Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on during deep power + * down mode, but this is has no effect as the voltages are cut off. + + * @return none + */ +void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd); + +/*! + * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. + * + * @param freq - The desired frequency at which the part would like to operate, + * note that the voltage and flash wait states should be set before changing frequency + * @return none + */ +void POWER_SetVoltageForFreq(uint32_t freq); + +/*! + * @brief Power Library API to return the library version. + * + * @param none + * @return version number of the power library + */ +uint32_t POWER_GetLibVersion(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _FSL_POWER_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_reset.c b/fnet_demos/common/startup/LPC54628/fsl_reset.c new file mode 100644 index 00000000..07a9ed9e --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_reset.c @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016, NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) + +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1u << bitPos; + + assert(bitPos < 32u); + + /* ASYNC_SYSCON registers have offset 1024 */ + if (regIndex >= SYSCON_PRESETCTRL_COUNT) + { + /* reset register is in ASYNC_SYSCON */ + + /* set bit */ + ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask; + /* wait until it reads 0b1 */ + while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) + { + } + } + else + { + /* reset register is in SYSCON */ + + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask)) + { + } + } +} + +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1u << bitPos; + + assert(bitPos < 32u); + + /* ASYNC_SYSCON registers have offset 1024 */ + if (regIndex >= SYSCON_PRESETCTRL_COUNT) + { + /* reset register is in ASYNC_SYSCON */ + + /* clear bit */ + ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) + { + } + } + else + { + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask)) + { + } + } +} + +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_reset.h b/fnet_demos/common/startup/LPC54628/fsl_reset.h new file mode 100644 index 00000000..71afa640 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_reset.h @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016, NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.0.0. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ + kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ + kEEPROM_RST_SHIFT_RSTn = 0 | 9U, /**< EEPROM reset control */ + kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ + kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */ + kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ + kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ + kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ + kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ + kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ + + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ + kMCAN0_RST_SHIFT_RSTn = 65536 | 7U, /**< MCAN0 reset control */ + kMCAN1_RST_SHIFT_RSTn = 65536 | 8U, /**< MCAN1 reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kDMIC_RST_SHIFT_RSTn = 65536 | 19U, /**< Digital microphone interface reset control */ + kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */ + kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0D reset control */ + kCT32B0_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B0 reset control */ + kCT32B1_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B1 reset control */ + + kLCD_RST_SHIFT_RSTn = 131072 | 2U, /**< LCD reset control */ + kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ + kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USB1H reset control */ + kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USB1D reset control */ + kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB1RAM reset control */ + kEMC_RST_SHIFT_RSTn = 131072 | 7U, /**< EMC reset control */ + kETH_RST_SHIFT_RSTn = 131072 | 8U, /**< ETH reset control */ + kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ + kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ + kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ + kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ + kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ + kFC8_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcomm Interface 8 reset control */ + kFC9_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcomm Interface 9 reset control */ + kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ + kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ + kSHA_RST_SHIFT_RSTn = 131072 | 18U, /**< SHA reset control */ + kSC0_RST_SHIFT_RSTn = 131072 | 19U, /**< SC0 reset control */ + kSC1_RST_SHIFT_RSTn = 131072 | 20U, /**< SC1 reset control */ + + kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */ + kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define AES_RSTS \ + { \ + kAES_RST_SHIFT_RSTn \ + } /* Reset bits for AES peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \ + kCT32B4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DMA_RSTS \ + { \ + kDMA_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ +#define DMIC_RSTS \ + { \ + kDMIC_RST_SHIFT_RSTn \ + } /* Reset bits for DMIC peripheral */ +#define EMC_RSTS \ + { \ + kEMC_RST_SHIFT_RSTn \ + } /* Reset bits for EMC peripheral */ +#define ETH_RST \ + { \ + kETH_RST_SHIFT_RSTn \ + } /* Reset bits for EMC peripheral */ +#define FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GINT_RSTS \ + { \ + kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ + } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ +#define GPIO_RSTS \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ + kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define IOCON_RSTS \ + { \ + kIOCON_RST_SHIFT_RSTn \ + } /* Reset bits for IOCON peripheral */ +#define FLASH_RSTS \ + { \ + kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define LCD_RSTS \ + { \ + kLCD_RST_SHIFT_RSTn \ + } /* Reset bits for LCD peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define MCAN_RSTS \ + { \ + kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \ + } /* Reset bits for MCAN0&MACN1 peripheral */ +#define OTP_RSTS \ + { \ + kOTP_RST_SHIFT_RSTn \ + } /* Reset bits for OTP peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define RNG_RSTS \ + { \ + kRNG_RST_SHIFT_RSTn \ + } /* Reset bits for RNG peripheral */ +#define SDIO_RST \ + { \ + kSDIO_RST_SHIFT_RSTn \ + } /* Reset bits for SDIO peripheral */ +#define SCT_RSTS \ + { \ + kSCT0_RST_SHIFT_RSTn \ + } /* Reset bits for SCT peripheral */ +#define SHA_RST \ + { \ + kSHA_RST_SHIFT_RSTn \ + } /* Reset bits for SHA peripheral */ +#define USB0D_RST \ + { \ + kUSB0D_RST_SHIFT_RSTn \ + } /* Reset bits for USB0D peripheral */ +#define USB0HMR_RST \ + { \ + kUSB0HMR_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HMR peripheral */ +#define USB0HSL_RST \ + { \ + kUSB0HSL_RST_SHIFT_RSTn \ + } /* Reset bits for USB0HSL peripheral */ +#define USB1H_RST \ + { \ + kUSB1H_RST_SHIFT_RSTn \ + } /* Reset bits for USB1H peripheral */ +#define USB1D_RST \ + { \ + kUSB1D_RST_SHIFT_RSTn \ + } /* Reset bits for USB1D peripheral */ +#define USB1RAM_RST \ + { \ + kUSB1RAM_RST_SHIFT_RSTn \ + } /* Reset bits for USB1RAM peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define WWDT_RSTS \ + { \ + kWWDT_RST_SHIFT_RSTn \ + } /* Reset bits for WWDT peripheral */ + +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/fsl_spi.c b/fnet_demos/common/startup/LPC54628/fsl_spi.c new file mode 100644 index 00000000..b2d5661d --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_spi.c @@ -0,0 +1,854 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_spi.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +/* Note: FIFOCFG[SIZE] has always value 1 = 8 items depth */ +#define SPI_FIFO_DEPTH(base) ((((base)->FIFOCFG & SPI_FIFOCFG_SIZE_MASK) >> SPI_FIFOCFG_SIZE_SHIFT) << 3) + +/* Convert transfer count to transfer bytes. dataWidth is a + * range <0,15>. Range <8,15> represents 2B transfer */ +#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) +#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief internal SPI config array */ +static spi_config_t g_configs[FSL_FEATURE_SOC_SPI_COUNT] = {(spi_data_width_t)0}; + +/*! @brief Array to map SPI instance number to base address. */ +static const uint32_t s_spiBaseAddrs[FSL_FEATURE_SOC_SPI_COUNT] = SPI_BASE_ADDRS; + +/*! @brief IRQ name array */ +static const IRQn_Type s_spiIRQ[] = SPI_IRQS; + +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the FLEXCOMM */ +uint32_t SPI_GetInstance(SPI_Type *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_SPI_COUNT; i++) + { + if ((uint32_t)base == s_spiBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = SPI_GetInstance(base); + s_dummyData[instance] = dummyData; +} + +void *SPI_GetConfig(SPI_Type *base) +{ + int32_t instance; + instance = SPI_GetInstance(base); + if (instance < 0) + { + return NULL; + } + return &g_configs[instance]; +} + +void SPI_MasterGetDefaultConfig(spi_master_config_t *config) +{ + assert(NULL != config); + + config->enableLoopback = false; + config->enableMaster = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->baudRate_Bps = 500000U; + config->dataWidth = kSPI_Data8Bits; + config->sselNum = kSPI_Ssel0; + config->txWatermark = kSPI_TxFifo0; + config->rxWatermark = kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; + config->delayConfig.preDelay = 0U; + config->delayConfig.postDelay = 0U; + config->delayConfig.frameDelay = 0U; + config->delayConfig.transferDelay = 0U; +} + +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) +{ + int32_t result = 0, instance = 0; + uint32_t tmp; + + /* assert params */ + assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to SPI mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + assert(kStatus_Success == result); + if (kStatus_Success != result) + { + return result; + } + + /* set divider */ + result = SPI_MasterSetBaud(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + /* get instance number */ + instance = SPI_GetInstance(base); + assert(instance >= 0); + + /* configure SPI mode */ + tmp = base->CFG; + tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); + /* phase */ + tmp |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmp |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmp |= SPI_CFG_LSBF(config->direction); + /* master mode */ + tmp |= SPI_CFG_MASTER(1); + /* loopback */ + tmp |= SPI_CFG_LOOP(config->enableLoopback); + /* configure active level for all CS */ + tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmp; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + g_configs[instance].sselNum = config->sselNum; + /* enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmp; + + /* Set the delay configuration. */ + SPI_SetTransferDelay(base, &config->delayConfig); + /* Set the dummy data. */ + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableMaster); + return kStatus_Success; +} + +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) +{ + assert(NULL != config); + + config->enableSlave = true; + config->polarity = kSPI_ClockPolarityActiveHigh; + config->phase = kSPI_ClockPhaseFirstEdge; + config->direction = kSPI_MsbFirst; + config->dataWidth = kSPI_Data8Bits; + config->txWatermark = kSPI_TxFifo0; + config->rxWatermark = kSPI_RxFifo1; + config->sselPol = kSPI_SpolActiveAllLow; +} + +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) +{ + int32_t result = 0, instance; + uint32_t tmp; + + /* assert params */ + assert(!((NULL == base) || (NULL == config))); + if ((NULL == base) || (NULL == config)) + { + return kStatus_InvalidArgument; + } + /* configure flexcomm to SPI, enable clock gate */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); + assert(kStatus_Success == result); + if (kStatus_Success != result) + { + return result; + } + + instance = SPI_GetInstance(base); + + /* configure SPI mode */ + tmp = base->CFG; + tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK | + SPI_SSELPOL_MASK); + /* phase */ + tmp |= SPI_CFG_CPHA(config->phase); + /* polarity */ + tmp |= SPI_CFG_CPOL(config->polarity); + /* direction */ + tmp |= SPI_CFG_LSBF(config->direction); + /* configure active level for all CS */ + tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmp; + + /* store configuration */ + g_configs[instance].dataWidth = config->dataWidth; + /* empty and enable FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; + /* trigger level - empty txFIFO, one item in rxFIFO */ + tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable generating interrupts for FIFOTRIG levels */ + tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + /* set FIFOTRIG */ + base->FIFOTRIG = tmp; + + SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); + + SPI_Enable(base, config->enableSlave); + return kStatus_Success; +} + +void SPI_Deinit(SPI_Type *base) +{ + /* Assert arguments */ + assert(NULL != base); + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXERR_MASK | SPI_FIFOINTENCLR_RXERR_MASK | SPI_FIFOINTENCLR_TXLVL_MASK | + SPI_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(SPI_FIFOCFG_DMATX_MASK | SPI_FIFOCFG_DMARX_MASK); + base->CFG &= ~(SPI_CFG_ENABLE_MASK); +} + +void SPI_EnableTxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMATX_MASK; + } +} + +void SPI_EnableRxDMA(SPI_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= SPI_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~SPI_FIFOCFG_DMARX_MASK; + } +} + +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t tmp; + + /* assert params */ + assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); + if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* calculate baudrate */ + tmp = (srcClock_Hz / baudrate_Bps) - 1; + if (tmp > 0xFFFF) + { + return kStatus_SPI_BaudrateNotSupport; + } + base->DIV &= ~SPI_DIV_DIVVAL_MASK; + base->DIV |= SPI_DIV_DIVVAL(tmp); + return kStatus_Success; +} + +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) +{ + uint32_t control = 0; + int32_t instance; + + /* check params */ + assert(NULL != base); + /* get and check instance */ + instance = SPI_GetInstance(base); + assert(!(instance < 0)); + if (instance < 0) + { + return; + } + + /* set data width */ + control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth); + /* set sssel */ + control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); + /* mask configFlags */ + control |= (configFlags & SPI_FIFOWR_FLAGS_MASK); + /* control should not affect lower 16 bits */ + assert(!(control & 0xFFFF)); + base->FIFOWR = data | control; +} + +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData) +{ + int32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + /* get flexcomm instance by 'base' param */ + instance = SPI_GetInstance(base); + assert(!(instance < 0)); + if (instance < 0) + { + return kStatus_InvalidArgument; + } + + memset(handle, 0, sizeof(*handle)); + /* Initialize the handle */ + if (base->CFG & SPI_CFG_MASTER_MASK) + { + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_MasterTransferHandleIRQ, handle); + } + else + { + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)SPI_SlaveTransferHandleIRQ, handle); + } + + handle->dataWidth = g_configs[instance].dataWidth; + /* in slave mode, the sselNum is not important */ + handle->sselNum = g_configs[instance].sselNum; + handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base); + handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base); + handle->callback = callback; + handle->userData = userData; + + /* Enable SPI NVIC */ + EnableIRQ(s_spiIRQ[instance]); + + return kStatus_Success; +} + +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) +{ + int32_t instance; + uint32_t tx_ctrl = 0, last_ctrl = 0; + uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; + uint32_t toReceiveCount = 0; + uint8_t *txData, *rxData; + uint32_t fifoDepth; + + /* check params */ + assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + fifoDepth = SPI_FIFO_DEPTH(base); + txData = xfer->txData; + rxData = xfer->rxData; + txRemainingBytes = txData ? xfer->dataSize : 0; + rxRemainingBytes = rxData ? xfer->dataSize : 0; + + instance = SPI_GetInstance(base); + assert(instance >= 0); + dataWidth = g_configs[instance].dataWidth; + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); + if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) + { + return kStatus_InvalidArgument; + } + + /* clear tx/rx errors and empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* select slave to talk with */ + tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); + /* set width of data - range asserted at entry */ + tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); + /* delay for frames */ + tx_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; + /* end of transfer */ + last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; + /* last index of loop */ + while (txRemainingBytes || rxRemainingBytes || toReceiveCount) + { + /* if rxFIFO is not empty */ + if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (rxRemainingBytes) + { + *(rxData++) = tmp32; + rxRemainingBytes--; + /* read 16 bits at once */ + if (dataWidth > 8) + { + *(rxData++) = tmp32 >> 8; + rxRemainingBytes--; + } + } + /* decrease number of data expected to receive */ + toReceiveCount -= 1; + } + /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) && + ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)))) + { + /* txBuffer is not empty */ + if (txRemainingBytes) + { + tmp32 = *(txData++); + txRemainingBytes--; + /* write 16 bit at once */ + if (dataWidth > 8) + { + tmp32 |= ((uint32_t)(*(txData++))) << 8U; + txRemainingBytes--; + } + if (!txRemainingBytes) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); + /* last transfer */ + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + toReceiveCount += 1; + } + } + /* wait if TX FIFO of previous transfer is not empty */ + while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) + { + } + return kStatus_Success; +} + +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer) +{ + /* check params */ + assert( + !((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ + assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); + if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) + { + return kStatus_InvalidArgument; + } + + /* Check if SPI is busy */ + if (handle->state == kStatus_SPI_Busy) + { + return kStatus_SPI_Busy; + } + + /* Set the handle information */ + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + /* set count */ + handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0; + handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0; + handle->totalByteCount = xfer->dataSize; + /* other options */ + handle->toReceiveCount = 0; + handle->configFlags = xfer->configFlags; + /* Set the SPI state to busy */ + handle->state = kStatus_SPI_Busy; + /* clear FIFOs when transfer starts */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; + /* enable generating txIRQ and rxIRQ, first transfer is fired by empty txFIFO */ + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK; + return kStatus_Success; +} + +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + /* SPI transfer blocking. */ + status = SPI_MasterTransferBlocking(base, &tempXfer); + + return status; +} + +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the PCS pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer); + + return status; +} + +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kStatus_SPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->rxRemainingBytes; + return kStatus_Success; +} + +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupt requests*/ + base->FIFOINTENSET &= ~(SPI_FIFOINTENSET_TXLVL_MASK | SPI_FIFOINTENSET_RXLVL_MASK); + /* Empty FIFOs */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + + handle->state = kStatus_SPI_Idle; + handle->txRemainingBytes = 0; + handle->rxRemainingBytes = 0; +} + +static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) +{ + uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32; + bool loopContinue; + uint32_t fifoDepth; + /* Get flexcomm instance by 'base' param */ + uint32_t instance = SPI_GetInstance(base); + + /* check params */ + assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); + + fifoDepth = SPI_FIFO_DEPTH(base); + /* select slave to talk with */ + tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum)); + /* set width of data */ + tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); + /* delay for frames */ + tx_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; + /* end of transfer */ + last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; + do + { + loopContinue = false; + + /* rxFIFO is not empty */ + if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + { + tmp32 = base->FIFORD; + /* rxBuffer is not empty */ + if (handle->rxRemainingBytes) + { + /* low byte must go first */ + *(handle->rxData++) = tmp32; + handle->rxRemainingBytes--; + /* read 16 bits at once */ + if (handle->dataWidth > kSPI_Data8Bits) + { + *(handle->rxData++) = tmp32 >> 8; + handle->rxRemainingBytes--; + } + } + /* decrease number of data expected to receive */ + handle->toReceiveCount -= 1; + loopContinue = true; + } + + /* - txFIFO is not full + * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO + * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer + */ + if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) && + ((handle->txRemainingBytes) || + (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)))) + { + /* txBuffer is not empty */ + if (handle->txRemainingBytes) + { + /* low byte must go first */ + tmp32 = *(handle->txData++); + handle->txRemainingBytes--; + /* write 16 bit at once */ + if (handle->dataWidth > kSPI_Data8Bits) + { + tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; + handle->txRemainingBytes--; + } + /* last transfer */ + if (!handle->txRemainingBytes) + { + tx_ctrl |= last_ctrl; + } + } + else + { + tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); + /* last transfer */ + if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)) + { + tx_ctrl |= last_ctrl; + } + } + /* send data */ + tmp32 = tx_ctrl | tmp32; + base->FIFOWR = tmp32; + /* increase number of expected data to receive */ + handle->toReceiveCount += 1; + loopContinue = true; + } + } while (loopContinue); +} + +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) +{ + assert((NULL != base) && (NULL != handle)); + + /* IRQ behaviour: + * - first interrupt is triggered by empty txFIFO. The transfer function + * then tries empty rxFIFO and fill txFIFO interleaved that results to + * strategy to process as many items as possible. + * - the next IRQs can be: + * rxIRQ from nonempty rxFIFO which requires to empty rxFIFO. + * txIRQ from empty txFIFO which requires to refill txFIFO. + * - last interrupt is triggered by empty txFIFO. The last state is + * known by empty rxBuffer and txBuffer. If there is nothing to receive + * or send - both operations have been finished and interrupts can be + * disabled. + */ + + /* Data to send or read or expected to receive */ + if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount)) + { + /* Transmit or receive data */ + SPI_TransferHandleIRQInternal(base, handle); + /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and + * enable txIRQ to confirm when txFIFO becomes empty */ + if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount)) + { + base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); + base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; + } + else + { + uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); + /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, + * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ + if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount)) + { + base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; + } + /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. + * Cannot clear rxFIFO, txFIFO might be still active */ + if (rxRemainingCount == 0) + { + if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) && + (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1); + } + } + /* Expected to receive less data than rxLevel value, we have to update rxLevel */ + else + { + if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1); + } + } + } + } + else + { + /* Empty txFIFO is confirmed. Disable IRQs and restore triggers values */ + base->FIFOINTENCLR = SPI_FIFOINTENCLR_RXLVL_MASK | SPI_FIFOINTENCLR_TXLVL_MASK; + base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | + SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); + /* set idle state and call user callback */ + handle->state = kStatus_SPI_Idle; + if (handle->callback) + { + (handle->callback)(base, handle, handle->state, handle->userData); + } + } +} diff --git a/fnet_demos/common/startup/LPC54628/fsl_spi.h b/fnet_demos/common/startup/LPC54628/fsl_spi.h new file mode 100644 index 00000000..14330ef2 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_spi.h @@ -0,0 +1,736 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SPI_H_ +#define _FSL_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/*! + * @addtogroup spi_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART driver version 2.0.0. */ +#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +#ifndef SPI_DUMMYDATA +/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */ +#define SPI_DUMMYDATA (0xFFU) +#endif + +#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF) +#define SPI_CTRLMASK (0xFFFF0000) + +#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000) +#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16)) +#define SPI_DEASSERT_ALL (0xF0000) + +#define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) + +#define SPI_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_TXLVL_MASK) >> SPI_FIFOTRIG_TXLVL_SHIFT) +#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief SPI transfer option.*/ +typedef enum _spi_xfer_option +{ + kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< Delay chip select */ + kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< When transfer ends, assert chip select */ +} spi_xfer_option_t; + +/*! @brief SPI data shifter direction options.*/ +typedef enum _spi_shift_direction +{ + kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */ + kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */ +} spi_shift_direction_t; + +/*! @brief SPI clock polarity configuration.*/ +typedef enum _spi_clock_polarity +{ + kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */ + kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */ +} spi_clock_polarity_t; + +/*! @brief SPI clock phase configuration.*/ +typedef enum _spi_clock_phase +{ + kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first + * cycle of a data transfer. */ + kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the + * first cycle of a data transfer. */ +} spi_clock_phase_t; + +/*! @brief txFIFO watermark values */ +typedef enum _spi_txfifo_watermark +{ + kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */ + kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */ + kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */ + kSPI_TxFifo3 = 3, /*!< SPI tx watermark at 3 items */ + kSPI_TxFifo4 = 4, /*!< SPI tx watermark at 4 items */ + kSPI_TxFifo5 = 5, /*!< SPI tx watermark at 5 items */ + kSPI_TxFifo6 = 6, /*!< SPI tx watermark at 6 items */ + kSPI_TxFifo7 = 7, /*!< SPI tx watermark at 7 items */ +} spi_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _spi_rxfifo_watermark +{ + kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */ + kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */ + kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */ + kSPI_RxFifo4 = 3, /*!< SPI rx watermark at 4 items */ + kSPI_RxFifo5 = 4, /*!< SPI rx watermark at 5 items */ + kSPI_RxFifo6 = 5, /*!< SPI rx watermark at 6 items */ + kSPI_RxFifo7 = 6, /*!< SPI rx watermark at 7 items */ + kSPI_RxFifo8 = 7, /*!< SPI rx watermark at 8 items */ +} spi_rxfifo_watermark_t; + +/*! @brief Transfer data width */ +typedef enum _spi_data_width +{ + kSPI_Data4Bits = 3, /*!< 4 bits data width */ + kSPI_Data5Bits = 4, /*!< 5 bits data width */ + kSPI_Data6Bits = 5, /*!< 6 bits data width */ + kSPI_Data7Bits = 6, /*!< 7 bits data width */ + kSPI_Data8Bits = 7, /*!< 8 bits data width */ + kSPI_Data9Bits = 8, /*!< 9 bits data width */ + kSPI_Data10Bits = 9, /*!< 10 bits data width */ + kSPI_Data11Bits = 10, /*!< 11 bits data width */ + kSPI_Data12Bits = 11, /*!< 12 bits data width */ + kSPI_Data13Bits = 12, /*!< 13 bits data width */ + kSPI_Data14Bits = 13, /*!< 14 bits data width */ + kSPI_Data15Bits = 14, /*!< 15 bits data width */ + kSPI_Data16Bits = 15, /*!< 16 bits data width */ +} spi_data_width_t; + +/*! @brief Slave select */ +typedef enum _spi_ssel +{ + kSPI_Ssel0 = 0, /*!< Slave select 0 */ + kSPI_Ssel1 = 1, /*!< Slave select 1 */ + kSPI_Ssel2 = 2, /*!< Slave select 2 */ + kSPI_Ssel3 = 3, /*!< Slave select 3 */ +} spi_ssel_t; + +/*! @brief ssel polarity */ +typedef enum _spi_spol +{ + kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), + kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), + kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), + kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), + kSPI_SpolActiveAllHigh = + (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), + kSPI_SpolActiveAllLow = 0, +} spi_spol_t; + +/*! + * @brief SPI delay time configure structure. + * Note: + * The DLY register controls several programmable delays related to SPI signalling, + * it stands for how many SPI clock time will be inserted. + * The maxinun value of these delay time is 15. + */ +typedef struct _spi_delay_config +{ + uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */ + uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */ + uint8_t frameDelay; /*!< Delay between frame to frame. */ + uint8_t transferDelay; /*!< Delay between transfer to transfer. */ +} spi_delay_config_t; + +/*! @brief SPI master user configure structure.*/ +typedef struct _spi_master_config +{ + bool enableLoopback; /*!< Enable loopback for test purpose */ + bool enableMaster; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_ssel_t sselNum; /*!< Slave select number */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + spi_delay_config_t delayConfig; /*!< Delay configuration. */ +} spi_master_config_t; + +/*! @brief SPI slave user configure structure.*/ +typedef struct _spi_slave_config +{ + bool enableSlave; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +} spi_slave_config_t; + +/*! @brief SPI transfer status.*/ +enum _spi_status +{ + kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ + kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ + kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ + kStatus_SPI_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */ +}; + +/*! @brief SPI interrupt sources.*/ +enum _spi_interrupt_enable +{ + kSPI_RxLvlIrq = SPI_FIFOINTENSET_RXLVL_MASK, /*!< Rx level interrupt */ + kSPI_TxLvlIrq = SPI_FIFOINTENSET_TXLVL_MASK, /*!< Tx level interrupt */ +}; + +/*! @brief SPI status flags.*/ +enum _spi_statusflags +{ + kSPI_TxEmptyFlag = SPI_FIFOSTAT_TXEMPTY_MASK, /*!< txFifo is empty */ + kSPI_TxNotFullFlag = SPI_FIFOSTAT_TXNOTFULL_MASK, /*!< txFifo is not full */ + kSPI_RxNotEmptyFlag = SPI_FIFOSTAT_RXNOTEMPTY_MASK, /*!< rxFIFO is not empty */ + kSPI_RxFullFlag = SPI_FIFOSTAT_RXFULL_MASK, /*!< rxFIFO is full */ +}; + +/*! @brief SPI transfer structure */ +typedef struct _spi_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + uint32_t configFlags; /*!< Additional option to control transfer */ + size_t dataSize; /*!< Transfer bytes */ +} spi_transfer_t; + +/*! @brief SPI half-duplex(master only) transfer structure */ +typedef struct _spi_half_duplex_transfer +{ + uint8_t *txData; /*!< Send buffer */ + uint8_t *rxData; /*!< Receive buffer */ + size_t txDataSize; /*!< Transfer bytes for transmit */ + size_t rxDataSize; /*!< Transfer bytes */ + uint32_t configFlags; /*!< Transfer configuration flags. */ + bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for + deassert. */ + bool isTransmitFirst; /*!< True for transmit first and false for receive first. */ +} spi_half_duplex_transfer_t; + +/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */ +typedef struct _spi_config +{ + spi_data_width_t dataWidth; + spi_ssel_t sselNum; +} spi_config_t; + +/*! @brief Master handle type */ +typedef struct _spi_master_handle spi_master_handle_t; + +/*! @brief Slave handle type */ +typedef spi_master_handle_t spi_slave_handle_t; + +/*! @brief SPI master callback for finished transmit */ +typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI slave callback for finished transmit */ +typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI transfer handle structure */ +struct _spi_master_handle +{ + uint8_t *volatile txData; /*!< Transfer buffer */ + uint8_t *volatile rxData; /*!< Receive buffer */ + volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ + volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ + volatile size_t toReceiveCount; /*!< Receive data remaining in bytes */ + size_t totalByteCount; /*!< A number of transfer bytes */ + volatile uint32_t state; /*!< SPI internal state */ + spi_master_callback_t callback; /*!< SPI callback */ + void *userData; /*!< Callback parameter */ + uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ + uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ + uint32_t configFlags; /*!< Additional option to control transfer */ + spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +}; + +#if defined(__cplusplus) +extern "C" { +#endif +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @brief Returns instance number for SPI peripheral base address. */ +uint32_t SPI_GetInstance(SPI_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Sets the SPI master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit(). + * User may use the initialized structure unchanged in SPI_MasterInit(), or modify + * some fields of the structure before calling SPI_MasterInit(). After calling this API, + * the master is ready to transfer. + * Example: + @code + spi_master_config_t config; + SPI_MasterGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master config structure + */ +void SPI_MasterGetDefaultConfig(spi_master_config_t *config); + +/*! + * @brief Initializes the SPI with master configuration. + * + * The configuration structure can be filled by user from scratch, or be set with default + * values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer. + * Example + @code + spi_master_config_t config = { + .baudRate_Bps = 400000, + ... + }; + SPI_MasterInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to master configuration structure + * @param srcClock_Hz Source clock frequency. + */ +status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Sets the SPI slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit(). + * Modify some fields of the structure before calling SPI_SlaveInit(). + * Example: + @code + spi_slave_config_t config; + SPI_SlaveGetDefaultConfig(&config); + @endcode + * + * @param config pointer to slave configuration structure + */ +void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config); + +/*! + * @brief Initializes the SPI with slave configuration. + * + * The configuration structure can be filled by user from scratch or be set with + * default values by SPI_SlaveGetDefaultConfig(). + * After calling this API, the slave is ready to transfer. + * Example + @code + spi_slave_config_t config = { + .polarity = flexSPIClockPolarity_ActiveHigh; + .phase = flexSPIClockPhase_FirstEdge; + .direction = flexSPIMsbFirst; + ... + }; + SPI_SlaveInit(SPI0, &config); + @endcode + * + * @param base SPI base pointer + * @param config pointer to slave configuration structure + */ +status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config); + +/*! + * @brief De-initializes the SPI. + * + * Calling this API resets the SPI module, gates the SPI clock. + * The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module. + * + * @param base SPI base pointer + */ +void SPI_Deinit(SPI_Type *base); + +/*! + * @brief Enable or disable the SPI Master or Slave + * @param base SPI base pointer + * @param enable or disable ( true = enable, false = disable) + */ +static inline void SPI_Enable(SPI_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= SPI_CFG_ENABLE_MASK; + } + else + { + base->CFG &= ~SPI_CFG_ENABLE_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the status flag. + * + * @param base SPI base pointer + * @return SPI Status, use status flag to AND @ref _spi_statusflags could get the related status. + */ +static inline uint32_t SPI_GetStatusFlags(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFOSTAT; +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENSET = irqs; +} + +/*! + * @brief Disables the interrupt for the SPI. + * + * @param base SPI base pointer + * @param irqs SPI interrupt source. The parameter can be any combination of the following values: + * @arg kSPI_RxLvlIrq + * @arg kSPI_TxLvlIrq + */ +static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs) +{ + assert(NULL != base); + base->FIFOINTENCLR = irqs; +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DMA request from SPI txFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableTxDMA(SPI_Type *base, bool enable); + +/*! + * @brief Enables the DMA request from SPI rxFIFO. + * + * @param base SPI base pointer + * @param enable True means enable DMA, false means disable DMA + */ +void SPI_EnableRxDMA(SPI_Type *base, bool enable); + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the baud rate for SPI transfer. This is only used in master. + * + * @param base SPI base pointer + * @param baudrate_Bps baud rate needed in Hz. + * @param srcClock_Hz SPI source clock frequency in Hz. + */ +status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Writes a data into the SPI data register. + * + * @param base SPI base pointer + * @param data needs to be write. + * @param configFlags transfer configuration options @ref spi_xfer_option_t + */ +void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags); + +/*! + * @brief Gets a data from the SPI data register. + * + * @param base SPI base pointer + * @return Data in the register. + */ +static inline uint32_t SPI_ReadData(SPI_Type *base) +{ + assert(NULL != base); + return base->FIFORD; +} + +/*! + * @brief Set delay time for transfer. + * the delay uint is SPI clock time, maximum value is 0xF. + * @param base SPI base pointer + * @param config configuration for delay option @ref spi_delay_config_t. + */ +static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config) +{ + assert(NULL != base); + assert(NULL != config); + base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) | + SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay)); +} + +/*! + * @brief Set up the dummy data. + * + * @param base SPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + */ +void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SPI master handle. + * + * This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +status_t SPI_MasterTransferCreateHandle(SPI_Type *base, + spi_master_handle_t *handle, + spi_master_callback_t callback, + void *userData); + +/*! + * @brief Transfers a block of data using a polling method. + * + * @param base SPI base pointer + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a polling method. + * + * This function will do a half-duplex transfer for SPI master, This is a blocking function, + * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex, + * users can set transmit first or receive first. + * + * @param base SPI base pointer + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPI interrupt transfer. + * + * This function using polling way to do the first half transimission and using interrupts to + * do the second half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_half_duplex_transfer_t structure + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, + spi_master_handle_t *handle, + spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count); + +/*! + * @brief SPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Interrupts the handler for the SPI. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state. + */ +void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle); + +/*! + * @brief Initializes the SPI slave handle. + * + * This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually, + * for a specified SPI instance, call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +static inline status_t SPI_SlaveTransferCreateHandle(SPI_Type *base, + spi_slave_handle_t *handle, + spi_slave_callback_t callback, + void *userData) +{ + return SPI_MasterTransferCreateHandle(base, handle, callback, userData); +} + +/*! + * @brief Performs a non-blocking SPI slave interrupt transfer. + * + * @note The API returns immediately after the transfer initialization is finished. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_master_handle_t structure which stores the transfer state + * @param xfer pointer to spi_xfer_config_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferNonBlocking(base, handle, xfer); +} + +/*! + * @brief Gets the slave transfer count. + * + * This function gets the slave transfer count. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count); +} + +/*! + * @brief SPI slave aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base SPI peripheral base address. + * @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state. + */ +static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle); +} + +/*! + * @brief Interrupts a handler for the SPI slave. + * + * @param base SPI peripheral base address. + * @param handle pointer to spi_slave_handle_t structure which stores the transfer state + */ +static inline void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle) +{ + SPI_MasterTransferHandleIRQ(base, handle); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_H_*/ diff --git a/fnet_demos/common/startup/LPC54628/fsl_spi_dma.c b/fnet_demos/common/startup/LPC54628/fsl_spi_dma.c new file mode 100644 index 00000000..499404e0 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_spi_dma.c @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_spi_dma.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +/*configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0; + *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0; +} + +static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) +{ + *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum))); + /* set width of data - range asserted at entry */ + *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); +} + +static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config) +{ + if (config->dataWidth > kSPI_Data8Bits) + { + *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1] << 8U) | (xfer->txData[xfer->dataSize - 2])); + } + else + { + *txLastWord = xfer->txData[xfer->dataSize - 1]; + } + XferToFifoWR(xfer, txLastWord); + SpiConfigToFifoWR(config, txLastWord); +} + +static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) +{ + uint32_t instance = SPI_GetInstance(base); + dummy->word = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + XferToFifoWR(xfer, &dummy->word); + XferToFifoWR(xfer, &dummy->lastWord); + SpiConfigToFifoWR(spi_config_p, &dummy->word); + SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); + /* Clear the end of transfer bit for continue word transfer. */ + dummy->word &= (uint32_t)(~kSPI_FrameAssert); +} + +status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + int32_t instance = 0; + + /* check 'base' */ + assert(!(NULL == base)); + if (NULL == base) + { + return kStatus_InvalidArgument; + } + /* check 'handle' */ + assert(!(NULL == handle)); + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + + instance = SPI_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + /* Set spi base to handle */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle */ + handle->state = kSPI_Idle; + + /* Set handle to global state */ + s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].handle = handle; + + /* Install callback for Tx dma channel */ + DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]); + DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]); + + return kStatus_Success; +} + +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + int32_t instance; + status_t result = kStatus_Success; + spi_config_t *spi_config_p; + + assert(!((NULL == handle) || (NULL == xfer))); + if ((NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + + /* Byte size is zero. */ + assert(!(xfer->dataSize == 0)); + if (xfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + /* cannot get instance from base address */ + instance = SPI_GetInstance(base); + assert(!(instance < 0)); + if (instance < 0) + { + return kStatus_InvalidArgument; + } + + /* Check if the device is busy */ + if (handle->state == kSPI_Busy) + { + return kStatus_SPI_Busy; + } + else + { + uint32_t tmp; + dma_transfer_config_t xferConfig = {0}; + spi_config_p = (spi_config_t *)SPI_GetConfig(base); + + handle->state = kStatus_SPI_Busy; + handle->transferSize = xfer->dataSize; + + /* receive */ + SPI_EnableRxDMA(base, true); + if (xfer->rxData) + { + DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_PeripheralToMemory, NULL); + } + else + { + DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); + } + DMA_SubmitTransfer(handle->rxHandle, &xferConfig); + handle->rxInProgress = true; + DMA_StartTransfer(handle->rxHandle); + + /* transmit */ + SPI_EnableTxDMA(base, true); + + if (xfer->configFlags & kSPI_FrameAssert) + { + PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); + } + + if (xfer->txData) + { + /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma + * descriptor to send the last data. + */ + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) + { + dma_xfercfg_t tmp_xfercfg = {0}; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], + (void *)&base->FIFOWR, NULL); + + DMA_PrepareTransfer( + &xferConfig, xfer->txData, (void *)&base->FIFOWR, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice. */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, xfer->txData, (void *)&base->FIFOWR, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_MemoryToPeripheral, NULL); + DMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + } + else + { + /* Setup tx dummy data. */ + SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) + { + dma_xfercfg_t tmp_xfercfg = {0}; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; + tmp_xfercfg.transferCount = 1; + /* Create chained descriptor to transmit last word */ + DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, + (uint32_t *)&base->FIFOWR, NULL); + /* Use common API to setup first descriptor */ + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); + /* Disable interrupts for first descriptor to avoid calling callback twice */ + xferConfig.xfercfg.intA = false; + xferConfig.xfercfg.intB = false; + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + else + { + DMA_PrepareTransfer( + &xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), + xfer->dataSize, kDMA_StaticToStatic, NULL); + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + if (result != kStatus_Success) + { + return result; + } + } + } + + handle->txInProgress = true; + tmp = 0; + XferToFifoWR(xfer, &tmp); + SpiConfigToFifoWR(spi_config_p, &tmp); + + /* Setup the control info. + * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. + * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR + * will push the data and the current control bits into the FIFO. + */ + if ((xfer->configFlags & kSPI_FrameAssert) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) + { + *(((uint16_t *)&(base->FIFOWR)) + 1) = (uint16_t)(tmp >> 16U); + } + else + { + /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ + tmp &= (uint32_t)(~kSPI_FrameAssert); + *(((uint16_t *)&(base->FIFOWR)) + 1) = (uint16_t)(tmp >> 16U); + } + + DMA_StartTransfer(handle->txHandle); + } + + return result; +} + +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) +{ + assert(xfer); + assert(handle); + spi_transfer_t tempXfer = {0}; + status_t status; + + if (xfer->isTransmitFirst) + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + else + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + /* If the pcs pin keep assert between transmit and receive. */ + if (xfer->isPcsAssertInTransfer) + { + tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + } + else + { + tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + } + + status = SPI_MasterTransferBlocking(base, &tempXfer); + if (status != kStatus_Success) + { + return status; + } + + if (xfer->isTransmitFirst) + { + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; + tempXfer.dataSize = xfer->rxDataSize; + } + else + { + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; + tempXfer.dataSize = xfer->txDataSize; + } + tempXfer.configFlags = xfer->configFlags; + + status = SPI_MasterTransferDMA(base, handle, &tempXfer); + + return status; +} + +static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* change the state */ + spiHandle->rxInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = kSPI_Idle; + if (spiHandle->callback) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) +{ + spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; + + /* change the state */ + spiHandle->txInProgress = false; + + /* All finished, call the callback */ + if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) + { + spiHandle->state = kSPI_Idle; + if (spiHandle->callback) + { + (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); + } + } +} + +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + assert(NULL != handle); + + /* Stop tx transfer first */ + DMA_AbortTransfer(handle->txHandle); + /* Then rx transfer */ + DMA_AbortTransfer(handle->rxHandle); + + /* Set the handle state */ + handle->txInProgress = false; + handle->rxInProgress = false; + handle->state = kSPI_Idle; +} + +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel); + + *count = handle->transferSize - bytes; + + return kStatus_Success; +} diff --git a/fnet_demos/common/startup/LPC54628/fsl_spi_dma.h b/fnet_demos/common/startup/LPC54628/fsl_spi_dma.h new file mode 100644 index 00000000..c1ac9f4a --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_spi_dma.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SPI_DMA_H_ +#define _FSL_SPI_DMA_H_ + +#include "fsl_dma.h" +#include "fsl_spi.h" + +/*! + * @addtogroup spi_dma_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +typedef struct _spi_dma_handle spi_dma_handle_t; + +/*! @brief SPI DMA callback called at the end of transfer. */ +typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData); + +/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/ +struct _spi_dma_handle +{ + volatile bool txInProgress; /*!< Send transfer finished */ + volatile bool rxInProgress; /*!< Receive transfer finished */ + dma_handle_t *txHandle; /*!< DMA handler for SPI send */ + dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI tranfer */ + spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ + uint32_t state; /*!< Internal state of SPI DMA transfer */ + size_t transferSize; /*!< Bytes need to be transfer */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DMA Transactional + * @{ + */ + +/*! + * @brief Initialize the SPI master DMA handle. + * + * This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle); + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); + +/*! + * @brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI base pointer + * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * @param transfer A pointer to the spi_half_duplex_transfer_t structure. + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); + +/*! + * @brief Initialize the SPI slave DMA handle. + * + * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs. + * Usually, for a specified SPI instance, user need only call this API once to get the initialized handle. + * + * @param base SPI peripheral base address. + * @param handle SPI handle pointer. + * @param callback User callback function called at the end of a transfer. + * @param userData User data for callback. + * @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users. + * @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users. + */ +static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base, + spi_dma_handle_t *handle, + spi_dma_callback_t callback, + void *userData, + dma_handle_t *txHandle, + dma_handle_t *rxHandle) +{ + return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Perform a non-blocking SPI transfer using DMA. + * + * @note This interface returned immediately after transfer initiates, users should call + * SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + * @param xfer Pointer to dma transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Busy SPI is not idle, is running another transfer. + */ +static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) +{ + return SPI_MasterTransferDMA(base, handle, xfer); +} + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle); + +/*! + * @brief Gets the master DMA transfer remaining bytes. + * + * This function gets the master DMA transfer remaining bytes. + * + * @param base SPI peripheral base address. + * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * @param count A number of bytes transferred by the non-blocking transaction. + * @return status of status_t. + */ +status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count); + +/*! + * @brief Abort a SPI transfer using DMA. + * + * @param base SPI peripheral base address. + * @param handle SPI DMA handle pointer. + */ +static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) +{ + SPI_MasterTransferAbortDMA(base, handle); +} + +/*! + * @brief Gets the slave DMA transfer remaining bytes. + * + * This function gets the slave DMA transfer remaining bytes. + * + * @param base SPI peripheral base address. + * @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state. + * @param count A number of bytes transferred by the non-blocking transaction. + * @return status of status_t. + */ +static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) +{ + return SPI_MasterTransferGetCountDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_SPI_DMA_H_*/ diff --git a/fnet_demos/common/startup/LPC54628/fsl_usart.c b/fnet_demos/common/startup/LPC54628/fsl_usart.c new file mode 100644 index 00000000..ab31fc3a --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_usart.c @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_flexcomm.h" + +enum _usart_transfer_states +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief IRQ name array */ +static const IRQn_Type s_usartIRQ[] = USART_IRQS; + +/*! @brief Array to map USART instance number to base address. */ +static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the USART */ +uint32_t USART_GetInstance(USART_Type *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++) + { + if ((uint32_t)base == s_usartBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +{ + size_t size; + + /* Check arguments */ + assert(NULL != handle); + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + return size; +} + +static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) +{ + bool full; + + /* Check arguments */ + assert(NULL != handle); + + if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + /* ring buffer is ready we can start receiving data */ + base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +} + +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + + if (handle->rxState == kUSART_RxIdle) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; + } + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) +{ + int result; + + /* check arguments */ + assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to USART mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); + if (kStatus_Success != result) + { + return result; + } + + /* setup baudrate */ + result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + + if (config->enableTx) + { + /* empty and enable txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; + } + + /* empty and enable rxFIFO */ + if (config->enableRx) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; + } + /* setup configuration and enable USART */ + base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | + USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK; + return kStatus_Success; +} + +void USART_Deinit(USART_Type *base) +{ + /* Check arguments */ + assert(NULL != base); + while (!(base->STAT & USART_STAT_TXIDLE_MASK)) + { + } + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | + USART_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); + base->CFG &= ~(USART_CFG_ENABLE_MASK); +} + +void USART_GetDefaultConfig(usart_config_t *config) +{ + /* Check arguments */ + assert(NULL != config); + + /* Set always all members ! */ + config->baudRate_Bps = 115200U; + config->parityMode = kUSART_ParityDisabled; + config->stopBitCount = kUSART_OneStopBit; + config->bitCountPerChar = kUSART_8BitsPerChar; + config->loopback = false; + config->enableRx = false; + config->enableTx = false; + config->txWatermark = kUSART_TxFifo0; + config->rxWatermark = kUSART_RxFifo1; +} + +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; + uint32_t osrval, brgval, diff, baudrate; + + /* check arguments */ + assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); + if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* + * Smaller values of OSR can make the sampling position within a data bit less accurate and may + * potentially cause more noise errors or incorrect data. + */ + for (osrval = best_osrval; osrval >= 8; osrval--) + { + brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1; + if (brgval > 0xFFFF) + { + continue; + } + baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1)); + diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate; + if (diff < best_diff) + { + best_diff = diff; + best_osrval = osrval; + best_brgval = brgval; + } + } + + /* value over range */ + if (best_brgval > 0xFFFF) + { + return kStatus_USART_BaudrateNotSupport; + } + + base->OSR = best_osrval; + base->BRG = best_brgval; + return kStatus_Success; +} + +void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return; + } + /* Check whether txFIFO is enabled */ + if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) + { + return; + } + for (; length > 0; length--) + { + /* Loop until txFIFO get some space for new data */ + while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) + { + } + base->FIFOWR = *data; + data++; + } + /* Wait to finish transfer */ + while (!(base->STAT & USART_STAT_TXIDLE_MASK)) + { + } +} + +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) +{ + uint32_t status; + + /* check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + + /* Check whether rxFIFO is enabled */ + if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK)) + { + return kStatus_Fail; + } + for (; length > 0; length--) + { + /* loop until rxFIFO have some data to read */ + while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) + { + } + /* check receive status */ + status = base->STAT; + if (status & USART_STAT_FRAMERRINT_MASK) + { + base->STAT |= USART_STAT_FRAMERRINT_MASK; + return kStatus_USART_FramingError; + } + if (status & USART_STAT_PARITYERRINT_MASK) + { + base->STAT |= USART_STAT_PARITYERRINT_MASK; + return kStatus_USART_ParityError; + } + if (status & USART_STAT_RXNOISEINT_MASK) + { + base->STAT |= USART_STAT_RXNOISEINT_MASK; + return kStatus_USART_NoiseError; + } + /* check rxFIFO status */ + if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + return kStatus_USART_RxError; + } + + *data = base->FIFORD; + data++; + } + return kStatus_Success; +} + +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData) +{ + int32_t instance = 0; + + /* Check 'base' */ + assert(!((NULL == base) || (NULL == handle))); + if ((NULL == base) || (NULL == handle)) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + /* Set the TX/RX state. */ + handle->rxState = kUSART_RxIdle; + handle->txState = kUSART_TxIdle; + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base); + handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base); + + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)(uintptr_t)USART_TransferHandleIRQ, handle); + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_usartIRQ[instance]); + + return kStatus_Success; +} + +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); + if ((0 == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kUSART_TxBusy == handle->txState) + { + return kStatus_USART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kUSART_TxBusy; + /* Enable transmiter interrupt. */ + base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK; + } + return kStatus_Success; +} + +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupts */ + base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; + /* Empty txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; + + handle->txDataSize = 0; + handle->txState = kUSART_TxIdle; +} + +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if (kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); + if ((0 == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + if (kUSART_RxBusy == handle->rxState) + { + return kStatus_USART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = DisableGlobalIRQ(); + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = USART_TransferGetRxRingBufferLength(handle); + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + bytesToReceive -= bytesToCopy; + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUSART_RxBusy; + } + /* Enable IRQ if previously enabled. */ + EnableGlobalIRQ(regPrimask); + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUSART_RxBusy; + + /* Enable RX interrupt. */ + base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK; + } + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + } + return kStatus_Success; +} + +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable interrupts */ + base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; + /* Empty rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + } + + handle->rxDataSize = 0U; + handle->rxState = kUSART_RxIdle; +} + +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if (kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer); + bool sendEnabled = handle->txDataSize; + + /* If RX overrun. */ + if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) + { + /* Clear rx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxError, handle->userData); + } + } + while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) || + (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))) + { + /* Receive data */ + if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) + { + /* Receive to app bufffer if app buffer is present */ + if (handle->rxDataSize) + { + *handle->rxData = base->FIFORD; + handle->rxDataSize--; + handle->rxData++; + receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer)); + if (!handle->rxDataSize) + { + if (!handle->rxRingBuffer) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; + } + handle->rxState = kUSART_RxIdle; + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Otherwise receive to ring buffer if ring buffer is present */ + else + { + if (handle->rxRingBuffer) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); + } + } + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD; + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + } + /* Send data */ + if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) + { + base->FIFOWR = *handle->txData; + handle->txDataSize--; + handle->txData++; + sendEnabled = handle->txDataSize != 0; + if (!sendEnabled) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; + handle->txState = kUSART_TxIdle; + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } + } + } + } + + /* ring buffer is not used */ + if (NULL == handle->rxRingBuffer) + { + /* restore if rx transfer ends and rxLevel is different from default value */ + if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); + } + /* decrease level if rx transfer is bellow */ + if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1))) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1)); + } + } +} diff --git a/fnet_demos/common/startup/LPC54628/fsl_usart.h b/fnet_demos/common/startup/LPC54628/fsl_usart.h new file mode 100644 index 00000000..9f44f161 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/fsl_usart.h @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_USART_H_ +#define _FSL_USART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART driver version 2.0.0. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) +#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief Error codes for the USART driver. */ +enum _usart_status +{ + kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ + kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ + kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ + kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ + kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ + kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ + kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ + kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ + kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ + kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ + kStatus_USART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ +}; + +/*! @brief USART parity mode. */ +typedef enum _usart_parity_mode +{ + kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} usart_parity_mode_t; + +/*! @brief USART stop bit count. */ +typedef enum _usart_stop_bit_count +{ + kUSART_OneStopBit = 0U, /*!< One stop bit */ + kUSART_TwoStopBit = 1U, /*!< Two stop bits */ +} usart_stop_bit_count_t; + +/*! @brief USART data size. */ +typedef enum _usart_data_len +{ + kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ + kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ +} usart_data_len_t; + +/*! @brief txFIFO watermark values */ +typedef enum _usart_txfifo_watermark +{ + kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ + kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ + kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ + kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ + kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ + kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ + kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ + kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ +} usart_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _usart_rxfifo_watermark +{ + kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ + kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ + kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ + kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ + kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ + kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ + kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ + kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ +} usart_rxfifo_watermark_t; + +/*! + * @brief USART interrupt configuration structure, default settings all disabled. + */ +enum _usart_interrupt_enable +{ + kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), + kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), + kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), + kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), +}; + +/*! + * @brief USART status flags. + * + * This provides constants for the USART status flags for use in the USART functions. + */ +enum _usart_flags +{ + kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ + kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ + kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ + kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ + kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ + kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ +}; + +/*! @brief USART configuration structure. */ +typedef struct _usart_config +{ + uint32_t baudRate_Bps; /*!< USART baud rate */ + usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ + bool loopback; /*!< Enable peripheral loopback */ + bool enableRx; /*!< Enable RX */ + bool enableTx; /*!< Enable TX */ + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +} usart_config_t; + +/*! @brief USART transfer structure. */ +typedef struct _usart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} usart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_handle usart_handle_t; + +/*! @brief USART transfer callback function. */ +typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); + +/*! @brief USART handle structure. */ +struct _usart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + usart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< USART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ + + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! @brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * @code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_InvalidArgument USART base address is not valid + * @retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * @param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config); + +/*! + * @brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * @code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param baudrate_Bps USART baudrate to be set. + * @param srcClock_Hz USART clock source freqency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get USART status flags. + * + * This function get all USART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _usart_flags. To check a specific status, + * compare the return value with enumerators in @ref _usart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) + * { + * ... + * } + * @endcode + * + * @param base USART peripheral base address. + * @return USART status flags which are ORed by the enumerators in the _usart_flags. + */ +static inline uint32_t USART_GetStatusFlags(USART_Type *base) +{ + return base->FIFOSTAT; +} + +/*! + * @brief Clear USART status flags. + * + * This function clear supported USART status flags + * Flags that can be cleared or set are: + * kUSART_TxError + * kUSART_RxError + * For example: + * @code + * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) + * @endcode + * + * @param base USART peripheral base address. + * @param mask status flags to be cleared. + */ +static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) +{ + /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ + base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables USART interrupts according to the provided mask. + * + * This function enables the USART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENSET = mask & 0xF; +} + +/*! + * @brief Disables USART interrupts according to a provided mask. + * + * This function disables the USART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENCLR = mask & 0xF; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return base->FIFOINTENSET; +} + +/*! +* @brief Enable DMA for Tx +*/ +static inline void USART_EnableTxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); + } +} + +/*! +* @brief Enable DMA for Rx +*/ +static inline void USART_EnableRxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); + } +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Writes to the FIFOWR register. + * + * This function writes data to the txFIFO directly. The upper layer must ensure + * that txFIFO has space for data to write before calling this function. + * + * @param base USART peripheral base address. + * @param data The byte to write. + */ +static inline void USART_WriteByte(USART_Type *base, uint8_t data) +{ + base->FIFOWR = data; +} + +/*! + * @brief Reads the FIFORD register directly. + * + * This function reads data from the rxFIFO directly. The upper layer must + * ensure that the rxFIFO is not empty before calling this function. + * + * @param base USART peripheral base address. + * @return The byte read from USART data register. + */ +static inline uint8_t USART_ReadByte(USART_Type *base) +{ + return base->FIFORD; +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @param base USART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base USART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * @retval kStatus_USART_ParityError Noise error happened while receiving data. + * @retval kStatus_USART_NoiseError Framing error happened while receiving data. + * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * @retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the @ref kStatus_USART_TxIdle as status parameter. + * + * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure. See #usart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, + usart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to USART TX register. + * + * This function gets the number of bytes that have been written to USART TX + * register by interrupt method. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure, see #usart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_USART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_H_ */ diff --git a/fnet_demos/common/startup/LPC54628/iar/LPC54628J512_flash_fnet.icf b/fnet_demos/common/startup/LPC54628/iar/LPC54628J512_flash_fnet.icf new file mode 100644 index 00000000..7fc9eec4 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/iar/LPC54628J512_flash_fnet.icf @@ -0,0 +1,106 @@ +/* +** ################################################################### +** Processor: LPC54628J512ET180 +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 +** Version: rev. 1.2, 2017-06-08 +** Build: b170821 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0007FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x20027FFF; + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40101FFF; + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; + diff --git a/fnet_demos/common/startup/LPC54628/iar/iar_lib_power.a b/fnet_demos/common/startup/LPC54628/iar/iar_lib_power.a new file mode 100644 index 0000000000000000000000000000000000000000..ffb36aa1c03a0e265e69db6e7da00899c729a1cc GIT binary patch literal 10462 zcmds6dvIJ=dH?R+m3H;8y_TP`O>!lRB0sd=ha}6clS*2>ku4#=n6T}>bmd)VwY%)D z{0Jea)G-OPshd8?n3SO%rcFB;m}Vd?ZQOV=6sB#;7$@$Nf}kBB9$MtY2_itZzwg|0 zS7(JpHErZSdhDy;`F-a*-}jyOxpx~6#qx>deYN|H%H(hNwFf)e{hb|#;S)vH-;TC6 z!2mqt)NHZrn6ju+x%$@2?*$w~zn z&7GJSG0&K3sS1%TsGTgNBROtXB%O+Tv-|$1-t_x??FU4EMr%LRH`1?Z8amZV8nw^@ zBMKQpUe!jNX`xmw^%jzaV!jxQBX@qvLdg@^sVOs4ByTE~_vVXJ=)N?0i{?3q;)Q~c zN6t)|k)#=$F!PpPp%_a%FkL`rk$1w3PoIiR=3`SJc{Baf0=BHy=pH}pjTMXeRD8N< z!UI>b9I_@Xol0dUvzELYQ5){0Tct4+F34_`Cc%Fb&+`!KR87;e+zn)Y5m!<W8mi${U?-i2W_X{1Akg6|Kp1CchDEWUs1|mtSG;Sz6yTMu@KKcSClu> ztKip^^4BWLcajF%-%`qJ%f5I#-br_X-&V@GeJXE4`MgrT2mHqhZ)1DTh4}6TcPhLe z+^z6Y@Op*67u=)p82Cnop9bHm@B;V_g+BytDEtxdW`#cv-lFi2gYQ-Nr@(y*|0D1= zg+B}4sqnu5Kcw(4f_EwW@4$N%{`cU63jYT9h{C@MKBn+n;KvmH7Py@p^e(a9)bg70 zSnznd7tK#MZBxp5jqd_K51T&Z8?at`zi^{?w0(6;Kvak?;l+M zH^9&1d9UPug8WzUurDtEOXUAe;a@@i2JC-YmVX<3AM*W@{}8+pdEO(qKJ^|9A3lFF zn|~lYm6&cVOgzvUSjc&O;R*9hDq$AFBV(cVwhmusxZ1={}Q-xSOZ4RWf@mP9j{5{l{spR&#%+hjQdF+*sabfV_LG1O} z#9?#FI$}C1jt{?&nsMszQ4ndXED1_+d!-muXfLv}Uy6as>Eu5k#hn%6fM1GHtY`;p zmx!uD-cHREvW6d3)hf1Mf1pxsJNCn-q93$9`zu=;EW563ZqRP7zp}l-vfpwBO%xqd zZgT*w5R!6p0|?TR*zN)d!;;vJ0&rwWY|8=La=>m>(6(G|PSCboZb;C!Ty8?pwpYN6R~vom^qaT_nq9oKXkxboXQz3Z|`nnwDuaI(eb{>;Wm*SJ07vOso{2i zpr<$B>oi(hCsMIfk-~H?mp2OqV=U%t_wB{s&VbRHHU5tgVb+9s=47Xfx#?nfG=3Tm zGucR@U|N~!Og@`VTlrKboytgg0@vcmRJMrs2CJ|bkHuu&^fb25d@6Iw;)O)g#5QVi zGlS-2?oFqP#Wb5r?|Ja$fNFfJ0fmeb^BAb~^oids*USs*} zDcr4%evEFxXgSx}u`A4Df7IHv!+le6b7I1rF!)r6o0&w?==Azp`%YrWTg6-mVlH&F zA873!85`^l$MRF*p(CMiBHW92p-4!0iX6%2r($VuvdL&2dOJGV>kZ@o+iGkgpE|=+ z_iZ(5#hFXTidZF6VcQ446lF83;VN|a=+M#dP$rR{o-kL>0p^&gco|La!VYOo8H{>9 zmOoEC{1A%y#vRMA#2xhg*F7`&=W+uxuX`TN4MgT~xk--AISDzBJDM9mWH<^>zm;J>Pz!vEaVnj-U`cf`4ijL!{hc@y8KN4p||uO zM{d59Uwx~2#I`otP6={oIwA&tH9(S{&E(mYQphm+NP_X3eaJ?h>_~(w`E0_z%ei4KWQiB$rFvsS$|%hX%bxOBZOv+I_rv2K|f+Lc)mqvINT^jy1V zRyXuZnxWyLOWIDYNs|^4A^Nvr*6}mT^;t{LbtN)46XhB_Iy2Qjx`8!~RZ^BzvBdKq zG>h*cU0rxQ)zq~S&l{!En|R^qa^f-g(edEb*3hWS2aYcbUG>l(!9y~={{7N@+Be^* z(ti8TYiawR5~aVUA0xdha(l*?8(^g>jqq>jzx9fIBj%+S1 zS9I3}-Svp>x~RK8qPri}-H+++kLvD^>F!_E-M^;0AJ^T#uGe#OWa2M8Q9L?6B~38e zpM1nuBM7jG@*5(526Zu3;jN!>jrcDL`3;djJ#And#alk(dcu50I%2(Xa^XG92k}(cbF0N5sC-~AqwF!Mv&u-1`)pUic0TegmRd%iRc#@-%S)}MDPj55gaazzd)2? z9J1b=@5Gq#ctr8=Ku$1XZ0^*2;jtFJ@meo@V;UlTp?zxXK{a_$u4>ZaEjMWW5 zU7O|Yai{c+<6|`&zohSXO5e?Q&Ug7p>XN>3EOsBlXoxRcqy>--;lqxPs>+`bsCtd- zaE)GDy+&KFH8{6wcWK)k+qE5zCT*|As~lfDNW&gay6(hfsa9XB@e$DRbJi7u5ly6y z7NXOPyNDi?|*&wM%-V#jJUrXVuU|jIjIi*PB0?g`x$Ysi2_CZjNnhR9Q8lL z*g^C?$@#}1<_$U!^*1v@|87RuKgfvw=#j`j#?*y+o6eCuRA=EO!!J zV5}y(#B#*>TZ{*YE;GXZ?{hh>Tz|$mNc19OKhaB!xLWa#BXzi+%`zV)`mV$|iSrW4 zVU@cjt_9ZpJjPRULt=|WpTtgyT@r^Sj!V2>VqD^BiFt_+0_!jzXBcsRe2V2q&@Sc} z$LA$~QS!fG#5lYn@gEuQBjO)9SbkG-{((tHo_|=<`F^bF70J0w($OE{=T+2&MRBba z7i#pexJzR!#2uP#^4;0Zh?BL35sRai5oZgkio37a2(Z)QIwtP2yioY=x{k3KzsxaW zf{6116Non|yuMm@b__7?65;|57vd))9Oi`I-`SP;nRY89I!fH>u@K;z2oql1k+1-E zFh|GW)DahVzNGNQU0fb8aSi5}kd2I(kO++k6Kp3VCJsU*!bHH{g;gU$6&L+?F-ONE zWO3JKP!rbJk_qdD=UO?j-d~s5LWcWKjD-~agb{?)O#BTE!c!0&E0V3IY=-LXu ztY??0dLxVUu0Sut3X4)0Ty4i5bX0ng4$~AKF?VIz$Dzml%6%{9GLXZ45Ra<&htTVU z1J<+Uthdd+&qZO6+}Eu_xBrGWPyqh4w;Ncy@eZtuABl zDD*ynvc+j}KYvBB$8(s|QtkaZ^j6Z|VQdI?d}xwLOWC_0dLNSIDlCrgpA>t@inNry zS5bIYH6-(k?M1Os+3|_J3VKV~%Rz4?_P(Ro6MNk<_I?1p_pcznB!aTz6MN+{_Rc|X zCH7ub?1{a08GAomp}o`C*zNclWqX$DzXzeWlKJv&#h%#fmx=Gq721nq5bXHGS+R`0 zJoHu)-`5p;;;fPO9tUDC%>hLEPv{-9iGrU*-rkp3+_Qt|Q`oF{zq0pi?!Tw;sQcu% ba6s;YY;k%H0@Yp}2G!pGa4!>y?bZG_E88@U literal 0 HcmV?d00001 diff --git a/fnet_demos/common/startup/LPC54628/iar/startup_LPC54628.s b/fnet_demos/common/startup/LPC54628/iar/startup_LPC54628.s new file mode 100644 index 00000000..152d64ed --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/iar/startup_LPC54628.s @@ -0,0 +1,615 @@ +;/***************************************************************************** +; * @file: startup_LPC54628.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * LPC54628 +; * @version: 1.2 +; * @date: 2017-6-8 +; *---------------------------------------------------------------------------- +; * +; * Copyright 1997-2016 Freescale Semiconductor, Inc. +; * Copyright 2016-2017 NXP +; * +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0xFFFFFFFF ;ECRP + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ; DMA controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD Reserved47_IRQHandler ; Reserved interrupt + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD RIT_IRQHandler ; Repetitive Interrupt Timer + DCD SPIFI0_IRQHandler ; SPI flash interface + DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM9_IRQHandler ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) + DCD SDIO_IRQHandler ; SD/MMC + DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 + DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 + DCD CAN1_IRQ0_IRQHandler ; CAN1 interrupt0 + DCD CAN1_IRQ1_IRQHandler ; CAN1 interrupt1 + DCD USB1_IRQHandler ; USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ; USB1 activity + DCD ETHERNET_IRQHandler ; Ethernet + DCD ETHERNET_PMT_IRQHandler ; Ethernet power management interrupt + DCD ETHERNET_MACLP_IRQHandler ; Ethernet MAC interrupt + DCD EEPROM_IRQHandler ; EEPROM interrupt + DCD LCD_IRQHandler ; LCD interrupt + DCD SHA_IRQHandler ; SHA interrupt + DCD SMARTCARD0_IRQHandler ; Smart card 0 interrupt + DCD SMARTCARD1_IRQHandler ; Smart card 1 interrupt +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR r0, =SystemInit + BLX r0 + LDR r0, =__iar_program_start + BX r0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + PUBWEAK ADC0_SEQA_IRQHandler + PUBWEAK ADC0_SEQA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQA_IRQHandler + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + PUBWEAK ADC0_SEQB_IRQHandler + PUBWEAK ADC0_SEQB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQB_IRQHandler + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + PUBWEAK ADC0_THCMP_IRQHandler + PUBWEAK ADC0_THCMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_THCMP_IRQHandler + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + PUBWEAK DMIC0_IRQHandler + PUBWEAK DMIC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMIC0_IRQHandler + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + PUBWEAK HWVAD0_IRQHandler + PUBWEAK HWVAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HWVAD0_IRQHandler + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + PUBWEAK Reserved47_IRQHandler + PUBWEAK Reserved47_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved47_IRQHandler + LDR R0, =Reserved47_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + PUBWEAK RIT_IRQHandler + PUBWEAK RIT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RIT_IRQHandler + LDR R0, =RIT_DriverIRQHandler + BX R0 + PUBWEAK SPIFI0_IRQHandler + PUBWEAK SPIFI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPIFI0_IRQHandler + LDR R0, =SPIFI0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM8_IRQHandler + PUBWEAK FLEXCOMM8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM8_IRQHandler + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM9_IRQHandler + PUBWEAK FLEXCOMM9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM9_IRQHandler + LDR R0, =FLEXCOMM9_DriverIRQHandler + BX R0 + PUBWEAK SDIO_IRQHandler + PUBWEAK SDIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SDIO_IRQHandler + LDR R0, =SDIO_DriverIRQHandler + BX R0 + PUBWEAK CAN0_IRQ0_IRQHandler + PUBWEAK CAN0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ0_IRQHandler + LDR R0, =CAN0_IRQ0_DriverIRQHandler + BX R0 + PUBWEAK CAN0_IRQ1_IRQHandler + PUBWEAK CAN0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ1_IRQHandler + LDR R0, =CAN0_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK CAN1_IRQ0_IRQHandler + PUBWEAK CAN1_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ0_IRQHandler + LDR R0, =CAN1_IRQ0_DriverIRQHandler + BX R0 + PUBWEAK CAN1_IRQ1_IRQHandler + PUBWEAK CAN1_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ1_IRQHandler + LDR R0, =CAN1_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK USB1_IRQHandler + PUBWEAK USB1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_IRQHandler + LDR R0, =USB1_DriverIRQHandler + BX R0 + PUBWEAK USB1_NEEDCLK_IRQHandler + PUBWEAK USB1_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_NEEDCLK_IRQHandler + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK ETHERNET_IRQHandler + PUBWEAK ETHERNET_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_IRQHandler + LDR R0, =ETHERNET_DriverIRQHandler + BX R0 + PUBWEAK ETHERNET_PMT_IRQHandler + PUBWEAK ETHERNET_PMT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_PMT_IRQHandler + LDR R0, =ETHERNET_PMT_DriverIRQHandler + BX R0 + PUBWEAK ETHERNET_MACLP_IRQHandler + PUBWEAK ETHERNET_MACLP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_MACLP_IRQHandler + LDR R0, =ETHERNET_MACLP_DriverIRQHandler + BX R0 + PUBWEAK EEPROM_IRQHandler + PUBWEAK EEPROM_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EEPROM_IRQHandler + LDR R0, =EEPROM_DriverIRQHandler + BX R0 + PUBWEAK LCD_IRQHandler + PUBWEAK LCD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LCD_IRQHandler + LDR R0, =LCD_DriverIRQHandler + BX R0 + PUBWEAK SHA_IRQHandler + PUBWEAK SHA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SHA_IRQHandler + LDR R0, =SHA_DriverIRQHandler + BX R0 + PUBWEAK SMARTCARD0_IRQHandler + PUBWEAK SMARTCARD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD0_IRQHandler + LDR R0, =SMARTCARD0_DriverIRQHandler + BX R0 + PUBWEAK SMARTCARD1_IRQHandler + PUBWEAK SMARTCARD1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD1_IRQHandler + LDR R0, =SMARTCARD1_DriverIRQHandler + BX R0 +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +Reserved47_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +RIT_DriverIRQHandler +SPIFI0_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +FLEXCOMM9_DriverIRQHandler +SDIO_DriverIRQHandler +CAN0_IRQ0_DriverIRQHandler +CAN0_IRQ1_DriverIRQHandler +CAN1_IRQ0_DriverIRQHandler +CAN1_IRQ1_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +ETHERNET_DriverIRQHandler +ETHERNET_PMT_DriverIRQHandler +ETHERNET_MACLP_DriverIRQHandler +EEPROM_DriverIRQHandler +LCD_DriverIRQHandler +SHA_DriverIRQHandler +SMARTCARD0_DriverIRQHandler +SMARTCARD1_DriverIRQHandler +DefaultISR + B . + + END diff --git a/fnet_demos/common/startup/LPC54628/pin_mux.c b/fnet_demos/common/startup/LPC54628/pin_mux.c new file mode 100644 index 00000000..51885af1 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/pin_mux.c @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v3.0 +processor: LPC54628J512 +package_id: LPC54628J512ET180 +mcu_data: ksdk2_0 +processor_version: 0.0.4 +pin_labels: +- {pin_num: A14, pin_signal: PIO4_7/CTIMER4_CAP3/USB0_PORTPWRN/USB0_FRAME/SCT0_GPI0, label: PWRON, identifier: PWRON} +- {pin_num: P11, pin_signal: PIO1_22/FC8_RTS_SCL_SSEL1/SD_CMD/CTIMER2_MAT3/SCT0_GPI5/FC4_SSEL3/EMC_CKE(1), label: IRQ, identifier: IRQ} +- {pin_num: A3, pin_signal: PIO3_10/SCT0_OUT3/CTIMER3_MAT0/EMC_DYCSN(1)/TRACEDATA(0), label: PWRON, identifier: PWRON} +- {pin_num: C10, pin_signal: PIO3_2/LCD_VD(16)/FC9_RXD_SDA_MOSI/CTIMER1_MAT2, label: IRQ, identifier: IRQ} +- {pin_num: E3, pin_signal: PIO3_14/SCT0_OUT4/FC9_RTS_SCL_SSEL1/CTIMER3_MAT1/TRACEDATA(2), label: KFFET, identifier: KFFET} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_iocon.h" +#include "pin_mux.h" + + + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: A2, peripheral: FLEXCOMM0, signal: TXD_SCL_MISO, pin_signal: PIO0_30/FC0_TXD_SCL_MISO/CTIMER0_MAT0/SCT0_OUT9/TRACEDATA(1), mode: inactive, invert: disabled, + glitch_filter: disabled, slew_rate: standard, open_drain: disabled} + - {pin_num: B13, peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI/CTIMER2_MAT3/SCT0_OUT8/TRACEDATA(2), mode: inactive, invert: disabled, + glitch_filter: disabled, slew_rate: standard, open_drain: disabled} + - {pin_num: D6, peripheral: FLEXCOMM3, signal: SCK, pin_signal: PIO0_0/CAN1_RD/FC3_SCK/CTIMER0_MAT0/SCT0_GPI0/PDM0_CLK, mode: pullUp, invert: disabled, glitch_filter: disabled, + slew_rate: standard, open_drain: disabled} + - {pin_num: A1, peripheral: FLEXCOMM3, signal: CTS_SDA_SSEL0, pin_signal: PIO0_1/CAN1_TD/FC3_CTS_SDA_SSEL0/CTIMER0_CAP0/SCT0_GPI1/PDM0_DATA, mode: pullUp, invert: disabled, + glitch_filter: disabled, slew_rate: standard, open_drain: disabled} + - {pin_num: E9, peripheral: FLEXCOMM3, signal: TXD_SCL_MISO, pin_signal: PIO0_2/FC3_TXD_SCL_MISO/CTIMER0_CAP1/SCT0_OUT0/SCT0_GPI2/EMC_D(0), mode: pullUp, invert: disabled, + glitch_filter: disabled, slew_rate: standard, open_drain: disabled} + - {pin_num: A10, peripheral: FLEXCOMM3, signal: RXD_SDA_MOSI, pin_signal: PIO0_3/FC3_RXD_SDA_MOSI/CTIMER0_MAT1/SCT0_OUT1/SCT0_GPI3/EMC_D(1), mode: pullUp, invert: disabled, + glitch_filter: disabled, slew_rate: standard, open_drain: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Core #0 (ARM Cortex-M4) */ +void BOARD_InitPins(void) +{ + /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin0_config = (/* Pin is configured as FC3_SCK */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN0 (coords: D6) is configured as FC3_SCK */ + IOCON_PinMuxSet(IOCON, 0U, 0U, port0_pin0_config); + + const uint32_t port0_pin1_config = (/* Pin is configured as FC3_CTS_SDA_SSEL0 */ + IOCON_PIO_FUNC2 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN1 (coords: A1) is configured as FC3_CTS_SDA_SSEL0 */ + IOCON_PinMuxSet(IOCON, 0U, 1U, port0_pin1_config); + + const uint32_t port0_pin2_config = (/* Pin is configured as FC3_TXD_SCL_MISO */ + IOCON_PIO_FUNC1 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN2 (coords: E9) is configured as FC3_TXD_SCL_MISO */ + IOCON_PinMuxSet(IOCON, 0U, 2U, port0_pin2_config); + + const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: B13) is configured as FC0_RXD_SDA_MOSI */ + IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config); + + const uint32_t port0_pin3_config = (/* Pin is configured as FC3_RXD_SDA_MOSI */ + IOCON_PIO_FUNC1 | + /* Selects pull-up function */ + IOCON_PIO_MODE_PULLUP | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN3 (coords: A10) is configured as FC3_RXD_SDA_MOSI */ + IOCON_PinMuxSet(IOCON, 0U, 3U, port0_pin3_config); + + const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: A2) is configured as FC0_TXD_SCL_MISO */ + IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitGT202Shield: +- options: {coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: N2, peripheral: FLEXCOMM9, signal: SCK, pin_signal: PIO3_20/FC9_SCK/SD_CARD_INT_N/CLKOUT/SCT0_OUT7} + - {pin_num: N5, peripheral: FLEXCOMM9, signal: TXD_SCL_MISO, pin_signal: PIO3_22/FC9_TXD_SCL_MISO/ADC0_10} + - {pin_num: P5, peripheral: FLEXCOMM9, signal: RXD_SDA_MOSI, pin_signal: PIO3_21/FC9_RXD_SDA_MOSI/SD_BACKEND_PWR/CTIMER4_MAT3/UTICK_CAP2/ADC0_9} + - {pin_num: K13, peripheral: FLEXCOMM9, signal: CTS_SDA_SSEL0, pin_signal: PIO3_30/FC9_CTS_SDA_SSEL0/SCT0_OUT4/FC4_SSEL2/EMC_A(19)} + - {pin_num: A14, peripheral: GPIO, signal: 'PIO4, 7', pin_signal: PIO4_7/CTIMER4_CAP3/USB0_PORTPWRN/USB0_FRAME/SCT0_GPI0, direction: OUTPUT, mode: pullDown, invert: disabled} + - {pin_num: P11, peripheral: GPIO, signal: 'PIO1, 22', pin_signal: PIO1_22/FC8_RTS_SCL_SSEL1/SD_CMD/CTIMER2_MAT3/SCT0_GPI5/FC4_SSEL3/EMC_CKE(1), direction: INPUT, + mode: pullUp, invert: disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitGT202Shield + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Core #0 (ARM Cortex-M4) */ +void BOARD_InitGT202Shield(void) +{ + /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + CLOCK_EnableClock(kCLOCK_Iocon); + + IOCON->PIO[1][22] = + ((IOCON->PIO[1][22] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_INVERT_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function.: PORT122 (pin P11) is configured as PIO1_22 */ + | IOCON_PIO_FUNC(PIO122_FUNC_ALT0) + + /* Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ + | IOCON_PIO_MODE(PIO122_MODE_PULL_UP) + + /* Input polarity.: Disabled. Input function is not inverted. */ + | IOCON_PIO_INVERT(PIO122_INVERT_DISABLED) + + /* Select Analog/Digital mode.: Digital mode. */ + | IOCON_PIO_DIGIMODE(PIO122_DIGIMODE_DIGITAL)); + + IOCON->PIO[3][20] = ((IOCON->PIO[3][20] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function.: PORT320 (pin N2) is configured as FC9_SCK */ + | IOCON_PIO_FUNC(PIO320_FUNC_ALT1) + + /* Select Analog/Digital mode.: Digital mode. */ + | IOCON_PIO_DIGIMODE(PIO320_DIGIMODE_DIGITAL)); + + IOCON->PIO[3][21] = ((IOCON->PIO[3][21] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function.: PORT321 (pin P5) is configured as FC9_RXD_SDA_MOSI */ + | IOCON_PIO_FUNC(PIO321_FUNC_ALT1) + + /* Select Analog/Digital mode.: Digital mode. */ + | IOCON_PIO_DIGIMODE(PIO321_DIGIMODE_DIGITAL)); + + IOCON->PIO[3][22] = ((IOCON->PIO[3][22] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function.: PORT322 (pin N5) is configured as FC9_TXD_SCL_MISO */ + | IOCON_PIO_FUNC(PIO322_FUNC_ALT1) + + /* Select Analog/Digital mode.: Digital mode. */ + | IOCON_PIO_DIGIMODE(PIO322_DIGIMODE_DIGITAL)); + + IOCON->PIO[3][30] = ((IOCON->PIO[3][30] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function.: PORT330 (pin K13) is configured as FC9_CTS_SDA_SSEL0 */ + | IOCON_PIO_FUNC(PIO330_FUNC_ALT1) + + /* Select Analog/Digital mode.: Digital mode. */ + | IOCON_PIO_DIGIMODE(PIO330_DIGIMODE_DIGITAL)); + + IOCON->PIO[4][7] = + ((IOCON->PIO[4][7] & + /* Mask bits to zero which are setting */ + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_MODE_MASK | IOCON_PIO_INVERT_MASK | IOCON_PIO_DIGIMODE_MASK))) + + /* Selects pin function.: PORT47 (pin A14) is configured as PIO4_7 */ + | IOCON_PIO_FUNC(PIO47_FUNC_ALT0) + + /* Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-down. Pull-down resistor enabled. */ + | IOCON_PIO_MODE(PIO47_MODE_PULL_DOWN) + + /* Input polarity.: Disabled. Input function is not inverted. */ + | IOCON_PIO_INVERT(PIO47_INVERT_DISABLED) + + /* Select Analog/Digital mode.: Digital mode. */ + | IOCON_PIO_DIGIMODE(PIO47_DIGIMODE_DIGITAL)); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/fnet_demos/common/startup/LPC54628/pin_mux.h b/fnet_demos/common/startup/LPC54628/pin_mux.h new file mode 100644 index 00000000..993e3aa9 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/pin_mux.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */ +#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */ +#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */ +#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */ +#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 7 */ +#define IOCON_PIO_INPFILT_OFF 0x0200u /*!<@brief Input filter disabled */ +#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */ +#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */ +#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */ +#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */ +#define IOCON_PIO_SLEW_FAST 0x0400u /*!<@brief Fast mode, slew rate control is disabled */ +#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M4F */ + +/*! + * @brief Select Analog/Digital mode.: Digital mode. */ +#define PIO122_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO122_FUNC_ALT0 0x00u +/*! + * @brief Input polarity.: Disabled. Input function is not inverted. */ +#define PIO122_INVERT_DISABLED 0x00u +/*! + * @brief Selects function mode (on-chip pull-up/pull-down resistor control).: Pull-up. Pull-up resistor enabled. */ +#define PIO122_MODE_PULL_UP 0x02u +/*! + * @brief Select Analog/Digital mode.: Digital mode. */ +#define PIO320_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 1. */ +#define PIO320_FUNC_ALT1 0x01u +/*! + * @brief Select Analog/Digital mode.: Digital mode. */ +#define PIO321_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 1. */ +#define PIO321_FUNC_ALT1 0x01u +/*! + * @brief Select Analog/Digital mode.: Digital mode. */ +#define PIO322_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 1. */ +#define PIO322_FUNC_ALT1 0x01u +/*! + * @brief Select Analog/Digital mode.: Digital mode. */ +#define PIO330_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 1. */ +#define PIO330_FUNC_ALT1 0x01u +/*! + * @brief Select Analog/Digital mode.: Digital mode. */ +#define PIO47_DIGIMODE_DIGITAL 0x01u +/*! + * @brief Selects pin function.: Alternative connection 0. */ +#define PIO47_FUNC_ALT0 0x00u +/*! + * @brief Input polarity.: Disabled. Input function is not inverted. */ +#define PIO47_INVERT_DISABLED 0x00u +/*! + * @brief + * Selects function mode (on-chip pull-up/pull-down resistor control). + * : Pull-down. + * Pull-down resistor enabled. + */ +#define PIO47_MODE_PULL_DOWN 0x01u + +/*! @name PIO4_7 (coord A14), PWRON + @{ */ +#define BOARD_INITGT202SHIELD_PWRON_PERIPHERAL GPIO /*!<@brief Device name: GPIO */ +#define BOARD_INITGT202SHIELD_PWRON_SIGNAL PIO4 /*!<@brief GPIO signal: PIO4 */ +#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO /*!<@brief GPIO device name: GPIO */ +#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 7U /*!<@brief PIO4 pin index: 7 */ +#define BOARD_INITGT202SHIELD_PWRON_PORT 4U /*!<@brief PORT device name: 4U */ +#define BOARD_INITGT202SHIELD_PWRON_PIN 7U /*!<@brief 4U pin index: 7 */ +#define BOARD_INITGT202SHIELD_PWRON_CHANNEL 7 /*!<@brief GPIO PIO4 channel: 7 */ +#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME PIO4_7 /*!<@brief Pin name */ +#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!<@brief Label */ +#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!<@brief Identifier name */ +#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kPIN_MUX_DirectionOutput /*!<@brief Direction */ + /* @} */ + +/*! @name PIO1_22 (coord P11), IRQ + @{ */ +#define BOARD_INITGT202SHIELD_IRQ_PERIPHERAL GPIO /*!<@brief Device name: GPIO */ +#define BOARD_INITGT202SHIELD_IRQ_SIGNAL PIO1 /*!<@brief GPIO signal: PIO1 */ +#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO /*!<@brief GPIO device name: GPIO */ +#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 22U /*!<@brief PIO1 pin index: 22 */ +#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!<@brief PORT device name: 1U */ +#define BOARD_INITGT202SHIELD_IRQ_PIN 22U /*!<@brief 1U pin index: 22 */ +#define BOARD_INITGT202SHIELD_IRQ_CHANNEL 22 /*!<@brief GPIO PIO1 channel: 22 */ +#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME PIO1_22 /*!<@brief Pin name */ +#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!<@brief Label */ +#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!<@brief Identifier name */ +#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kPIN_MUX_DirectionInput /*!<@brief Direction */ + /* @} */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitGT202Shield(void); /* Function assigned for the Cortex-M4F */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/fnet_demos/common/startup/LPC54628/system_LPC54628.c b/fnet_demos/common/startup/LPC54628/system_LPC54628.c new file mode 100644 index 00000000..1477bf8e --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/system_LPC54628.c @@ -0,0 +1,363 @@ +/* +** ################################################################### +** Processor: LPC54628J512ET180 +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 +** Version: rev. 1.2, 2017-06-08 +** Build: b170609 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-08-12) +** Initial version. +** - rev. 1.1 (2016-11-25) +** Update CANFD and Classic CAN register. +** Add MAC TIMERSTAMP registers. +** - rev. 1.2 (2017-06-08) +** Remove RTC_CTRL_RTC_OSC_BYPASS. +** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. +** Remove RESET and HALT from SYSCON_AHBCLKDIV. +** +** ################################################################### +*/ + +/*! + * @file LPC54628 + * @version 1.2 + * @date 2017-06-08 + * @brief Device specific configuration file for LPC54628 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#define NVALMAX (0x100) +#define PVALMAX (0x20) +#define MVALMAX (0x8000) +#define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */ +#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P) +#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) + +extern void *__Vectors; + +static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, + 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; +/* Get WATCH DOG Clk */ +static uint32_t getWdtOscFreq(void) +{ + uint8_t freq_sel, div_sel; + if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) + { + return 0U; + } + else + { + div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1; + freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; + return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); + } +} +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC) +{ + uint32_t n, x, i; + + /* Find NDec */ + switch (NDEC) + { + case 0x3FF: + n = 0; + break; + case 0x302: + n = 1; + break; + case 0x202: + n = 2; + break; + default: + x = 0x080; + n = 0xFFFFFFFFU; + for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); + if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) + { + /* Decoded value of NDEC */ + n = i; + } + } + break; + } + return n; +} + +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC) +{ + uint32_t p, x, i; + /* Find PDec */ + switch (PDEC) + { + case 0x7F: + p = 0; + break; + case 0x62: + p = 1; + break; + case 0x42: + p = 2; + break; + default: + x = 0x10; + p = 0xFFFFFFFFU; + for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xFU); + if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) + { + /* Decoded value of PDEC */ + p = i; + } + } + break; + } + return p; +} + +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC) +{ + uint32_t m, i, x; + + /* Find MDec */ + switch (MDEC) + { + case 0x1FFFF: + m = 0; + break; + case 0x18003: + m = 1; + break; + case 0x10003: + m = 2; + break; + default: + x = 0x04000; + m = 0xFFFFFFFFU; + for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFFU); + if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC) + { + /* Decoded value of MDEC */ + m = i; + } + } + break; + } + return m; +} + +/* Get predivider (N) from PLL NDEC setting */ +static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0) + { + /* Decode NDEC value to get (N) pre divider */ + preDiv = pllDecodeN(nDecReg & 0x3FF); + if (preDiv == 0) + { + preDiv = 1; + } + } + /* Adjusted by 1, directi is used to bypass */ + return preDiv; +} + +/* Get postdivider (P) from PLL PDEC setting */ +static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) +{ + uint32_t postDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0) + { + /* Decode PDEC value to get (P) post divider */ + postDiv = 2 * pllDecodeP(pDecReg & 0x7F); + if (postDiv == 0) + { + postDiv = 2; + } + } + /* Adjusted by 1, directo is used to bypass */ + return postDiv; +} + +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) +{ + uint32_t mMult = 1; + + /* Decode MDEC value to get (M) multiplier */ + mMult = pllDecodeM(mDecReg & 0x1FFFF); + if (mMult == 0) + { + mMult = 1; + } + return mMult; +} + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + SYSCON->ARMTRACECLKDIV = 0; +/* Optionally enable RAM banks that may be off by default at reset */ +#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK; +#endif +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { +uint32_t clkRate = 0; + uint32_t prediv, postdiv; + uint64_t workRate; + + switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) + { + case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ + switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLK_FRO_12MHZ; + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLK_CLK_IN; + break; + case 0x02: /* Watchdog oscillator (wdt_clk) */ + clkRate = getWdtOscFreq(); + break; + default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */ + if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) + { + clkRate = CLK_FRO_96MHZ; + } + else + { + clkRate = CLK_FRO_48MHZ; + } + break; + } + break; + case 0x02: /* System PLL clock (pll_clk)*/ + switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLK_FRO_12MHZ; + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLK_CLK_IN; + break; + case 0x02: /* Watchdog oscillator (wdt_clk) */ + clkRate = getWdtOscFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLK_RTC_32K_CLK; + break; + default: + break; + } + if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0) + { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC); + postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC); + /* Adjust input clock */ + clkRate = clkRate / prediv; + + /* MDEC used for rate */ + workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC); + clkRate = workRate / ((uint64_t)postdiv); + clkRate = workRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */ + } + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLK_RTC_32K_CLK; + break; + default: + break; + } + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); +} diff --git a/fnet_demos/common/startup/LPC54628/system_LPC54628.h b/fnet_demos/common/startup/LPC54628/system_LPC54628.h new file mode 100644 index 00000000..d4927415 --- /dev/null +++ b/fnet_demos/common/startup/LPC54628/system_LPC54628.h @@ -0,0 +1,123 @@ +/* +** ################################################################### +** Processor: LPC54628J512ET180 +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 +** Version: rev. 1.2, 2017-06-08 +** Build: b170609 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-08-12) +** Initial version. +** - rev. 1.1 (2016-11-25) +** Update CANFD and Classic CAN register. +** Add MAC TIMERSTAMP registers. +** - rev. 1.2 (2017-06-08) +** Remove RTC_CTRL_RTC_OSC_BYPASS. +** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. +** Remove RESET and HALT from SYSCON_AHBCLKDIV. +** +** ################################################################### +*/ + +/*! + * @file LPC54628 + * @version 1.2 + * @date 2017-06-08 + * @brief Device specific configuration file for LPC54628 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC54628_H_ +#define _SYSTEM_LPC54628_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ +#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC54628_H_ */ diff --git a/fnet_demos/common/startup/MK60D10/gcc/MK60DN512xxx10_flash_fnet_boot.ld b/fnet_demos/common/startup/MK60D10/gcc/MK60DN512xxx10_flash_fnet_boot.ld index 1254c210..59d16421 100644 --- a/fnet_demos/common/startup/MK60D10/gcc/MK60DN512xxx10_flash_fnet_boot.ld +++ b/fnet_demos/common/startup/MK60D10/gcc/MK60DN512xxx10_flash_fnet_boot.ld @@ -57,9 +57,9 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x0000D000, LENGTH = 0x00000400 /* 52KB reserved for FNET bootloader.*/ - m_flash_config (RX) : ORIGIN = 0x0000D400, LENGTH = 0x00000010 - m_text (RX) : ORIGIN = 0x0000D410, LENGTH = 0x000723F0 /* Original 0x0007FBF0/7F3F0 */ + m_interrupts (RX) : ORIGIN = 0x0000F000, LENGTH = 0x00000400 /* 60KB reserved for FNET bootloader.*/ + m_flash_config (RX) : ORIGIN = 0x0000F400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x0000F410, LENGTH = 0x000703F0 /* Original 0x0007FBF0/7F3F0 */ fapp_paramsrom (RW) : ORIGIN = 0x0007F800, LENGTH = 0x00000800 /*!!! 2KBytes = Last logical-block reserved for FNET params.*/ m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00010000 diff --git a/fnet_demos/common/startup/MK60D10/iar/MK60DN512xxx10_flash_fnet_boot.icf b/fnet_demos/common/startup/MK60D10/iar/MK60DN512xxx10_flash_fnet_boot.icf index 156a1e99..20062973 100644 --- a/fnet_demos/common/startup/MK60D10/iar/MK60DN512xxx10_flash_fnet_boot.icf +++ b/fnet_demos/common/startup/MK60D10/iar/MK60DN512xxx10_flash_fnet_boot.icf @@ -47,7 +47,7 @@ ** ################################################################### */ -define symbol __flash_offset__ = 0x0000D000; //52KB reserved for FNET bootloader. +define symbol __flash_offset__ = 0x0000F000; //60KB reserved for FNET bootloader. define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; diff --git a/fnet_demos/common/startup/MK64F12/gcc/MK64FN1M0xxx12_flash_fnet_boot.ld b/fnet_demos/common/startup/MK64F12/gcc/MK64FN1M0xxx12_flash_fnet_boot.ld index d92ff75b..211ddfce 100644 --- a/fnet_demos/common/startup/MK64F12/gcc/MK64FN1M0xxx12_flash_fnet_boot.ld +++ b/fnet_demos/common/startup/MK64F12/gcc/MK64FN1M0xxx12_flash_fnet_boot.ld @@ -58,9 +58,9 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x0000D000, LENGTH = 0x00000400 /* 52KB reserved for FNET bootloader.*/ - m_flash_config (RX) : ORIGIN = 0x0000D400, LENGTH = 0x00000010 - m_text (RX) : ORIGIN = 0x0000D410, LENGTH = 0x000F1BF0 /* Original 0x000FFBF0/FEBF0 */ + m_interrupts (RX) : ORIGIN = 0x0000F000, LENGTH = 0x00000400 /* 60KB reserved for FNET bootloader.*/ + m_flash_config (RX) : ORIGIN = 0x0000F400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x0000F410, LENGTH = 0x000D1BF0 /* Original 0x000FFBF0/FEBF0 */ fapp_paramsrom (RW) : ORIGIN = 0x000FF000, LENGTH = 0x00001000 /*!!! 4KBytes = Last logical-block reserved for FNET params.*/ m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 diff --git a/fnet_demos/common/startup/MK64F12/iar/MK64FN1M0xxx12_flash_fnet_boot.icf b/fnet_demos/common/startup/MK64F12/iar/MK64FN1M0xxx12_flash_fnet_boot.icf index 84366919..734e1a39 100644 --- a/fnet_demos/common/startup/MK64F12/iar/MK64FN1M0xxx12_flash_fnet_boot.icf +++ b/fnet_demos/common/startup/MK64F12/iar/MK64FN1M0xxx12_flash_fnet_boot.icf @@ -48,7 +48,7 @@ ** ################################################################### */ -define symbol __flash_offset__ = 0x0000D000; //52KB reserved for FNET bootloader. +define symbol __flash_offset__ = 0x0000F000; //60KB reserved for FNET bootloader. define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; diff --git a/fnet_demos/common/startup/MK66F18/gcc/MK66FN2M0xxx18_flash_fnet_boot.ld b/fnet_demos/common/startup/MK66F18/gcc/MK66FN2M0xxx18_flash_fnet_boot.ld index eb48f677..df143525 100644 --- a/fnet_demos/common/startup/MK66F18/gcc/MK66FN2M0xxx18_flash_fnet_boot.ld +++ b/fnet_demos/common/startup/MK66F18/gcc/MK66FN2M0xxx18_flash_fnet_boot.ld @@ -55,9 +55,9 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x0000D000, LENGTH = 0x00000400 /* 52KB reserved for FNET bootloader.*/ - m_flash_config (RX) : ORIGIN = 0x0000D400, LENGTH = 0x00000010 - m_text (RX) : ORIGIN = 0x0000D410, LENGTH = 0x000F1BF0 /* Original 0x001FFBF0/1FEBF0 */ + m_interrupts (RX) : ORIGIN = 0x0000F000, LENGTH = 0x00000400 /* 60KB reserved for FNET bootloader.*/ + m_flash_config (RX) : ORIGIN = 0x0000F400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x0000F410, LENGTH = 0x000D1BF0 /* Original 0x001FFBF0/1FEBF0 */ fapp_paramsrom (RW) : ORIGIN = 0x001FF000, LENGTH = 0x00001000 /*!!! 4KBytes = Last logical-block reserved for FNET params.*/ m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 diff --git a/fnet_demos/common/startup/MK66F18/iar/MK66FN2M0xxx18_flash_fnet_boot.icf b/fnet_demos/common/startup/MK66F18/iar/MK66FN2M0xxx18_flash_fnet_boot.icf index 05ba0a86..6e057adb 100644 --- a/fnet_demos/common/startup/MK66F18/iar/MK66FN2M0xxx18_flash_fnet_boot.icf +++ b/fnet_demos/common/startup/MK66F18/iar/MK66FN2M0xxx18_flash_fnet_boot.icf @@ -45,7 +45,7 @@ ** ################################################################### */ -define symbol __flash_offset__ = 0x0000D000; //52KB reserved for FNET bootloader. +define symbol __flash_offset__ = 0x0000F000; //60KB reserved for FNET bootloader. define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; diff --git a/fnet_demos/src/bench/fnet_user_config.h b/fnet_demos/src/bench/fnet_user_config.h index 18d0a2ca..3fcdd57c 100644 --- a/fnet_demos/src/bench/fnet_user_config.h +++ b/fnet_demos/src/bench/fnet_user_config.h @@ -97,8 +97,4 @@ #define FNET_CFG_BENCH_SRV (1) #define FNET_CFG_BENCH_CLN (1) -#define FNET_CFG_DEBUG_BENCH_SRV 1 //DM -#define FNET_CFG_DEBUG_BENCH_CLN 1 //DM -#define FNET_CFG_DEBUG 1 - #endif /* _FNET_USER_CONFIG_H_ */ diff --git a/fnet_demos/src/bench/main.c b/fnet_demos/src/bench/main.c index d1e81849..bc026bd0 100644 --- a/fnet_demos/src/bench/main.c +++ b/fnet_demos/src/bench/main.c @@ -5,11 +5,8 @@ int main (void) { - /* Init UART. */ - fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200u); - - /* Enable Interrupts.*/ - fnet_cpu_irq_enable(0u); + /* Board-specific HW initialization. Default serial port initialization. Interrupt enabling. */ + fapp_hw_init(); /* Run application. */ fapp_main(); diff --git a/fnet_demos/src/boot/fapp_user_config.h b/fnet_demos/src/boot/fapp_user_config.h index 00a08572..1811f056 100644 --- a/fnet_demos/src/boot/fapp_user_config.h +++ b/fnet_demos/src/boot/fapp_user_config.h @@ -12,8 +12,9 @@ #define _FAPP_USER_CONFIG_H_ -#define FAPP_CFG_BOOTLOADER_SIZE (52*1024) /* First 52 KBs of FLASH are reserved by - * the Bootloader application.*/ +#define FAPP_CFG_BOOTLOADER_SIZE (60*1024) /* First 52 KBs of FLASH are reserved by the Bootloader application. + * This value must be dividable by FNET_CFG_CPU_FLASH_PAGE_SIZE. + * On any change, must be updated the linker file of shell_boot application. */ #define FAPP_CFG_NAME "FNET Bootloader" #define FAPP_CFG_SHELL_PROMPT "BOOT> " diff --git a/fnet_demos/src/boot/main.c b/fnet_demos/src/boot/main.c index 3015b30c..07f3fa53 100644 --- a/fnet_demos/src/boot/main.c +++ b/fnet_demos/src/boot/main.c @@ -5,11 +5,8 @@ int main (void) { - /* Init UART. */ - fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200u); - - /* Enable Interrupts.*/ - fnet_cpu_irq_enable(0u); + /* Board-specific HW initialization. Default serial port initialization. Interrupt enabling. */ + fapp_hw_init(); /* Run application. */ fapp_main(); diff --git a/fnet_demos/src/shell/fnet_user_config.h b/fnet_demos/src/shell/fnet_user_config.h index 968858fb..bfb6e5ac 100644 --- a/fnet_demos/src/shell/fnet_user_config.h +++ b/fnet_demos/src/shell/fnet_user_config.h @@ -78,7 +78,7 @@ #define FNET_CFG_TELNET (1) /***************************************************************************** -* Flash Module driver support. It is valid only if a platform-specific +* Flash Module driver support. It is valid only if a platform-specific * Flash driver is availble (FNET_CFG_CPU_FLASH). ******************************************************************************/ #define FNET_CFG_FLASH (1) @@ -114,4 +114,8 @@ ******************************************************************************/ #define FNET_CFG_LINK (1) + +//DM +#define FNET_CFG_CPU_ETH_ATONEGOTIATION_TIMEOUT (20000U) /*ms*/ + #endif /* _FNET_USER_CONFIG_H_ */ diff --git a/fnet_demos/src/shell/main.c b/fnet_demos/src/shell/main.c index 3015b30c..07f3fa53 100644 --- a/fnet_demos/src/shell/main.c +++ b/fnet_demos/src/shell/main.c @@ -5,11 +5,8 @@ int main (void) { - /* Init UART. */ - fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200u); - - /* Enable Interrupts.*/ - fnet_cpu_irq_enable(0u); + /* Board-specific HW initialization. Default serial port initialization. Interrupt enabling. */ + fapp_hw_init(); /* Run application. */ fapp_main(); diff --git a/fnet_demos/src/shell_boot/main.c b/fnet_demos/src/shell_boot/main.c index ab43f8a8..14c29101 100644 --- a/fnet_demos/src/shell_boot/main.c +++ b/fnet_demos/src/shell_boot/main.c @@ -1,15 +1,16 @@ #include "fapp.h" +#if !FNET_CFG_CPU_VECTOR_TABLE_IS_IN_RAM + #warning For the shell_boot application the vector table must be in RAM. +#endif + /********************************************************************/ -fnet_int32_t main (void) +int main (void) { - /* Init UART. */ - fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200u); - - /* Enable Interrupts.*/ - fnet_cpu_irq_enable(0u); + /* Board-specific HW initialization. Default serial port initialization. Interrupt enabling. */ + fapp_hw_init(); /* Run application. */ fapp_main(); diff --git a/fnet_demos/src/shell_freertos/main.c b/fnet_demos/src/shell_freertos/main.c index 43e6a8a4..f3c07b2e 100644 --- a/fnet_demos/src/shell_freertos/main.c +++ b/fnet_demos/src/shell_freertos/main.c @@ -5,11 +5,8 @@ int main (void) { - /* Init UART. */ - fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200u); - - /* Enable Interrupts.*/ - fnet_cpu_irq_enable(0u); + /* Board-specific HW initialization. Default serial port initialization. Interrupt enabling. */ + fapp_hw_init(); /* Run application. */ fapp_main_freertos(); diff --git a/fnet_demos/src/shell_freertos_wifi_qca/main.c b/fnet_demos/src/shell_freertos_wifi_qca/main.c index d6849dac..f3c07b2e 100644 --- a/fnet_demos/src/shell_freertos_wifi_qca/main.c +++ b/fnet_demos/src/shell_freertos_wifi_qca/main.c @@ -5,17 +5,8 @@ int main (void) { -#if FNET_MK /* Board specific initialization */ - #include "clock_config.h" - /* Init clock to run mode */ - BOARD_BootClockRUN(); -#endif - - /* Init UART. */ - fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200u); - - /* Enable Interrupts.*/ - fnet_cpu_irq_enable(0u); + /* Board-specific HW initialization. Default serial port initialization. Interrupt enabling. */ + fapp_hw_init(); /* Run application. */ fapp_main_freertos(); diff --git a/fnet_demos/src/shell_mbedtls/main.c b/fnet_demos/src/shell_mbedtls/main.c index 3015b30c..07f3fa53 100644 --- a/fnet_demos/src/shell_mbedtls/main.c +++ b/fnet_demos/src/shell_mbedtls/main.c @@ -5,11 +5,8 @@ int main (void) { - /* Init UART. */ - fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200u); - - /* Enable Interrupts.*/ - fnet_cpu_irq_enable(0u); + /* Board-specific HW initialization. Default serial port initialization. Interrupt enabling. */ + fapp_hw_init(); /* Run application. */ fapp_main(); diff --git a/fnet_demos/src/test_ip6/fapp_user_config.h b/fnet_demos/src/test_ip6/fapp_user_config.h deleted file mode 100644 index 8300a637..00000000 --- a/fnet_demos/src/test_ip6/fapp_user_config.h +++ /dev/null @@ -1,70 +0,0 @@ -/**********************************************************************/ /*! -* -* @file fapp_user_config.h -* -* @brief FNET Application User configuration file. -* It should be used to change any default configuration parameter of FAPP. -* -***************************************************************************/ - -#ifndef _FAPP_USER_CONFIG_H_ - -#define _FAPP_USER_CONFIG_H_ - -#define FAPP_CFG_NAME "FNET Shell Application" -#define FAPP_CFG_SHELL_PROMPT "shell> \r\n shell>" - -/* "dhcpc" command.*/ -//#define FAPP_CFG_DHCPC_CMD (1) -//#define FAPP_CFG_DHCPC_CMD_DISCOVER_MAX (5) - -/* "set/get" command.*/ -#define FAPP_CFG_SETGET_CMD_IP (1) -#define FAPP_CFG_SETGET_CMD_GATEWAY (1) -#define FAPP_CFG_SETGET_CMD_NETMASK (1) -#define FAPP_CFG_SETGET_CMD_MAC (1) -#define FAPP_CFG_SETGET_CMD_DNS (1) - -/* "info" command. */ -#define FAPP_CFG_INFO_CMD (1) - -/* "http" command.*/ -//#define FAPP_CFG_HTTP_CMD (1) - -/* "exp" command.*/ -//#define FAPP_CFG_EXP_CMD (1) - -/* "save" command.*/ -//#define FAPP_CFG_SAVE_CMD (1) - -/* "reset" command.*/ -#define FAPP_CFG_REBOOT_CMD (1) - -/* "telnet" command.*/ -//#define FAPP_CFG_TELNET_CMD (1) - -/* "dns" command.*/ -//#define FAPP_CFG_DNS_CMD (1) - -/* "ping6" command.*/ -#define FAPP_CFG_PING6_CMD (1) -#define FAPP_CFG_SHELL_MAX_LINE_LENGTH (70) - -#define FAPP_CFG_BIND_CMD (1) -#define FAPP_CFG_UNBIND_CMD (1) - -/* Reading of the configuration parameters from the Flash - * memory during the application bootup.*/ -//#define FAPP_CFG_PARAMS_READ_FLASH (1) - -/* Rewriting of the configuration parameters in the Flash - * memory duiring flashing of the application. */ -//#define FAPP_CFG_PARAMS_REWRITE_FLASH (1) - -//DM -#if 0 /* To run HTTP and Telnet server on startup set to 1. */ - #define FAPP_CFG_STARTUP_SCRIPT "bind fe80::1111" -#endif - -#endif /* _FAPP_USER_CONFIG_H_ */ - diff --git a/fnet_demos/src/test_ip6/fnet_user_config.h b/fnet_demos/src/test_ip6/fnet_user_config.h deleted file mode 100644 index b4df6a71..00000000 --- a/fnet_demos/src/test_ip6/fnet_user_config.h +++ /dev/null @@ -1,112 +0,0 @@ -/**********************************************************************/ /*! -* -* @file fnet_user_config.h -* -* @brief FNET User configuration file. -* It should be used to change any default configuration parameter. -* -***************************************************************************/ - -#ifndef _FNET_USER_CONFIG_H_ - -#define _FNET_USER_CONFIG_H_ - - -/***************************************************************************** -* Compiler support FNET_CFG_COMP_ is defined in project options. -******************************************************************************/ -/***************************************************************************** -* Processor type FNET_CFG_CPU_ is defined in project options. -******************************************************************************/ -/***************************************************************************** -* Default serial port number FNET_CFG_CPU_SERIAL_PORT_DEFAULT is defined -* in project options. -******************************************************************************/ - -/***************************************************************************** -* IPv4 and/or IPv6 protocol support. -******************************************************************************/ -#define FNET_CFG_IP4 (0) -#define FNET_CFG_IP6 (1) - -/***************************************************************************** -* IP address for the Ethernet interface. -* At runtime it can be changed by the fnet_netif_set_ip4_addr() or -* by the DHCP client service. -******************************************************************************/ -#define FNET_CFG_ETH0_IP4_ADDR (FNET_IP4_ADDR_INIT(192U, 168U, 0U, 22U)) - -/***************************************************************************** -* IP Subnet mask for the Ethernet interface. -* At runtime it can be changed by the fnet_netif_set_ip4_subnet_mask() or -* by the DHCP client service. -******************************************************************************/ -#define FNET_CFG_ETH0_IP4_MASK (FNET_IP4_ADDR_INIT(255U, 255U, 255U, 0U)) - -/***************************************************************************** -* Gateway IP address for the Ethernet interface. -* At runtime it can be changed by the fnet_netif_set_ip4_gateway() or -* by the DHCP client service. -******************************************************************************/ -#define FNET_CFG_ETH0_IP4_GW (FNET_IP4_ADDR_INIT(0U, 0U, 0U, 0U)) - -/***************************************************************************** -* DNS server IP address for the Ethernet interface. -* At runtime it can be changed by the fnet_netif_set_ip4_dns() or -* by the DHCP client service. -* It is used only if FNET_CFG_DNS is set to 1. -******************************************************************************/ -#define FNET_CFG_ETH0_IP4_DNS (FNET_IP4_ADDR_INIT(0U, 0U, 0U, 0U)) - -/***************************************************************************** -* TCP protocol support. -* You can disable it to save a substantial amount of code if -* your application only needs UDP. By default it is enabled. -******************************************************************************/ -#define FNET_CFG_TCP (1) - -/***************************************************************************** -* UDP protocol support. -* You can disable it to save a some amount of code if your -* application only needs TCP. By default it is enabled. -******************************************************************************/ -#define FNET_CFG_UDP (1) - -/***************************************************************************** -* UDP checksum. -* If enabled, the UDP checksum will be generated for transmitted -* datagrams and be verified on received UDP datagrams. -* You can disable it to speedup UDP applications. -* By default it is enabled. -******************************************************************************/ -#define FNET_CFG_UDP_CHECKSUM (1) - -/***************************************************************************** -* IP fragmentation. -* If the IP fragmentation is enabled, the IP will attempt to reassemble IP -* packet fragments and will able to generate fragmented IP packets. -* If disabled, the IP will silently discard fragmented IP packets.. -******************************************************************************/ -#define FNET_CFG_IP4_FRAGMENTATION (1) - -/***************************************************************************** -* MTU. -* Defines the Maximum Transmission Unit for the Ethernet interface. -* The largest value is 1500. Recommended range is 600 - 1500 -******************************************************************************/ -#define FNET_CFG_CPU_ETH0_MTU (1500) - -/***************************************************************************** -* PING service support. -******************************************************************************/ -#define FNET_CFG_PING (1) - -/* IPv6 test specific parameters.*/ -#define FNET_CFG_CPU_ETH0_MAC_ADDR ("00:00:5E:A8:00:16") -#define FNET_CFG_DEBUG (1) -#define FNET_CFG_DEBUG_STARTUP_MS (12000) /*ms*/ -#define FNET_CFG_PING_PACKET_MAX (2000) -#define FNET_CFG_CPU_ETH_RX_BUFS_MAX (10) - -#endif /* _FNET_USER_CONFIG_H_ */ - diff --git a/fnet_demos/src/test_ip6/main.c b/fnet_demos/src/test_ip6/main.c deleted file mode 100644 index ab43f8a8..00000000 --- a/fnet_demos/src/test_ip6/main.c +++ /dev/null @@ -1,20 +0,0 @@ - -#include "fapp.h" - -/********************************************************************/ - -fnet_int32_t main (void) -{ - /* Init UART. */ - fnet_cpu_serial_init(FNET_CFG_CPU_SERIAL_PORT_DEFAULT, 115200u); - - /* Enable Interrupts.*/ - fnet_cpu_irq_enable(0u); - - /* Run application. */ - fapp_main(); - - return(0); -} - - diff --git a/fnet_doc/doxygen/fnet_doc.dox b/fnet_doc/doxygen/fnet_doc.dox index 8714f33d..afaef9a6 100644 --- a/fnet_doc/doxygen/fnet_doc.dox +++ b/fnet_doc/doxygen/fnet_doc.dox @@ -48,18 +48,20 @@ preferred way to configure stack features). @n @par The stack provides following protocols and services: - Supported Platforms: - - @b ARM Cortex-M4, Kinetis: - - @b MK64FN1M (FRDM-K64F board) - - @b MK66FN2M (FRDM-K66F board) - - @b MK6DN512 (TWR-K60D100M board) - - Older Platforms (not supported): + - @b ARM Cortex-M4 + - Kinetis: + - @b MK64FN1M (FRDM-K64F board) + - @b MK66FN2M (FRDM-K66F board) + - @b MK6DN512 (TWR-K60D100M board) + - LPC: LPC54628 (OM13098: LPCXpresso54628 board) + - Qualcomm: QCA4002 (GT202 802.11 Wireless board). + - Other platforms (not supported): - ColdFire: MCF51CN128, MCF5282, MCF52235, MCF54418, MCF52259 - PowerPC: MPC5668G, MPC5566, MPC564xBC, MPC5744P, S32R274. - Kinetis: MK70FN1M, MK60FN1M. - - LPC: LPC54628. - Supported Compilers: - - IAR: Embedded Workbench for ARM, version 7.8 - - GCC: Kinetis Design Studio, version 3.0 + - IAR: Embedded Workbench for ARM, version 8.22 + - GCC: Kinetis Design Studio, version 3.2 - Bare-metal TCP/IP stack. No underlying RTOS is required, although it can be used with it. FreeRTOS example is provided. - Non-blocking Socket API (DGRAM, STREAM, RAW). - Core Protocols: @@ -167,21 +169,23 @@ fnet - FNET root directory. | | |-- tftp - TFTP server and client. | | |-- tls - TLS library. | |-- port - FNET port-specific source code. +| |-- compiler - Compiler-specific source code. | |-- cpu - FNET platform-specific source code. -| | |-- netif - Platform-specific network interface drivers. -| | | |-- fec - FEC/ENET Ethernet module driver. -| | | |-- qca - QCA4002 Wi-Fi module driver, using "third_party/qca-x.x.x". +| | |-- lpc - LPC-specific source code. | | |-- mcf - ColdFire-specific source code. | | |-- mk - Kinetis-specific source code. | | |-- mpc - Power Architecture-specific source code. -| |-- compiler - Compiler-specific source code. +| |-- netif - Platform-specific network interface drivers. +| |-- enet - ENET Ethernet module driver, used by LPC platform. +| |-- fec - FEC/ENET Ethernet module driver, used by MCF,MPC and MK platforms. +| |-- qca - QCA4002 Wi-Fi module driver, adapter for "third_party/qca-x.x.x". |-- fnet_doc - FNET documentation. |-- fnet_demos - FNET demo projects. | |-- common - Common source code used by demos. | | |-- fnet_application - Demo application source code. | | |-- fnet_webpage - Demo web page source code. | | |-- startup - Platform-specific startup source code. -| |-- boards - Demo projects. +| |-- build - Demo projects. | |-- - Demo projects for a board. | |-- boot - FNET TFTP Bootloader. | |-- benchmark - TCP/UDP Throughput Benchmark application. @@ -222,7 +226,7 @@ fnet - FNET root directory. The FNET project supplied with several demo applications. They can be used for demonstration of FNET features or as an example of FNET User-API usage. @n It is recommended to use them as starting point for your new applications.@n -Project files are placed in @verbatim fnet\fnet_demos\boards\\\\ @endverbatim +Project files are placed in @verbatim fnet\fnet_demos\build\\\\ @endverbatim There are six types of demo projects: - @c shell - This is the main demo application. @n The "Shell" demo allows to view/change various system parameters (e.g. IP address, subnet mask), to explore mounted file systems, to run DHCP and DNS clients, HTTP and Telnet servers, via a serial-terminal application. @n @@ -258,32 +262,41 @@ The following table summarizes the supported demo applications, platforms and co Shell FreeRTOS QCA Wi-Fi - MK64FN1M (Kinetis) - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 + MK64FN1M + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 - MK66FN2M (Kinetis) - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 + MK66FN2M + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 - - MK60DN512 (Kinetis) - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 - IAR7.8
KDS3.0 + MK60DN512 + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 + IAR8.22
KDS3.2 - - - + + LPC54628 + IAR8.22 + - + IAR8.22 + IAR8.22 + IAR8.22 + IAR8.22 + @note All demo applications support IPv4 (by default) or IPv6. Both IPv4 and IPv6 are enabled, where it is possible (cause of memory constrains), for Shell and Benchmark applications. It can be changed via @ref FNET_CFG_IP4 and @ref FNET_CFG_IP6 parameter, in the fnet_user_config.h application file. @@ -329,7 +342,7 @@ Follow these steps to run the FNET Shell demo application: - Launch IDE. - Open the project: -@verbatim fnet\fnet_demos\boards\\shell\\ +@verbatim fnet\fnet_demos\build\\shell\\ @endverbatim - In the IDE, choose a project target you want to compile. @@ -748,7 +761,7 @@ Follow these steps to run the FNET Shell demo application: - Launch IDE. - Open the project: -@verbatim fnet\fnet_demos\boards\\shell_mbedtls\\ +@verbatim fnet\fnet_demos\build\\shell_mbedtls\\ @endverbatim - In the IDE, choose a project target you want to compile. @@ -915,7 +928,7 @@ Follow these steps to run the FNET Shell demo application: - Launch IDE. - Open the project: -@verbatim fnet\fnet_demos\boards\\shell_mbedtls\\ +@verbatim fnet\fnet_demos\build\\shell_mbedtls\\ @endverbatim @note So far, it is was tested only with frdmk64f board. @@ -1209,7 +1222,7 @@ Follow these steps to run the FNET Bootloader: @par Prepare the example-application image file that is to be downloaded by the TFTP Bootloader: - Open the project: -@verbatim fnet\fnet_demos\boards\\shell_boot\\ +@verbatim fnet\fnet_demos\build\\shell_boot\\ @endverbatim - In the IDE choose the @a Release target. - Compile the project. @@ -1219,7 +1232,7 @@ Follow these steps to run the FNET Bootloader: @par Prepare the FNET TFTP Bootloader: - Open the project: -@verbatim fnet\fnet_demos\boards\\boot\\ +@verbatim fnet\fnet_demos\build\\boot\\ @endverbatim - In the IDE choose @a Release target. - Compile the project. @@ -1715,7 +1728,7 @@ or on http://fbench.sf.net @par Prepare the FNET Throughput Benchmark application: - Open the project: -@verbatim fnet\fnet_demos\boards\\bench\\ +@verbatim fnet\fnet_demos\build\\bench\\ @endverbatim - In the IDE choose the @a Release target. - Compile the project. @@ -2007,27 +2020,26 @@ fnet_cpu_isr, /**** 91 (0x16C) FEC Receive frame interru /*! @page how_to_add_boot Add FNET Bootloader support to an existing project -The Bootloader reserves the first 52 Kbytes of the on-chip Flash memory for its own needs (actually it can occupy less space). @n The last page of the on-chip Flash memory is used by the Bootloader for parameter storage and may be modified by a user application to change the Bootloader behaviour. +The Bootloader reserves the first 60 Kbytes of the on-chip Flash memory for its own needs (actually it can occupy less space). @n The last page of the on-chip Flash memory is used by the Bootloader for parameter storage and may be modified by a user application to change the Bootloader behaviour. To use an existing application with the FNET Bootloader, the following changes should be applied in the application project: -# Add additional sections to the application linker command file and update the already defined memory sections to avoid section overlapping. -The example of MCF52259 lcf file modification: +The example of MK64FN IAR linker file modification (added __flash_offset__): @verbatim ... -MEMORY -{ - # 512KB FLASH - - fnet_bootloader (RX) : ORIGIN = 0x00000000, LENGTH = 0x0000D000 # 52KB (Reserved for FNET Bootloader) - - vectorrom (RX) : ORIGIN = 0x0000D000, LENGTH = 0x00000400 - code (RX) : ORIGIN = 0x0000D400, LENGTH = 0x0007DC00 +define symbol __flash_offset__ = 0x0000F000; //60KB reserved for FNET bootloader. - fnet_params (RW) : ORIGIN = 0x0007F000, LENGTH = 0x00001000 # 4Kbytes (Last logical-block reserved for parameters) - - vectorram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00000400 # 64KB SRAM - userram (RWX) : ORIGIN = 0x20000400, LENGTH = 0x0000FC00 -} +define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; +define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; + +define symbol m_interrupts_start = 0x00000000 + __flash_offset__; +define symbol m_interrupts_end = 0x000003FF + __flash_offset__; + +define symbol m_flash_config_start = 0x00000400 + __flash_offset__; +define symbol m_flash_config_end = 0x0000040F + __flash_offset__; + +define symbol m_text_start = 0x00000410 + __flash_offset__; +define symbol m_text_end = 0x000FFFFF - __flash_offset__; ... @endverbatim -# An application may change the Bootloader parameters. They are placed at the beginning of the last logical-block of the on-chip flash memory. @n @@ -2120,6 +2132,16 @@ Press any key to continue . . . FNET public releases: +- Version 4.1.1 + - LPC54628 support: + - Added bench, shell, shell_freertos, shell_freertos_wifi_qca, shell_mbedtls projects for lpcxpresso54628. + - Added Ethernet and WiFi interface. + - Is fully functional, but still under development. + - Added fapp_hw_init() which contains a board-specific initialization. + - Upgraded projects to IAR v8.22. + - Moved projects to fnet/fnet_demos/build. + - Other minor fixes. + - Version 4.1.0 - QCA Wi-Fi: - Fixed SSID scanning in the QCA Wi-Fi driver and following failed connection. diff --git a/fnet_doc/doxygen/fnet_gen_doc.in b/fnet_doc/doxygen/fnet_gen_doc.in index 196a8e6c..9611b730 100644 --- a/fnet_doc/doxygen/fnet_gen_doc.in +++ b/fnet_doc/doxygen/fnet_gen_doc.in @@ -38,7 +38,7 @@ PROJECT_NAME = "Embedded TCP/IP stack" # could be handy for archiving the generated documentation or if some version # control system is used. -PROJECT_NUMBER = 4.1.0 +PROJECT_NUMBER = 4.1.1 # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a diff --git a/fnet_doc/doxygen/fnet_gen_doc_chm.in b/fnet_doc/doxygen/fnet_gen_doc_chm.in index 6eb3d470..8c755f5c 100644 --- a/fnet_doc/doxygen/fnet_gen_doc_chm.in +++ b/fnet_doc/doxygen/fnet_gen_doc_chm.in @@ -38,7 +38,7 @@ PROJECT_NAME = "Embedded TCP/IP stack" # could be handy for archiving the generated documentation or if some version # control system is used. -PROJECT_NUMBER = 4.1.0 +PROJECT_NUMBER = 4.1.1 # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a diff --git a/fnet_doc/fnet_user_manual.chm b/fnet_doc/fnet_user_manual.chm index 3d0514389b2d39b06c68eb685973507124024597..03a0025c7a0991e838ab71b5f3dc557e48ff78fd 100644 GIT binary patch delta 2556226 zcmd?RcUTn37qH6!-Q=8eo&m`jlnkOMD&|a%20%c}z>ri-K&ePhf+8TG2#A;?K?Oy0 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zltIZk`e5oHQCpfGMYyL>f}&Qk&|@i6@E1|q%R#;!4~Iw(wSUUli-v$W z1YgGCVso2McuLR&HxFipi|G?#@lrEKPUs^ZG3j{(bw~ZS39naurua*-WOtd-T6m!A zKbT`?PHU+V2gX2gzkQDg=596vS(tR*U|2Xd$#wkm+Z+-tN6|qnrdK+At~G=;T2cWV zmm7aCPkt𝔑_9k?&)TwSU6z{UAtxeBP``-#nr5=C*=aPY*TCzSoM^4brIp9uVW1 z23rC;m-cEUB>&=%sOZ{(D+b9m9tD=e(2t|w8~uKCw}#7;ei=K=n-V^7e;+gY&Om;^ z>!DO*lHkTDILU2$FXXf&d%=44sysJrtofq);-~;}A(1-N`!>6Iy?#@Omr|4?@7&vUo7=VQt z*xJABP4rZlP-Ur$%kZwn!sAE6JKm{cJKL*9l#Ryf3+iI<$3tFzWYx{O$cKzL#v3(9 zxQTL4cZ$}sYFn8kR5*Prw?admNNVLZLla4Fz)v#Ev&_pZ%rY#qGRw2f%Ph16) + if(vector_number > 16) { /* Install FNET ISR into the Vector Table in RAM */ - #if FNET_CFG_CPU_VECTOR_TABLE_IS_IN_RAM +#if FNET_CFG_CPU_VECTOR_TABLE_IS_IN_RAM { fnet_uint32_t *irq_vec; irq_vec = (fnet_uint32_t *)(FNET_CFG_CPU_VECTOR_TABLE) + vector_number; @@ -48,7 +48,7 @@ fnet_return_t fnet_cpu_isr_install(fnet_uint32_t vector_number, fnet_uint32_t pr *irq_vec = (fnet_uint32_t) FNET_ISR_HANDLER; } } - #endif +#endif /* Initialize NVIC */ if(priority > FNET_CFG_CPU_VECTOR_PRIORITY_MAX) diff --git a/fnet_stack/port/cpu/lpc/fnet_lpc_serial.c b/fnet_stack/port/cpu/lpc/fnet_lpc_serial.c index 2575c913..1925eadf 100644 --- a/fnet_stack/port/cpu/lpc/fnet_lpc_serial.c +++ b/fnet_stack/port/cpu/lpc/fnet_lpc_serial.c @@ -33,10 +33,12 @@ #include #include - /* Array of USART base addresses. */ -static USART_Type * const fnet_lpc_serial_usart_base_addr[] = USART_BASE_PTRS; -#define FNET_LPC_USART_COUNT (sizeof(fnet_lpc_serial_usart_base_addr) / sizeof(fnet_lpc_serial_usart_base_addr[0])) +static USART_Type *const fnet_lpc_serial_usart_base_addr[] = USART_BASE_PTRS; +/* Array of USART clocks. */ +static const clock_name_t fnet_lpc_serial_usart_clock[] = {kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm4, kCLOCK_Flexcomm5, kCLOCK_Flexcomm6, kCLOCK_Flexcomm7, kCLOCK_Flexcomm8, kCLOCK_Flexcomm9}; + +#define FNET_LPC_USART_COUNT (sizeof(fnet_lpc_serial_usart_base_addr) / sizeof(fnet_lpc_serial_usart_base_addr[0])) /********************************************************************/ void fnet_cpu_serial_putchar (fnet_index_t port_number, fnet_char_t character) @@ -55,7 +57,7 @@ void fnet_cpu_serial_putchar (fnet_index_t port_number, fnet_char_t character) /* Wait to finish transfer */ /* It looks like optional, but whithout it there are lost symbols */ while (!(base->STAT & USART_STAT_TXIDLE_MASK)) - {}; + {}; } } /********************************************************************/ @@ -79,7 +81,7 @@ fnet_int32_t fnet_cpu_serial_getchar (fnet_index_t port_number) return FNET_ERR; } -#if FNET_CFG_CPU_SERIAL_IO_INIT +#if FNET_CFG_CPU_SERIAL_IO_INIT static inline void fnet_cpu_serial_gpio_init(fnet_index_t port_number) { switch(port_number) @@ -96,51 +98,51 @@ static inline void fnet_cpu_serial_gpio_init(fnet_index_t port_number) * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ case 0: - { - /* attach 12 MHz clock to FLEXCOMM0 */ - CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); - - /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ - CLOCK_EnableClock(kCLOCK_Iocon); - - const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI */ - IOCON_PIO_FUNC1 | - /* No addition pin function */ - IOCON_PIO_MODE_INACT | - /* Input function is not inverted */ - IOCON_PIO_INV_DI | - /* Enables digital function */ - IOCON_PIO_DIGITAL_EN | - /* Input filter disabled */ - IOCON_PIO_INPFILT_OFF | - /* Standard mode, output slew rate control is enabled */ - IOCON_PIO_SLEW_STANDARD | - /* Open drain is disabled */ - IOCON_PIO_OPENDRAIN_DI); - /* PORT0 PIN29 (coords: B13) is configured as FC0_RXD_SDA_MOSI */ - IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config); - - const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO */ - IOCON_PIO_FUNC1 | - /* No addition pin function */ - IOCON_PIO_MODE_INACT | - /* Input function is not inverted */ - IOCON_PIO_INV_DI | - /* Enables digital function */ - IOCON_PIO_DIGITAL_EN | - /* Input filter disabled */ - IOCON_PIO_INPFILT_OFF | - /* Standard mode, output slew rate control is enabled */ - IOCON_PIO_SLEW_STANDARD | - /* Open drain is disabled */ - IOCON_PIO_OPENDRAIN_DI); - /* PORT0 PIN30 (coords: A2) is configured as FC0_TXD_SCL_MISO */ - IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config); - } - break; + { + /* attach 12 MHz clock to FLEXCOMM0 */ + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); + + /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + CLOCK_EnableClock(kCLOCK_Iocon); + + const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN29 (coords: B13) is configured as FC0_RXD_SDA_MOSI */ + IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config); + + const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO */ + IOCON_PIO_FUNC1 | + /* No addition pin function */ + IOCON_PIO_MODE_INACT | + /* Input function is not inverted */ + IOCON_PIO_INV_DI | + /* Enables digital function */ + IOCON_PIO_DIGITAL_EN | + /* Input filter disabled */ + IOCON_PIO_INPFILT_OFF | + /* Standard mode, output slew rate control is enabled */ + IOCON_PIO_SLEW_STANDARD | + /* Open drain is disabled */ + IOCON_PIO_OPENDRAIN_DI); + /* PORT0 PIN30 (coords: A2) is configured as FC0_TXD_SCL_MISO */ + IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config); + } + break; default: //TBD - break; + break; } } #endif /* FNET_CFG_CPU_SERIAL_IO_INIT */ @@ -150,23 +152,22 @@ void fnet_cpu_serial_init(fnet_index_t port_number, fnet_uint32_t baud_rate) { usart_config_t config; uint32_t srcClock_Hzl; - USART_Type *base; + USART_Type *base; if(port_number < FNET_LPC_USART_COUNT) { - - #if FNET_CFG_CPU_SERIAL_IO_INIT +#if FNET_CFG_CPU_SERIAL_IO_INIT /* Init GPIO.*/ fnet_cpu_serial_gpio_init(port_number); - #endif +#endif base = fnet_lpc_serial_usart_base_addr[port_number]; - srcClock_Hzl = CLOCK_GetFreq(kCLOCK_Flexcomm0); + srcClock_Hzl = CLOCK_GetFreq(fnet_lpc_serial_usart_clock[port_number]); /* Set USART driver parameters. */ USART_GetDefaultConfig(&config); config.baudRate_Bps = baud_rate; config.enableTx = true; - config.enableRx = true; + config.enableRx = true; USART_Init(base, &config, srcClock_Hzl); } diff --git a/fnet_stack/port/cpu/lpc/fnet_lpc_timer.c b/fnet_stack/port/cpu/lpc/fnet_lpc_timer.c index 67455ff2..ef605f1d 100644 --- a/fnet_stack/port/cpu/lpc/fnet_lpc_timer.c +++ b/fnet_stack/port/cpu/lpc/fnet_lpc_timer.c @@ -34,8 +34,8 @@ #include /* Array of CTIMER base addresses. */ -static CTIMER_Type * const fnet_lpc_ctimer_base_addr[] = CTIMER_BASE_PTRS; -#define FNET_LPC_CTIMER_COUNT (sizeof(fnet_lpc_ctimer_base_addr) / sizeof(fnet_lpc_ctimer_base_addr[0])) +static CTIMER_Type *const fnet_lpc_ctimer_base_addr[] = CTIMER_BASE_PTRS; +#define FNET_LPC_CTIMER_COUNT (sizeof(fnet_lpc_ctimer_base_addr) / sizeof(fnet_lpc_ctimer_base_addr[0])) static void fnet_cpu_timer_handler_top(void *cookie); @@ -49,7 +49,7 @@ static void fnet_cpu_timer_handler_top(void *cookie) base = fnet_lpc_ctimer_base_addr[FNET_CFG_CPU_TIMER_NUMBER]; - /* Get Interrupt status flags and clear it were set*/ + /* Get Interrupt status flags and clear it*/ base->IR = base->IR; /* Update FNET timer tick counter.*/ @@ -74,23 +74,23 @@ fnet_return_t fnet_cpu_timer_init( fnet_time_t period_ms ) /* Install interrupt handler and enable interrupt in NVIC. */ result = fnet_isr_vector_init(FNET_CFG_CPU_TIMER_VECTOR_NUMBER, fnet_cpu_timer_handler_top, - fnet_timer_handler_bottom, - FNET_CFG_CPU_TIMER_VECTOR_PRIORITY, 0u); + fnet_timer_handler_bottom, + FNET_CFG_CPU_TIMER_VECTOR_PRIORITY, 0u); if(result == FNET_OK) { - /*UM: Set the appropriate bits to enable clocks to timers that will be used: + /*UM: Set the appropriate bits to enable clocks to timers that will be used: * CTIMER0 and CTIMER1, and CTIMER2 in the AHBCLKCTRL1 register, - * CTIMER3 and CTIMER4 in the ASYNCAPBCLKCTRL register */ - #if (FNET_CFG_CPU_TIMER_NUMBER == 0) || (FNET_CFG_CPU_TIMER_NUMBER == 1) || (FNET_CFG_CPU_TIMER_NUMBER == 2) - clock_name = kCLOCK_BusClk; - #elif (FNET_CFG_CPU_TIMER_NUMBER == 3) || (FNET_CFG_CPU_TIMER_NUMBER == 4) - clock_name = kCLOCK_AsyncApbClk; - /* Use 12 MHz clock. - Asynchronous APB bridge is enabled inside this function. */ - CLOCK_AttachClk(kFRO12M_to_ASYNC_APB); - #else - #error Not suported FNET_CFG_CPU_TIMER_NUMBER - #endif + * CTIMER3 and CTIMER4 in the ASYNCAPBCLKCTRL register */ +#if (FNET_CFG_CPU_TIMER_NUMBER == 0) || (FNET_CFG_CPU_TIMER_NUMBER == 1) || (FNET_CFG_CPU_TIMER_NUMBER == 2) + clock_name = kCLOCK_BusClk; +#elif (FNET_CFG_CPU_TIMER_NUMBER == 3) || (FNET_CFG_CPU_TIMER_NUMBER == 4) + clock_name = kCLOCK_AsyncApbClk; + /* Use 12 MHz clock. + Asynchronous APB bridge is enabled inside this function. */ + CLOCK_AttachClk(kFRO12M_to_ASYNC_APB); +#else +#error Not suported FNET_CFG_CPU_TIMER_NUMBER +#endif /* Set CTIMER driver parameters. */ CTIMER_GetDefaultConfig(&config); @@ -99,7 +99,7 @@ fnet_return_t fnet_cpu_timer_init( fnet_time_t period_ms ) matchConfig.enableCounterReset = true; matchConfig.enableCounterStop = false; - matchConfig.matchValue = (CLOCK_GetFreq(clock_name)*period_ms)/1000; + matchConfig.matchValue = (CLOCK_GetFreq(clock_name) * period_ms) / 1000; matchConfig.enableInterrupt = true; CTIMER_SetupMatch(base, kCTIMER_Match_0, &matchConfig); diff --git a/fnet_stack/port/cpu/lpc/fnet_lpc_wifi.c b/fnet_stack/port/cpu/lpc/fnet_lpc_wifi.c index aae24333..49cbcdfd 100644 --- a/fnet_stack/port/cpu/lpc/fnet_lpc_wifi.c +++ b/fnet_stack/port/cpu/lpc/fnet_lpc_wifi.c @@ -25,7 +25,7 @@ #include "fnet.h" #if FNET_LPC && FNET_CFG_CPU_WIFI -#include "port/cpu/netif/qca/fnet_qca.h" +#include "port/netif/qca/fnet_qca.h" /* MCUXpresso */ #include @@ -58,6 +58,7 @@ fnet_netif_t fnet_cpu_wifi_if = *************************************************************************/ void BOARD_InitGT202Shield(void) { +#if FNET_CFG_CPU_LPC54628 /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ CLOCK_EnableClock(kCLOCK_Iocon); @@ -134,17 +135,18 @@ void BOARD_InitGT202Shield(void) /* Select Analog/Digital mode.: Digital mode. */ | IOCON_PIO_DIGIMODE(PIO47_DIGIMODE_DIGITAL)); +#endif /* FNET_CFG_CPU_LPC54628 */ } /************************************************************************ * DESCRIPTION: Silex2401/QCA4002 Wi-Fi board pin initialization. *************************************************************************/ -void BOARD_InitSilex2401Shield(void) +void BOARD_InitSilex2401Shield(void) { -//TBD + //TBD } #if !FNET_CFG_CPU_LPC54628 - #warning "QCA400x Wi-Fi board pin initialization is not tested for your platform." + #warning "QCA400x Wi-Fi board pin initialization is not tested for your platform." #endif #endif /* FNET_CFG_CPU_WIFI_IO_INIT */ diff --git a/fnet_stack/port/cpu/mcf/fnet_mcf_config.h b/fnet_stack/port/cpu/mcf/fnet_mcf_config.h index f0c8e4b4..97f8f294 100644 --- a/fnet_stack/port/cpu/mcf/fnet_mcf_config.h +++ b/fnet_stack/port/cpu/mcf/fnet_mcf_config.h @@ -117,10 +117,10 @@ #if FNET_CFG_MCF_TIMER_PIT #define FNET_CFG_CPU_TIMER_NUMBER_MAX (1) #endif - + /******************************************************************************* - * Timer number used by the FNET. It can range from 0 to FNET_CFG_CPU_TIMER_NUMBER_MAX. - ******************************************************************************/ + * Timer number used by the FNET. It can range from 0 to FNET_CFG_CPU_TIMER_NUMBER_MAX. + ******************************************************************************/ #ifndef FNET_CFG_CPU_TIMER_NUMBER #define FNET_CFG_CPU_TIMER_NUMBER (FNET_CFG_CPU_TIMER_NUMBER_MAX) #endif diff --git a/fnet_stack/port/cpu/mcf/fnet_mcf_eth.c b/fnet_stack/port/cpu/mcf/fnet_mcf_eth.c index 07789a04..3a4ae018 100644 --- a/fnet_stack/port/cpu/mcf/fnet_mcf_eth.c +++ b/fnet_stack/port/cpu/mcf/fnet_mcf_eth.c @@ -25,7 +25,7 @@ #include "fnet.h" #if FNET_MCF && (FNET_CFG_CPU_ETH0 ||FNET_CFG_CPU_ETH1) -#include "port/cpu/netif/fec/fnet_fec.h" +#include "port/netif/fec/fnet_fec.h" #if FNET_CFG_CPU_ETH0 /************************************************************************ diff --git a/fnet_stack/port/cpu/mcf/fnet_mcf_isr_inst.c b/fnet_stack/port/cpu/mcf/fnet_mcf_isr_inst.c index c05ad0c8..7731b1e3 100644 --- a/fnet_stack/port/cpu/mcf/fnet_mcf_isr_inst.c +++ b/fnet_stack/port/cpu/mcf/fnet_mcf_isr_inst.c @@ -39,23 +39,23 @@ fnet_return_t fnet_cpu_isr_install(fnet_uint32_t vector_number, fnet_uint32_t pr if(vector_number > 0x40) { /* Install FNET ISR into the Vector Table in RAM */ - #if FNET_CFG_CPU_VECTOR_TABLE_IS_IN_RAM +#if FNET_CFG_CPU_VECTOR_TABLE_IS_IN_RAM { fnet_uint32_t *irq_vec; - irq_vec = (fnet_uint32_t *)(FNET_CFG_CPU_VECTOR_TABLE) + vector_number; + irq_vec = (fnet_uint32_t *)(FNET_CFG_CPU_VECTOR_TABLE) + vector_number; - if(*irq_vec != (fnet_uint32_t)FNET_ISR_HANDLER) - { - /* It's not installed yet.*/ - *irq_vec = (fnet_uint32_t) FNET_ISR_HANDLER; - } + if(*irq_vec != (fnet_uint32_t)FNET_ISR_HANDLER) + { + /* It's not installed yet.*/ + *irq_vec = (fnet_uint32_t) FNET_ISR_HANDLER; + } } - #endif +#endif - if(priority > FNET_CFG_CPU_VECTOR_PRIORITY_MAX) - { - priority = FNET_CFG_CPU_VECTOR_PRIORITY_MAX; - } + if(priority > FNET_CFG_CPU_VECTOR_PRIORITY_MAX) + { + priority = FNET_CFG_CPU_VECTOR_PRIORITY_MAX; + } #if !FNET_CFG_MCF_V1 /* Not for MCF Ver.1 */ /* Set priority. */ diff --git a/fnet_stack/port/cpu/mcf/fnet_mcf_serial.c b/fnet_stack/port/cpu/mcf/fnet_mcf_serial.c index 3f5454e8..e5c7bda8 100644 --- a/fnet_stack/port/cpu/mcf/fnet_mcf_serial.c +++ b/fnet_stack/port/cpu/mcf/fnet_mcf_serial.c @@ -68,7 +68,7 @@ fnet_int32_t fnet_cpu_serial_getchar (fnet_index_t port_number) return FNET_ERR; } -#if FNET_CFG_CPU_SERIAL_IO_INIT +#if FNET_CFG_CPU_SERIAL_IO_INIT static inline void fnet_cpu_serial_gpio_init(fnet_index_t port_number) { /* Enable the proper UART pins */ @@ -192,9 +192,9 @@ void fnet_cpu_serial_init(fnet_index_t port_number, fnet_uint32_t baud_rate) */ fnet_uint16_t ubgs; -#if FNET_CFG_CPU_SERIAL_IO_INIT +#if FNET_CFG_CPU_SERIAL_IO_INIT /* Init GPIO.*/ - fnet_cpu_serial_gpio_init(port_number); + fnet_cpu_serial_gpio_init(port_number); #endif diff --git a/fnet_stack/port/cpu/mk/fnet_mk_config.h b/fnet_stack/port/cpu/mk/fnet_mk_config.h index f92d4c3a..e604d335 100644 --- a/fnet_stack/port/cpu/mk/fnet_mk_config.h +++ b/fnet_stack/port/cpu/mk/fnet_mk_config.h @@ -58,8 +58,8 @@ #define FNET_CFG_CPU_TIMER_NUMBER_MAX (3u) /******************************************************************************* - * Timer number used by the FNET. It can range from 0 to FNET_CFG_CPU_TIMER_NUMBER_MAX. - ******************************************************************************/ + * Timer number used by the FNET. It can range from 0 to FNET_CFG_CPU_TIMER_NUMBER_MAX. + ******************************************************************************/ #ifndef FNET_CFG_CPU_TIMER_NUMBER #define FNET_CFG_CPU_TIMER_NUMBER (FNET_CFG_CPU_TIMER_NUMBER_MAX) #endif diff --git a/fnet_stack/port/cpu/mk/fnet_mk_eth.c b/fnet_stack/port/cpu/mk/fnet_mk_eth.c index 1e3544c4..9a88e616 100644 --- a/fnet_stack/port/cpu/mk/fnet_mk_eth.c +++ b/fnet_stack/port/cpu/mk/fnet_mk_eth.c @@ -25,7 +25,7 @@ #include "fnet.h" #if FNET_MK && FNET_CFG_CPU_ETH0 -#include "port/cpu/netif/fec/fnet_fec.h" +#include "port/netif/fec/fnet_fec.h" /************************************************************************ * Ethernet interface structure. @@ -145,7 +145,7 @@ void fnet_eth_phy_init(fnet_fec_if_t *ethif) FNET_COMP_UNUSED_ARG(ethif); } -/* If vector table is in ROM, pre-installed FNET ISR for ENET Receive Frame interrupt*/ +/* If vector table is in ROM, pre-install FNET ISR for ENET Receive Frame interrupt*/ #if !FNET_CFG_CPU_VECTOR_TABLE_IS_IN_RAM void ENET_Receive_IRQHandler (void) { diff --git a/fnet_stack/port/cpu/mk/fnet_mk_isr_inst.c b/fnet_stack/port/cpu/mk/fnet_mk_isr_inst.c index 8d59f67d..051233f2 100644 --- a/fnet_stack/port/cpu/mk/fnet_mk_isr_inst.c +++ b/fnet_stack/port/cpu/mk/fnet_mk_isr_inst.c @@ -35,10 +35,10 @@ fnet_return_t fnet_cpu_isr_install(fnet_uint32_t vector_number, fnet_uint32_t pr fnet_uint32_t divider; fnet_uint32_t irq_number; /* The irq number NOT the vector number.*/ - if(vector_number>16) + if(vector_number > 16) { /* Install FNET ISR into the Vector Table in RAM */ - #if FNET_CFG_CPU_VECTOR_TABLE_IS_IN_RAM +#if FNET_CFG_CPU_VECTOR_TABLE_IS_IN_RAM { fnet_uint32_t *irq_vec; irq_vec = (fnet_uint32_t *)(FNET_CFG_CPU_VECTOR_TABLE) + vector_number; @@ -48,7 +48,7 @@ fnet_return_t fnet_cpu_isr_install(fnet_uint32_t vector_number, fnet_uint32_t pr *irq_vec = (fnet_uint32_t) FNET_ISR_HANDLER; } } - #endif +#endif /* Initialize NVIC */ if(priority > FNET_CFG_CPU_VECTOR_PRIORITY_MAX) diff --git a/fnet_stack/port/cpu/mk/fnet_mk_serial.c b/fnet_stack/port/cpu/mk/fnet_mk_serial.c index d75d2dc3..0cdb2c59 100644 --- a/fnet_stack/port/cpu/mk/fnet_mk_serial.c +++ b/fnet_stack/port/cpu/mk/fnet_mk_serial.c @@ -66,7 +66,7 @@ fnet_int32_t fnet_cpu_serial_getchar (fnet_index_t port_number) return FNET_ERR; } -#if FNET_CFG_CPU_SERIAL_IO_INIT +#if FNET_CFG_CPU_SERIAL_IO_INIT static inline void fnet_cpu_serial_gpio_init(fnet_index_t port_number) { /* Enable the pins for the selected UART */ @@ -199,9 +199,9 @@ void fnet_cpu_serial_init(fnet_index_t port_number, fnet_uint32_t baud_rate) fnet_uint16_t brfa; fnet_uint8_t temp; -#if FNET_CFG_CPU_SERIAL_IO_INIT +#if FNET_CFG_CPU_SERIAL_IO_INIT /* Init GPIO.*/ - fnet_cpu_serial_gpio_init(port_number); + fnet_cpu_serial_gpio_init(port_number); #endif diff --git a/fnet_stack/port/cpu/mk/fnet_mk_timer.c b/fnet_stack/port/cpu/mk/fnet_mk_timer.c index a0b4b7c2..0f45110d 100644 --- a/fnet_stack/port/cpu/mk/fnet_mk_timer.c +++ b/fnet_stack/port/cpu/mk/fnet_mk_timer.c @@ -71,8 +71,8 @@ fnet_return_t fnet_cpu_timer_init( fnet_time_t period_ms ) /* Install interrupt handler and enable interrupt in NVIC. */ result = fnet_isr_vector_init(FNET_CFG_CPU_TIMER_VECTOR_NUMBER, fnet_cpu_timer_handler_top, - fnet_timer_handler_bottom, - FNET_CFG_CPU_TIMER_VECTOR_PRIORITY, 0u); + fnet_timer_handler_bottom, + FNET_CFG_CPU_TIMER_VECTOR_PRIORITY, 0u); if(result == FNET_OK) { /* Initialize the PIT timer to generate an interrupt every period_ms */ diff --git a/fnet_stack/port/cpu/mk/fnet_mk_wifi.c b/fnet_stack/port/cpu/mk/fnet_mk_wifi.c index 2310bb01..bab1b365 100644 --- a/fnet_stack/port/cpu/mk/fnet_mk_wifi.c +++ b/fnet_stack/port/cpu/mk/fnet_mk_wifi.c @@ -25,7 +25,7 @@ #include "fnet.h" #if FNET_MK && FNET_CFG_CPU_WIFI -#include "port/cpu/netif/qca/fnet_qca.h" +#include "port/netif/qca/fnet_qca.h" /************************************************************************ * Wi-Fi interface structures. @@ -68,8 +68,8 @@ void BOARD_InitGT202Shield(void) FNET_MK_SIM_SCGC5 |= FNET_MK_SIM_SCGC5_PORTC_MASK | FNET_MK_SIM_SCGC5_PORTD_MASK; pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTC_BASE_PTR; - pctl->PCR[12] = FNET_MK_PORT_PCR_MUX(1)|FNET_MK_PORT_PCR_PE(1); /* PORTC12 (pin 84) is configured as PTC12 (GPIO). Pull Enable: Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.*/ - pctl->PCR[3] = FNET_MK_PORT_PCR_MUX(1)|FNET_MK_PORT_PCR_PE(1)|FNET_MK_PORT_PCR_PS(1); /* PPORTC3 (pin 73) is configured as PTC3 (GPIO). + pctl->PCR[12] = FNET_MK_PORT_PCR_MUX(1) | FNET_MK_PORT_PCR_PE(1); /* PORTC12 (pin 84) is configured as PTC12 (GPIO). Pull Enable: Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.*/ + pctl->PCR[3] = FNET_MK_PORT_PCR_MUX(1) | FNET_MK_PORT_PCR_PE(1) | FNET_MK_PORT_PCR_PS(1); /* PPORTC3 (pin 73) is configured as PTC3 (GPIO). Pull Enable: Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. */ @@ -84,7 +84,7 @@ void BOARD_InitGT202Shield(void) /************************************************************************ * DESCRIPTION: Silex2401/QCA4002 Wi-Fi board pin initialization. *************************************************************************/ -void BOARD_InitSilex2401Shield(void) +void BOARD_InitSilex2401Shield(void) { #if FNET_CFG_CPU_MK64FN1 FNET_MK_PORT_MemMapPtr pctl; @@ -100,9 +100,9 @@ void BOARD_InitSilex2401Shield(void) FNET_MK_SIM_SCGC5 |= FNET_MK_SIM_SCGC5_PORTB_MASK | FNET_MK_SIM_SCGC5_PORTD_MASK; pctl = (FNET_MK_PORT_MemMapPtr)FNET_MK_PORTB_BASE_PTR; - pctl->PCR[23] = FNET_MK_PORT_PCR_MUX(1)|FNET_MK_PORT_PCR_PE(1); /* PORTB23 (pin 69) is configured as PTB23 (GPIO). + pctl->PCR[23] = FNET_MK_PORT_PCR_MUX(1) | FNET_MK_PORT_PCR_PE(1); /* PORTB23 (pin 69) is configured as PTB23 (GPIO). Pull Enable: Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.*/ - pctl->PCR[9] = FNET_MK_PORT_PCR_MUX(1)|FNET_MK_PORT_PCR_PE(1)|FNET_MK_PORT_PCR_PS(1); /* PORTB9 (pin 57) is configured as PTB9 (GPIO). + pctl->PCR[9] = FNET_MK_PORT_PCR_MUX(1) | FNET_MK_PORT_PCR_PE(1) | FNET_MK_PORT_PCR_PS(1); /* PORTB9 (pin 57) is configured as PTB9 (GPIO). Pull Enable: Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. */ @@ -114,7 +114,7 @@ void BOARD_InitSilex2401Shield(void) #endif /* FNET_CFG_CPU_MK64FN1 */ } #if !FNET_CFG_CPU_MK64FN1 - #warning "QCA400x Wi-Fi board pin initialization is not tested for your platform." + #warning "QCA400x Wi-Fi board pin initialization is not tested for your platform." #endif #endif /* FNET_CFG_CPU_WIFI_IO_INIT */ diff --git a/fnet_stack/port/cpu/mpc/fnet_mpc_config.h b/fnet_stack/port/cpu/mpc/fnet_mpc_config.h index 8329bce3..f64a2493 100644 --- a/fnet_stack/port/cpu/mpc/fnet_mpc_config.h +++ b/fnet_stack/port/cpu/mpc/fnet_mpc_config.h @@ -35,8 +35,8 @@ #if FNET_MPC /******************************************************************************* - * Timer number used by the FNET. It can range from 0 to FNET_CFG_CPU_TIMER_NUMBER_MAX. - ******************************************************************************/ + * Timer number used by the FNET. It can range from 0 to FNET_CFG_CPU_TIMER_NUMBER_MAX. + ******************************************************************************/ #ifndef FNET_CFG_CPU_TIMER_NUMBER #define FNET_CFG_CPU_TIMER_NUMBER (FNET_CFG_CPU_TIMER_NUMBER_MAX) #endif diff --git a/fnet_stack/port/cpu/mpc/fnet_mpc_eth.c b/fnet_stack/port/cpu/mpc/fnet_mpc_eth.c index 0adda90e..a91c443e 100644 --- a/fnet_stack/port/cpu/mpc/fnet_mpc_eth.c +++ b/fnet_stack/port/cpu/mpc/fnet_mpc_eth.c @@ -26,7 +26,7 @@ #include "fnet.h" #if FNET_MPC && (FNET_CFG_CPU_ETH0 ||FNET_CFG_CPU_ETH1) -#include "port/cpu/netif/fec/fnet_fec.h" +#include "port/netif/fec/fnet_fec.h" /************************************************************************ * Ethernet interface structure. diff --git a/fnet_stack/port/cpu/mpc/fnet_mpc_isr_inst.c b/fnet_stack/port/cpu/mpc/fnet_mpc_isr_inst.c index b273343c..e4b014f1 100644 --- a/fnet_stack/port/cpu/mpc/fnet_mpc_isr_inst.c +++ b/fnet_stack/port/cpu/mpc/fnet_mpc_isr_inst.c @@ -35,7 +35,7 @@ extern fnet_uint32_t FNET_CFG_CPU_VECTOR_TABLE []; *************************************************************************/ fnet_return_t fnet_cpu_isr_install(fnet_uint32_t vector_number, fnet_uint32_t priority) { - + /* Install FNET ISR into the Vector Table in RAM */ #if FNET_CFG_CPU_VECTOR_TABLE_IS_IN_RAM { diff --git a/fnet_stack/port/cpu/mpc/fnet_mpc_serial.c b/fnet_stack/port/cpu/mpc/fnet_mpc_serial.c index 3deeb546..84ca47ed 100644 --- a/fnet_stack/port/cpu/mpc/fnet_mpc_serial.c +++ b/fnet_stack/port/cpu/mpc/fnet_mpc_serial.c @@ -197,7 +197,7 @@ void fnet_cpu_serial_init(fnet_index_t port_number, fnet_uint32_t baud_rate) */ /* Init GPIO.*/ -#if FNET_CFG_CPU_SERIAL_IO_INIT +#if FNET_CFG_CPU_SERIAL_IO_INIT fnet_cpu_serial_gpio_init(port_number); #endif diff --git a/fnet_stack/port/netif/enet/fnet_enet.c b/fnet_stack/port/netif/enet/fnet_enet.c new file mode 100644 index 00000000..1690426e --- /dev/null +++ b/fnet_stack/port/netif/enet/fnet_enet.c @@ -0,0 +1,720 @@ +/************************************************************************** +* +* Copyright 2018 by Andrey Butok. FNET Community. +* +*************************************************************************** +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*************************************************************************** +* +* LPC ENET module driver implementation. +* This is a prototype wrapper for LPC MCUX driver. +* +***************************************************************************/ + +#include "fnet.h" +#if (FNET_LPC && FNET_CFG_CPU_ETH0) + +#if FNET_CFG_DEBUG_ENET && FNET_CFG_DEBUG + #define FNET_DEBUG_ENET FNET_DEBUG_PRINTF +#else + #define FNET_DEBUG_ENET(...) do{}while(0) +#endif + +#include "fnet_enet.h" + +/************************************************************************ +* Function Prototypes +*************************************************************************/ +static fnet_return_t fnet_enet_init(fnet_netif_t *netif); +static void fnet_enet_release(fnet_netif_t *netif); +static fnet_return_t fnet_enet_get_hw_addr(fnet_netif_t *netif, fnet_uint8_t *hw_addr); +static fnet_return_t fnet_enet_set_hw_addr(fnet_netif_t *netif, fnet_uint8_t *hw_addr); +static fnet_bool_t fnet_enet_is_connected(fnet_netif_t *netif); +static fnet_return_t fnet_enet_get_statistics(fnet_netif_t *netif, struct fnet_netif_statistics *statistics); +static fnet_return_t fnet_enet_phy_init(fnet_enet_if_t *enet_if); +static void fnet_enet_rx_buf_next( fnet_enet_if_t *enet_if); +#if FNET_CFG_CPU_ETH_PHY_ADDR_DISCOVER + static void fnet_enet_phy_discover_addr (fnet_enet_if_t *enet_if, fnet_uint8_t phy_addr_start); +#endif + +static void fnet_enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, uint8_t channel, void *param); + +/* ENET interrup handler. */ +static void fnet_enet_isr_handler_top(void *cookie); +static void fnet_enet_isr_handler_bottom(void *cookie); + +static void fnet_enet_get_mac_addr(fnet_enet_if_t *enet_if, fnet_mac_addr_t *mac_addr); + +/***************************************************************************** + * ENET network-interface general API structure. + ******************************************************************************/ +const fnet_netif_api_t fnet_enet_api = +{ + .netif_type = FNET_NETIF_TYPE_ETHERNET, /* Data-link type. */ + .netif_hw_addr_size = sizeof(fnet_mac_addr_t), + .netif_init = fnet_enet_init, /* Initialization function.*/ + .netif_release = fnet_enet_release, /* Shutdown function.*/ +#if FNET_CFG_IP4 + .netif_output_ip4 = fnet_eth_output_ip4, /* IPv4 Transmit function.*/ +#endif + .netif_change_addr_notify = fnet_eth_change_addr_notify, /* Address change notification function.*/ + .netif_drain = fnet_eth_drain, /* Drain function.*/ + .netif_get_hw_addr = fnet_enet_get_hw_addr, + .netif_set_hw_addr = fnet_enet_set_hw_addr, + .netif_is_connected = fnet_enet_is_connected, + .netif_get_statistics = fnet_enet_get_statistics +#if FNET_CFG_MULTICAST +#if FNET_CFG_IP4 + , .netif_multicast_join_ip4 = fnet_eth_multicast_join_ip4 + , .netif_multicast_leave_ip4 = fnet_eth_multicast_leave_ip4 +#endif +#if FNET_CFG_IP6 + , .netif_multicast_join_ip6 = fnet_eth_multicast_join_ip6 + , .netif_multicast_leave_ip6 = fnet_eth_multicast_leave_ip6 +#endif +#endif +#if FNET_CFG_IP6 + , .netif_output_ip6 = fnet_eth_output_ip6 /* IPv6 Transmit function.*/ +#endif +}; + + +//TBD move to the structure +#define FNET_ENET_BUF_SIZE (((FNET_CFG_CPU_ETH0_MTU>FNET_CFG_CPU_ETH1_MTU)?FNET_CFG_CPU_ETH0_MTU:FNET_CFG_CPU_ETH1_MTU)+FNET_ETH_HDR_SIZE+FNET_ETH_CRC_SIZE) /* Ring Buffer size in bytes.*/ + +typedef uint8_t fnet_enet_buffer_t[SDK_SIZEALIGN(FNET_ENET_BUF_SIZE, ENET_BUFF_ALIGNMENT)]; +AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t rxBuffDescrip[FNET_CFG_CPU_ETH_RX_BUFS_MAX], ENET_BUFF_ALIGNMENT); +AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t txBuffDescrip[FNET_CFG_CPU_ETH_TX_BUFS_MAX], ENET_BUFF_ALIGNMENT); +SDK_ALIGN(static fnet_enet_buffer_t rxDataBuff[FNET_CFG_CPU_ETH_RX_BUFS_MAX], ENET_BUFF_ALIGNMENT); +SDK_ALIGN(static fnet_enet_buffer_t txDataBuff[FNET_CFG_CPU_ETH_TX_BUFS_MAX], ENET_BUFF_ALIGNMENT); + +/************************************************************************ +* Global Data Structures +*************************************************************************/ + +fnet_enet_if_t fnet_enet0_if = {.base = ENET, /* Peripheral ENET base pointer */ + .vector_number = FNET_CFG_CPU_ETH0_VECTOR_NUMBER, + .phy_addr = FNET_CFG_CPU_ETH0_PHY_ADDR + }; + +/************************************************************************ +* DESCRIPTION: ENET Ethernet module initialization. +*************************************************************************/ +static fnet_return_t fnet_enet_init(fnet_netif_t *netif) +{ + fnet_return_t result = FNET_ERR; + fnet_enet_if_t *enet_if; + enet_config_t enet_config; /* ENET driver configuration */ + enet_buffer_config_t enet_buffer_config; /* ENET driver buffer configuration */ + uint32_t rxBufferStartAddr[FNET_CFG_CPU_ETH_RX_BUFS_MAX]; /* Start addresses of the rx buffers. */ + fnet_index_t i; + + enet_if = (fnet_enet_if_t *)(((fnet_eth_if_t *)(netif->netif_prv))->eth_prv); + + /* Clear statistics. */ + fnet_memset_zero(&enet_if->statistics, sizeof(struct fnet_netif_statistics)); + +#if FNET_CFG_CPU_ETH_IO_INIT + fnet_eth_io_init(); +#endif + /* Clear descriptors */ + fnet_memset_zero(rxBuffDescrip, sizeof(rxBuffDescrip)); + fnet_memset_zero(txBuffDescrip, sizeof(rxBuffDescrip)); + /* Phy initialization */ + if (fnet_enet_phy_init(enet_if) == FNET_OK) + { + /* Init start address of the rx buffers.*/ + for (i = 0; i < FNET_CFG_CPU_ETH_RX_BUFS_MAX; i++) + { + rxBufferStartAddr[i] = (uint32_t) & (rxDataBuff[i][0]); + } + + /* Init buffer descriptor configure structure. */ + enet_buffer_config.rxRingLen = FNET_CFG_CPU_ETH_RX_BUFS_MAX; /* The length of receive buffer descriptor ring. */ + enet_buffer_config.txRingLen = FNET_CFG_CPU_ETH_TX_BUFS_MAX; /* The length of transmit buffer descriptor ring. */ + enet_buffer_config.txDescStartAddrAlign = &txBuffDescrip[0]; /* Aligned transmit descriptor start address. */ + enet_buffer_config.txDescTailAddrAlign = &txBuffDescrip[0]; /* Aligned transmit descriptor tail address. */ + enet_buffer_config.rxDescStartAddrAlign = &rxBuffDescrip[0]; /* Aligned receive descriptor start address. */ + enet_buffer_config.rxDescTailAddrAlign = &rxBuffDescrip[FNET_CFG_CPU_ETH_RX_BUFS_MAX]; /* Aligned receive descriptor tail address. */ + enet_buffer_config.rxBufferStartAddr = rxBufferStartAddr; /* Start addresses of the rx buffers. */ + enet_buffer_config.rxBuffSizeAlign = sizeof(fnet_enet_buffer_t); /* Aligned receive data buffer size. */ + + ENET_GetDefaultConfig(&enet_config); + +#if FNET_CFG_CPU_ETH_PROMISCUOUS + enet_config.specialControl |= kENET_PromiscuousEnable; /* Receive all */ +#else + enet_config.specialControl |= kENET_MulticastAllEnable; /* Pass all multicast. */ +#endif + + enet_if->txIdx = 0; + + /* Install ENET interrupt handler.*/ + result = fnet_isr_vector_init(enet_if->vector_number, fnet_enet_isr_handler_top, fnet_enet_isr_handler_bottom, FNET_CFG_CPU_ETH_VECTOR_PRIORITY, netif); + + /* Initializes the ENET module. */ + ENET_Init(enet_if->base, &enet_config, FNET_NULL, kCLOCK_CoreSysClk); + + /* Enable ENET interrupt */ + ENET_EnableInterrupts(enet_if->base, kENET_DmaRx | kENET_DmaTx); + /* Create handler. */ + ENET_CreateHandler(enet_if->base, &enet_if->handle, &enet_config, &enet_buffer_config, fnet_enet_callback, 0); + + /* Initialize for all ENET descriptors. + * the descriptor initialization should be called after ENET_Init(), ENET_EnableInterrupts()*/ + if(ENET_DescriptorInit(enet_if->base, &enet_config, &enet_buffer_config) != kStatus_Success) + { + FNET_DEBUG_ENET("[ENET] Descriptor init is failed"); + } + else + { + /* Starts the ENET rx/tx. */ + ENET_StartRxTx(enet_if->base, 1, 1); + + result = FNET_OK; + } + } + else + { + FNET_DEBUG_ENET("[ENET] PHY init is failed"); + } + + return result; +} + +static void fnet_enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, uint8_t channel, void *param) +{ + /*DUMB function to avoid assert in SDK ENET driver */ +} + +/************************************************************************ +* DESCRIPTION: ENET Ethernet module release. +*************************************************************************/ +static void fnet_enet_release(fnet_netif_t *netif) +{ + fnet_enet_if_t *enet_if = (fnet_enet_if_t *)((fnet_eth_if_t *)(netif->netif_prv))->eth_prv; + + ENET_Deinit(enet_if->base); + + fnet_isr_unregister(enet_if->vector_number); + + fnet_eth_release(netif); /* Common Ethernet-interface release.*/ +} + +/************************************************************************ +* DESCRIPTION: Ethernet input function. +*************************************************************************/ +static void fnet_enet_input(fnet_netif_t *netif) +{ + fnet_enet_if_t *enet_if = (fnet_enet_if_t *)((fnet_eth_if_t *)(netif->netif_prv))->eth_prv; + uint32_t length = 0; + fnet_uint8_t *frame; + enet_handle_t *handle = &enet_if->handle; + + enet_rx_bd_ring_t *rxBdRing = &handle->rxBdRing[0]; + enet_rx_bd_struct_t *rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; /* Get current RX descriptor */ + +#if FNET_CFG_CPU_CACHE_INVALIDATE + fnet_cpu_cache_invalidate(); +#endif + + /* While buffer NOT(empty or rx in progress)*/ + while((rxDesc->control & ENET_RXDESCRIP_WR_OWN_MASK) == 0u) + { + /* If NOT(buffer is last in the frame) */ + if ((rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK) == 0u) + { + /* Skip the splitted frame. */ + do /* Keep going until we find the last one. */ + { + fnet_enet_rx_buf_next(enet_if); + rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; + } + while ((rxDesc->control & ENET_RXDESCRIP_WR_LD_MASK) == 0u); + } + else + { + if (rxDesc->control & ENET_RXDESCRIP_WR_ERRSUM_MASK) /* Any Error. */ + { + /* Drop packet */ + goto NEXT_FRAME; + } + + length = rxDesc->control & ENET_RXDESCRIP_WR_PACKETLEN_MASK; + frame = (void *)rxDesc->buff1Addr; + + /* Ethernet input.*/ + fnet_eth_input( netif, frame, length); + } + + NEXT_FRAME: + fnet_enet_rx_buf_next(enet_if); + rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; + } +} + +/************************************************************************ +* DESCRIPTION: Goes not the next Rx buffer. +*************************************************************************/ +static void fnet_enet_rx_buf_next( fnet_enet_if_t *enet_if) +{ + ENET_Type *base = enet_if->base; + enet_handle_t *handle = &enet_if->handle; + + enet_rx_bd_ring_t *rxBdRing = &handle->rxBdRing[0]; + enet_rx_bd_struct_t *rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx; /* Get current RX descriptor */ + + /* Increment current available receive buffer descriptor pointer to the next one. */ + rxBdRing->rxGenIdx++; + if (rxBdRing->rxGenIdx >= rxBdRing->rxRingLen) + { + rxBdRing->rxGenIdx = 0; + } + /* Updates the receive buffer descriptor. */ + //DM ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable); + rxDesc->control = ENET_RXDESCRIP_RD_OWN_MASK | /* Own bit - Ethernet block's DMA owns the descriptor */ + ENET_RXDESCRIP_RD_BUFF1VALID_MASK | /* Buffer 1 address valid */ + ENET_RXDESCRIP_RD_IOC_MASK; /* Interrupt enabled on completion */ + rxDesc->buff2Addr = 0; /* Just in case. We support only Buffer 1. */ + + /* The Rx process is suspended. To resume processing Rx data, the application + should change the ownership and issue a receive poll demand command. If this command is + not issued, the Rx process resumes when the next recognized incoming packet is received. + In ring mode, the application should advance the receive tail pointer register of a channel.*/ + if (base->DMA_CH[0].DMA_CHX_STAT & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) + { + /* Set command for rx. */ + base->DMA_CH[0].DMA_CHX_RXDESC_TAIL_PTR = base->DMA_CH[0].DMA_CHX_RXDESC_TAIL_PTR; + } +} + +/************************************************************************ +* DESCRIPTION: Ethernet low-level output function. +*************************************************************************/ +void fnet_enet_output(fnet_netif_t *netif, fnet_netbuf_t *nb) +{ + fnet_enet_if_t *enet_if = (fnet_enet_if_t *)((fnet_eth_if_t *)(netif->netif_prv))->eth_prv; + fnet_uint8_t *tx_buffer; + + if(nb && (nb->total_length >= FNET_ETH_HDR_SIZE)) + { + /* Buffer descriptors will be updated by DMA, so we need to invalidate cache */ + fnet_cpu_cache_invalidate(); + + /* Wait for a free TX descriptor */ + while(ENET_IsTxDescriptorDmaOwn(&txBuffDescrip[enet_if->txIdx])) + {} /* If you are blocked here forever, there is a communication issue between ENET and PHY.*/ + + tx_buffer = txDataBuff[enet_if->txIdx]; + enet_if->txIdx = (enet_if->txIdx + 1U) % FNET_CFG_CPU_ETH_TX_BUFS_MAX; + + fnet_netbuf_to_buf(nb, 0u, FNET_NETBUF_COPYALL, tx_buffer); + + if (ENET_SendFrame(enet_if->base, &enet_if->handle, tx_buffer, nb->total_length) != kStatus_Success) + { + FNET_DEBUG_ENET("[ENET] TX is failed"); + } + + enet_if->statistics.tx_packet++; + } + + fnet_netbuf_free_chain(nb); +} + +/************************************************************************ +* DESCRIPTION: This function polls ENET driver. +* !!!! Used only for debug needs. !!!!! +*************************************************************************/ +void fnet_enet_poll(fnet_netif_desc_t netif_desc) +{ + fnet_netif_t *netif = (fnet_netif_t *)netif_desc; + + fnet_isr_lock(); + + fnet_enet_input(netif); + + fnet_isr_unlock(); +} + +/************************************************************************ +* DESCRIPTION: Sets MAC address. +*************************************************************************/ +static fnet_return_t fnet_enet_set_hw_addr(fnet_netif_t *netif, fnet_uint8_t *hw_addr) +{ + fnet_enet_if_t *enet_if; + fnet_return_t result; + + /* Set the source address for the controller. */ + if(netif + && (netif->netif_api->netif_type == FNET_NETIF_TYPE_ETHERNET) + && ((enet_if = (fnet_enet_if_t *)((fnet_eth_if_t *)(netif->netif_prv))->eth_prv) != 0) + && hw_addr + && (fnet_memcmp(hw_addr, fnet_eth_null_addr, sizeof(fnet_mac_addr_t))) + && (fnet_memcmp(hw_addr, fnet_eth_broadcast, sizeof(fnet_mac_addr_t))) + && ((hw_addr[0] & 0x01U) == 0x00U)) /* Most significant nibble should be always even.*/ + { + /* Set Macaddr */ + ENET_SetMacAddr(enet_if->base, hw_addr); + + fnet_eth_change_addr_notify(netif); + + result = FNET_OK; + } + else + { + result = FNET_ERR; + } + + return result; +} + +/************************************************************************ +* DESCRIPTION: This function reads HW address. +*************************************************************************/ +static fnet_return_t fnet_enet_get_hw_addr(fnet_netif_t *netif, fnet_uint8_t *hw_addr) +{ + fnet_enet_if_t *enet_if; + fnet_return_t result; + + if(netif && (netif->netif_api->netif_type == FNET_NETIF_TYPE_ETHERNET) + && ((enet_if = (fnet_enet_if_t *)((fnet_eth_if_t *)(netif->netif_prv))->eth_prv) != FNET_NULL) + && (hw_addr) ) + { + fnet_enet_get_mac_addr(enet_if, (fnet_mac_addr_t *) hw_addr); + result = FNET_OK; + } + else + { + result = FNET_ERR; + } + + return result; +} + +/************************************************************************ +* DESCRIPTION: This function reads MAC address. +*************************************************************************/ +static void fnet_enet_get_mac_addr(fnet_enet_if_t *enet_if, fnet_mac_addr_t *mac_addr) +{ +#if 0 /* Driver function returns swapped/wrong address */ + ENET_GetMacAddr(enet_if->base, (uint8_t *)mac_addr); +#else + fnet_uint32_t address; + uint8_t *hw_addr = (uint8_t *)mac_addr; + + /* Physical address lower register. */ + address = enet_if->base->MAC_ADDR_LOW; + hw_addr[3] = 0xFFU & (address >> 24U); + hw_addr[2] = 0xFFU & (address >> 16U); + hw_addr[1] = 0xFFU & (address >> 8U); + hw_addr[0] = 0xFFU & address; + + /* Physical address high register. */ + address = enet_if->base->MAC_ADDR_HIGH; + hw_addr[5] = 0xFFU & (address >> 8U); + hw_addr[4] = 0xFFU & address; +#endif +} + +/************************************************************************ +* DESCRIPTION: Returns Ethernet statistics information +*************************************************************************/ +static fnet_return_t fnet_enet_get_statistics(fnet_netif_t *netif, struct fnet_netif_statistics *statistics) +{ + fnet_enet_if_t *enet_if; + fnet_return_t result = FNET_ERR; + + if(netif && (netif->netif_api->netif_type == FNET_NETIF_TYPE_ETHERNET)) + { + enet_if = (fnet_enet_if_t *)((fnet_eth_if_t *)(netif->netif_prv))->eth_prv; + + *statistics = enet_if->statistics; + + result = FNET_OK; + } + + return result; +} + +/************************************************************************ +* DESCRIPTION: Top Ethernet receive frame interrupt handler. +* Clear event flag +*************************************************************************/ +static void fnet_enet_isr_handler_top (void *cookie) +{ + fnet_enet_if_t *enet_if = (fnet_enet_if_t *)((fnet_eth_if_t *)(((fnet_netif_t *)cookie)->netif_prv))->eth_prv; + + ENET_IRQHandler(enet_if->base, &enet_if->handle); /* SDK ENET driver IRQ */ +} + +/************************************************************************ +* DESCRIPTION: This function implements the Ethernet receive +* frame interrupt handler. +*************************************************************************/ +static void fnet_enet_isr_handler_bottom (void *cookie) +{ + fnet_netif_t *netif = (fnet_netif_t *)cookie; + + fnet_isr_lock(); + + fnet_enet_input(netif); + + fnet_isr_unlock(); +} + +/************************************************************************ +* PHY/MII Staff +*************************************************************************/ + +/************************************************************************ +* DESCRIPTION: PHY initialization/reset. +*************************************************************************/ +static fnet_return_t fnet_enet_phy_init(fnet_enet_if_t *enet_if) +{ + fnet_uint16_t reg_value = 0; + uint32_t counter; + fnet_return_t result = FNET_ERR; + + /* Enable ENET SMI(serial management interface)- MII management interface clock. */ + CLOCK_EnableClock(kCLOCK_Eth); + + /* Set the ENET SMI(serial management interface)- MII management interface.*/ + ENET_SetSMI(enet_if->base); + + /* Looking for a valid PHY address. */ +#if FNET_CFG_CPU_ETH_PHY_ADDR_DISCOVER + fnet_enet_phy_discover_addr (enet_if, enet_if->phy_addr); +#endif + + /* == Reset PHY, wait for completion. == */ + fnet_enet_mii_write(enet_if, FNET_ETH_MII_REG_CR, FNET_ETH_MII_REG_CR_RESET); + for (counter = FNET_ENET_MII_TIMEOUT; counter > 0; counter--) + { + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_CR, ®_value); + if(reg_value & FNET_ETH_MII_REG_CR_RESET) + { + break; /* Completed */ + } + } + + if(counter) /* No timeout */ + { + /*== Start auto-negotiation == */ + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_CR, ®_value); + fnet_enet_mii_write(enet_if, FNET_ETH_MII_REG_CR, (fnet_uint16_t)(reg_value | FNET_ETH_MII_REG_CR_ANE | FNET_ETH_MII_REG_CR_ANE_RESTART)); + +#if FNET_CFG_CPU_ETH_ATONEGOTIATION_TIMEOUT + /* Wait for auto-negotiation completion. */ + { + fnet_time_t last_time = fnet_timer_get_ms(); + + do + { + /* Read Basic Mode Status Register*/ + if(fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_SR, ®_value) == FNET_ERR) + { + break; + } + + /* Auto-Negotiation Complete */ + if(reg_value & FNET_ETH_MII_REG_SR_AN_COMPLETE) + { + break; + } + } + while((fnet_timer_get_ms() - last_time) < FNET_CFG_CPU_ETH_ATONEGOTIATION_TIMEOUT); + } +#endif /* FNET_CFG_CPU_ETH_ATONEGOTIATION_TIMEOUT */ + result = FNET_OK; + } + + return result; +} + +/************************************************************************ +* DESCRIPTION: Looking for a valid PHY address. +*************************************************************************/ +#if FNET_CFG_CPU_ETH_PHY_ADDR_DISCOVER +static void fnet_enet_phy_discover_addr (fnet_enet_if_t *enet_if, fnet_uint8_t phy_addr_start) +{ + fnet_uint8_t i; + fnet_uint8_t phy_addr = enet_if->phy_addr; /* Save old value just in case the discover + * is failed, in case communication with + * the PHY via MDIO is not possible.*/ + + for (i = (fnet_uint8_t)phy_addr_start; i < 32U; i++) + { + fnet_uint16_t id; + + enet_if->phy_addr = i; + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_IDR1, &id); + + if (!((id == 0U) || (id == 0xffffU) || (id == 0x7fffU))) + { + return; /* FHY address is discovered.*/ + } + } + enet_if->phy_addr = phy_addr; +} +#endif + +/************************************************************************ +* DESCRIPTION: Read a value from a PHY's MII register. +* reg_addr < address of the register in the PHY +* data < Pointer to storage for the Data to be read from the PHY register (passed by reference) +* Return FNET_ERR on failure, FNET_OK on success +*************************************************************************/ +fnet_return_t fnet_enet_mii_read(fnet_enet_if_t *enet_if, fnet_uint32_t reg_addr, fnet_uint16_t *data) +{ + fnet_return_t result = FNET_ERR; + uint32_t counter; + + ENET_StartSMIRead(enet_if->base, enet_if->phy_addr, reg_addr); + + /* Wait for MII complete. */ + for (counter = FNET_ENET_MII_TIMEOUT; counter > 0; counter--) + { + if(ENET_IsSMIBusy(enet_if->base) == false) + { + break; /* Result is ready */ + } + } + + if(counter) + { + *data = ENET_ReadSMIData(enet_if->base); + result = FNET_OK; + } + + return result; +} + +/************************************************************************ +* DESCRIPTION: Write a value to a PHY's MII register. +* reg_addr = address of the register in the PHY +* data = Data to be writen to the PHY register (passed by reference) +* Return FNET_ERR on failure (timeout), FNET_OK on success +*************************************************************************/ +fnet_return_t fnet_enet_mii_write(fnet_enet_if_t *enet_if, fnet_uint32_t reg_addr, fnet_uint16_t data) +{ + fnet_return_t result = FNET_ERR; + fnet_uint32_t counter; + + ENET_StartSMIWrite(enet_if->base, enet_if->phy_addr, reg_addr, data); + + /* Wait for MII complete. */ + for (counter = FNET_ENET_MII_TIMEOUT; counter > 0; counter--) + { + if(ENET_IsSMIBusy(enet_if->base) == false) + { + break; /* Completed. */ + } + } + + if(counter) + { + result = FNET_OK; + } + + return result; +} + +/************************************************************************ +* DESCRIPTION: Link status. +*************************************************************************/ +static fnet_bool_t fnet_enet_is_connected(fnet_netif_t *netif) +{ + fnet_uint16_t data; + fnet_enet_if_t *enet_if; + fnet_bool_t res = FNET_FALSE; + + enet_if = (fnet_enet_if_t *)((fnet_eth_if_t *)(netif->netif_prv))->eth_prv; + + /* Some PHY (e.g.DP8340) returns "unconnected" and than "connected" state + * just to show that was transition event from one state to another. + * As we need only curent state, read 2 times and returtn + * the current/latest state. + */ + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_SR, &data); + + if (fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_SR, &data) == FNET_OK) + { + res = (((data & FNET_ETH_MII_REG_SR_LINK_STATUS) != 0u) ? FNET_TRUE : FNET_FALSE); + } + else /* Return previous value in case read PHY error. */ + { + res = netif->is_connected; + } + + return res; +} + +/************************************************************************ +* DESCRIPTION: Compute the CRC-32 polynomial on the multicast group +*************************************************************************/ +#if FNET_CFG_MULTICAST + +/************************************************************************ +* DESCRIPTION: Joins a multicast group on ENET interface. +*************************************************************************/ +void fnet_enet_multicast_join(fnet_netif_t *netif, fnet_mac_addr_t multicast_addr ) +{ + //TBD +} + +/************************************************************************ +* DESCRIPTION: Leavess a multicast group on ENET interface. +*************************************************************************/ +void fnet_enet_multicast_leave(fnet_netif_t *netif, fnet_mac_addr_t multicast_addr ) +{ + //TBD +} + +#endif /*FNET_CFG_MULTICAST*/ + +/************************************************************************ +* DESCRIPTION: Prints all MII register. +* !!!! Used only for debug needs. !!!!! +*************************************************************************/ +void fnet_enet_debug_mii_print_regs(fnet_netif_t *netif) +{ + fnet_enet_if_t *enet_if; + fnet_uint16_t reg_value; + + if(netif->netif_api->netif_type == FNET_NETIF_TYPE_ETHERNET) + { + enet_if = (fnet_enet_if_t *)((fnet_eth_if_t *)(netif->netif_prv))->eth_prv; + + fnet_printf(" === MII registers ===\r\n"); + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_CR, ®_value); + fnet_printf("\tCR = 0x%04X\n", reg_value ); + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_SR, ®_value); + fnet_printf("\tSR = 0x%04X\n", reg_value ); + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_IDR1, ®_value); + fnet_printf("\tIDR1 = 0x%04X\n", reg_value ); + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_IDR2, ®_value); + fnet_printf("\tIDR2 = 0x%04X\n", reg_value ); + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_ANAR, ®_value); + fnet_printf("\tANAR = 0x%04X\n", reg_value ); + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_ANLPAR, ®_value); + fnet_printf("\tANLPAR = 0x%04X\n", reg_value ); + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_ANER, ®_value); + fnet_printf("\tANER = 0x%04X\n", reg_value ); + fnet_enet_mii_read(enet_if, FNET_ETH_MII_REG_ANNPTR, ®_value); + fnet_printf("\tANNPTR = 0x%04X\n", reg_value ); + } +} + +#endif /* FNET_LPC && FNET_CFG_CPU_ETH0 */ diff --git a/fnet_stack/port/netif/enet/fnet_enet.h b/fnet_stack/port/netif/enet/fnet_enet.h new file mode 100644 index 00000000..40af8be8 --- /dev/null +++ b/fnet_stack/port/netif/enet/fnet_enet.h @@ -0,0 +1,84 @@ +/************************************************************************** +* +* Copyright 2018 by Andrey Butok. FNET Community. +* +*************************************************************************** +* +* Licensed under the Apache License, Version 2.0 (the "License"); you may +* not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*************************************************************************** +* +* LPC ENET driver definitions. +* This is a prototype wrapper for LPC MCUX driver. +* +***************************************************************************/ +#ifndef _FNET_ENET_H_ +#define _FNET_ENET_H_ + +#include "fnet.h" +#if (FNET_LPC && FNET_CFG_CPU_ETH0) + +#include "stack/fnet_eth_prv.h" + +/* SDK */ +#include "fsl_enet.h" + +#define FNET_ENET_MII_TIMEOUT (0x10000U) /* Timeout counter for MII communications.*/ +#define FNET_ENET_TIMEOUT (0x10000U) /* Timeout counter for ENET operations.*/ + +/* ENET Module control data structure */ +typedef struct +{ + ENET_Type *base; + enet_handle_t handle; + uint8_t txIdx; /* TX buffer index */ + //TBD + fnet_uint32_t vector_number; /* Vector number of the Ethernet interrupt.*/ + fnet_uint8_t phy_addr; + struct fnet_netif_statistics statistics; /* Statistic counters.*/ +} fnet_enet_if_t; + +/* ENET driver API */ +extern const fnet_netif_api_t fnet_enet_api; +/* Ethernet specific control data structure.*/ +extern fnet_enet_if_t fnet_enet0_if; + +/************************************************************************ +* Function Prototypes +*************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/* Ethernet IO initialization.*/ +#if FNET_CFG_CPU_ETH_IO_INIT +void fnet_eth_io_init(void); +#endif +void fnet_enet_output(fnet_netif_t *netif, fnet_netbuf_t *nb); +#if FNET_CFG_MULTICAST +void fnet_enet_multicast_join(fnet_netif_t *netif, fnet_mac_addr_t multicast_addr); +void fnet_enet_multicast_leave(fnet_netif_t *netif, fnet_mac_addr_t multicast_addr); +#endif + +/* For debug needs.*/ +void fnet_enet_poll(fnet_netif_desc_t netif_desc); +fnet_return_t fnet_enet_mii_read(fnet_enet_if_t *enet_if, fnet_uint32_t reg_addr, fnet_uint16_t *data); +fnet_return_t fnet_enet_mii_write(fnet_enet_if_t *enet_if, fnet_uint32_t reg_addr, fnet_uint16_t data); + +#if defined(__cplusplus) +} +#endif + +#endif /* FNET_LPC && FNET_CFG_CPU_ETH0*/ + +#endif /*_FNET_enet_H_*/ diff --git a/fnet_stack/port/cpu/netif/fec/fnet_fec.c b/fnet_stack/port/netif/fec/fnet_fec.c similarity index 94% rename from fnet_stack/port/cpu/netif/fec/fnet_fec.c rename to fnet_stack/port/netif/fec/fnet_fec.c index 2649e90b..81d70805 100644 --- a/fnet_stack/port/cpu/netif/fec/fnet_fec.c +++ b/fnet_stack/port/netif/fec/fnet_fec.c @@ -267,52 +267,52 @@ static fnet_return_t fnet_fec_init(fnet_netif_t *netif) /* Set the transceiver interface.*/ fec_if->reg->RCR = FNET_FEC_RCR_MII_MODE | FNET_FEC_RCR_MAX_FL(FNET_FEC_BUF_SIZE) #if FNET_CFG_CPU_ETH_RMII /*Kinetis, Modelo*/ - /* Set the transceiver interface to RMII mode (for Kinetis).*/ - | FNET_FEC_RCR_RMII_MODE + /* Set the transceiver interface to RMII mode (for Kinetis).*/ + | FNET_FEC_RCR_RMII_MODE #if FNET_CFG_CPU_ETH_RMII_10T - | FNET_FEC_RCR_RMII_10T + | FNET_FEC_RCR_RMII_10T #endif #endif /* FNET_CFG_CPU_ETH_RMII */ #if FNET_CFG_CPU_S32R274 - | FNET_FEC_RCR_RGMII_EN /* TBD: make it configurable */ + | FNET_FEC_RCR_RGMII_EN /* TBD: make it configurable */ #endif #if FNET_CFG_CPU_ETH_PROMISCUOUS - | FNET_FEC_RCR_PROM /* Enable promiscuous mode.*/ + | FNET_FEC_RCR_PROM /* Enable promiscuous mode.*/ #endif #if !FNET_CFG_CPU_ETH_FULL_DUPLEX - | FNET_FEC_RCR_DRT /* Enable Half duplex.*/ + | FNET_FEC_RCR_DRT /* Enable Half duplex.*/ #endif - ; + ; /* Configure the transmit block.*/ fec_if->reg->TCR = 0U #if FNET_CFG_CPU_ETH_FULL_DUPLEX - | FNET_FEC_TCR_FDEN /* Enable Full duplex.*/ + | FNET_FEC_TCR_FDEN /* Enable Full duplex.*/ #endif - ; + ; #if FNET_CFG_CPU_ETH_HW_TX_IP_CHECKSUM || FNET_CFG_CPU_ETH_HW_TX_PROTOCOL_CHECKSUM || FNET_CFG_CPU_ETH_HW_RX_IP_CHECKSUM || FNET_CFG_CPU_ETH_HW_RX_PROTOCOL_CHECKSUM || FNET_CFG_CPU_ETH_HW_RX_MAC_ERR /* Transmit Accelerator Function Configuration. */ fec_if->reg->TACC = 0 #if FNET_CFG_CPU_ETH_HW_TX_IP_CHECKSUM - | FNET_FEC_TACC_IPCHK /* Insert IP header checksum.*/ + | FNET_FEC_TACC_IPCHK /* Insert IP header checksum.*/ #endif #if FNET_CFG_CPU_ETH_HW_TX_PROTOCOL_CHECKSUM - | FNET_FEC_TACC_PROCHK /* Insert Protocol checksum.*/ + | FNET_FEC_TACC_PROCHK /* Insert Protocol checksum.*/ #endif - ; + ; /* Receive Accelerator Function Configuration. */ fec_if->reg->RACC = 0 #if FNET_CFG_CPU_ETH_HW_RX_IP_CHECKSUM - | FNET_FEC_RACC_IPDIS /* Discard of frames with wrong IPv4 header checksum.*/ + | FNET_FEC_RACC_IPDIS /* Discard of frames with wrong IPv4 header checksum.*/ #endif #if FNET_CFG_CPU_ETH_HW_RX_PROTOCOL_CHECKSUM - | FNET_FEC_RACC_PRODIS /* Discard of frames with wrong protocol checksum.*/ + | FNET_FEC_RACC_PRODIS /* Discard of frames with wrong protocol checksum.*/ #endif #if FNET_CFG_CPU_ETH_HW_RX_MAC_ERR - | FNET_FEC_RACC_LINEDIS /* Discard of frames with MAC layer errors.*/ + | FNET_FEC_RACC_LINEDIS /* Discard of frames with MAC layer errors.*/ #endif - | FNET_FEC_RACC_PADREM /* Padding removal for short IP frames.*/ - ; + | FNET_FEC_RACC_PADREM /* Padding removal for short IP frames.*/ + ; #if FNET_CFG_CPU_ETH_HW_TX_IP_CHECKSUM || FNET_CFG_CPU_ETH_HW_TX_PROTOCOL_CHECKSUM /* Transmit FIFO Watermark Register. @@ -489,7 +489,7 @@ static void fnet_fec_input(fnet_netif_t *netif) fnet_cpu_cache_invalidate(); #endif - /* While buffer !(empty or rx in progress)*/ + /* While buffer NOT(empty or rx in progress)*/ while((fec_if->rx_buf_desc_cur->status & FNET_HTONS(FNET_FEC_RX_BD_E)) == 0u) { @@ -516,7 +516,7 @@ static void fnet_fec_input(fnet_netif_t *netif) | FNET_FEC_RX_BD_CR /* CRC Error.*/ | FNET_FEC_RX_BD_OV /* FIFO overrun.*/ | FNET_FEC_RX_BD_TR /* Frame is truncated.*/ - )) != 0u ) + )) != 0u ) { goto NEXT_FRAME; } @@ -569,7 +569,7 @@ fnet_size_t fnet_fec_input_frame(fnet_netif_t *netif, fnet_uint8_t *buf, fnet_si | FNET_FEC_RX_BD_CR /* CRC Error.*/ | FNET_FEC_RX_BD_OV /* FIFO overrun.*/ | FNET_FEC_RX_BD_TR /* Frame is truncated.*/ - )) != 0u ) + )) != 0u ) { goto NEXT_FRAME; } @@ -632,9 +632,9 @@ static void fnet_fec_rx_buf_next( fnet_fec_if_t *fec_if) static void fnet_fec_checksum_clear(fnet_uint8_t *datagram, fnet_size_t datagram_size) { fnet_eth_header_t *eth_hdr = (fnet_eth_header_t *)datagram; - fnet_uint8_t *ip_hdr = datagram+sizeof(fnet_eth_header_t); + fnet_uint8_t *ip_hdr = datagram + sizeof(fnet_eth_header_t); fnet_uint8_t protocol = 0; - fnet_size_t ip_hdr_size; + fnet_size_t ip_hdr_size = 0; fnet_uint8_t *prot_hdr; /* IPv4 */ @@ -698,8 +698,9 @@ void fnet_fec_output(fnet_netif_t *netif, fnet_netbuf_t *nb) /* fec_if->tx_buf_desc_cur->status will be updated by FEC-DMA so we need to invalidate cache */ fnet_cpu_cache_invalidate(); + /* Wait for a free TX descriptor */ while((fec_if->tx_buf_desc_cur->status & FNET_HTONS(FNET_FEC_TX_BD_R)) != 0u) - {} /* If you are blocked here forever, there is communication issue between ENET and PHY.*/ + {} /* If you are blocked here forever, there is a communication issue between ENET and PHY.*/ tx_buffer = (fnet_uint8_t *)fnet_ntohl((fnet_uint32_t)fec_if->tx_buf_desc_cur->buf_ptr); @@ -737,7 +738,7 @@ void fnet_fec_output(fnet_netif_t *netif, fnet_netbuf_t *nb) fec_if->tx_buf_desc_cur++; } - while(fec_if->reg->TDAR) /* Workaround.*/ + while(fec_if->reg->TDAR) /* Workaround for ENET module bug.*/ {} #ifdef FNET_FEC_TEST_RACE_CONDITION @@ -947,7 +948,7 @@ static void fnet_fec_phy_discover_addr (fnet_fec_if_t *fec_if, fnet_uint8_t phy_ { fnet_uint8_t i; fnet_uint8_t phy_addr = fec_if->phy_addr; /* Save old value just in case the discover - * is failed, in case ommunication with + * is failed, in case communication with * the PHY via MDIO is not possible.*/ for (i = (fnet_uint8_t)phy_addr_start; i < 32U; i++) @@ -987,11 +988,11 @@ fnet_return_t fnet_fec_mii_read(fnet_fec_if_t *fec_if, fnet_uint32_t reg_addr, f /* Kick-off the MII read */ fec_if->reg_phy->MMFR = (fnet_vuint32_t)(0U - | FNET_FEC_MMFR_ST_01 - | FNET_FEC_MMFR_OP_READ - | FNET_FEC_MMFR_PA((fnet_uint32_t)fec_if->phy_addr) - | FNET_FEC_MMFR_RA(reg_addr) - | FNET_FEC_MMFR_TA_10); + | FNET_FEC_MMFR_ST_01 + | FNET_FEC_MMFR_OP_READ + | FNET_FEC_MMFR_PA((fnet_uint32_t)fec_if->phy_addr) + | FNET_FEC_MMFR_RA(reg_addr) + | FNET_FEC_MMFR_TA_10); /* Poll for the MII interrupt */ for (timeout = 0U; timeout < FNET_FEC_MII_TIMEOUT; timeout++) @@ -1023,8 +1024,8 @@ fnet_return_t fnet_fec_mii_read(fnet_fec_if_t *fec_if, fnet_uint32_t reg_addr, f /************************************************************************ * DESCRIPTION: Write a value to a PHY's MII register. -* reg_addr < address of the register in the PHY -* data < Data to be writen to the PHY register (passed by reference) +* reg_addr = address of the register in the PHY +* data = Data to be writen to the PHY register (passed by reference) * Return FNET_ERR on failure (timeout), FNET_OK on success *************************************************************************/ fnet_return_t fnet_fec_mii_write(fnet_fec_if_t *fec_if, fnet_uint32_t reg_addr, fnet_uint16_t data) @@ -1042,12 +1043,12 @@ fnet_return_t fnet_fec_mii_write(fnet_fec_if_t *fec_if, fnet_uint32_t reg_addr, /* Kick-off the MII write */ fec_if->reg_phy->MMFR = (fnet_vuint32_t)(0U - | FNET_FEC_MMFR_ST_01 - | FNET_FEC_MMFR_OP_WRITE - | FNET_FEC_MMFR_PA((fnet_uint32_t)fec_if->phy_addr) - | FNET_FEC_MMFR_RA((fnet_uint32_t)reg_addr) - | FNET_FEC_MMFR_TA_10 - | (fnet_uint32_t)(data & 0xffffU)); + | FNET_FEC_MMFR_ST_01 + | FNET_FEC_MMFR_OP_WRITE + | FNET_FEC_MMFR_PA((fnet_uint32_t)fec_if->phy_addr) + | FNET_FEC_MMFR_RA((fnet_uint32_t)reg_addr) + | FNET_FEC_MMFR_TA_10 + | (fnet_uint32_t)(data & 0xffffU)); /* Poll for the MII interrupt */ for (timeout = 0U; timeout < FNET_FEC_MII_TIMEOUT; timeout++) @@ -1208,7 +1209,6 @@ void fnet_fec_multicast_leave(fnet_netif_t *netif, fnet_mac_addr_t multicast_add /************************************************************************ * DESCRIPTION: This function polls fec driver. -* I has sence only if * !!!! Used only for debug needs. !!!!! *************************************************************************/ void fnet_fec_poll(fnet_netif_desc_t netif_desc) diff --git a/fnet_stack/port/cpu/netif/fec/fnet_fec.h b/fnet_stack/port/netif/fec/fnet_fec.h similarity index 99% rename from fnet_stack/port/cpu/netif/fec/fnet_fec.h rename to fnet_stack/port/netif/fec/fnet_fec.h index 490977e5..360a4093 100644 --- a/fnet_stack/port/cpu/netif/fec/fnet_fec.h +++ b/fnet_stack/port/netif/fec/fnet_fec.h @@ -179,8 +179,6 @@ #define FNET_FEC_MII_REG_SR_AN_ABILITY (0x0008U) #define FNET_FEC_MII_REG_SR_AN_COMPLETE (0x0020U) -#define FNET_FEC_MII_REG_ANAR_NEXT_PAGE (0x8000U) - #define FNET_FEC_MII_REG_CR_RESET (0x8000U) /* Resetting a port is accomplished by setting this bit to 1.*/ #define FNET_FEC_MII_REG_CR_LOOPBACK (0x4000U) /* Determines Digital Loopback Mode. */ #define FNET_FEC_MII_REG_CR_DATARATE (0x2000U) /* Speed Selection bit.*/ @@ -576,12 +574,12 @@ typedef struct { volatile fnet_fec_reg_t *reg; /* Pointer to the eth registers. */ volatile fnet_fec_reg_t *reg_phy; /* Pointer to the eth registers, used for comunication with phy. */ - fnet_uint32_t vector_number; /* Vector number of the Ethernet Receive Frame interrupt.*/ + fnet_uint32_t vector_number; /* Vector number of the Ethernet Receive Frame interrupt.*/ fnet_fec_buf_desc_t *tx_buf_desc; /* Tx Buffer Descriptors.*/ fnet_fec_buf_desc_t *tx_buf_desc_cur; /* Points to the descriptor of the current outcoming buffer.*/ fnet_fec_buf_desc_t *rx_buf_desc; /* Rx Buffer Descriptors.*/ fnet_fec_buf_desc_t *rx_buf_desc_cur; /* Points to the descriptor of the current incoming buffer.*/ - fnet_uint8_t phy_addr; + fnet_uint8_t phy_addr; /* PHY address */ fnet_uint8_t tx_buf_desc_num; /* Number of allocated Tx Buffer Descriptors.*/ fnet_uint8_t rx_buf_desc_num; /* Number of allocated Tx Buffer Descriptors.*/ #if FNET_CFG_MULTICAST @@ -615,7 +613,9 @@ extern "C" { #endif /* Ethernet IO initialization.*/ +#if FNET_CFG_CPU_ETH_IO_INIT void fnet_eth_io_init(void); +#endif /* Ethernet On-chip Physical Transceiver initialization and/or reset. */ void fnet_eth_phy_init(fnet_fec_if_t *ethif); void fnet_fec_output(fnet_netif_t *netif, fnet_netbuf_t *nb); diff --git a/fnet_stack/port/cpu/netif/qca/fnet_qca.c b/fnet_stack/port/netif/qca/fnet_qca.c similarity index 93% rename from fnet_stack/port/cpu/netif/qca/fnet_qca.c rename to fnet_stack/port/netif/qca/fnet_qca.c index 5f07b39a..91ee6ac0 100644 --- a/fnet_stack/port/cpu/netif/qca/fnet_qca.c +++ b/fnet_stack/port/netif/qca/fnet_qca.c @@ -72,15 +72,15 @@ static fnet_return_t fnet_qca_get_statistics(fnet_netif_t *netif, struct fnet_ne static fnet_bool_t fnet_qca_is_connected(fnet_netif_t *netif); static fnet_return_t fnet_qca_set_hw_addr(fnet_netif_t *netif, fnet_uint8_t *hw_addr); static fnet_return_t fnet_qca_wifi_connect(struct fnet_netif *netif, fnet_wifi_connect_params_t *params); -static fnet_return_t fnet_qca_wifi_access_point(fnet_netif_t *netif, fnet_wifi_access_point_params_t *params); +static fnet_return_t fnet_qca_wifi_access_point(fnet_netif_t *netif, fnet_wifi_access_point_params_t *params); static fnet_return_t fnet_qca_wifi_disconnect(struct fnet_netif *netif); static void fnet_qca_on_connect(uint8_t event, uint8_t devId, char *bssid, uint8_t bssConn); -static fnet_return_t fnet_qca_get_ssid_info(const char* ssid, WLAN_AUTH_MODE *auth_mode, WLAN_CRYPT_TYPE *encrypt_mode); +static fnet_return_t fnet_qca_get_ssid_info(const char *ssid, WLAN_AUTH_MODE *auth_mode, WLAN_CRYPT_TYPE *encrypt_mode); static fnet_wifi_op_mode_t fnet_qca_get_op_mode(struct fnet_netif *netif); static fnet_uint32_t fnet_qca_fw_get_version(struct fnet_netif *netif); static void fnet_qca_input(void *cookie); #if FNET_CFG_CPU_WIFI_FW_UPDATE -static fnet_return_t fnet_qca_wifi_fw_update(fnet_netif_t *netif, const fnet_uint8_t *fw_buffer, fnet_size_t fw_buffer_size); + static fnet_return_t fnet_qca_wifi_fw_update(fnet_netif_t *netif, const fnet_uint8_t *fw_buffer, fnet_size_t fw_buffer_size); #endif /************************************************************************ @@ -221,7 +221,7 @@ static fnet_return_t fnet_qca_init(fnet_netif_t *netif) { FNET_DEBUG_QCA("[QCA] Initialized\r\n"); - #if FNET_CFG_DEBUG_QCA && FNET_CFG_DEBUG +#if FNET_CFG_DEBUG_QCA && FNET_CFG_DEBUG { ATH_VERSION_STR versionstr; if(A_FAILED(qcom_get_versionstr(&versionstr))) @@ -244,7 +244,7 @@ static fnet_return_t fnet_qca_init(fnet_netif_t *netif) /* In this mode, target version number is not real.*/ } } - #endif +#endif qca_if->netif = netif; result = FNET_OK; @@ -264,10 +264,10 @@ static void fnet_qca_release(fnet_netif_t *netif) if(fnet_qca_if.netif) /* If initialized */ { - if((fnet_qca_if.is_connected == FNET_TRUE) - && (fnet_qca_wifi_disconnect(netif) != FNET_OK)) + if((fnet_qca_if.is_connected == FNET_TRUE) + && (fnet_qca_wifi_disconnect(netif) != FNET_OK)) { - FNET_DEBUG_QCA("ERROR: qcom_disconnect failed\r\n"); + FNET_DEBUG_QCA("ERROR: qcom_disconnect failed\r\n"); } ATHEROS_WIFI_IF.STOP(&wifiCtx); @@ -302,9 +302,9 @@ static void fnet_qca_print_ssid_info(QCA_SCAN_INFO_PTR scan_info) FNET_DEBUG_QCA("\t ssid = %s\r\n", temp_ssid); FNET_DEBUG_QCA("\t bssid = %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\r\n", scan_info->bssid[0], - scan_info->bssid[1], scan_info->bssid[2], - scan_info->bssid[3], scan_info->bssid[4], - scan_info->bssid[5]); + scan_info->bssid[1], scan_info->bssid[2], + scan_info->bssid[3], scan_info->bssid[4], + scan_info->bssid[5]); FNET_DEBUG_QCA("\t channel = %d\r\n", scan_info->channel); FNET_DEBUG_QCA("\t indicator = %d\r\n", scan_info->rssi); @@ -415,7 +415,7 @@ static void fnet_qca_print_ssid_info(QCA_SCAN_INFO_PTR scan_info) /************************************************************************ * DESCRIPTION: Scans for SSID authentication parameters. *************************************************************************/ -static fnet_return_t fnet_qca_get_ssid_info(const char* ssid, WLAN_AUTH_MODE *auth_mode, WLAN_CRYPT_TYPE *encrypt_mode) +static fnet_return_t fnet_qca_get_ssid_info(const char *ssid, WLAN_AUTH_MODE *auth_mode, WLAN_CRYPT_TYPE *encrypt_mode) { FNET_ASSERT(ssid != FNET_NULL); FNET_ASSERT(auth_mode != FNET_NULL); @@ -432,25 +432,25 @@ static fnet_return_t fnet_qca_get_ssid_info(const char* ssid, WLAN_AUTH_MODE *au FNET_DEBUG_QCA("[QCA] ERROR: qcom_power_set_mode failed\r\n"); } /* Set SSID filter */ - else if (qcom_set_ssid(FNET_QCA_DEVICE_ID, (QCOM_SSID*)ssid) != A_OK) + else if (qcom_set_ssid(FNET_QCA_DEVICE_ID, (QCOM_SSID *)ssid) != A_OK) { FNET_DEBUG_QCA("[QCA] ERROR: qcom_set_ssid failed\r\n"); } else { - for(i=0; (num_results == 0) && (i < FNET_CFG_QCA_SCAN_MAX); i++) + for(i = 0; (num_results == 0) && (i < FNET_CFG_QCA_SCAN_MAX); i++) { FNET_DEBUG_QCA("[QCA] Scanning for SSID \"%s\"...\r\n", ssid); /* Start BSS channel scan. */ - if(qcom_set_scan(FNET_QCA_DEVICE_ID, NULL)!= A_OK) + if(qcom_set_scan(FNET_QCA_DEVICE_ID, NULL) != A_OK) { FNET_DEBUG_QCA("[QCA] ERROR: qcom_set_scan() failed\r\n"); break; } /* Get the scan results*/ - if(qcom_get_scan(FNET_QCA_DEVICE_ID, (QCOM_BSS_SCAN_INFO **)&(param.scan_info_list), &num_results) != A_OK) + if(qcom_get_scan(FNET_QCA_DEVICE_ID, (QCOM_BSS_SCAN_INFO **) & (param.scan_info_list), &num_results) != A_OK) { FNET_DEBUG_QCA("[QCA] ERROR: qcom_get_scan() failed\r\n"); break; @@ -464,9 +464,9 @@ static fnet_return_t fnet_qca_get_ssid_info(const char* ssid, WLAN_AUTH_MODE *au QCA_SCAN_INFO_PTR scan_info = ¶m.scan_info_list[0]; /* Take first result */ /* Print result */ - #if FNET_CFG_DEBUG_QCA && FNET_CFG_DEBUG +#if FNET_CFG_DEBUG_QCA && FNET_CFG_DEBUG fnet_qca_print_ssid_info(scan_info); - #endif +#endif /* Default values.*/ *auth_mode = WLAN_AUTH_NONE; @@ -559,8 +559,8 @@ static void fnet_qca_on_connect(uint8_t event, uint8_t devId, char *bssid, uint8 if(fnet_qca_auth_mode == WLAN_AUTH_NONE) /* Open security.*/ { - if(((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_STATION) && (bssConn==0)) || - ((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_AP) && (bssConn==1))) + if(((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_STATION) && (bssConn == 0)) || + ((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_AP) && (bssConn == 1))) { fnet_qca_if.is_connected = FNET_TRUE; } @@ -570,8 +570,8 @@ static void fnet_qca_on_connect(uint8_t event, uint8_t devId, char *bssid, uint8 case INVALID_PROFILE: /* This event is used to indicate RSNA failure */ FNET_DEBUG_QCA("[QCA] (EVENT) 4 way handshake failure \r\n"); - if(((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_STATION) && (bssConn==0)) || - ((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_AP) && (bssConn==1))) + if(((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_STATION) && (bssConn == 0)) || + ((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_AP) && (bssConn == 1))) { fnet_qca_if.is_connected = FNET_FALSE; } @@ -579,8 +579,8 @@ static void fnet_qca_on_connect(uint8_t event, uint8_t devId, char *bssid, uint8 case PEER_FIRST_NODE_JOIN_EVENT: /* This event is used to RSNA success */ FNET_DEBUG_QCA("[QCA] (EVENT) 4 way handshake success\r\n"); - if(((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_STATION) && (bssConn==0)) || - ((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_AP) && (bssConn==1))) + if(((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_STATION) && (bssConn == 0)) || + ((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_AP) && (bssConn == 1))) { fnet_qca_if.is_connected = FNET_TRUE; } @@ -588,8 +588,8 @@ static void fnet_qca_on_connect(uint8_t event, uint8_t devId, char *bssid, uint8 case QCOM_ONCONNECT_EVENT_DISCONNECT: /* Disconnected.*/ FNET_DEBUG_QCA("[QCA] (EVENT) %s disconnect\r\n", bssConn ? "AP" : "CLIENT"); - if(((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_STATION) && (bssConn==0)) || - ((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_AP) && (bssConn==1))) + if(((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_STATION) && (bssConn == 0)) || + ((fnet_qca_dev_mode == QCOM_WLAN_DEV_MODE_AP) && (bssConn == 1))) { fnet_qca_if.is_connected = FNET_FALSE; } @@ -616,8 +616,8 @@ static fnet_return_t fnet_qca_wifi_connect(struct fnet_netif *netif, fnet_wifi_c /* Disconnect. If the host has issued a CONNECT command, it must issue the DISCONNECT command before it issues the next CONNECT command.*/ - if((fnet_qca_if.is_connected == FNET_TRUE) - && (fnet_qca_wifi_disconnect(netif) != FNET_OK)) + if((fnet_qca_if.is_connected == FNET_TRUE) + && (fnet_qca_wifi_disconnect(netif) != FNET_OK)) { FNET_DEBUG_QCA("ERROR: qcom_disconnect failed\r\n"); } @@ -634,11 +634,11 @@ static fnet_return_t fnet_qca_wifi_connect(struct fnet_netif *netif, fnet_wifi_c goto EXIT; } } - + FNET_DEBUG_QCA("[QCA] Connecting to \"%s\"...\r\n", params->ssid); - + /* Set station mode */ - if(qcom_op_set_mode(FNET_QCA_DEVICE_ID, QCOM_WLAN_DEV_MODE_STATION)!= A_OK) + if(qcom_op_set_mode(FNET_QCA_DEVICE_ID, QCOM_WLAN_DEV_MODE_STATION) != A_OK) { FNET_DEBUG_QCA("ERROR: qcom_op_set_mode failed\r\n"); } @@ -648,9 +648,9 @@ static fnet_return_t fnet_qca_wifi_connect(struct fnet_netif *netif, fnet_wifi_c FNET_DEBUG_QCA("ERROR: qcom_power_set_mode failed\r\n"); } /* NOTE: qcom API requires to first set a valid SSID (before auth, cipher and passphrase)*/ - else if (qcom_set_ssid(FNET_QCA_DEVICE_ID, (QCOM_SSID*)params->ssid) != A_OK) + else if (qcom_set_ssid(FNET_QCA_DEVICE_ID, (QCOM_SSID *)params->ssid) != A_OK) { - FNET_DEBUG_QCA("ERROR: qcom_set_ssid failed\r\n"); + FNET_DEBUG_QCA("ERROR: qcom_set_ssid failed\r\n"); } /* Note that only 4 of all modes listed in QCA 80-Y9106-1 are supported! * The modes are: WLAN_AUTH_NONE, WLAN_AUTH_WPA_PSK, WLAN_AUTH_WPA2_PSK, WLAN_AUTH_WEP*/ @@ -661,23 +661,25 @@ static fnet_return_t fnet_qca_wifi_connect(struct fnet_netif *netif, fnet_wifi_c /* Set encryption mode.*/ else if(qcom_sec_set_encrypt_mode(FNET_QCA_DEVICE_ID, encrypt_mode) != A_OK) { - FNET_DEBUG_QCA("ERROR:qcom_sec_set_encrypt_mode failed\r\n"); + FNET_DEBUG_QCA("ERROR:qcom_sec_set_encrypt_mode failed\r\n"); } else { - if(params->wpa_passphrase) + if(params->wpa_passphrase && fnet_strlen(params->wpa_passphrase)) { fnet_size_t passphrase_len = fnet_strlen(params->wpa_passphrase); - if(passphrase_len < (FNET_WIFI_PASSPHRASE_SIZE_MAX-1 /*64*/)) - { /* 8-63 passphrase*/ - if(qcom_sec_set_passphrase(FNET_QCA_DEVICE_ID, (QCOM_PASSPHRASE*)(params->wpa_passphrase)) != A_OK) + if(passphrase_len < (FNET_WIFI_PASSPHRASE_SIZE_MAX - 1 /*64*/)) + { + /* 8-63 passphrase*/ + if(qcom_sec_set_passphrase(FNET_QCA_DEVICE_ID, (QCOM_PASSPHRASE *)(params->wpa_passphrase)) != A_OK) { FNET_DEBUG_QCA("ERROR: qcom_sec_set_passphrase() failed\r\n"); goto EXIT; } } - else if(passphrase_len == (FNET_WIFI_PASSPHRASE_SIZE_MAX-1 /*64*/)) - { /* Pre-shared key */ + else if(passphrase_len == (FNET_WIFI_PASSPHRASE_SIZE_MAX - 1 /*64*/)) + { + /* Pre-shared key */ if(qcom_sec_set_pmk(FNET_QCA_DEVICE_ID, params->wpa_passphrase) != A_OK) { FNET_DEBUG_QCA("[QCA] ERROR: qcom_sec_set_pmk() failed\r\n"); @@ -743,8 +745,8 @@ static fnet_return_t fnet_qca_wifi_access_point(fnet_netif_t *netif, fnet_wifi_a /* Disconnect. If the host has issued a CONNECT command, it must issue the DISCONNECT command before it issues the next CONNECT command.*/ - if((fnet_qca_if.is_connected == FNET_TRUE) - && (fnet_qca_wifi_disconnect(netif) != FNET_OK)) + if((fnet_qca_if.is_connected == FNET_TRUE) + && (fnet_qca_wifi_disconnect(netif) != FNET_OK)) { FNET_DEBUG_QCA("ERROR: qcom_disconnect failed\r\n"); } @@ -752,9 +754,9 @@ static fnet_return_t fnet_qca_wifi_access_point(fnet_netif_t *netif, fnet_wifi_a { FNET_DEBUG_QCA("[QCA] (MODE) Access Point\r\n"); - if((params->wpa_mode != FNET_WIFI_WPA_NONE) - && params->wpa_passphrase - && fnet_strlen(params->wpa_passphrase)) /* Security */ + if((params->wpa_mode != FNET_WIFI_WPA_NONE) + && params->wpa_passphrase + && fnet_strlen(params->wpa_passphrase)) /* Security */ { switch(params->wpa_mode) { @@ -768,11 +770,11 @@ static fnet_return_t fnet_qca_wifi_access_point(fnet_netif_t *netif, fnet_wifi_a break; default: goto EXIT; - } + } } - + /* Set station mode */ - if(qcom_op_set_mode(FNET_QCA_DEVICE_ID, QCOM_WLAN_DEV_MODE_AP)!= A_OK) + if(qcom_op_set_mode(FNET_QCA_DEVICE_ID, QCOM_WLAN_DEV_MODE_AP) != A_OK) { FNET_DEBUG_QCA("ERROR: qcom_op_set_mode failed\r\n"); } @@ -782,9 +784,9 @@ static fnet_return_t fnet_qca_wifi_access_point(fnet_netif_t *netif, fnet_wifi_a FNET_DEBUG_QCA("ERROR: qcom_power_set_mode failed\r\n"); } /* NOTE: qcom API requires to first set a valid SSID (before auth, cipher and passphrase)*/ - else if (qcom_set_ssid(FNET_QCA_DEVICE_ID, (QCOM_SSID*)params->ssid) != A_OK) + else if (qcom_set_ssid(FNET_QCA_DEVICE_ID, (QCOM_SSID *)params->ssid) != A_OK) { - FNET_DEBUG_QCA("ERROR: qcom_set_ssid failed\r\n"); + FNET_DEBUG_QCA("ERROR: qcom_set_ssid failed\r\n"); } /* Note that only 4 of all modes listed in QCA 80-Y9106-1 are supported! * The modes are: WLAN_AUTH_NONE, WLAN_AUTH_WPA_PSK, WLAN_AUTH_WPA2_PSK, WLAN_AUTH_WEP*/ @@ -795,23 +797,25 @@ static fnet_return_t fnet_qca_wifi_access_point(fnet_netif_t *netif, fnet_wifi_a /* Set encryption mode.*/ else if(qcom_sec_set_encrypt_mode(FNET_QCA_DEVICE_ID, encrypt_mode) != A_OK) { - FNET_DEBUG_QCA("ERROR:qcom_sec_set_encrypt_mode failed\r\n"); + FNET_DEBUG_QCA("ERROR:qcom_sec_set_encrypt_mode failed\r\n"); } else { if(params->wpa_passphrase) { fnet_size_t passphrase_len = fnet_strlen(params->wpa_passphrase); - if(passphrase_len < (FNET_WIFI_PASSPHRASE_SIZE_MAX-1 /*64*/)) - { /* 8-63 passphrase*/ - if(qcom_sec_set_passphrase(FNET_QCA_DEVICE_ID, (QCOM_PASSPHRASE*)(params->wpa_passphrase)) != A_OK) + if(passphrase_len < (FNET_WIFI_PASSPHRASE_SIZE_MAX - 1 /*64*/)) + { + /* 8-63 passphrase*/ + if(qcom_sec_set_passphrase(FNET_QCA_DEVICE_ID, (QCOM_PASSPHRASE *)(params->wpa_passphrase)) != A_OK) { FNET_DEBUG_QCA("ERROR: qcom_sec_set_passphrase() failed\r\n"); goto EXIT; } } - else if(passphrase_len == (FNET_WIFI_PASSPHRASE_SIZE_MAX-1 /*64*/)) - { /* Pre-shared key */ + else if(passphrase_len == (FNET_WIFI_PASSPHRASE_SIZE_MAX - 1 /*64*/)) + { + /* Pre-shared key */ if(qcom_sec_set_pmk(FNET_QCA_DEVICE_ID, params->wpa_passphrase) != A_OK) { FNET_DEBUG_QCA("[QCA] ERROR: qcom_sec_set_pmk() failed\r\n"); @@ -852,7 +856,7 @@ static fnet_return_t fnet_qca_wifi_access_point(fnet_netif_t *netif, fnet_wifi_a { FNET_DEBUG_QCA("ERROR: qcom_set_appie failed\r\n"); goto EXIT; - } + } A_MDELAY(1000); /* Workaround QCA connection issue */ @@ -943,11 +947,11 @@ void fnet_qca_output(fnet_netif_t *netif, fnet_netbuf_t *nb) A_NETBUF *a_netbuf_ptr; fnet_qca_if_t *qca_if; - if(netif && netif->netif_prv && (fnet_qca_is_connected(netif) == FNET_TRUE) - && nb && (nb->total_length >= FNET_ETH_HDR_SIZE)) + if(netif && netif->netif_prv && (fnet_qca_is_connected(netif) == FNET_TRUE) + && nb && (nb->total_length >= FNET_ETH_HDR_SIZE)) { qca_if = (fnet_qca_if_t *)(((fnet_eth_if_t *)(netif->netif_prv))->eth_prv); - + if(qca_if) { /* Allocate atheros pcb. */ @@ -956,7 +960,7 @@ void fnet_qca_output(fnet_netif_t *netif, fnet_netbuf_t *nb) FNET_DEBUG_QCA("[QCA] ERROR: A_NETBUF_ALLOC failed\r\n"); goto EXIT_1; } - + fnet_netbuf_to_buf(nb, 0u, FNET_NETBUF_COPYALL, a_netbuf_ptr->tail); A_NETBUF_PUT(a_netbuf_ptr, nb->total_length); @@ -998,7 +1002,7 @@ static fnet_return_t fnet_qca_wifi_fw_update(fnet_netif_t *netif, const fnet_uin if(netif && (netif->netif_api->netif_type == FNET_NETIF_TYPE_WIFI) && netif->netif_prv && fw_buffer && fw_buffer_size) { qca_if = (fnet_qca_if_t *)(((fnet_eth_if_t *)(netif->netif_prv))->eth_prv); - + if(qca_if) { ATH_PROGRAM_FLASH_STRUCT flash_msg; @@ -1006,7 +1010,7 @@ static fnet_return_t fnet_qca_wifi_fw_update(fnet_netif_t *netif, const fnet_uin /* Switch to BMI mode */ - + /* Release QCA driver */ fnet_qca_release(netif); @@ -1021,7 +1025,7 @@ static fnet_return_t fnet_qca_wifi_fw_update(fnet_netif_t *netif, const fnet_uin /* Init QCA driver in BMI mode*/ result = fnet_qca_init(netif); - #if 1 /* TARGET_AR400X_REV2 does not support FW update (stuck). Proved on practice. */ +#if 1 /* TARGET_AR400X_REV2 does not support FW update (stuck). Proved on practice. */ { ATH_VERSION qca_version; if(A_FAILED(qcom_get_version(&qca_version))) @@ -1029,18 +1033,18 @@ static fnet_return_t fnet_qca_wifi_fw_update(fnet_netif_t *netif, const fnet_uin FNET_DEBUG_QCA("[QCA] ERROR: Failed to get QCA version\r\n"); goto EXIT; } - + if(qca_version.target_ver == TARGET_AR400X_REV2) { FNET_DEBUG_QCA("[QCA] ERROR: AR400X_REV2 does not support fw update!\r\n"); goto EXIT; } } - #endif +#endif if(result == FNET_OK) { - /*------- Load the firmware buffer to QCA --------------*/ + /*------- Load the firmware buffer to QCA --------------*/ FNET_DEBUG_QCA("[QCA] Flashing firmware %d bytes ...\r\n", fw_buffer_size); fnet_memset_zero(&flash_msg, sizeof(flash_msg)); fnet_memset_zero(&inout_param, sizeof(inout_param)); @@ -1053,7 +1057,7 @@ static fnet_return_t fnet_qca_wifi_fw_update(fnet_netif_t *netif, const fnet_uin inout_param.cmd_id = ATH_PROGRAM_FLASH; inout_param.data = &flash_msg; inout_param.length = sizeof(flash_msg); - + if (A_OK != Custom_Api_Mediactl(&wifiCtx, QCA_MEDIACTL_VENDOR_SPECIFIC, &inout_param)) { FNET_DEBUG_QCA("[QCA] ERROR: Custom_Api_Mediactl(ATH_PROGRAM_FLASH) failed\r\n"); @@ -1072,7 +1076,7 @@ static fnet_return_t fnet_qca_wifi_fw_update(fnet_netif_t *netif, const fnet_uin inout_param.cmd_id = ATH_EXECUTE_FLASH; inout_param.data = &flash_msg; inout_param.length = sizeof(flash_msg); - + if (A_OK != Custom_Api_Mediactl(&wifiCtx, QCA_MEDIACTL_VENDOR_SPECIFIC, &inout_param)) { FNET_DEBUG_QCA("[QCA] ERROR: Custom_Api_Mediactl(ATH_EXECUTE_FLASH) failed\r\n"); @@ -1081,7 +1085,7 @@ static fnet_return_t fnet_qca_wifi_fw_update(fnet_netif_t *netif, const fnet_uin FNET_DEBUG_QCA("[QCA] Flashing is done.\r\n"); } -EXIT: + EXIT: /* Switch to the normal mode */ /* Release driver */ @@ -1091,7 +1095,7 @@ static fnet_return_t fnet_qca_wifi_fw_update(fnet_netif_t *netif, const fnet_uin { ath_custom_init.skipWmi = false; ath_custom_init.exitAtBmi = false; - + ar4XXX_boot_param = AR4XXX_PARAM_MODE_NORMAL; } @@ -1111,15 +1115,15 @@ static fnet_uint32_t fnet_qca_fw_get_version(struct fnet_netif *netif) { fnet_uint32_t fw_version = 0; fnet_qca_if_t *qca_if; - - if(netif && netif->netif_prv) + + if(netif && netif->netif_prv) { qca_if = (fnet_qca_if_t *)(((fnet_eth_if_t *)(netif->netif_prv))->eth_prv); - + if(qca_if) { QCOM_WLAN_DEV_MODE mode; - + if(qcom_op_get_mode(FNET_QCA_DEVICE_ID, &mode) == A_OK) { ATH_VERSION qca_version; @@ -1145,11 +1149,11 @@ static fnet_bool_t fnet_qca_is_connected(fnet_netif_t *netif) { fnet_bool_t res = FNET_FALSE; fnet_qca_if_t *qca_if; - + if(netif && netif->netif_prv) { qca_if = (fnet_qca_if_t *)(((fnet_eth_if_t *)(netif->netif_prv))->eth_prv); - + if(qca_if) { res = qca_if->is_connected; @@ -1166,15 +1170,15 @@ static fnet_wifi_op_mode_t fnet_qca_get_op_mode(struct fnet_netif *netif) { fnet_wifi_op_mode_t result = FNET_WIFI_OP_MODE_NONE; fnet_qca_if_t *qca_if; - - if(netif && netif->netif_prv && fnet_qca_is_connected(netif)) + + if(netif && netif->netif_prv && fnet_qca_is_connected(netif)) { qca_if = (fnet_qca_if_t *)(((fnet_eth_if_t *)(netif->netif_prv))->eth_prv); - + if(qca_if) { QCOM_WLAN_DEV_MODE mode; - + if(qcom_op_get_mode(FNET_QCA_DEVICE_ID, &mode) == A_OK) { switch(mode) @@ -1255,7 +1259,7 @@ static void fnet_qca_input(void *cookie) void Custom_DeliverFrameToNetworkStack(void *pCxt, void *pReq) { if(fnet_qca_if.pReq) /* Just in case */ - { + { A_NETBUF_FREE(fnet_qca_if.pReq); } fnet_qca_if.pReq = pReq; @@ -1267,7 +1271,7 @@ void Custom_DeliverFrameToNetworkStack(void *pCxt, void *pReq) /* This functions is not used, it is here just to make compilable the QCA driver */ uint32_t Custom_Api_Send(QCA_CONTEXT_STRUCT_PTR qca_ptr, PCB_PTR pcb_ptr, uint32_t size, uint32_t frags, uint32_t flags); uint32_t Custom_Api_Send(QCA_CONTEXT_STRUCT_PTR qca_ptr, PCB_PTR pcb_ptr, uint32_t size, uint32_t frags, uint32_t flags) -{ +{ return QCA_ERROR; } diff --git a/fnet_stack/port/cpu/netif/qca/fnet_qca.h b/fnet_stack/port/netif/qca/fnet_qca.h similarity index 100% rename from fnet_stack/port/cpu/netif/qca/fnet_qca.h rename to fnet_stack/port/netif/qca/fnet_qca.h diff --git a/fnet_stack/service/autoip/fnet_autoip.c b/fnet_stack/service/autoip/fnet_autoip.c index f93eb3bd..cafcb2b3 100644 --- a/fnet_stack/service/autoip/fnet_autoip.c +++ b/fnet_stack/service/autoip/fnet_autoip.c @@ -557,7 +557,7 @@ fnet_autoip_desc_t fnet_autoip_get_by_netif(fnet_netif_desc_t netif) { fnet_autoip_if_t *autoip_if; fnet_index_t i; - fnet_autoip_desc_t autoip_desc = 0; + fnet_autoip_desc_t autoip_desc = 0; if(netif) { @@ -572,7 +572,7 @@ fnet_autoip_desc_t fnet_autoip_get_by_netif(fnet_netif_desc_t netif) } } } - + return autoip_desc; } diff --git a/fnet_stack/service/autoip/fnet_autoip.h b/fnet_stack/service/autoip/fnet_autoip.h index 44231cc0..d3f9a7f8 100644 --- a/fnet_stack/service/autoip/fnet_autoip.h +++ b/fnet_stack/service/autoip/fnet_autoip.h @@ -210,7 +210,7 @@ fnet_bool_t fnet_autoip_is_enabled(fnet_autoip_desc_t desc); * ****************************************************************************** * - * This function is looking for a Auto-IP service assigned to + * This function is looking for a Auto-IP service assigned to * the @c netif network interface set during its initialization. * ******************************************************************************/ diff --git a/fnet_stack/service/bench/fnet_bench_cln.c b/fnet_stack/service/bench/fnet_bench_cln.c index 01b2d048..ae89a46e 100644 --- a/fnet_stack/service/bench/fnet_bench_cln.c +++ b/fnet_stack/service/bench/fnet_bench_cln.c @@ -36,7 +36,7 @@ *************************************************************************/ #define FNET_BENCH_CLN_UDP_END_LENGTH (1) /* End of UDP session mark */ -#define FNET_BENCH_CLN_UDP_END_ITERATION (5) +#define FNET_BENCH_CLN_UDP_END_ITERATION (5) /* Error strings.*/ #define FNET_BENCH_CLN_ERR_PARAMS "[BENCH cln] Wrong input parameters" @@ -67,17 +67,17 @@ typedef struct fnet_bench_cln_if fnet_socket_type_t type; struct fnet_sockaddr address_foreign; fnet_socket_t socket_foreign; /* Foreign socket.*/ - fnet_size_t message_size; /* Size of one message to send. */ + fnet_size_t message_size; /* Size of one message to send. */ fnet_index_t message_number; /* Number of messages to send. */ fnet_size_t message_offset; /* Partial send (TCP) */ - fnet_bench_cln_callback_session_end_t callback; - void *cookie; + fnet_bench_cln_callback_session_end_t callback; + void *cookie; fnet_time_t time_begin; struct fnet_bench_cln_result bench_cln_result; } fnet_bench_cln_if_t; /* Tx buffer */ -static fnet_uint8_t fnet_bench_cln_buffer[FNET_CFG_BENCH_CLN_BUFFER_SIZE]; +static fnet_uint8_t fnet_bench_cln_buffer[FNET_CFG_BENCH_CLN_BUFFER_SIZE]; /* The Benchmark server interface list*/ static fnet_bench_cln_if_t fnet_bench_cln_if_list[FNET_CFG_BENCH_CLN]; @@ -96,10 +96,10 @@ fnet_bench_srv_desc_t fnet_bench_cln_init( struct fnet_bench_cln_params *params fnet_bench_cln_if_t *bench_cln_if = FNET_NULL; fnet_size_t bufsize_option = FNET_CFG_BENCH_CLN_BUFFER_SIZE; - if((params == 0) || - !((params->type == SOCK_STREAM) || (params->type == SOCK_DGRAM)) || - (params->message_number == 0) || (params->callback == 0) || - (params->message_size == 0) || (params->message_size > sizeof(fnet_bench_cln_buffer))) + if((params == 0) || + !((params->type == SOCK_STREAM) || (params->type == SOCK_DGRAM)) || + (params->message_number == 0) || (params->callback == 0) || + (params->message_size == 0) || (params->message_size > sizeof(fnet_bench_cln_buffer))) { FNET_DEBUG_BENCH_CLN(FNET_BENCH_CLN_ERR_PARAMS); goto ERROR_1; @@ -123,7 +123,7 @@ fnet_bench_srv_desc_t fnet_bench_cln_init( struct fnet_bench_cln_params *params } /* Clear all parameters.*/ - fnet_memset_zero(bench_cln_if,sizeof(*bench_cln_if)); + fnet_memset_zero(bench_cln_if, sizeof(*bench_cln_if)); /* Set parameters */ fnet_memcpy(&bench_cln_if->address_foreign, ¶ms->address, sizeof(bench_cln_if->address_foreign)); @@ -200,7 +200,7 @@ void fnet_bench_cln_release(fnet_bench_cln_desc_t desc) { fnet_uint32_t bytes; fnet_index_t i; - + /* Send UDP session End mark.*/ for(i = 0; i < FNET_BENCH_CLN_UDP_END_ITERATION; i++) { @@ -208,15 +208,15 @@ void fnet_bench_cln_release(fnet_bench_cln_desc_t desc) fnet_socket_send(bench_cln_if->socket_foreign, &bytes, 1, 0); } } - + bench_cln_if->is_enabled = FNET_FALSE; fnet_service_unregister(bench_cln_if->service_descriptor); /* Delete service. */ fnet_socket_close(bench_cln_if->socket_foreign); - + bench_cln_if->state = FNET_BENCH_CLN_STATE_DISABLED; - + /* Inform a user application about the session end */ bench_cln_if->bench_cln_result.time_ms = fnet_timer_get_ms() - bench_cln_if->time_begin; bench_cln_if->callback(bench_cln_if, &bench_cln_if->bench_cln_result, bench_cln_if->cookie); @@ -236,60 +236,60 @@ static void fnet_bench_cln_poll( void *fnet_bench_cln_if_p ) switch(bench_cln_if->state) { case FNET_BENCH_CLN_STATE_CONNECTING: /* Benchmark client is connecting.*/ - { - fnet_socket_state_t connection_state; - fnet_size_t option_len; + { + fnet_socket_state_t connection_state; + fnet_size_t option_len; - option_len = sizeof(connection_state); - fnet_socket_getopt(bench_cln_if->socket_foreign, SOL_SOCKET, SO_STATE, &connection_state, &option_len); + option_len = sizeof(connection_state); + fnet_socket_getopt(bench_cln_if->socket_foreign, SOL_SOCKET, SO_STATE, &connection_state, &option_len); - if(connection_state != SS_CONNECTING) - { - bench_cln_if->time_begin = fnet_timer_get_ms(); - bench_cln_if->state = FNET_BENCH_CLN_STATE_TX; - } + if(connection_state != SS_CONNECTING) + { + bench_cln_if->time_begin = fnet_timer_get_ms(); + bench_cln_if->state = FNET_BENCH_CLN_STATE_TX; } - break; + } + break; case FNET_BENCH_CLN_STATE_TX: /* Benchmark client is sending.*/ - { - fnet_bool_t is_session_end = FNET_FALSE; + { + fnet_bool_t is_session_end = FNET_FALSE; - send_result = fnet_socket_send(bench_cln_if->socket_foreign, &fnet_bench_cln_buffer[bench_cln_if->message_offset], (bench_cln_if->message_size - bench_cln_if->message_offset), 0); + send_result = fnet_socket_send(bench_cln_if->socket_foreign, &fnet_bench_cln_buffer[bench_cln_if->message_offset], (bench_cln_if->message_size - bench_cln_if->message_offset), 0); - if (send_result == FNET_ERR) + if (send_result == FNET_ERR) + { + is_session_end = FNET_TRUE; + } + else if(send_result) + { + bench_cln_if->bench_cln_result.bytes += send_result; + if(bench_cln_if->bench_cln_result.bytes >= 1000000) { - is_session_end = FNET_TRUE; + bench_cln_if->bench_cln_result.megabytes ++; + bench_cln_if->bench_cln_result.bytes -= 1000000; } - else if(send_result) + bench_cln_if->message_offset += send_result; + + if(bench_cln_if->message_offset >= bench_cln_if->message_size) { - bench_cln_if->bench_cln_result.bytes += send_result; - if(bench_cln_if->bench_cln_result.bytes >= 1000000) - { - bench_cln_if->bench_cln_result.megabytes ++; - bench_cln_if->bench_cln_result.bytes -= 1000000; - } - bench_cln_if->message_offset += send_result; + bench_cln_if->message_offset = 0; + bench_cln_if->message_number--; - if(bench_cln_if->message_offset >= bench_cln_if->message_size) + if(bench_cln_if->message_number == 0) { - bench_cln_if->message_offset = 0; - bench_cln_if->message_number--; - - if(bench_cln_if->message_number == 0) - { - is_session_end = FNET_TRUE; - } + is_session_end = FNET_TRUE; } } - else /* 0 */ - {} + } + else /* 0 */ + {} - if(is_session_end == FNET_TRUE) - { - fnet_bench_cln_release(bench_cln_if); - } + if(is_session_end == FNET_TRUE) + { + fnet_bench_cln_release(bench_cln_if); } - break; + } + break; default: break; } diff --git a/fnet_stack/service/bench/fnet_bench_cln.h b/fnet_stack/service/bench/fnet_bench_cln.h index 00678fa4..23704c17 100644 --- a/fnet_stack/service/bench/fnet_bench_cln.h +++ b/fnet_stack/service/bench/fnet_bench_cln.h @@ -35,7 +35,7 @@ * the user application should call the main service-polling function * @ref fnet_service_poll() periodically in background.@n * The benchmark results will be passed to the @ref fnet_bench_cln_callback_session_end_t callback function, -* which is set during the benchmark client initialization. +* which is set during the benchmark client initialization. * @n * The benchmark client service is released automatically as soon as the benchmark session is * finished or an error occurs. Your application may continue @@ -57,7 +57,7 @@ * @brief Benchmark client descriptor. * @see fnet_bench_cln_init() ******************************************************************************/ -typedef void* fnet_bench_cln_desc_t; +typedef void *fnet_bench_cln_desc_t; /**************************************************************************/ /*! * @brief Benchmark client result passed to the "session end" event handler callback. @@ -88,8 +88,8 @@ struct fnet_bench_cln_params { struct fnet_sockaddr address; /**< @brief Socket address of the remote benchmark server to connect to. */ fnet_socket_type_t type; /**< @brief Protocol type. It can be @ref SOCK_STREAM (TCP) or @ref SOCK_DGRAM (UDP).*/ - fnet_size_t message_size; /**< @brief Size of one message to send. Its value must be less than @ref FNET_CFG_BENCH_CLN_BUFFER_SIZE. */ - fnet_index_t message_number; /**< @brief Number of messages to send. */ + fnet_size_t message_size; /**< @brief Size of one message to send. Its value must be less than @ref FNET_CFG_BENCH_CLN_BUFFER_SIZE. */ + fnet_index_t message_number; /**< @brief Number of messages to send. */ fnet_bench_cln_callback_session_end_t callback; /**< @brief Pointer to the callback function defined by * @ref fnet_bench_cln_callback_session_end_t. It is called when the * benchmark session is finished. */ @@ -116,7 +116,7 @@ extern "C" { * ****************************************************************************** * - * This function initializes the Benchmark client/transmitter service and starts + * This function initializes the Benchmark client/transmitter service and starts * the benchmark session. It allocates all * resources needed and registers the Benchmark client in the service polling list.@n * After the initialization, the user application should call the main polling diff --git a/fnet_stack/service/bench/fnet_bench_config.h b/fnet_stack/service/bench/fnet_bench_config.h index f5fa180b..03744fb2 100644 --- a/fnet_stack/service/bench/fnet_bench_config.h +++ b/fnet_stack/service/bench/fnet_bench_config.h @@ -46,7 +46,7 @@ /**************************************************************************/ /*! * @def FNET_CFG_BENCH_SRV_PORT * @brief Default benchmark server port number (in network byte order).@n - * The benchmark server uses this port for sending and receiving of + * The benchmark server uses this port for sending and receiving of * messages. @n * It can be changed during the benchmark server initialization by the * @ref fnet_bench_srv_init() function.@n @@ -59,7 +59,7 @@ /**************************************************************************/ /*! * @def FNET_CFG_BENCH_SRV_BUFFER_SIZE - * @brief Defines the socket recieve buffer size. + * @brief Defines the socket recieve buffer size. * @showinitializer ******************************************************************************/ #ifndef FNET_CFG_BENCH_SRV_BUFFER_SIZE @@ -84,7 +84,7 @@ /**************************************************************************/ /*! * @def FNET_CFG_BENCH_CLN_PORT * @brief Default benchmark client port number (in network byte order).@n - * The benchmark client uses this port for sending and receiving of + * The benchmark client uses this port for sending and receiving of * messages. @n * It can be changed during the benchmark client initialization by the * @ref fnet_bench_cln_init() function.@n @@ -97,7 +97,7 @@ /**************************************************************************/ /*! * @def FNET_CFG_BENCH_CLN_BUFFER_SIZE - * @brief Defines the socket transmit buffer size. + * @brief Defines the socket transmit buffer size. * @showinitializer ******************************************************************************/ #ifndef FNET_CFG_BENCH_CLN_BUFFER_SIZE diff --git a/fnet_stack/service/bench/fnet_bench_srv.c b/fnet_stack/service/bench/fnet_bench_srv.c index 00f51c24..7d295f65 100644 --- a/fnet_stack/service/bench/fnet_bench_srv.c +++ b/fnet_stack/service/bench/fnet_bench_srv.c @@ -67,17 +67,17 @@ typedef struct fnet_bench_srv_if fnet_socket_t socket_listen; /* Listening socket.*/ fnet_socket_t socket_foreign; /* Foreign socket.*/ struct fnet_sockaddr address; /* Address of the remote client at the other end of the connection.*/ - fnet_bench_srv_callback_session_begin_t callback_session_begin; - fnet_bench_srv_callback_session_end_t callback_session_end; - void *callback_session_begin_cookie; - void *callback_session_end_cookie; + fnet_bench_srv_callback_session_begin_t callback_session_begin; + fnet_bench_srv_callback_session_end_t callback_session_end; + void *callback_session_begin_cookie; + void *callback_session_end_cookie; fnet_time_t time_last; /* Last receive timestamp. Used for session timeout control */ fnet_time_t time_begin; struct fnet_bench_srv_result bench_srv_result; } fnet_bench_srv_if_t; /* Receive buffer */ -static fnet_uint8_t fnet_bench_srv_buffer[FNET_CFG_BENCH_SRV_BUFFER_SIZE]; +static fnet_uint8_t fnet_bench_srv_buffer[FNET_CFG_BENCH_SRV_BUFFER_SIZE]; /* The Benchmark server interface list*/ static fnet_bench_srv_if_t fnet_bench_srv_if_list[FNET_CFG_BENCH_SRV]; @@ -161,51 +161,51 @@ fnet_bench_srv_desc_t fnet_bench_srv_init( struct fnet_bench_srv_params *params switch(bench_srv_if->type) { case SOCK_STREAM: + { + const struct fnet_linger linger_option = { - const struct fnet_linger linger_option = - { - .l_onoff = FNET_TRUE, - .l_linger = 4 /*sec*/ - }; - const fnet_int32_t keepalive_option = 1; - /* Keepalive probe retransmit limit.*/ - const fnet_int32_t keepcnt_option = 2; + .l_onoff = FNET_TRUE, + .l_linger = 4 /*sec*/ + }; + const fnet_int32_t keepalive_option = 1; + /* Keepalive probe retransmit limit.*/ + const fnet_int32_t keepcnt_option = 2; + /* Keepalive retransmit interval.*/ + const fnet_int32_t keepintvl_option = 5; /*sec*/ + /* Time between keepalive probes.*/ + const fnet_int32_t keepidle_option = 5; /* sec */ + + /* Set TCP Socket options. */ + if( /* Setup linger option. */ + (fnet_socket_setopt (bench_srv_if->socket_listen, SOL_SOCKET, SO_LINGER, &linger_option, sizeof(linger_option)) == FNET_ERR) || + /* Enable keepalive_option option. */ + (fnet_socket_setopt (bench_srv_if->socket_listen, SOL_SOCKET, SO_KEEPALIVE, &keepalive_option, sizeof(keepalive_option)) == FNET_ERR) || + /* Keepalive probe retransmit limit. */ + (fnet_socket_setopt (bench_srv_if->socket_listen, IPPROTO_TCP, TCP_KEEPCNT, &keepcnt_option, sizeof(keepcnt_option)) == FNET_ERR) || /* Keepalive retransmit interval.*/ - const fnet_int32_t keepintvl_option = 5; /*sec*/ + (fnet_socket_setopt (bench_srv_if->socket_listen, IPPROTO_TCP, TCP_KEEPINTVL, &keepintvl_option, sizeof(keepintvl_option)) == FNET_ERR) || /* Time between keepalive probes.*/ - const fnet_int32_t keepidle_option = 5; /* sec */ - - /* Set TCP Socket options. */ - if( /* Setup linger option. */ - (fnet_socket_setopt (bench_srv_if->socket_listen, SOL_SOCKET, SO_LINGER, &linger_option, sizeof(linger_option)) == FNET_ERR) || - /* Enable keepalive_option option. */ - (fnet_socket_setopt (bench_srv_if->socket_listen, SOL_SOCKET, SO_KEEPALIVE, &keepalive_option, sizeof(keepalive_option)) == FNET_ERR) || - /* Keepalive probe retransmit limit. */ - (fnet_socket_setopt (bench_srv_if->socket_listen, IPPROTO_TCP, TCP_KEEPCNT, &keepcnt_option, sizeof(keepcnt_option)) == FNET_ERR) || - /* Keepalive retransmit interval.*/ - (fnet_socket_setopt (bench_srv_if->socket_listen, IPPROTO_TCP, TCP_KEEPINTVL, &keepintvl_option, sizeof(keepintvl_option)) == FNET_ERR) || - /* Time between keepalive probes.*/ - (fnet_socket_setopt (bench_srv_if->socket_listen, IPPROTO_TCP, TCP_KEEPIDLE, &keepidle_option, sizeof(keepidle_option)) == FNET_ERR) - ) - { - FNET_DEBUG_BENCH_SRV(FNET_BENCH_SRV_ERR_SOCKET_OPTION); - goto ERROR_2; - } + (fnet_socket_setopt (bench_srv_if->socket_listen, IPPROTO_TCP, TCP_KEEPIDLE, &keepidle_option, sizeof(keepidle_option)) == FNET_ERR) + ) + { + FNET_DEBUG_BENCH_SRV(FNET_BENCH_SRV_ERR_SOCKET_OPTION); + goto ERROR_2; + } - /* Listen. */ - if(fnet_socket_listen(bench_srv_if->socket_listen, 1) == FNET_ERR) - { - FNET_DEBUG_BENCH_SRV(FNET_BENCH_SRV_ERR_SOCKET_LISTEN); - goto ERROR_2; - } + /* Listen. */ + if(fnet_socket_listen(bench_srv_if->socket_listen, 1) == FNET_ERR) + { + FNET_DEBUG_BENCH_SRV(FNET_BENCH_SRV_ERR_SOCKET_LISTEN); + goto ERROR_2; } - break; + } + break; case SOCK_DGRAM: /* Join multicast group, if set. */ //TBD add drop membership if(fnet_socket_addr_is_multicast(&local_addr)) { /* Join multicast group. */ - #if FNET_CFG_IP4 +#if FNET_CFG_IP4 if(local_addr.sa_family == AF_INET) { struct fnet_ip_mreq mreq; /* Multicast group information.*/ @@ -220,8 +220,8 @@ fnet_bench_srv_desc_t fnet_bench_srv_init( struct fnet_bench_srv_params *params goto ERROR_2; } } - #endif - #if FNET_CFG_IP6 +#endif +#if FNET_CFG_IP6 if(local_addr.sa_family == AF_INET6) { struct fnet_ipv6_mreq mreq6; /* Multicast group information.*/ @@ -236,10 +236,10 @@ fnet_bench_srv_desc_t fnet_bench_srv_init( struct fnet_bench_srv_params *params goto ERROR_2; } } - #endif +#endif } break; - default: + default: goto ERROR_2; } @@ -275,7 +275,7 @@ void fnet_bench_srv_release(fnet_bench_srv_desc_t desc) fnet_bench_srv_close_session(bench_srv_if); } - fnet_socket_close(bench_srv_if->socket_listen); + fnet_socket_close(bench_srv_if->socket_listen); bench_srv_if->state = FNET_BENCH_SRV_STATE_DISABLED; bench_srv_if->is_enabled = FNET_FALSE; @@ -327,7 +327,7 @@ static void fnet_bench_srv_close_session(fnet_bench_srv_if_t *bench_srv_if) fnet_socket_close(bench_srv_if->socket_foreign); bench_srv_if->socket_foreign = 0; } - + bench_srv_if->bench_srv_result.megabytes = 0; bench_srv_if->bench_srv_result.bytes = 0; } @@ -346,94 +346,94 @@ static void fnet_bench_srv_poll( void *fnet_bench_srv_if_p ) switch(bench_srv_if->state) { case FNET_BENCH_SRV_STATE_LISTENING: /* Benchmark server is listening for incoming connection.*/ - { - fnet_bool_t is_session_begin = FNET_FALSE; + { + fnet_bool_t is_session_begin = FNET_FALSE; - if(bench_srv_if->type == SOCK_STREAM) /* TCP */ + if(bench_srv_if->type == SOCK_STREAM) /* TCP */ + { + /*Accept*/ + addr_len = sizeof(bench_srv_if->address); + bench_srv_if->socket_foreign = fnet_socket_accept(bench_srv_if->socket_listen, &bench_srv_if->address, &addr_len); + if(bench_srv_if->socket_foreign) { - /*Accept*/ - addr_len = sizeof(bench_srv_if->address); - bench_srv_if->socket_foreign = fnet_socket_accept(bench_srv_if->socket_listen, &bench_srv_if->address, &addr_len); - if(bench_srv_if->socket_foreign) - { - is_session_begin = FNET_TRUE; - } + is_session_begin = FNET_TRUE; } - else /* UDP */ + } + else /* UDP */ + { + /* Accept */ + addr_len = sizeof(bench_srv_if->address); + received = fnet_socket_recvfrom(bench_srv_if->socket_listen, fnet_bench_srv_buffer, sizeof(fnet_bench_srv_buffer), 0, + &bench_srv_if->address, &addr_len); + + if(received > FNET_BENCH_SRV_UDP_END_LENGTH) /* First UDP datagram is mark of session begin.*/ { - /* Accept */ - addr_len = sizeof(bench_srv_if->address); - received = fnet_socket_recvfrom(bench_srv_if->socket_listen, fnet_bench_srv_buffer, sizeof(fnet_bench_srv_buffer), 0, - &bench_srv_if->address, &addr_len); - - if(received > FNET_BENCH_SRV_UDP_END_LENGTH) /* First UDP datagram is mark of session begin.*/ - { - is_session_begin = FNET_TRUE; - } + is_session_begin = FNET_TRUE; } + } - if(is_session_begin == FNET_TRUE) + if(is_session_begin == FNET_TRUE) + { + if(bench_srv_if->callback_session_begin) /* Inform a user application about the session begin */ { - if(bench_srv_if->callback_session_begin) /* Inform a user application about the session begin */ - { - bench_srv_if->callback_session_begin((fnet_bench_srv_desc_t)bench_srv_if, bench_srv_if->address, bench_srv_if->callback_session_begin_cookie); - } - - bench_srv_if->time_begin = fnet_timer_get_ms(); - bench_srv_if->time_last = bench_srv_if->time_begin; - - bench_srv_if->state = FNET_BENCH_SRV_STATE_RX; + bench_srv_if->callback_session_begin((fnet_bench_srv_desc_t)bench_srv_if, bench_srv_if->address, bench_srv_if->callback_session_begin_cookie); } + + bench_srv_if->time_begin = fnet_timer_get_ms(); + bench_srv_if->time_last = bench_srv_if->time_begin; + + bench_srv_if->state = FNET_BENCH_SRV_STATE_RX; } - break; + } + break; case FNET_BENCH_SRV_STATE_RX: /* Benchmark server is receiving.*/ - { - fnet_bool_t is_session_end = FNET_FALSE; - fnet_time_t time_current = fnet_timer_get_ms(); + { + fnet_bool_t is_session_end = FNET_FALSE; + fnet_time_t time_current = fnet_timer_get_ms(); - if(bench_srv_if->type == SOCK_STREAM) /* TCP */ + if(bench_srv_if->type == SOCK_STREAM) /* TCP */ + { + received = fnet_socket_recv(bench_srv_if->socket_foreign, fnet_bench_srv_buffer, sizeof(fnet_bench_srv_buffer), 0); + if(received == FNET_ERR) { - received = fnet_socket_recv(bench_srv_if->socket_foreign, fnet_bench_srv_buffer, sizeof(fnet_bench_srv_buffer), 0); - if(received == FNET_ERR) - { - is_session_end = FNET_TRUE; - } + is_session_end = FNET_TRUE; } - else /* UDP */ + } + else /* UDP */ + { + addr_len = sizeof(bench_srv_if->address); + received = fnet_socket_recvfrom(bench_srv_if->socket_listen, fnet_bench_srv_buffer, sizeof(fnet_bench_srv_buffer), 0, + &bench_srv_if->address, &addr_len); + + if((received == FNET_ERR) || (received == FNET_BENCH_SRV_UDP_END_LENGTH)) /* End of session. */ { - addr_len = sizeof(bench_srv_if->address); - received = fnet_socket_recvfrom(bench_srv_if->socket_listen, fnet_bench_srv_buffer, sizeof(fnet_bench_srv_buffer), 0, - &bench_srv_if->address, &addr_len); - - if((received == FNET_ERR) || (received == FNET_BENCH_SRV_UDP_END_LENGTH)) /* End of session. */ - { - is_session_end = FNET_TRUE; - } + is_session_end = FNET_TRUE; } - - if(received > 0) + } + + if(received > 0) + { + bench_srv_if->bench_srv_result.bytes += received; + if(bench_srv_if->bench_srv_result.bytes >= 1000000) { - bench_srv_if->bench_srv_result.bytes += received; - if(bench_srv_if->bench_srv_result.bytes >= 1000000) - { - bench_srv_if->bench_srv_result.megabytes ++; - bench_srv_if->bench_srv_result.bytes -= 1000000; - } - bench_srv_if->time_last = time_current; + bench_srv_if->bench_srv_result.megabytes ++; + bench_srv_if->bench_srv_result.bytes -= 1000000; } + bench_srv_if->time_last = time_current; + } - /* Session End */ - if ((is_session_end == FNET_TRUE) || - ((time_current - bench_srv_if->time_last) > FNET_BENCH_SRV_SESSION_TIMEOUT_MS)) /* Session timeout */ - - { - fnet_bench_srv_close_session(bench_srv_if); + /* Session End */ + if ((is_session_end == FNET_TRUE) || + ((time_current - bench_srv_if->time_last) > FNET_BENCH_SRV_SESSION_TIMEOUT_MS)) /* Session timeout */ - bench_srv_if->state = FNET_BENCH_SRV_STATE_LISTENING; - break; - } + { + fnet_bench_srv_close_session(bench_srv_if); + + bench_srv_if->state = FNET_BENCH_SRV_STATE_LISTENING; + break; } - break; + } + break; default: break; } diff --git a/fnet_stack/service/bench/fnet_bench_srv.h b/fnet_stack/service/bench/fnet_bench_srv.h index 63c49480..cdca355a 100644 --- a/fnet_stack/service/bench/fnet_bench_srv.h +++ b/fnet_stack/service/bench/fnet_bench_srv.h @@ -33,7 +33,7 @@ * The FNET benchmark server/receiver is used for performance measuring and stress test of TCP and UDP.@n * After the FNET benchmark server is initialized by calling the @ref fnet_bench_srv_init() function, * the user application should call the main service-polling function -* @ref fnet_service_poll() periodically in background. +* @ref fnet_service_poll() periodically in background. * @n * For the FNET benchmark server example, refer to the FNET Bench demo source code.@n * @@ -49,7 +49,7 @@ * @brief Benchmark server descriptor. * @see fnet_bench_srv_init() ******************************************************************************/ -typedef void* fnet_bench_srv_desc_t; +typedef void *fnet_bench_srv_desc_t; /**************************************************************************/ /*! * @brief Initialization parameters for the @ref fnet_bench_srv_init() function. @@ -151,7 +151,7 @@ void fnet_bench_srv_release(fnet_bench_srv_desc_t desc); * @param callback_session_begin Pointer to the callback function defined by * @ref fnet_bench_srv_callback_session_begin_t. * @param cookie Optional application-specific parameter. @n - * It's passed to the @c callback_session_begin + * It's passed to the @c callback_session_begin * function as the input parameter. * ****************************************************************************** @@ -171,7 +171,7 @@ void fnet_bench_srv_set_callback_session_begin (fnet_bench_srv_desc_t desc, fnet * @param callback_session_end Pointer to the callback function defined by * @ref fnet_bench_srv_callback_session_end_t. * @param cookie Optional application-specific parameter. @n - * It's passed to the @c callback_session_end + * It's passed to the @c callback_session_end * function as the input parameter. * ****************************************************************************** diff --git a/fnet_stack/service/dhcp/fnet_dhcp.c b/fnet_stack/service/dhcp/fnet_dhcp.c index 0e819d71..dcd3cb64 100644 --- a/fnet_stack/service/dhcp/fnet_dhcp.c +++ b/fnet_stack/service/dhcp/fnet_dhcp.c @@ -28,7 +28,7 @@ #include "fnet_dhcp_prv.h" /* The first four octets of the vendor information field have been assigned to the "magic cookie".*/ -const fnet_uint8_t fnet_dhcp_magic_cookie[4] = {99, 130, 83, 99}; +const fnet_uint8_t fnet_dhcp_magic_cookie[4] = {99, 130, 83, 99}; /************************************************************************ * DESCRIPTION: Add DHCPv4 option. @@ -40,7 +40,7 @@ fnet_uint8_t *fnet_dhcp_add_option(fnet_uint8_t *option_buffer, fnet_size_t opti { FNET_ASSERT(option_buffer != FNET_NULl); FNET_ASSERT(option_value != FNET_NULl); - + fnet_uint8_t *result = FNET_NULL; if(option_buffer_size >= (2U/*type+length*/ + 1U/* END option*/ + option_length)) diff --git a/fnet_stack/service/dhcp/fnet_dhcp_cln.c b/fnet_stack/service/dhcp/fnet_dhcp_cln.c index a8ed6fe9..cb580ddc 100644 --- a/fnet_stack/service/dhcp/fnet_dhcp_cln.c +++ b/fnet_stack/service/dhcp/fnet_dhcp_cln.c @@ -158,7 +158,7 @@ typedef struct fnet_dhcp_cln_if * callback function, that is * called when the DHCP client has * updated the IP parameters.*/ - fnet_dhcp_cln_callback_t callback_discover; /* Optional pointer to the handler + fnet_dhcp_cln_callback_t callback_discover; /* Optional pointer to the handler * callback function, that is * called when the DHCP client send * the DHCP discover message.*/ @@ -628,9 +628,9 @@ static fnet_ssize_t fnet_dhcp_cln_receive_message( fnet_dhcp_cln_if_t *dhcp, str dhcp->message.next_option_position = &dhcp_header->file[0]; if(options->private_options.overload & FNET_DHCP_OPTION_OVERLOAD_FILE) - dhcp->message.end_position = &dhcp_header->file[128-1]; + dhcp->message.end_position = &dhcp_header->file[128 - 1]; else - dhcp->message.end_position = &dhcp_header->sname[64-1]; + dhcp->message.end_position = &dhcp_header->sname[64 - 1]; fnet_dhcp_cln_parse_options(&dhcp->message, options); } @@ -1197,7 +1197,7 @@ fnet_dhcp_cln_desc_t fnet_dhcp_cln_get_by_netif(fnet_netif_desc_t netif) { fnet_dhcp_cln_if_t *dhcp_if; fnet_index_t i; - fnet_dhcp_cln_desc_t dhcp_desc = 0; + fnet_dhcp_cln_desc_t dhcp_desc = 0; if(netif) { @@ -1212,7 +1212,7 @@ fnet_dhcp_cln_desc_t fnet_dhcp_cln_get_by_netif(fnet_netif_desc_t netif) } } } - + return dhcp_desc; } diff --git a/fnet_stack/service/dhcp/fnet_dhcp_cln.h b/fnet_stack/service/dhcp/fnet_dhcp_cln.h index be9ebd9b..0fa80828 100644 --- a/fnet_stack/service/dhcp/fnet_dhcp_cln.h +++ b/fnet_stack/service/dhcp/fnet_dhcp_cln.h @@ -56,7 +56,7 @@ * else * { * fnet_memset_zero(&dhcp_params, sizeof(dhcp_params)); -* dhcp_params.netif = netif; +* dhcp_params.netif = netif; * * // Enable DHCP client. * if(fnet_dhcp_cln_init(&dhcp_params)) @@ -176,7 +176,7 @@ extern "C" { * @brief DHCPv4 client descriptor. * @see fnet_dhcp_cln_init() ******************************************************************************/ -typedef void* fnet_dhcp_cln_desc_t; +typedef void *fnet_dhcp_cln_desc_t; /***************************************************************************/ /*! * @@ -324,7 +324,7 @@ fnet_bool_t fnet_dhcp_cln_is_enabled(fnet_dhcp_cln_desc_t desc); * ****************************************************************************** * - * This function is looking for a DHCP Client service assigned to + * This function is looking for a DHCP Client service assigned to * the @c netif network interface set during its initialization. * ******************************************************************************/ diff --git a/fnet_stack/service/dhcp/fnet_dhcp_prv.h b/fnet_stack/service/dhcp/fnet_dhcp_prv.h index e8ac9d9a..55b217c2 100644 --- a/fnet_stack/service/dhcp/fnet_dhcp_prv.h +++ b/fnet_stack/service/dhcp/fnet_dhcp_prv.h @@ -187,9 +187,9 @@ extern const fnet_uint8_t fnet_dhcp_magic_cookie[4]; fnet_uint8_t *fnet_dhcp_add_option(fnet_uint8_t *option_buffer, fnet_size_t option_buffer_size, fnet_uint8_t option_code, fnet_uint8_t option_length, const void *option_value); #if FNET_CFG_DEBUG_TRACE_DHCP_SRV && FNET_CFG_DEBUG_TRACE - void fnet_dhcp_trace(fnet_uint8_t *str, fnet_dhcp_header_t *header); +void fnet_dhcp_trace(fnet_uint8_t *str, fnet_dhcp_header_t *header); #else - #define fnet_dhcp_trace(str, header) do{}while(0) +#define fnet_dhcp_trace(str, header) do{}while(0) #endif #if defined(__cplusplus) diff --git a/fnet_stack/service/dhcp/fnet_dhcp_srv.c b/fnet_stack/service/dhcp/fnet_dhcp_srv.c index 275d6898..48a3407a 100644 --- a/fnet_stack/service/dhcp/fnet_dhcp_srv.c +++ b/fnet_stack/service/dhcp/fnet_dhcp_srv.c @@ -46,7 +46,7 @@ #define FNET_DHCP_SRV_ERR_IS_INITIALIZED "[DHCP srv] Is already initialized." /* DHCP options */ -typedef struct +typedef struct { fnet_uint8_t message_type; /* The DHCP Message Type. This option is used to convey the type of the DHCP message. @@ -74,7 +74,7 @@ typedef struct This option is used to indicate that the DHCP 'sname' or 'file' fields are being overloaded by using them to carry DHCP options. A DHCP server inserts this option if the returned parameters will - exceed the usual space allotted for options. + exceed the usual space allotted for options. If this option is present, the client interprets the specified additional fields after it concludes interpretation of the standard option fields. */ @@ -83,7 +83,7 @@ typedef struct to allow the client to request a lease time for the IP address. In a server reply (DHCPOFFER), a DHCP server uses this option to specify the lease time it is willing to offer. - The time is in units of seconds, and is specified as a 32-bit unsigned integer.*/ + The time is in units of seconds, and is specified as a 32-bit unsigned integer.*/ fnet_uint8_t request_list[12]; /* Parameter Request List. This option is used by a DHCP client to request values for specified configuration parameters. The list of requested parameters is @@ -94,7 +94,7 @@ typedef struct but MUST try to insert the requested options in the order requested by the client.*/ fnet_uint8_t request_list_length; /* Parameter Request List length. Its minimum length is 1.*/ -}fnet_dhcp_srv_options_t; +} fnet_dhcp_srv_options_t; /* Address pool entry state */ typedef enum @@ -102,7 +102,7 @@ typedef enum FNET_DHCP_SRV_ADDR_POOL_STATE_FREE = 0, FNET_DHCP_SRV_ADDR_POOL_STATE_OFFERED, FNET_DHCP_SRV_ADDR_POOL_STATE_BOUND, - /* FNET_DHCP_SRV_ADDR_POOL_STATE_EXPIRED */ + /* FNET_DHCP_SRV_ADDR_POOL_STATE_EXPIRED */ } fnet_dhcp_srv_addr_pool_state_t; /* Timeout for the FNET_DHCP_SRV_ADDR_POOL_STATE_OFFERED state */ @@ -136,11 +136,11 @@ typedef struct fnet_dhcp_srv_if fnet_ip4_addr_t dns; /* DNS server IPv4 address.*/ #endif fnet_uint32_t lease_time; /* Lease time in seconds.*/ - fnet_dhcp_header_t message; + fnet_dhcp_header_t message; -/* TBD RFC: Servers SHOULD be implemented so that -network administrators MAY choose to disable probes of newly -allocated addresses.*/ + /* TBD RFC: Servers SHOULD be implemented so that + network administrators MAY choose to disable probes of newly + allocated addresses.*/ } fnet_dhcp_srv_if_t; @@ -254,7 +254,7 @@ fnet_dhcp_srv_desc_t fnet_dhcp_srv_init(struct fnet_dhcp_srv_params *params) dhcp_srv_if->dns = fnet_netif_get_ip4_dns(dhcp_srv_if->netif); } #endif - + if((dhcp_srv_if->ip_addr_pool_size == 0) || (dhcp_srv_if->ip_addr_pool_size > FNET_CFG_DHCP_SRV_ADDR_POOL_SIZE)) { dhcp_srv_if->ip_addr_pool_size = FNET_CFG_DHCP_SRV_ADDR_POOL_SIZE; @@ -337,7 +337,7 @@ fnet_bool_t fnet_dhcp_srv_get_addr_pool_info(fnet_dhcp_srv_desc_t desc, fnet_ind if(n == 0u) { FNET_MAC_ADDR_COPY(addr_pool->client_identifier, addr_info->client_mac_addr); /* Client-identifier (MAC address)*/ - addr_info->client_ip4_addr = fnet_htonl(fnet_ntohl(dhcp_srv_if->ip_addr_pool_start) + i); /* Client IPv4 address allocated by the DHCPv4 server.*/ + addr_info->client_ip4_addr = fnet_htonl(fnet_ntohl(dhcp_srv_if->ip_addr_pool_start) + i); /* Client IPv4 address allocated by the DHCPv4 server.*/ addr_info->lease_time = addr_pool->lease_time - (fnet_timer_get_seconds() - addr_pool->state_timestamp); /* Lease time (in seconds).*/ result = FNET_TRUE; @@ -367,10 +367,10 @@ static void fnet_dhcp_srv_poll( void *fnet_dhcp_srv_if_p ) fnet_mac_addr_t *client_identifier; fnet_index_t i; fnet_ip4_addr_t server_identifier; - fnet_uint8_t message_type_tx = 0; + fnet_uint8_t message_type_tx = 0; /* Check address pool timeouts.*/ - for(i=0; i< dhcp_srv_if->ip_addr_pool_size; i++) + for(i = 0; i < dhcp_srv_if->ip_addr_pool_size; i++) { ip_addr_pool = &dhcp_srv_if->ip_addr_pool[i]; if(ip_addr_pool->state != FNET_DHCP_SRV_ADDR_POOL_STATE_FREE) @@ -397,13 +397,13 @@ static void fnet_dhcp_srv_poll( void *fnet_dhcp_srv_if_p ) size = fnet_socket_recvfrom(dhcp_srv_if->socket_srv, dhcp_header, sizeof(fnet_dhcp_header_t), 0U, &addr_from, &addr_len); /* Common field check */ - if((size > (fnet_ssize_t)(sizeof(fnet_dhcp_header_t) - FNET_DHCP_OPTIONS_LENGTH)) /* Check minimum size */ - && (dhcp_header->op == FNET_DHCP_OP_BOOTREQUEST) /* The 'op' field of each DHCP message sent from a client to a server contains BOOTREQUEST.*/ - && (dhcp_header->htype == FNET_DHCP_HTYPE_ETHERNET) /* Ethernet type.*/ - && (fnet_memcmp(dhcp_header->chaddr, fnet_eth_null_addr, sizeof(fnet_mac_addr_t))) /* Client HW address is not null */ - && (dhcp_header->hlen == sizeof(fnet_mac_addr_t)) /* Supports MAC address only as HW address */ - && !(fnet_memcmp(&dhcp_header->magic_cookie[0], fnet_dhcp_magic_cookie, sizeof(fnet_dhcp_magic_cookie))) /* Check magic cookie */ - ) + if((size > (fnet_ssize_t)(sizeof(fnet_dhcp_header_t) - FNET_DHCP_OPTIONS_LENGTH)) /* Check minimum size */ + && (dhcp_header->op == FNET_DHCP_OP_BOOTREQUEST) /* The 'op' field of each DHCP message sent from a client to a server contains BOOTREQUEST.*/ + && (dhcp_header->htype == FNET_DHCP_HTYPE_ETHERNET) /* Ethernet type.*/ + && (fnet_memcmp(dhcp_header->chaddr, fnet_eth_null_addr, sizeof(fnet_mac_addr_t))) /* Client HW address is not null */ + && (dhcp_header->hlen == sizeof(fnet_mac_addr_t)) /* Supports MAC address only as HW address */ + && !(fnet_memcmp(&dhcp_header->magic_cookie[0], fnet_dhcp_magic_cookie, sizeof(fnet_dhcp_magic_cookie))) /* Check magic cookie */ + ) { fnet_dhcp_trace("RX DHCP Server", dhcp_header); @@ -414,7 +414,7 @@ static void fnet_dhcp_srv_poll( void *fnet_dhcp_srv_if_p ) be interpreted.*/ fnet_dhcp_srv_parse_options(dhcp_header->options, size - (sizeof(fnet_dhcp_header_t) - FNET_DHCP_OPTIONS_LENGTH), &options_rx); - /* Parse overload options in sname/file + /* Parse overload options in sname/file Value Meaning ----- -------- 1 the 'file' field is used to hold options @@ -447,8 +447,8 @@ static void fnet_dhcp_srv_poll( void *fnet_dhcp_srv_if_p ) /* Get a network address for the requesting client. */ addr_pool_index = fnet_dhcp_srv_get_addr_pool(dhcp_srv_if, dhcp_header, client_identifier, options_rx.requested_ip_address); - - /* === Handle received message ===*/ + + /* === Handle received message ===*/ switch(options_rx.message_type) { /* DHCPDISCOVER message. @@ -460,7 +460,7 @@ static void fnet_dhcp_srv_poll( void *fnet_dhcp_srv_if_p ) /* Allocate a new address from the server’s pool of available addresses. */ if(addr_pool_index == FNET_ERR) { - addr_pool_index = fnet_dhcp_srv_get_addr_pool_free(dhcp_srv_if); + addr_pool_index = fnet_dhcp_srv_get_addr_pool_free(dhcp_srv_if); } if(addr_pool_index != FNET_ERR) @@ -492,7 +492,7 @@ static void fnet_dhcp_srv_poll( void *fnet_dhcp_srv_if_p ) if(addr_pool_index != FNET_ERR) { ip_addr_pool = &dhcp_srv_if->ip_addr_pool[addr_pool_index]; - + /* Must be allocated/offered by us */ if(ip_addr_pool->state != FNET_DHCP_SRV_ADDR_POOL_STATE_FREE) { @@ -506,12 +506,12 @@ static void fnet_dhcp_srv_poll( void *fnet_dhcp_srv_if_p ) /* Client inserts the address of the selected server in ’server identifier’. MUST (after MUST SELECTING)*/ if((server_identifier == options_rx.server_identifier) && - (dhcp_header->ciaddr == INADDR_ANY) ) /*’ciaddr’ MUST be zero */ + (dhcp_header->ciaddr == INADDR_ANY) ) /*’ciaddr’ MUST be zero */ { - /* Mark as bound */ - ip_addr_pool->state = FNET_DHCP_SRV_ADDR_POOL_STATE_BOUND; - /* Send ACK */ - message_type_tx = FNET_DHCP_OPTION_MSG_TYPE_ACK; + /* Mark as bound */ + ip_addr_pool->state = FNET_DHCP_SRV_ADDR_POOL_STATE_BOUND; + /* Send ACK */ + message_type_tx = FNET_DHCP_OPTION_MSG_TYPE_ACK; } } /* Otherwise, the message is a request to verify or extend an existing lease. */ @@ -535,10 +535,10 @@ static void fnet_dhcp_srv_poll( void *fnet_dhcp_srv_if_p ) if(options_rx.server_identifier) { /* Client inserts the address of the selected server in ’server identifier’*/ - if(server_identifier == options_rx.server_identifier) + if(server_identifier == options_rx.server_identifier) { - /* Send DHCPNAK */ - message_type_tx = FNET_DHCP_OPTION_MSG_TYPE_NAK; + /* Send DHCPNAK */ + message_type_tx = FNET_DHCP_OPTION_MSG_TYPE_NAK; } } } @@ -593,7 +593,7 @@ static void fnet_dhcp_srv_poll( void *fnet_dhcp_srv_if_p ) configuration parameters appropriate for the client without: allocating a new address, checking for an existing binding, filling in ’yiaddr’ or including lease time parameters.*/ - addr_pool_index = FNET_ERR; + addr_pool_index = FNET_ERR; message_type_tx = FNET_DHCP_OPTION_MSG_TYPE_ACK; } break; @@ -627,7 +627,7 @@ static void fnet_dhcp_srv_send_message(fnet_dhcp_srv_if_t *dhcp_if, fnet_ip4_add fnet_bool_t add_lease_time = FNET_FALSE; fnet_index_t i; fnet_uint16_t port_number = FNET_CFG_DHCP_CLN_PORT; - + /* == Common reply message parameters == */ message->op = FNET_DHCP_OP_BOOTREPLY; /* ’op’ BOOTREPLY */ message->htype = FNET_DHCP_HTYPE_ETHERNET; /* Ethernet */ @@ -643,7 +643,7 @@ static void fnet_dhcp_srv_send_message(fnet_dhcp_srv_if_t *dhcp_if, fnet_ip4_add fnet_memset_zero(message->file, sizeof(message->file)); /* Clear 'file' options.*/ fnet_memcpy(message->magic_cookie, fnet_dhcp_magic_cookie, sizeof(fnet_dhcp_magic_cookie)); /* Add "magic cookie" */ fnet_memset_zero(message->options, sizeof(message->options)); /* Clear 'options' options.*/ - + /* If the ’giaddr’ field in a DHCP message from a client is non-zero, the server sends any return messages to the ’DHCP server’ port on the BOOTP relay agent whose address appears in ’giaddr’. If the ’giaddr’ @@ -673,14 +673,14 @@ static void fnet_dhcp_srv_send_message(fnet_dhcp_srv_if_t *dhcp_if, fnet_ip4_add /* Add DHCP options */ option_position = message->options; - + /* Add DHCP message type option */ option_position = fnet_dhcp_srv_add_option(option_position, ((message->options + sizeof(message->options)) - option_position), FNET_DHCP_OPTION_MSG_TYPE, FNET_DHCP_OPTION_MSG_TYPE_LENGTH, &message_type); if(option_position == FNET_NULL) { goto EXIT; } - + /* Add server identifier. A DHCP server always returns its own address in the ’server identifier’ option.*/ option_position = fnet_dhcp_srv_add_option(option_position, ((message->options + sizeof(message->options)) - option_position), FNET_DHCP_OPTION_SERVER_ID, FNET_DHCP_OPTION_SERVER_ID_LENGTH, &server_identifier); if(option_position == FNET_NULL) @@ -743,18 +743,18 @@ static void fnet_dhcp_srv_send_message(fnet_dhcp_srv_if_t *dhcp_if, fnet_ip4_add case FNET_DHCP_OPTION_ROUTER: option_position_tmp = fnet_dhcp_srv_add_option(option_position, ((message->options + sizeof(message->options)) - option_position), FNET_DHCP_OPTION_ROUTER, FNET_DHCP_OPTION_ROUTER_LENGTH_MIN, &dhcp_if->gateway); break; - #if FNET_CFG_DNS +#if FNET_CFG_DNS case FNET_DHCP_OPTION_DNS: option_position_tmp = fnet_dhcp_srv_add_option(option_position, ((message->options + sizeof(message->options)) - option_position), FNET_DHCP_OPTION_DNS, FNET_DHCP_OPTION_DNS_LENGTH_MIN, &dhcp_if->dns); break; - #endif +#endif /*RFC: Times T1 and T2 are configurable by the server through options. T1 defaults to (0.5 * duration_of_lease). */ case FNET_DHCP_OPTION_T1: if(add_lease_time == FNET_TRUE) { fnet_uint32_t t1; - t1 = fnet_htonl(dhcp_if->ip_addr_pool[addr_pool_index].lease_time>>1); + t1 = fnet_htonl(dhcp_if->ip_addr_pool[addr_pool_index].lease_time >> 1); option_position_tmp = fnet_dhcp_srv_add_option(option_position, ((message->options + sizeof(message->options)) - option_position), FNET_DHCP_OPTION_T1, FNET_DHCP_OPTION_T1_LENGTH, &t1); } break; @@ -763,7 +763,7 @@ static void fnet_dhcp_srv_send_message(fnet_dhcp_srv_if_t *dhcp_if, fnet_ip4_add if(add_lease_time == FNET_TRUE) { fnet_uint32_t t2; - t2 = fnet_htonl(dhcp_if->ip_addr_pool[addr_pool_index].lease_time - (dhcp_if->ip_addr_pool[addr_pool_index].lease_time>>3)); + t2 = fnet_htonl(dhcp_if->ip_addr_pool[addr_pool_index].lease_time - (dhcp_if->ip_addr_pool[addr_pool_index].lease_time >> 3)); option_position_tmp = fnet_dhcp_srv_add_option(option_position, ((message->options + sizeof(message->options)) - option_position), FNET_DHCP_OPTION_T2, FNET_DHCP_OPTION_T2_LENGTH, &t2); } break; @@ -773,7 +773,7 @@ static void fnet_dhcp_srv_send_message(fnet_dhcp_srv_if_t *dhcp_if, fnet_ip4_add if(option_position_tmp != FNET_NULL) { option_position = option_position_tmp; - } + } } } @@ -804,7 +804,7 @@ static fnet_uint8_t *fnet_dhcp_srv_add_option(fnet_uint8_t *option_buffer, fnet_ { FNET_ASSERT(option_buffer != FNET_NULl); FNET_ASSERT(option_value != FNET_NULl); - + fnet_uint8_t *result = FNET_NULL; if(option_buffer_size >= (2U/*type+length*/ + 1U/* END option*/ + option_length)) @@ -943,14 +943,14 @@ static void fnet_dhcp_srv_parse_options( fnet_uint8_t *option_buffer, fnet_size_ This option is used by DHCP clients to specify their unique identifier. DHCP servers use this value to index their database of address bindings. This value is expected to be unique for all - clients in an administrative domain. + clients in an administrative domain. Code Len Type Client-Identifier +-----+-----+-----+-----+-----+--- | 61 | n | t1 | i1 | i2 | ... +-----+-----+-----+-----+-----+---*/ case FNET_DHCP_OPTION_CLIENT_ID: - if((option_length == FNET_DHCP_OPTION_CLIENT_ID_LENGTH) - && (option_data[0] == FNET_DHCP_HTYPE_ETHERNET)) /* Supported only Ethernet type */ + if((option_length == FNET_DHCP_OPTION_CLIENT_ID_LENGTH) + && (option_data[0] == FNET_DHCP_HTYPE_ETHERNET)) /* Supported only Ethernet type */ { fnet_memcpy(&options->client_identifier, &option_data[1], sizeof(options->client_identifier)); } @@ -959,10 +959,10 @@ static void fnet_dhcp_srv_parse_options( fnet_uint8_t *option_buffer, fnet_size_ This option is used to indicate that the DHCP 'sname' or 'file' fields are being overloaded by using them to carry DHCP options. A DHCP server inserts this option if the returned parameters will - exceed the usual space allotted for options. + exceed the usual space allotted for options. If this option is present, the client interprets the specified additional fields after it concludes interpretation of the standard - option fields. + option fields. Value Meaning ----- -------- 1 the 'file' field is used to hold options @@ -1032,7 +1032,7 @@ static void fnet_dhcp_srv_parse_options( fnet_uint8_t *option_buffer, fnet_size_ } /************************************************************************ -* DESCRIPTION: Choose client address. Returns address pool index. +* DESCRIPTION: Choose client address. Returns address pool index. * FNET_ERR means there is no address in the address pool. ************************************************************************/ static fnet_int32_t fnet_dhcp_srv_get_addr_pool(fnet_dhcp_srv_if_t *dhcp_srv_if, fnet_dhcp_header_t *dhcp_header, fnet_mac_addr_t *client_identifier, fnet_ip4_addr_t requested_ip_address) @@ -1051,7 +1051,7 @@ static fnet_int32_t fnet_dhcp_srv_get_addr_pool(fnet_dhcp_srv_if_t *dhcp_srv_if, o The client’s previous address as recorded in the client’s (now expired or released) binding, if that address is in the server’s pool of available addresses and not already allocated, ELSE*/ - for(i=0; i< dhcp_srv_if->ip_addr_pool_size; i++) + for(i = 0; i < dhcp_srv_if->ip_addr_pool_size; i++) { ip_addr_pool = &dhcp_srv_if->ip_addr_pool[i]; if(!fnet_memcmp(client_identifier, ip_addr_pool->client_identifier, sizeof(fnet_mac_addr_t))) @@ -1077,17 +1077,17 @@ static fnet_int32_t fnet_dhcp_srv_get_addr_pool(fnet_dhcp_srv_if_t *dhcp_srv_if, address is valid and not already allocated, ELSE*/ if(ip_addr_pool->state == FNET_DHCP_SRV_ADDR_POOL_STATE_FREE) { - result = i; + result = i; } } } - } + } return result; } /************************************************************************ -* DESCRIPTION: Get free client address from the pool. Returns address pool index. +* DESCRIPTION: Get free client address from the pool. Returns address pool index. * FNET_ERR means the pool is full. ************************************************************************/ static fnet_int32_t fnet_dhcp_srv_get_addr_pool_free(fnet_dhcp_srv_if_t *dhcp_srv_if) @@ -1099,7 +1099,7 @@ static fnet_int32_t fnet_dhcp_srv_get_addr_pool_free(fnet_dhcp_srv_if_t *dhcp_sr fnet_dhcp_srv_addr_pool_t *ip_addr_pool; /* A new address allocated from the server’s pool of available addresses. */ - for(i=0; i< dhcp_srv_if->ip_addr_pool_size; i++) + for(i = 0; i < dhcp_srv_if->ip_addr_pool_size; i++) { ip_addr_pool = &dhcp_srv_if->ip_addr_pool[i]; if(ip_addr_pool->state == FNET_DHCP_SRV_ADDR_POOL_STATE_FREE) @@ -1108,7 +1108,7 @@ static fnet_int32_t fnet_dhcp_srv_get_addr_pool_free(fnet_dhcp_srv_if_t *dhcp_sr break; } } - + return result; } @@ -1124,7 +1124,7 @@ static void fnet_dhcp_srv_set_lease_time(fnet_dhcp_srv_if_t *dhcp_srv_if, fnet_d /*RFC: The server must also choose an expiration time for the lease, as follows:*/ - + if(options->lease_time == 0) { /*o IF the client has not requested a specific lease in the @@ -1187,7 +1187,7 @@ fnet_dhcp_srv_desc_t fnet_dhcp_srv_get_by_netif(fnet_netif_desc_t netif) { fnet_dhcp_srv_if_t *dhcp_if; fnet_index_t i; - fnet_dhcp_srv_desc_t dhcp_desc = 0; + fnet_dhcp_srv_desc_t dhcp_desc = 0; if(netif) { @@ -1202,7 +1202,7 @@ fnet_dhcp_srv_desc_t fnet_dhcp_srv_get_by_netif(fnet_netif_desc_t netif) } } } - + return dhcp_desc; } diff --git a/fnet_stack/service/dhcp/fnet_dhcp_srv.h b/fnet_stack/service/dhcp/fnet_dhcp_srv.h index 2a2a2327..7c7efccf 100644 --- a/fnet_stack/service/dhcp/fnet_dhcp_srv.h +++ b/fnet_stack/service/dhcp/fnet_dhcp_srv.h @@ -73,7 +73,7 @@ struct fnet_dhcp_srv_params typedef struct { fnet_mac_addr_t client_mac_addr; /**< @brief Client-identifier (MAC address)*/ - fnet_ip4_addr_t client_ip4_addr; /**< @brief Client IPv4 address allocated by the DHCPv4 server.*/ + fnet_ip4_addr_t client_ip4_addr; /**< @brief Client IPv4 address allocated by the DHCPv4 server.*/ fnet_time_t lease_time; /**< @brief Lease time (in seconds).*/ } fnet_dhcp_srv_addr_pool_info_t; @@ -81,7 +81,7 @@ typedef struct * @brief DHCPv4 server descriptor. * @see fnet_dhcp_srv_init() ******************************************************************************/ -typedef void* fnet_dhcp_srv_desc_t; +typedef void *fnet_dhcp_srv_desc_t; #if defined(__cplusplus) extern "C" { @@ -142,7 +142,7 @@ void fnet_dhcp_srv_release(fnet_dhcp_srv_desc_t desc); * ****************************************************************************** * - * This function is used to retrieve an information about addresses allocated by + * This function is used to retrieve an information about addresses allocated by * the DHCPv4 server. * ******************************************************************************/ @@ -179,7 +179,7 @@ fnet_bool_t fnet_dhcp_srv_is_enabled(fnet_dhcp_srv_desc_t desc); * ****************************************************************************** * - * This function is looking for a DHCP Server service assigned to + * This function is looking for a DHCP Server service assigned to * the @c netif network interface set during its initialization. * ******************************************************************************/ diff --git a/fnet_stack/service/fnet_service.h b/fnet_stack/service/fnet_service.h index c8282acf..a34c57e7 100644 --- a/fnet_stack/service/fnet_service.h +++ b/fnet_stack/service/fnet_service.h @@ -143,5 +143,7 @@ void fnet_service_unregister( fnet_service_desc_t desc ); } #endif -#endif +/*! @} */ + +#endif /* _FNET_SERVICE_H_ */ diff --git a/fnet_stack/service/link/fnet_link.c b/fnet_stack/service/link/fnet_link.c index 66ef0261..17585a1e 100644 --- a/fnet_stack/service/link/fnet_link.c +++ b/fnet_stack/service/link/fnet_link.c @@ -166,7 +166,7 @@ fnet_link_desc_t fnet_link_get_by_netif(fnet_netif_desc_t netif) { fnet_link_if_t *link_if; fnet_index_t i; - fnet_link_desc_t link_desc = 0; + fnet_link_desc_t link_desc = 0; if(netif) { @@ -181,7 +181,7 @@ fnet_link_desc_t fnet_link_get_by_netif(fnet_netif_desc_t netif) } } } - + return link_desc; } diff --git a/fnet_stack/service/link/fnet_link.h b/fnet_stack/service/link/fnet_link.h index 6db8ed4d..f4a44a42 100644 --- a/fnet_stack/service/link/fnet_link.h +++ b/fnet_stack/service/link/fnet_link.h @@ -140,7 +140,7 @@ fnet_bool_t fnet_link_is_enabled(fnet_link_desc_t desc); * ****************************************************************************** * - * This function is looking for a Link-Detection service assigned to + * This function is looking for a Link-Detection service assigned to * the @c netif network interface set during its initialization. * ******************************************************************************/ diff --git a/fnet_stack/service/link/fnet_link_config.h b/fnet_stack/service/link/fnet_link_config.h index 33426ce9..def6fe76 100644 --- a/fnet_stack/service/link/fnet_link_config.h +++ b/fnet_stack/service/link/fnet_link_config.h @@ -27,7 +27,7 @@ /**************************************************************************/ /*! * @def FNET_CFG_LINK * @brief Link-detection service support: - * - @c 1..n = is enabled. Its value defines maximum number of + * - @c 1..n = is enabled. Its value defines maximum number of * the Link-Detection services that can be run simultaneously. * - @b @c 0 = is disabled (Default value). ******************************************************************************/ diff --git a/fnet_stack/service/llmnr/fnet_llmnr.c b/fnet_stack/service/llmnr/fnet_llmnr.c index 2205b62d..c6a70f5a 100644 --- a/fnet_stack/service/llmnr/fnet_llmnr.c +++ b/fnet_stack/service/llmnr/fnet_llmnr.c @@ -569,7 +569,7 @@ fnet_llmnr_desc_t fnet_llmnr_get_by_netif(fnet_netif_desc_t netif) { fnet_llmnr_if_t *llmnr_if; fnet_index_t i; - fnet_llmnr_desc_t llmnr_desc = 0; + fnet_llmnr_desc_t llmnr_desc = 0; if(netif) { @@ -584,7 +584,7 @@ fnet_llmnr_desc_t fnet_llmnr_get_by_netif(fnet_netif_desc_t netif) } } } - + return llmnr_desc; } diff --git a/fnet_stack/service/llmnr/fnet_llmnr.h b/fnet_stack/service/llmnr/fnet_llmnr.h index f9153fd1..6d33e772 100644 --- a/fnet_stack/service/llmnr/fnet_llmnr.h +++ b/fnet_stack/service/llmnr/fnet_llmnr.h @@ -147,7 +147,7 @@ fnet_bool_t fnet_llmnr_is_enabled(fnet_llmnr_desc_t desc); * ****************************************************************************** * - * This function is looking for a LLMNR Server service assigned to + * This function is looking for a LLMNR Server service assigned to * the @c netif network interface set during its initialization. * ******************************************************************************/ diff --git a/fnet_stack/service/llmnr/fnet_llmnr_config.h b/fnet_stack/service/llmnr/fnet_llmnr_config.h index 8b6eda68..f669e391 100644 --- a/fnet_stack/service/llmnr/fnet_llmnr_config.h +++ b/fnet_stack/service/llmnr/fnet_llmnr_config.h @@ -36,8 +36,8 @@ /**************************************************************************/ /*! * @def FNET_CFG_LLMNR * @brief Link-Local Multicast Name Resolution (LLMNR) Server/Responder support: - * - @c 1..n = is enabled. Its value defines maximum number of - * the LLMNR Servers that can be run simultaneously. + * - @c 1..n = is enabled. Its value defines maximum number of + * the LLMNR Servers that can be run simultaneously. * - @b @c 0 = is disabled (Default value). ******************************************************************************/ #ifndef FNET_CFG_LLMNR diff --git a/fnet_stack/service/mdns/fnet_mdns.c b/fnet_stack/service/mdns/fnet_mdns.c index c0f3be40..28f116be 100644 --- a/fnet_stack/service/mdns/fnet_mdns.c +++ b/fnet_stack/service/mdns/fnet_mdns.c @@ -545,7 +545,7 @@ fnet_mdns_service_desc_t fnet_mdns_service_get_by_type(fnet_mdns_desc_t mdns_des { if(mdns_if->service_if_list[i].service_type) { - if (!fnet_strcmp(mdns_if->service_if_list[i].service_type, service_type)) + if (!fnet_strcmp(mdns_if->service_if_list[i].service_type, service_type)) { result = (fnet_mdns_service_desc_t)&mdns_if->service_if_list[i]; break; /* Found.*/ @@ -628,7 +628,7 @@ fnet_mdns_desc_t fnet_mdns_get_by_netif(fnet_netif_desc_t netif) { fnet_mdns_if_t *mdns_if; fnet_index_t i; - fnet_mdns_desc_t mdns_desc = 0; + fnet_mdns_desc_t mdns_desc = 0; if(netif) { @@ -643,7 +643,7 @@ fnet_mdns_desc_t fnet_mdns_get_by_netif(fnet_netif_desc_t netif) } } } - + return mdns_desc; } @@ -1126,16 +1126,16 @@ static const fnet_uint8_t *fnet_mdns_process_query(fnet_mdns_if_t *mdns_if, fnet mdns_if->is_shared = FNET_TRUE; mdns_if->is_shared_timestamp = fnet_timer_get_ms(); /* Calculated shared response delay */ - #if 0 /* Original */ - mdns_if->is_shared_response_delay = FNET_MDNS_SHARED_RESPONSE_DELAY_MIN + (fnet_rand()% (FNET_MDNS_SHARED_RESPONSE_DELAY_MAX - FNET_MDNS_SHARED_RESPONSE_DELAY_MIN)); - #else /* To workaround BCT warning */ - mdns_if->is_shared_response_delay += (FNET_MDNS_SHARED_RESPONSE_DELAY_MAX - FNET_MDNS_SHARED_RESPONSE_DELAY_MIN)/4; +#if 0 /* Original */ + mdns_if->is_shared_response_delay = FNET_MDNS_SHARED_RESPONSE_DELAY_MIN + (fnet_rand() % (FNET_MDNS_SHARED_RESPONSE_DELAY_MAX - FNET_MDNS_SHARED_RESPONSE_DELAY_MIN)); +#else /* To workaround BCT warning */ + mdns_if->is_shared_response_delay += (FNET_MDNS_SHARED_RESPONSE_DELAY_MAX - FNET_MDNS_SHARED_RESPONSE_DELAY_MIN) / 4; mdns_if->is_shared_response_delay = mdns_if->is_shared_response_delay % FNET_MDNS_SHARED_RESPONSE_DELAY_MAX; if(mdns_if->is_shared_response_delay < FNET_MDNS_SHARED_RESPONSE_DELAY_MIN) { - mdns_if->is_shared_response_delay += FNET_MDNS_SHARED_RESPONSE_DELAY_MIN; + mdns_if->is_shared_response_delay += FNET_MDNS_SHARED_RESPONSE_DELAY_MIN; } - #endif +#endif } } } @@ -1732,7 +1732,7 @@ static const fnet_uint8_t *fnet_mdns_process_response(fnet_mdns_if_t *mdns_if, c { rr_header = (fnet_mdns_rr_header_t *)ptr; ptr += sizeof(fnet_mdns_rr_header_t) + fnet_htons(rr_header->data_length); - + /* Compare received name with our names */ fnet_bool_t is_our_host_name = fnet_mdns_is_our_host_name(mdns_if, rr_name); fnet_bool_t is_our_service_name = fnet_mdns_is_our_service_name(mdns_if, rr_name); @@ -1743,7 +1743,7 @@ static const fnet_uint8_t *fnet_mdns_process_response(fnet_mdns_if_t *mdns_if, c (rr_header->type == FNET_HTONS(FNET_MDNS_RR_A)) || (rr_header->type == FNET_HTONS(FNET_MDNS_RR_AAAA))) #endif - ) + ) { #if FNET_CFG_DEBUG_MDNS && FNET_CFG_DEBUG fnet_mdns_print_qe_name("MDNS: RX response for:", rr_name); @@ -1756,7 +1756,7 @@ static const fnet_uint8_t *fnet_mdns_process_response(fnet_mdns_if_t *mdns_if, c /* If in Probing state, change name and try again */ if((mdns_if->state == FNET_MDNS_STATE_PROBING) - ||(mdns_if->state == FNET_MDNS_STATE_PROBING_WAIT)) + || (mdns_if->state == FNET_MDNS_STATE_PROBING_WAIT)) { /* Regenerate names.*/ if(is_our_host_name) @@ -1816,9 +1816,9 @@ static void fnet_mdns_recv(fnet_mdns_if_t *mdns_if) if(received > sizeof(fnet_mdns_header_t)) { mdns_header = (fnet_mdns_header_t *)&mdns_if->buffer[0]; - + char *hostname = (char *)&mdns_if->buffer[sizeof(fnet_mdns_header_t)]; - + /* Query */ if( ((mdns_header->flags & FNET_HTONS(FNET_MDNS_HEADER_FLAGS_QR)) == 0) /* Query.*/ && ((mdns_header->flags & FNET_HTONS(FNET_MDNS_HEADER_FLAGS_OPCODE)) == 0) ) /* Standard Query */ @@ -1831,7 +1831,7 @@ static void fnet_mdns_recv(fnet_mdns_if_t *mdns_if) { mdns_if->is_legacy_unicast = FNET_FALSE; } - + if( (mdns_header->flags & FNET_HTONS(FNET_MDNS_HEADER_FLAGS_TC)) == 0) /* Trancation.*/ { mdns_if->is_truncated = FNET_FALSE; @@ -1840,7 +1840,7 @@ static void fnet_mdns_recv(fnet_mdns_if_t *mdns_if) { mdns_if->is_truncated = FNET_TRUE; } - + ptr = (fnet_uint8_t *)hostname; for(i = 0; i < fnet_htons(mdns_header->qdcount); i++) { @@ -1850,14 +1850,14 @@ static void fnet_mdns_recv(fnet_mdns_if_t *mdns_if) return; } } - + /* Duplicate Suppression.*/ if(mdns_if->response_type != FNET_MDNS_QUERY_NONE) { const fnet_uint8_t *an_ptr; - + an_ptr = fnet_mdns_get_an(mdns_if->buffer, received); - + /* Eliminate duplicated answers */ if(an_ptr) { @@ -1867,14 +1867,14 @@ static void fnet_mdns_recv(fnet_mdns_if_t *mdns_if) } /* Response */ else if( ( ((mdns_header->flags & FNET_HTONS(FNET_MDNS_HEADER_FLAGS_QR)) != 0) && /* Response.*/ - (mdns_header->qdcount == 0)) && - ( (mdns_header->nscount > 0) - || (mdns_header->arcount > 0) - || (mdns_header->ancount > 0)) - ) + (mdns_header->qdcount == 0)) && + ( (mdns_header->nscount > 0) + || (mdns_header->arcount > 0) + || (mdns_header->ancount > 0)) + ) { cnt = fnet_htons(mdns_header->nscount) + fnet_htons(mdns_header->arcount) + fnet_htons(mdns_header->ancount) + fnet_htons(mdns_header->qdcount); - + ptr = (fnet_uint8_t *)hostname; for(i = 0; (i < cnt) && (ptr < (mdns_if->buffer + received)); i++) { @@ -1886,7 +1886,7 @@ static void fnet_mdns_recv(fnet_mdns_if_t *mdns_if) } } } - + } } } diff --git a/fnet_stack/service/mdns/fnet_mdns.h b/fnet_stack/service/mdns/fnet_mdns.h index f398d3c2..8c771aea 100644 --- a/fnet_stack/service/mdns/fnet_mdns.h +++ b/fnet_stack/service/mdns/fnet_mdns.h @@ -194,7 +194,7 @@ void fnet_mdns_service_unregister(fnet_mdns_service_desc_t service_desc); * * @param mdns_desc mDNS server descriptor. * - * @param service_type Service Type. Null-terminated string. Example "_http._tcp". + * @param service_type Service Type. Null-terminated string. Example "_http._tcp". * * @return This function returns: * - mDNS service descriptor that matches the @c service_type parameter. @@ -262,7 +262,7 @@ fnet_bool_t fnet_mdns_is_enabled(fnet_mdns_desc_t desc); * ****************************************************************************** * - * This function is looking for a mDNS Server service assigned to + * This function is looking for a mDNS Server service assigned to * the @c netif network interface set during its initialization. * ******************************************************************************/ diff --git a/fnet_stack/service/mdns/fnet_mdns_config.h b/fnet_stack/service/mdns/fnet_mdns_config.h index 5feb8dd7..5e98c3f9 100644 --- a/fnet_stack/service/mdns/fnet_mdns_config.h +++ b/fnet_stack/service/mdns/fnet_mdns_config.h @@ -36,7 +36,7 @@ /**************************************************************************/ /*! * @def FNET_CFG_MDNS * @brief Multicast Domain Name System (mDNS/Bonjour) Server/Responder (RFC6762) support: - * - @c 1..n = is enabled. Its value defines maximum number of + * - @c 1..n = is enabled. Its value defines maximum number of * the mDNS Servers that can be run simultaneously. * - @b @c 0 = is disabled (Default value). ******************************************************************************/ diff --git a/fnet_stack/service/ping/fnet_ping.h b/fnet_stack/service/ping/fnet_ping.h index a0582453..8184e884 100644 --- a/fnet_stack/service/ping/fnet_ping.h +++ b/fnet_stack/service/ping/fnet_ping.h @@ -87,7 +87,7 @@ typedef enum * * @see fnet_ping_request(), fnet_ping_params ******************************************************************************/ -typedef void(*fnet_ping_callback_t)(fnet_error_t result, fnet_size_t packet_count, struct fnet_sockaddr *target_addr, void* cookie); +typedef void(*fnet_ping_callback_t)(fnet_error_t result, fnet_size_t packet_count, struct fnet_sockaddr *target_addr, void *cookie); /**************************************************************************/ /*! * @brief Initialization parameters for the @ref fnet_ping_request() function. diff --git a/fnet_stack/service/shell/fnet_shell.c b/fnet_stack/service/shell/fnet_shell.c index 3fe12822..fad080a2 100644 --- a/fnet_stack/service/shell/fnet_shell.c +++ b/fnet_stack/service/shell/fnet_shell.c @@ -108,11 +108,11 @@ static void fnet_shell_poll( void *shell_if_p ) const struct fnet_shell *shell = ((struct fnet_shell_if *)shell_if_p)->shell; fnet_int32_t ch; fnet_index_t argc; - fnet_char_t *argv[FNET_CFG_SHELL_ARGS_MAX + 1u]={0}; /* One extra for 0 terminator.*/ + fnet_char_t *argv[FNET_CFG_SHELL_ARGS_MAX + 1u] = {0}; /* One extra for 0 terminator.*/ if(shell_if->is_active == FNET_FALSE) { - shell_if->is_active = FNET_TRUE; + shell_if->is_active = FNET_TRUE; switch(shell_if->state) { @@ -559,10 +559,10 @@ fnet_return_t fnet_shell_script(fnet_shell_desc_t desc, fnet_char_t *script ) fnet_shell_unblock(desc); script_size = fnet_strlen(script); - + if(script_size) { - if(script_size+1/*splitter*/+1/*size*/ > shell_if->cmd_line_size) + if(script_size + 1/*splitter*/ + 1/*size*/ > shell_if->cmd_line_size) { goto ERROR; } @@ -575,7 +575,7 @@ fnet_return_t fnet_shell_script(fnet_shell_desc_t desc, fnet_char_t *script ) fnet_int32_t cmd_line_shift; fnet_index_t i; - if(cmd_line_end_size+script_size+1/*splitter*/+1/*size*/ > shell_if->cmd_line_size) + if(cmd_line_end_size + script_size + 1/*splitter*/ + 1/*size*/ > shell_if->cmd_line_size) { goto ERROR; } @@ -583,16 +583,16 @@ fnet_return_t fnet_shell_script(fnet_shell_desc_t desc, fnet_char_t *script ) cmd_line_shift = (shell_if->cmd_line + script_size + 1) - shell_if->cmd_line_end; if(cmd_line_shift < 0) /* Shift left */ { - for(i=0; i<= cmd_line_end_size; i++) + for(i = 0; i <= cmd_line_end_size; i++) { - shell_if->cmd_line_end[cmd_line_shift+i] = shell_if->cmd_line_end[i]; + shell_if->cmd_line_end[cmd_line_shift + i] = shell_if->cmd_line_end[i]; } } else if(cmd_line_shift > 0) /* Shift right */ { - for(i=0; i<= cmd_line_end_size; i++) + for(i = 0; i <= cmd_line_end_size; i++) { - shell_if->cmd_line_end[cmd_line_end_size+cmd_line_shift-i] = shell_if->cmd_line_end[cmd_line_end_size-i]; + shell_if->cmd_line_end[cmd_line_end_size + cmd_line_shift - i] = shell_if->cmd_line_end[cmd_line_end_size - i]; } } diff --git a/fnet_stack/service/shell/fnet_shell_config.h b/fnet_stack/service/shell/fnet_shell_config.h index 799fc672..58bda67e 100644 --- a/fnet_stack/service/shell/fnet_shell_config.h +++ b/fnet_stack/service/shell/fnet_shell_config.h @@ -40,7 +40,7 @@ * Default value is @b @c 1. ******************************************************************************/ #ifndef FNET_CFG_SHELL_MAX - #define FNET_CFG_SHELL_MAX (1u+(FNET_CFG_TELNET*FNET_CFG_TELNET_SESSION_MAX)) + #define FNET_CFG_SHELL_MAX (1u+(FNET_CFG_TELNET*FNET_CFG_TELNET_SESSION_MAX)) #endif /**************************************************************************/ /*! diff --git a/fnet_stack/service/telnet/fnet_telnet_config.h b/fnet_stack/service/telnet/fnet_telnet_config.h index 13c0c920..682522c2 100644 --- a/fnet_stack/service/telnet/fnet_telnet_config.h +++ b/fnet_stack/service/telnet/fnet_telnet_config.h @@ -37,7 +37,7 @@ /**************************************************************************/ /*! * @def FNET_CFG_TELNET * @brief Telnet server support: - * - @c 1..n = is enabled. Its value defines maximum number of + * - @c 1..n = is enabled. Its value defines maximum number of * the Telnet Servers that can be run simultaneously. * - @b @c 0 = is disabled (Default value). ******************************************************************************/ diff --git a/fnet_stack/service/tftp/fnet_tftp_config.h b/fnet_stack/service/tftp/fnet_tftp_config.h index c70199c3..1e96a98a 100644 --- a/fnet_stack/service/tftp/fnet_tftp_config.h +++ b/fnet_stack/service/tftp/fnet_tftp_config.h @@ -47,8 +47,8 @@ /**************************************************************************/ /*! * @def FNET_CFG_TFTP_SRV * @brief TFTP Server support: - * - @c 1..n = is enabled. Its value defines maximum number of - * the TFTP Servers that can be run simultaneously. + * - @c 1..n = is enabled. Its value defines maximum number of + * the TFTP Servers that can be run simultaneously. * - @b @c 0 = is disabled (Default value). ******************************************************************************/ #ifndef FNET_CFG_TFTP_SRV diff --git a/fnet_stack/service/tls/fnet_tls_config.h b/fnet_stack/service/tls/fnet_tls_config.h index 96373bb1..27d59316 100644 --- a/fnet_stack/service/tls/fnet_tls_config.h +++ b/fnet_stack/service/tls/fnet_tls_config.h @@ -36,7 +36,7 @@ /**************************************************************************/ /*! * @def FNET_CFG_TLS * @brief TLS Library support: - * - @c 1..n = is enabled (mbedTLS). Its value defines + * - @c 1..n = is enabled (mbedTLS). Its value defines * the maximum number of the TLS contexts that can be initialized * simultaneously, using fnet_tls_init(). * - @b @c 0 = is disabled (Default value). diff --git a/fnet_stack/stack/fnet_eth.c b/fnet_stack/stack/fnet_eth.c index eefbed63..2332d6da 100644 --- a/fnet_stack/stack/fnet_eth.c +++ b/fnet_stack/stack/fnet_eth.c @@ -187,14 +187,14 @@ static const fnet_eth_prot_if_t fnet_eth_prot_if_list[] = }while(0) #if 0 /* Done by fnet_netif_is_connected()*/ -#define FNET_ETH_TIMER_PERIOD (500U) /*ms*/ + #define FNET_ETH_TIMER_PERIOD (500U) /*ms*/ #endif /****************************************************************************** * Function Prototypes *******************************************************************************/ #if 0 /* Done by fnet_netif_is_connected()*/ -static void fnet_eth_timer(fnet_uint32_t cookie ); + static void fnet_eth_timer(fnet_uint32_t cookie ); #endif /************************************************************************ @@ -219,23 +219,23 @@ void fnet_eth_input( fnet_netif_t *netif, fnet_uint8_t *frame, fnet_size_t frame { goto DROP; } - + fnet_eth_trace("\nRX", ethheader); /* Print ETH header.*/ - + nb = fnet_netbuf_from_buf( ((fnet_uint8_t *)ethheader + sizeof(fnet_eth_header_t)), - (frame_size - sizeof(fnet_eth_header_t)), FNET_TRUE ); + (frame_size - sizeof(fnet_eth_header_t)), FNET_TRUE ); if(nb) { if(FNET_MAC_ADDR_IS_BROADCAST(ethheader->destination_addr)) /* Broadcast */ { nb->flags |= FNET_NETBUF_FLAG_BROADCAST; } - + if(FNET_MAC_ADDR_IS_MULTICAST(ethheader->destination_addr)) /* Multicast */ { nb->flags |= FNET_NETBUF_FLAG_MULTICAST; } - + /* Network-layer input (IPv4/6, ARP).*/ protocol_type = ethheader->type; @@ -390,7 +390,7 @@ void fnet_eth_release( fnet_netif_t *netif) #endif /* FNET_CFG_IP6 */ -#if 0 +#if 0 fnet_timer_free(((fnet_eth_if_t *)(netif->netif_prv))->eth_timer); #endif @@ -618,7 +618,7 @@ void fnet_eth_multicast_leave_ip4(fnet_netif_t *netif, fnet_ip4_addr_t multicast FNET_ASSERT(netif->netif_prv != FNET_NULL); fnet_mac_addr_t mac_addr; - + if(((fnet_eth_if_t *)(netif->netif_prv))->eth_multicast_leave) { FNET_ETH_MULTICAST_IP4_TO_MAC(multicast_addr, mac_addr); @@ -656,7 +656,7 @@ void fnet_eth_multicast_leave_ip6(fnet_netif_t *netif, fnet_ip6_addr_t *multicas FNET_ASSERT(netif->netif_prv != FNET_NULL); fnet_mac_addr_t mac_addr; - + if(((fnet_eth_if_t *)(netif->netif_prv))->eth_multicast_leave) { FNET_ETH_MULTICAST_IP6_TO_MAC(multicast_addr, mac_addr); diff --git a/fnet_stack/stack/fnet_eth.h b/fnet_stack/stack/fnet_eth.h index 6b3399ff..bc468e20 100644 --- a/fnet_stack/stack/fnet_eth.h +++ b/fnet_stack/stack/fnet_eth.h @@ -75,11 +75,11 @@ typedef fnet_uint8_t fnet_mac_addr_t[6]; /* MAC address type.*/ /* MAC address is broadcast. */ #define FNET_MAC_ADDR_IS_BROADCAST(a) (((((a)[0]) == 0xFFU) && \ - (((a)[1]) == 0xFFU)&& \ - (((a)[1]) == 0xFFU)&& \ - (((a)[1]) == 0xFFU)&& \ - (((a)[1]) == 0xFFU)&& \ - (((a)[1]) == 0xFFU))? FNET_TRUE:FNET_FALSE) + (((a)[1]) == 0xFFU)&& \ + (((a)[1]) == 0xFFU)&& \ + (((a)[1]) == 0xFFU)&& \ + (((a)[1]) == 0xFFU)&& \ + (((a)[1]) == 0xFFU))? FNET_TRUE:FNET_FALSE) /* Copying address. */ #define FNET_MAC_ADDR_COPY(from_addr, to_addr) \ (fnet_memcpy(&to_addr[0], &from_addr[0], sizeof(fnet_mac_addr_t))) diff --git a/fnet_stack/stack/fnet_eth_prv.h b/fnet_stack/stack/fnet_eth_prv.h index 1f58bcad..f1a07aed 100644 --- a/fnet_stack/stack/fnet_eth_prv.h +++ b/fnet_stack/stack/fnet_eth_prv.h @@ -44,6 +44,33 @@ #define FNET_ETH_HDR_SIZE (14U) /* Size of Ethernet header.*/ #define FNET_ETH_CRC_SIZE (4U) /* Size of Ethernet CRC.*/ +/************************************************************************ +* IEEE802.3 PHY MII management register set +*************************************************************************/ +#define FNET_ETH_MII_REG_CR (0x0000U) /* Control Register */ +#define FNET_ETH_MII_REG_SR (0x0001U) /* Status Register */ +#define FNET_ETH_MII_REG_IDR1 (0x0002U) /* Identification Register #1 */ +#define FNET_ETH_MII_REG_IDR2 (0x0003U) /* Identification Register #2 */ +#define FNET_ETH_MII_REG_ANAR (0x0004U) /* Auto-Negotiation Advertisement Register */ +#define FNET_ETH_MII_REG_ANLPAR (0x0005U) /* Auto-Negotiation Link Partner Ability Register */ +#define FNET_ETH_MII_REG_ANER (0x0006U) /* Auto-Negotiation Expansion Register */ +#define FNET_ETH_MII_REG_ANNPTR (0x0007U) /* Auto-Negotiation Next Page TX Register */ + +/* Status Register flags*/ +#define FNET_ETH_MII_REG_SR_LINK_STATUS (0x0004U) +#define FNET_ETH_MII_REG_SR_AN_ABILITY (0x0008U) +#define FNET_ETH_MII_REG_SR_AN_COMPLETE (0x0020U) + +/* Control Register flags*/ +#define FNET_ETH_MII_REG_CR_RESET (0x8000U) /* Resetting a port is accomplished by setting this bit to 1.*/ +#define FNET_ETH_MII_REG_CR_LOOPBACK (0x4000U) /* Determines Digital Loopback Mode. */ +#define FNET_ETH_MII_REG_CR_DATARATE (0x2000U) /* Speed Selection bit.*/ +#define FNET_ETH_MII_REG_CR_ANE (0x1000U) /* Auto-Negotiation Enable bit. */ +#define FNET_ETH_MII_REG_CR_PDWN (0x0800U) /* Power Down bit. */ +#define FNET_ETH_MII_REG_CR_ISOL (0x0400U) /* Isolate bit.*/ +#define FNET_ETH_MII_REG_CR_ANE_RESTART (0x0200U) /* Restart Auto-Negotiation bit.*/ +#define FNET_ETH_MII_REG_CR_DPLX (0x0100U) /* Duplex Mode bit.*/ + /************************************************************************ * Network Layer Protocol interface control structure. *************************************************************************/ diff --git a/fnet_stack/stack/fnet_icmp4.c b/fnet_stack/stack/fnet_icmp4.c index be00fc90..5a9bfa88 100644 --- a/fnet_stack/stack/fnet_icmp4.c +++ b/fnet_stack/stack/fnet_icmp4.c @@ -88,13 +88,13 @@ static void fnet_icmp4_input(fnet_netif_t *netif, struct fnet_sockaddr *src_addr src_ip_tx = dest_ip_rx; dest_ip_tx = src_ip_rx; - if( + if(( #if FNET_CFG_CPU_ETH_HW_RX_PROTOCOL_CHECKSUM || FNET_CFG_CPU_ETH_HW_TX_PROTOCOL_CHECKSUM - ((nb->flags & FNET_NETBUF_FLAG_HW_PROTOCOL_CHECKSUM) == 0) && + ((nb->flags & FNET_NETBUF_FLAG_HW_PROTOCOL_CHECKSUM) == 0) && #endif - (fnet_checksum(nb, nb->total_length)) - || (fnet_ip4_addr_is_broadcast(src_ip_rx, netif)) - || FNET_IP4_ADDR_IS_MULTICAST(src_ip_rx)) + (fnet_checksum(nb, nb->total_length))) + || (fnet_ip4_addr_is_broadcast(src_ip_rx, netif)) + || FNET_IP4_ADDR_IS_MULTICAST(src_ip_rx)) { goto DISCARD; } diff --git a/fnet_stack/stack/fnet_ip4.c b/fnet_stack/stack/fnet_ip4.c index 03f30aa2..8930b0b9 100644 --- a/fnet_stack/stack/fnet_ip4.c +++ b/fnet_stack/stack/fnet_ip4.c @@ -437,10 +437,10 @@ static void fnet_ip4_netif_output(struct fnet_netif *netif, fnet_ip4_addr_t dest #if FNET_CFG_LOOPBACK && (FNET_CFG_LOOPBACK_MULTICAST || FNET_CFG_LOOPBACK_BROADCAST) fnet_netbuf_t *nb_loop; - if((netif != FNET_LOOP_IF) /* Avoid double send to the loopback interface.*/ - { - /* Datagrams sent to a broadcast/multicast address are copied to the loopback interface.*/ - if((nb_loop = fnet_netbuf_copy(nb, 0, FNET_NETBUF_COPYALL, FNET_TRUE)) != 0) + if(netif != FNET_LOOP_IF) /* Avoid double send to the loopback interface.*/ + { + /* Datagrams sent to a broadcast/multicast address are copied to the loopback interface.*/ + if((nb_loop = fnet_netbuf_copy(nb, 0, FNET_NETBUF_COPYALL, FNET_TRUE)) != 0) { fnet_loop_output_ip4(netif, dest_ip_addr, nb_loop); } @@ -836,13 +836,13 @@ static void fnet_ip4_reassembly( fnet_netbuf_t **nb_ptr ) fnet_ip4_frag_list_del(&ip_frag_list_head, frag_list_ptr); fnet_free(frag_list_ptr); -goto EXIT; + goto EXIT; DROP_FRAG: fnet_netbuf_free_chain(nb); NEXT_FRAG: nb = FNET_NULL; -EXIT: +EXIT: *nb_ptr = nb; } #endif /* FNET_CFG_IP4_FRAGMENTATION */ diff --git a/fnet_stack/stack/fnet_isr.c b/fnet_stack/stack/fnet_isr.c index d93eb091..786abd37 100644 --- a/fnet_stack/stack/fnet_isr.c +++ b/fnet_stack/stack/fnet_isr.c @@ -201,41 +201,32 @@ static fnet_return_t fnet_isr_register(fnet_uint32_t vector_number, void fnet_isr_unregister(fnet_uint32_t vector_number) { fnet_isr_entry_t *isr_temp; + fnet_isr_entry_t *isr_temp2; - isr_temp = fnet_isr_table; - - while (isr_temp != 0) + for(isr_temp = fnet_isr_table; isr_temp; isr_temp = isr_temp->next) { if (isr_temp->vector_number == vector_number) { - break; - } - - isr_temp = isr_temp->next; - } - - if (isr_temp != 0) /* if handler wasn't registered in queue */ - { - fnet_free(isr_temp); - - if (fnet_isr_table->vector_number == vector_number) - { - fnet_isr_table = fnet_isr_table->next; - } - else - { - isr_temp = fnet_isr_table; - - while (isr_temp->next != 0) + if (isr_temp == fnet_isr_table) /* First element */ { - if (isr_temp->next->vector_number == vector_number) + fnet_isr_table = fnet_isr_table->next; + } + else /* Middle element */ + { + isr_temp2 = fnet_isr_table; + + for(isr_temp2 = fnet_isr_table; isr_temp2->next; isr_temp2 = isr_temp2->next) { - isr_temp->next = isr_temp->next->next; - break; + if (isr_temp2->next->vector_number == vector_number) + { + isr_temp2->next = isr_temp2->next->next; + break; + } } - - isr_temp = isr_temp->next; } + + fnet_free(isr_temp); + break; } } } @@ -294,7 +285,8 @@ void fnet_isr_unlock(void) } isr_temp = isr_temp->next; } - } while(again); + } + while(again); } --fnet_locked; diff --git a/fnet_stack/stack/fnet_mld.c b/fnet_stack/stack/fnet_mld.c index 4b7c680b..25139ffd 100644 --- a/fnet_stack/stack/fnet_mld.c +++ b/fnet_stack/stack/fnet_mld.c @@ -42,7 +42,8 @@ static const fnet_mld_ra_option_header_t mld_ra_option = { .next_header = FNET_ .hdr_ext_length = 0, /* Length-8 */ .ra_option_header = {.type = FNET_IP6_OPTION_TYPE_ROUTER_ALERT, .data_length = 2}, /* Router Alert Option. */ .ra_option_value = FNET_IP6_OPTION_TYPE_ROUTER_ALERT_VALUE_MLD, /* Router Alert Option value. */ - .padn_option_header = {.type = FNET_IP6_OPTION_TYPE_PADN, .data_length = 0} /* Padding. */}; + .padn_option_header = {.type = FNET_IP6_OPTION_TYPE_PADN, .data_length = 0} /* Padding. */ + }; static void fnet_mld_send( fnet_netif_t *netif, fnet_ip6_addr_t *group_addr, fnet_uint8_t type); diff --git a/fnet_stack/stack/fnet_netbuf.c b/fnet_stack/stack/fnet_netbuf.c index 35c377ec..41af2f10 100644 --- a/fnet_stack/stack/fnet_netbuf.c +++ b/fnet_stack/stack/fnet_netbuf.c @@ -417,7 +417,8 @@ fnet_return_t fnet_netbuf_pullup( fnet_netbuf_t **nb_ptr, fnet_size_t len) { tot_len += tmp_nb->length; tmp_nb = tmp_nb->next; - }while((tot_len < len) && tmp_nb); + } + while((tot_len < len) && tmp_nb); new_buf = (struct net_buf_data *)fnet_malloc_netbuf((fnet_size_t)len + sizeof(fnet_uint32_t)/* For reference_counter */); diff --git a/fnet_stack/stack/fnet_netif.c b/fnet_stack/stack/fnet_netif.c index a5663f9a..7bf934aa 100644 --- a/fnet_stack/stack/fnet_netif.c +++ b/fnet_stack/stack/fnet_netif.c @@ -890,15 +890,15 @@ fnet_bool_t fnet_netif_is_connected( fnet_netif_desc_t netif_desc ) { if(connection_flag == FNET_FALSE) /* =>Connected. */ { - #if FNET_CFG_IP4 +#if FNET_CFG_IP4 if(netif->netif_api->netif_change_addr_notify) { netif->netif_api->netif_change_addr_notify(netif); /* Send ARP announcement*/ } - #endif - #if FNET_CFG_IP6 +#endif +#if FNET_CFG_IP6 fnet_nd6_rd_start(netif); /* Restart IPv6 router discovery */ - #endif +#endif } } } diff --git a/fnet_stack/stack/fnet_raw.c b/fnet_stack/stack/fnet_raw.c index 8ff2515f..825f4c91 100644 --- a/fnet_stack/stack/fnet_raw.c +++ b/fnet_stack/stack/fnet_raw.c @@ -88,7 +88,7 @@ static void fnet_raw_release( void ) * DESCRIPTION: RAW output function *************************************************************************/ static fnet_error_t fnet_raw_output( struct fnet_sockaddr *src_addr, const struct fnet_sockaddr *dest_addr, fnet_uint8_t protocol_number, - fnet_socket_option_t *sockoption, fnet_netbuf_t *nb ) + fnet_socket_option_t *sockoption, fnet_netbuf_t *nb ) { fnet_error_t error = FNET_ERR_OK; diff --git a/fnet_stack/stack/fnet_socket_prv.h b/fnet_stack/stack/fnet_socket_prv.h index 30ca4dfc..9432ae84 100644 --- a/fnet_stack/stack/fnet_socket_prv.h +++ b/fnet_stack/stack/fnet_socket_prv.h @@ -155,8 +155,8 @@ typedef struct fnet_socket_prot_if fnet_return_t (*prot_detach)(fnet_socket_if_t *sk); /* Protocol "detach" function. */ fnet_return_t (*prot_connect)(fnet_socket_if_t *sk, struct fnet_sockaddr *foreign_addr); /* Protocol "connect" function. */ fnet_socket_if_t *( *prot_accept)(fnet_socket_if_t *sk); /* Protocol "accept" function. */ - fnet_int32_t (*prot_rcv)(fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, struct fnet_sockaddr *foreign_addr ); /* Protocol "receive" function. */ - fnet_int32_t (*prot_snd)(fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, const struct fnet_sockaddr *foreign_addr ); /* Protocol "send" function. */ + fnet_ssize_t (*prot_rcv)(fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, struct fnet_sockaddr *foreign_addr ); /* Protocol "receive" function. */ + fnet_ssize_t (*prot_snd)(fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, const struct fnet_sockaddr *foreign_addr ); /* Protocol "send" function. */ fnet_return_t (*prot_shutdown)(fnet_socket_if_t *sk, fnet_sd_flags_t how); /* Protocol "shutdown" function. */ fnet_return_t (*prot_setsockopt)(fnet_socket_if_t *sk, fnet_protocol_t level, fnet_socket_options_t optname, const void *optval, fnet_size_t optlen); /* Protocol "setsockopt" function. */ fnet_return_t (*prot_getsockopt)(fnet_socket_if_t *sk, fnet_protocol_t level, fnet_socket_options_t optname, void *optval, fnet_size_t *optlen); /* Protocol "getsockopt" function. */ diff --git a/fnet_stack/stack/fnet_stack_config.h b/fnet_stack/stack/fnet_stack_config.h index 9dd77313..642d226e 100644 --- a/fnet_stack/stack/fnet_stack_config.h +++ b/fnet_stack/stack/fnet_stack_config.h @@ -625,7 +625,7 @@ * - @b @c 1 = is enabled (Default value).@n * It means that FNET automatically controls all internal protocol timeouts. * - @b @c 0 = is disabled.@n - * In this case a user application + * In this case a user application * must call fnet_timer_poll() periodically. * @see fnet_timer_poll() * @showinitializer @@ -772,6 +772,10 @@ #define FNET_CFG_DEBUG_QCA (0) #endif +#ifndef FNET_CFG_DEBUG_ENET + #define FNET_CFG_DEBUG_ENET (0) +#endif + #ifndef FNET_CFG_DEBUG_TRACE #define FNET_CFG_DEBUG_TRACE (0) #endif diff --git a/fnet_stack/stack/fnet_stack_prv.h b/fnet_stack/stack/fnet_stack_prv.h index bc109a9f..171f76ca 100644 --- a/fnet_stack/stack/fnet_stack_prv.h +++ b/fnet_stack/stack/fnet_stack_prv.h @@ -18,7 +18,7 @@ * limitations under the License. * *************************************************************************** -* +* * Main including header for the FNET TCP/IP stack. * ***************************************************************************/ diff --git a/fnet_stack/stack/fnet_tcp.c b/fnet_stack/stack/fnet_tcp.c index 59ad19fb..195c4cf5 100644 --- a/fnet_stack/stack/fnet_tcp.c +++ b/fnet_stack/stack/fnet_tcp.c @@ -105,8 +105,8 @@ static fnet_return_t fnet_tcp_attach( fnet_socket_if_t *sk ); static fnet_return_t fnet_tcp_close( fnet_socket_if_t *sk ); static fnet_return_t fnet_tcp_connect( fnet_socket_if_t *sk, struct fnet_sockaddr *foreign_addr); static fnet_socket_if_t *fnet_tcp_accept( fnet_socket_if_t *listensk ); -static fnet_int32_t fnet_tcp_rcv( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, struct fnet_sockaddr *foreign_addr); -static fnet_int32_t fnet_tcp_snd( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, const struct fnet_sockaddr *foreign_addr); +static fnet_ssize_t fnet_tcp_rcv( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, struct fnet_sockaddr *foreign_addr); +static fnet_ssize_t fnet_tcp_snd( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, const struct fnet_sockaddr *foreign_addr); static fnet_return_t fnet_tcp_shutdown( fnet_socket_if_t *sk, fnet_sd_flags_t how ); static fnet_return_t fnet_tcp_setsockopt( fnet_socket_if_t *sk, fnet_protocol_t level, fnet_socket_options_t optname, const void *optval, fnet_size_t optlen ); static fnet_return_t fnet_tcp_getsockopt( fnet_socket_if_t *sk, fnet_protocol_t level, fnet_socket_options_t optname, void *optval, fnet_size_t *optlen ); @@ -653,7 +653,7 @@ static fnet_socket_if_t *fnet_tcp_accept( fnet_socket_if_t *listensk ) * RETURNS: If no error occurs, this function returns the length * of the received data. Otherwise, it returns FNET_ERR. *************************************************************************/ -static fnet_int32_t fnet_tcp_rcv( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, struct fnet_sockaddr *foreign_addr) +static fnet_ssize_t fnet_tcp_rcv( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, struct fnet_sockaddr *foreign_addr) { fnet_tcp_control_t *cb = (fnet_tcp_control_t *)sk->protocol_control; fnet_bool_t flag_remove; /* Remove flag. 1 means that the data must be deleted @@ -784,7 +784,7 @@ static fnet_int32_t fnet_tcp_rcv( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_ * of the data that is added to the output buffer. * Otherwise, it returns FNET_ERR. *************************************************************************/ -static fnet_int32_t fnet_tcp_snd( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, const struct fnet_sockaddr *foreign_addr) +static fnet_ssize_t fnet_tcp_snd( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, const struct fnet_sockaddr *foreign_addr) { fnet_tcp_control_t *cb = (fnet_tcp_control_t *)sk->protocol_control; fnet_netbuf_t *netbuf; diff --git a/fnet_stack/stack/fnet_timer.c b/fnet_stack/stack/fnet_timer.c index f866cd52..7ebee3b7 100644 --- a/fnet_stack/stack/fnet_timer.c +++ b/fnet_stack/stack/fnet_timer.c @@ -116,7 +116,7 @@ void fnet_timer_ticks_inc( void ) #if FNET_CFG_DEBUG_TIMER && FNET_CFG_DEBUG /* Print once per second */ - if((fnet_current_time % (1000/FNET_TIMER_PERIOD_MS)) == 0) + if((fnet_current_time % (1000 / FNET_TIMER_PERIOD_MS)) == 0) { FNET_DEBUG_TIMER("!"); } diff --git a/fnet_stack/stack/fnet_timer.h b/fnet_stack/stack/fnet_timer.h index 7bdabfbe..322c018d 100644 --- a/fnet_stack/stack/fnet_timer.h +++ b/fnet_stack/stack/fnet_timer.h @@ -179,7 +179,7 @@ void fnet_timer_delay( fnet_time_t delay_ticks ); ****************************************************************************** * * This function checks timeouts for TCP, ARP, IP and other stack activities.@n - * The user application should call this function periodically, + * The user application should call this function periodically, * after the FNET stack initialization, and only if @ref FNET_CFG_TIMER_POLL_AUTOMATIC is 0.@n * Recommended polling period is 100ms or less.@n * If @ref FNET_CFG_TIMER_POLL_AUTOMATIC is 1, this function is called automatically diff --git a/fnet_stack/stack/fnet_udp.c b/fnet_stack/stack/fnet_udp.c index 840f1d00..79518222 100644 --- a/fnet_stack/stack/fnet_udp.c +++ b/fnet_stack/stack/fnet_udp.c @@ -39,8 +39,8 @@ static fnet_return_t fnet_udp_attach( fnet_socket_if_t *sk ); static fnet_return_t fnet_udp_detach( fnet_socket_if_t *sk ); static fnet_return_t fnet_udp_connect( fnet_socket_if_t *sk, struct fnet_sockaddr *foreign_addr); -static fnet_int32_t fnet_udp_snd( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, const struct fnet_sockaddr *addr); -static fnet_int32_t fnet_udp_rcv(fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, struct fnet_sockaddr *addr); +static fnet_ssize_t fnet_udp_snd( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, const struct fnet_sockaddr *addr); +static fnet_ssize_t fnet_udp_rcv(fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, struct fnet_sockaddr *addr); static void fnet_udp_control_input(fnet_prot_notify_t command, struct fnet_sockaddr *src_addr, struct fnet_sockaddr *dest_addr, fnet_netbuf_t *nb); static fnet_return_t fnet_udp_shutdown( fnet_socket_if_t *sk, fnet_sd_flags_t how ); static void fnet_udp_input( fnet_netif_t *netif, struct fnet_sockaddr *foreign_addr, struct fnet_sockaddr *local_addr, fnet_netbuf_t *nb, fnet_netbuf_t *ip_nb); @@ -497,7 +497,7 @@ static fnet_return_t fnet_udp_connect( fnet_socket_if_t *sk, struct fnet_sockadd /************************************************************************ * DESCRIPTION: UDP send function. *************************************************************************/ -static fnet_int32_t fnet_udp_snd( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, const struct fnet_sockaddr *addr) +static fnet_ssize_t fnet_udp_snd( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, const struct fnet_sockaddr *addr) { fnet_netbuf_t *nb; fnet_error_t error = FNET_ERR_OK; @@ -556,7 +556,7 @@ static fnet_int32_t fnet_udp_snd( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_ if((error == FNET_ERR_OK) && (sk->options.local_error == FNET_ERR_OK)) /* We get UDP or ICMP error.*/ { fnet_isr_unlock(); - return (fnet_int32_t)(len); + return (fnet_ssize_t)(len); } ERROR: @@ -568,7 +568,7 @@ static fnet_int32_t fnet_udp_snd( fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_ /************************************************************************ * DESCRIPTION :UDP receive function. *************************************************************************/ -static fnet_int32_t fnet_udp_rcv(fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, struct fnet_sockaddr *addr) +static fnet_ssize_t fnet_udp_rcv(fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_size_t len, fnet_flag_t flags, struct fnet_sockaddr *addr) { fnet_error_t error = FNET_ERR_OK; fnet_int32_t length; @@ -586,19 +586,22 @@ static fnet_int32_t fnet_udp_rcv(fnet_socket_if_t *sk, fnet_uint8_t *buf, fnet_s if(sk->options.local_error == FNET_ERR_OK) { - if((length = fnet_socket_buffer_read_address(&(sk->receive_buffer), buf, - len, &foreign_addr, ((flags & MSG_PEEK) == 0u) ? FNET_TRUE : FNET_FALSE)) == FNET_ERR) - { - /* The message was too large to fit into the specified buffer and was truncated.*/ - error = FNET_ERR_MSGSIZE; - goto ERROR; - } + + length = fnet_socket_buffer_read_address(&(sk->receive_buffer), buf, + len, &foreign_addr, ((flags & MSG_PEEK) == 0u) ? FNET_TRUE : FNET_FALSE); if(addr) { fnet_socket_addr_copy(&foreign_addr, addr); } + if(length == FNET_ERR) + { + /* The message was too large to fit into the specified buffer and was truncated.*/ + error = FNET_ERR_MSGSIZE; + goto ERROR; + } + return (length); } else /* We get UDP or ICMP error.*/ diff --git a/fnet_stack/stack/fnet_wifi.h b/fnet_stack/stack/fnet_wifi.h index d593fe7f..3e74672f 100644 --- a/fnet_stack/stack/fnet_wifi.h +++ b/fnet_stack/stack/fnet_wifi.h @@ -58,7 +58,7 @@ * @brief Wi-Fi operation mode. * @see fnet_wifi_get_op_mode() ***********************************s*******************************************/ -typedef enum +typedef enum { FNET_WIFI_OP_MODE_NONE, /**< @brief Disconnected. Wi-Fi radio is off @see fnet_wifi_disconnect()*/ FNET_WIFI_OP_MODE_STATION, /**< @brief Station mode. @see fnet_wifi_connect()*/ @@ -68,7 +68,7 @@ typedef enum /**************************************************************************/ /*! * @brief WPA-personal security mode. ***********************************s*******************************************/ -typedef enum +typedef enum { FNET_WIFI_WPA_NONE, /**< @brief None. The Wi-Fi network is open.*/ FNET_WIFI_WPA, /**< @brief WPA. This mode uses TKIP cipher. It is used mainly for legacy devices.*/ @@ -79,7 +79,7 @@ typedef enum /**************************************************************************/ /*! * @brief Wi-Fi connection parameters for @ref fnet_wifi_connect(). ******************************************************************************/ -typedef struct +typedef struct { fnet_char_t *ssid ; /**< @brief Wi-Fi SSID (Subscription Service Identifier), also called Wireless Network Name. @n It can be up to 32 alphanumeric character unique identifier (zero-terminated string).*/ @@ -90,7 +90,7 @@ typedef struct /**************************************************************************/ /*! * @brief Wi-Fi access point parameters for @ref fnet_wifi_access_point(). ******************************************************************************/ -typedef struct +typedef struct { fnet_char_t *ssid ; /**< @brief Wi-Fi SSID (Subscription Service Identifier), also called Wireless Network Name. @n It can be up to 32 alphanumeric character unique identifier (zero-terminated string).*/ diff --git a/third_party/qca-3.3.5/common_src/storerecall/dset_api.c b/third_party/qca-3.3.5/common_src/storerecall/dset_api.c index 51046632..8d52e735 100644 --- a/third_party/qca-3.3.5/common_src/storerecall/dset_api.c +++ b/third_party/qca-3.3.5/common_src/storerecall/dset_api.c @@ -152,7 +152,7 @@ uint32_t qcom_dset_write(HOST_DSET_HANDLE *pDsetHandle, //AB if(pDsetHandle->data_ptr == NULL) - return A_ERROR; + return (uint32_t)A_ERROR; memcpy(pDsetHandle->data_ptr + DSET_WRITE_HEAD_SIZE, buffer, length); @@ -183,7 +183,7 @@ uint32_t qcom_dset_read(HOST_DSET_HANDLE *pDsetHandle, //AB if(pDsetHandle->data_ptr == NULL) - return A_ERROR; + return (uint32_t)A_ERROR; status = remote_dset_op(DSET_OP_READ, pDsetHandle); memcpy(buffer, pDsetHandle->data_ptr, length); diff --git a/third_party/qca-3.3.5/port/boards/lpcxpresso54628/freertos/gt202/wifi_shield_gt202.h b/third_party/qca-3.3.5/port/boards/lpcxpresso54628/freertos/gt202/wifi_shield_gt202.h new file mode 100644 index 00000000..a004edbd --- /dev/null +++ b/third_party/qca-3.3.5/port/boards/lpcxpresso54628/freertos/gt202/wifi_shield_gt202.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2017, NXP Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of NXP Semiconductor, Inc. nor the names of its + * contributors may be used tom endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __WIFI_SHIELD_GT202_H__ +#define __WIFI_SHIELD_GT202_H__ + +#include "wifi_common.h" +#include "pin_mux.h" + +/* This file cannot be included directly in common code, it must pass through "wifi_shield.h" */ +#ifndef WIFISHIELD_ENABLED +# define WIFISHIELD_ENABLED +#else +# error "Other WiFi shield is already enabled !" +#endif + +/* Pinmux function, generated by pinmuxtool */ +#define WIFISHIELD_PINMUX_INIT BOARD_InitGT202Shield + +/* WLAN_IRQ PINT */ +#define WIFISHIELD_WLAN_PINT (kPINT_PinInt0) +#define WIFISHIELD_WLAN_PINT_EDGE (kPINT_PinIntEnableFallEdge) +#define WIFISHIELD_WLAN_PINT_CONNECT (kINPUTMUX_GpioPort1Pin22ToPintsel) +#define WIFISHIELD_WLAN_PINT_IRQ (PIN_INT0_IRQn) + +/* WLAN_IRQ signal */ +#define WIFISHIELD_WLAN_IRQ_DIRECTION (BOARD_INITGT202SHIELD_IRQ_DIRECTION) +#define WIFISHIELD_WLAN_IRQ_PORT (BOARD_INITGT202SHIELD_IRQ_PORT) +#define WIFISHIELD_WLAN_IRQ_GPIO (BOARD_INITGT202SHIELD_IRQ_GPIO) +#define WIFISHIELD_WLAN_IRQ_PIN (BOARD_INITGT202SHIELD_IRQ_GPIO_PIN) +#define WIFISHIELD_WLAN_IRQ_CLOCKSRC (kCLOCK_Gpio1) + +/* WLAN_PWRON (PWRDWN) signal */ +#define WIFISHIELD_WLAN_PWRON_DIRECTION (BOARD_INITGT202SHIELD_PWRON_DIRECTION) +#define WIFISHIELD_WLAN_PWRON_PORT (BOARD_INITGT202SHIELD_PWRON_PORT) +#define WIFISHIELD_WLAN_PWRON_GPIO (BOARD_INITGT202SHIELD_PWRON_GPIO) +#define WIFISHIELD_WLAN_PWRON_PIN (BOARD_INITGT202SHIELD_PWRON_GPIO_PIN) +#define WIFISHIELD_WLAN_PWRON_CLOCKSRC (kCLOCK_Gpio4) + +/* SPI settings */ +#define WIFISHIELD_SPI (SPI9) +#define WIFISHIELD_SPI_INIT_CS (kSPI_Ssel0) +#define WIFISHIELD_SPI_CLK_CONNECT (kFRO12M_to_FLEXCOMM9) +#define WIFISHIELD_SPI_IP_RESET (kFC9_RST_SHIFT_RSTn) +#define WIFISHIELD_SPI_BAUDRATE (10000000) +#define WIFISHIELD_SPI_THRESHOLD 0xFFFFFFFF /* Disable transfer over DMA */ //DM (8) + +/* EDMA settings */ +#define WIFISHIELD_DMA (DMA0) +#define WIFISHIELD_DMA_RX_CHNL (22) +#define WIFISHIELD_DMA_TX_CHNL (23) + +#endif diff --git a/third_party/qca-3.3.5/port/boards/lpcxpresso54628/freertos/wifi_shield.c b/third_party/qca-3.3.5/port/boards/lpcxpresso54628/freertos/wifi_shield.c new file mode 100644 index 00000000..30b0c8de --- /dev/null +++ b/third_party/qca-3.3.5/port/boards/lpcxpresso54628/freertos/wifi_shield.c @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2017, NXP Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of NXP Semiconductor, Inc. nor the names of its + * contributors may be used tom endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include "wifi_common.h" +#include "fsl_gpio.h" +#include "driver_cxt.h" +#include "wifi_spi.h" +#include "wifi_shield.h" +#include "fsl_pint.h" +#include "fsl_inputmux.h" +#include "fsl_inputmux_connections.h" + +static void PINT_callback(pint_pin_int_t pintr, uint32_t pmatch_status); + +/*! + * @brief Low level initialization, RTOS does not have to run yet + */ +A_STATUS WIFISHIELD_Init(void) +{ + gpio_pin_config_t config; + memset(&config, 0, sizeof(config)); + + /* Initialize pinmux */ +#ifdef WIFISHIELD_PINMUX_INIT + WIFISHIELD_PINMUX_INIT(); +#endif + + /* Enable clocks for GPIO */ + CLOCK_EnableClock(WIFISHIELD_WLAN_PWRON_CLOCKSRC); + CLOCK_EnableClock(WIFISHIELD_WLAN_IRQ_CLOCKSRC); + + /* Enable clocks for SPI */ + CLOCK_AttachClk(WIFISHIELD_SPI_CLK_CONNECT); + RESET_PeripheralReset(WIFISHIELD_SPI_IP_RESET); + + /* Set up WLAN_PWRON signal */ + config.pinDirection = (gpio_pin_direction_t)WIFISHIELD_WLAN_PWRON_DIRECTION; + GPIO_PinInit(WIFISHIELD_WLAN_PWRON_GPIO, WIFISHIELD_WLAN_PWRON_PORT, WIFISHIELD_WLAN_PWRON_PIN, &config); + + /* Set up WLAN_IRQ signal */ + config.pinDirection = (gpio_pin_direction_t)WIFISHIELD_WLAN_IRQ_DIRECTION; + GPIO_PinInit(WIFISHIELD_WLAN_IRQ_GPIO, WIFISHIELD_WLAN_IRQ_PORT, WIFISHIELD_WLAN_IRQ_PIN, &config); + + /* Set up Inputmux */ + INPUTMUX_Init(INPUTMUX); + INPUTMUX_AttachSignal(INPUTMUX, WIFISHIELD_WLAN_PINT, WIFISHIELD_WLAN_PINT_CONNECT); + INPUTMUX_Deinit(INPUTMUX); + + /* Set up PINT for WLAN_IRQ */ + PINT_Init(PINT); + PINT_PinInterruptConfig(PINT, WIFISHIELD_WLAN_PINT, WIFISHIELD_WLAN_PINT_EDGE, PINT_callback); + PINT_EnableCallback(PINT); + + /* Enable NVIC interrupt for WLAN_IRQ */ + NVIC_EnableIRQ(WIFISHIELD_WLAN_PINT_IRQ); + + /* Set NVIC priority if is required by Freertos */ + NVIC_SetPriority(WIFISHIELD_WLAN_PINT_IRQ, WIFISHIELD_WLAN_IRQ_PRIORITY); + + return A_OK; +} + +/*! + * @brief Initialization is maintained by WIFI stack + */ +A_STATUS WIFISHIELD_InitDrivers(void *param) +{ + /* Set up capabilities of SPI transfer, used in upper layer */ + A_DRIVER_CONTEXT *pDCxt = GET_DRIVER_COMMON(param); + + /* Force WIFI stack to use this SPI settings */ + pDCxt->spi_hcd.PowerUpDelay = 1; + pDCxt->spi_hcd.SpiHWCapabilitiesFlags = (HW_SPI_FRAME_WIDTH_8 | HW_SPI_NO_DMA | HW_SPI_INT_EDGE_DETECT); + + /* Complex DMAMUX/DMA/SPI config structure */ + WIFIDRVS_SPI_config_t spi_config = {0}; + + /* Load default settings */ + WIFIDRVS_SPI_GetDefaultConfig(&spi_config); + +#if defined(WIFISHIELD_DMA) + /* Configure dma_mode */ + spi_config.dma_mode.enabled = true; + spi_config.dma_mode.dma_base = (void*)WIFISHIELD_DMA; + spi_config.dma_mode.dma_rx_chnl = WIFISHIELD_DMA_RX_CHNL; + spi_config.dma_mode.dma_rx_chnl_prio = kDMA_ChannelPriority3; + spi_config.dma_mode.dma_tx_chnl = WIFISHIELD_DMA_TX_CHNL; + spi_config.dma_mode.dma_tx_chnl_prio = kDMA_ChannelPriority4; + spi_config.dma_mode.dma_irq_prio = WIFISHIELD_DMA_IRQ_PRIORITY; +#endif + +#if defined(WIFISHIELD_SPI_IRQ_PRIORITY) + /* Configure irq_mode */ + spi_config.irq_mode.enabled = true; + spi_config.irq_mode.spi_irq_prio = WIFISHIELD_SPI_IRQ_PRIORITY; +#endif + + /* Configure spi */ + spi_config.spi.base = (void*)WIFISHIELD_SPI; + spi_config.spi.clk_hz = CLOCK_GetFreq(kCLOCK_Flexcomm9); + spi_config.spi.baudrate = WIFISHIELD_SPI_BAUDRATE; + spi_config.spi.irq_threshold = WIFISHIELD_SPI_THRESHOLD; + + /* Load recommended SPI settings */ + WIFIDRVS_SPI_GetSPIConfig(&spi_config.spi.config, WIFISHIELD_SPI_BAUDRATE, WIFISHIELD_SPI_INIT_CS); + + /* Initialize driver */ + A_STATUS result = WIFIDRVS_SPI_Init(&spi_config); + assert(A_OK == result); + + return A_OK; +} + +/*! + * @brief Deinitialization is maintained by WIFI stack + */ +A_STATUS WIFISHIELD_DeinitDrivers(void *param) +{ + // WIFI_Spi_Deinit(); + return A_OK; +} + +/*! + * @brief Power up WiFi shield, RTOS does not have to run yet + */ +A_STATUS WIFISHIELD_PowerUp(uint32_t enable) +{ + if (enable) + { + GPIO_PinWrite(WIFISHIELD_WLAN_PWRON_GPIO, WIFISHIELD_WLAN_PWRON_PORT, WIFISHIELD_WLAN_PWRON_PIN, 1); + } + else + { + GPIO_PinWrite(WIFISHIELD_WLAN_PWRON_GPIO, WIFISHIELD_WLAN_PWRON_PORT, WIFISHIELD_WLAN_PWRON_PIN, 0); + } + return A_OK; +} + +/*! + * @brief Fn post DriverTask semaphore, can be called only from WLAN_IRQ ISR + */ +void WIFISHIELD_NotifyDriverTask(void *param) +{ + extern QCA_CONTEXT_STRUCT wifiCtx; + void HW_InterruptHandler(void *pCxt); + + void *pCxt = wifiCtx.MAC_CONTEXT_PTR; + if (pCxt) + { + HW_InterruptHandler(pCxt); + } +} + +/* ISR callback for WLAN_IRQ */ +static void PINT_callback(pint_pin_int_t pintr, uint32_t pmatch_status) +{ + WIFISHIELD_NotifyDriverTask(NULL); +} + diff --git a/third_party/qca-3.3.5/port/boards/lpcxpresso54628/freertos/wifi_shield.h b/third_party/qca-3.3.5/port/boards/lpcxpresso54628/freertos/wifi_shield.h new file mode 100644 index 00000000..5c457bcc --- /dev/null +++ b/third_party/qca-3.3.5/port/boards/lpcxpresso54628/freertos/wifi_shield.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2017, NXP Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of NXP Semiconductor, Inc. nor the names of its + * contributors may be used tom endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __WIFI_SHIELD_H__ +#define __WIFI_SHIELD_H__ + +/* Select specific shield support */ +#define WIFISHIELD_IS_GT202 + +/* NOTE: Silex is not supported. WLAN_IRQ is routed to P3_2 + * that does not support interrupts */ + +/* Include shields support */ +#if defined(WIFISHIELD_IS_GT202) +#include "wifi_shield_gt202.h" +#else +#error "No shield is selected !" +#endif + +/* define IRQ priority level */ +#ifndef WIFISHIELD_SPI_IRQ_PRIORITY +# define WIFISHIELD_SPI_IRQ_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1) +#endif +#ifndef WIFISHIELD_DMA_IRQ_PRIORITY +# define WIFISHIELD_DMA_IRQ_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1) +#endif +#ifndef WIFISHIELD_WLAN_IRQ_PRIORITY +# define WIFISHIELD_WLAN_IRQ_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1) +#endif + +/* Fn prototypes, which need to be implemented */ +A_STATUS WIFISHIELD_Init(void); +A_STATUS WIFISHIELD_InitDrivers(void *param); +A_STATUS WIFISHIELD_DeinitDrivers(void *param); +A_STATUS WIFISHIELD_PowerUp(uint32_t enable); +void WIFISHIELD_NotifyDriverTask(void *param); + +#endif diff --git a/third_party/qca-3.3.5/port/drivers/flexcomm_freertos/wifi_spi.c b/third_party/qca-3.3.5/port/drivers/flexcomm_freertos/wifi_spi.c new file mode 100644 index 00000000..8c0c1c6c --- /dev/null +++ b/third_party/qca-3.3.5/port/drivers/flexcomm_freertos/wifi_spi.c @@ -0,0 +1,422 @@ +/* + * Copyright (c) 2016, NXP Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of NXP Semiconductor, Inc. nor the names of its + * contributors may be used tom endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "wifi_common.h" +#include "athdefs.h" + +#include "fsl_spi.h" +#include "fsl_spi_dma.h" +//#include "fsl_dmamux.h" +//#include "fsl_edma.h" +//#include "fsl_dspi_edma.h" +#include "wifi_spi.h" + +static spi_dma_handle_t g_spi_edma_m_handle; +static dma_handle_t g_m_tx_handle; +static dma_handle_t g_m_rx_handle; +static spi_dma_handle_t g_m_dma_handle; +static spi_master_handle_t g_m_handle; + +static SemaphoreHandle_t mutex; +static SemaphoreHandle_t event; +static int32_t g_dma_chunk = 1023; +//static enum IRQn g_dma_irqs[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; +static enum IRQn g_spi_irqs[] = SPI_IRQS; +static spi_master_config_t g_spi_config; + +static SPI_Type *g_spi_base = NULL; +static uint32_t g_xfer_cs = 0; +static uint32_t g_irq_threshold = 0; + +extern uint32_t SPI_GetInstance(SPI_Type *base); + +/*! @brief Array to map DMA instance number to IRQ number. */ +static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; + +/*! @brief Array to map DMA instance number to base pointer. */ +static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS; + +static int32_t DMA_GetInstance(DMA_Type *base) +{ + int32_t instance; + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) + { + if (s_dmaBases[instance] == base) + { + break; + } + } + assert(instance < ARRAY_SIZE(s_dmaBases)); + return instance < ARRAY_SIZE(s_dmaBases) ? instance : -1; +} + +/* + * DMA handler, release transfer semaphore + */ +static void SPI_DMA_MasterUserCallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData) +{ + /* disable DMA requests before invoke callback */ + BaseType_t reschedule = pdFALSE; + xSemaphoreGiveFromISR(event, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/* + * IRQ handler, release transfer semaphore + */ +static void SPI_MasterUserCallback(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData) +{ + /* disable IRQ requests before invoke callback */ + BaseType_t reschedule = pdFALSE; + xSemaphoreGiveFromISR(event, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/* + * Initialize SPI IRQ mode + */ +static A_STATUS WIFIDRVS_SPI_InitIRQMode(WIFIDRVS_SPI_config_t *config) +{ + uint32_t spi_id = SPI_GetInstance(config->spi.base); + NVIC_SetPriority(g_spi_irqs[spi_id], config->irq_mode.spi_irq_prio); + + /* SPI IRQ non-blocking handle */ + SPI_MasterTransferCreateHandle(config->spi.base, &g_m_handle, SPI_MasterUserCallback, NULL); + + return A_OK; +} + +/* + * Initialize SPI DMA mode + */ +static A_STATUS WIFIDRVS_SPI_InitDMAMode(WIFIDRVS_SPI_config_t *config) +{ + int32_t dmaInstance; + DMA_Init(config->dma_mode.dma_base); + DMA_EnableChannel(config->dma_mode.dma_base, config->dma_mode.dma_rx_chnl); + DMA_EnableChannel(config->dma_mode.dma_base, config->dma_mode.dma_tx_chnl); + DMA_SetChannelPriority(config->dma_mode.dma_base, config->dma_mode.dma_rx_chnl, config->dma_mode.dma_rx_chnl_prio); + DMA_SetChannelPriority(config->dma_mode.dma_base, config->dma_mode.dma_tx_chnl, config->dma_mode.dma_tx_chnl_prio); + DMA_CreateHandle(&g_m_rx_handle, config->dma_mode.dma_base, config->dma_mode.dma_rx_chnl); + DMA_CreateHandle(&g_m_tx_handle, config->dma_mode.dma_base, config->dma_mode.dma_tx_chnl); + SPI_MasterTransferCreateHandleDMA(config->spi.base, &g_m_dma_handle, SPI_DMA_MasterUserCallback, NULL, &g_m_tx_handle, + &g_m_rx_handle); + dmaInstance = DMA_GetInstance(config->dma_mode.dma_base); + NVIC_SetPriority(s_dmaIRQNumber[dmaInstance], config->dma_mode.dma_irq_prio); + return A_OK; +} + +/* + * Initialize SPI peripheral + */ +static A_STATUS WIFIDRVS_SPI_InitPeriph( + SPI_Type *base, + uint32_t src_clk_hz, + uint32_t xfer_cs, + spi_master_config_t *user_config +) +{ + assert(NULL != base); + assert(NULL != user_config); + + mutex = xSemaphoreCreateMutex(); + assert(NULL != mutex); + event = xSemaphoreCreateBinary(); + assert(NULL != event); + + /* DSPI init */ + SPI_MasterInit(base, &g_spi_config, src_clk_hz); + + return A_OK; +} + +/* + * Transfer data in DMA mode + */ +static A_STATUS WIFIDRVS_SPI_DMA_Transfer(spi_transfer_t *transfer) +{ + assert(NULL != transfer); + + status_t result = SPI_MasterTransferDMA(g_spi_base, &g_m_dma_handle, transfer); + if (kStatus_Success != result) + { + assert(0); + return A_ERROR; + } + /* semaphore is released in callback fn */ + if (pdTRUE != xSemaphoreTake(event, portMAX_DELAY)) + { + assert(0); + return A_ERROR; + } + + SPI_EnableTxDMA(g_spi_base, false); + SPI_EnableRxDMA(g_spi_base, false); + + return A_OK; +} + +/* + * Transfer data in IRQ mode + */ +static A_STATUS WIFIDRVS_SPI_IRQ_Transfer(spi_transfer_t *transfer) +{ + assert(NULL != transfer); + + status_t result = SPI_MasterTransferNonBlocking(g_spi_base, &g_m_handle, transfer); + if (kStatus_Success != result) + { + assert(0); + return A_ERROR; + } + if (pdTRUE != xSemaphoreTake(event, portMAX_DELAY)) + { + assert(0); + result = A_ERROR; + } + return A_OK; +} + +/* + * Transfer data + */ +static A_STATUS WIFIDRVS_SPI_Transfer(spi_transfer_t *transfer) +{ + A_STATUS result = A_OK; + + /* NOTE: following code expects that SDK drivers do not + * modify members of 'transfer' argument */ + for (int32_t to_transfer = transfer->dataSize; to_transfer;) + { + if (to_transfer < g_irq_threshold) + { + /* DMA is unefficient for small amount of data, so use IRQ mode. + * IRQ mode can transfer unlimited number of data */ + transfer->dataSize = to_transfer; + transfer->configFlags |= kSPI_FrameAssert; + result = WIFIDRVS_SPI_IRQ_Transfer(transfer); + if (A_OK != result) + break; + to_transfer = 0; + } + else + { + /* DSPI over EDMA can transfer only limited number of bytes + * so we have to split transfer into chunks */ + //transfer->dataSize = to_transfer < g_dma_chunk ? to_transfer : g_dma_chunk; + // TODO: need to verify behaviour when transfer is splitted in default continuous mode + // TODO: allows CS for every word ? + if (to_transfer < g_dma_chunk) + { + transfer->dataSize = to_transfer; + transfer->configFlags |= kSPI_FrameAssert; + } + else + { + transfer->dataSize = g_dma_chunk; + } + result = WIFIDRVS_SPI_DMA_Transfer(transfer); + if (A_OK != result) + break; + to_transfer -= transfer->dataSize; + /* recalculate rx/rx offsets */ + if (NULL != transfer->txData) + { + transfer->txData += transfer->dataSize; + } + if (NULL != transfer->rxData) + { + transfer->rxData += transfer->dataSize; + } + } + } + + return result; +} + +/*! + * @brief Initialize SPI driver + */ +A_STATUS WIFIDRVS_SPI_Init(WIFIDRVS_SPI_config_t *config) +{ + /* No SPI base address, invalid config*/ + assert(!((NULL == config) || (NULL == config->spi.base))); + if ((NULL == config) || (NULL == config->spi.base)) return A_ERROR; + + /* IRQ mode only - set threshold to max value */ + if ((config->irq_mode.enabled) && (!config->dma_mode.enabled)) + { + g_irq_threshold = (uint32_t)-1; + } + /* DMA mode only - set threshold to 0 */ + else if ((!config->irq_mode.enabled) && (config->dma_mode.enabled)) + { + g_irq_threshold = 0; + } + /* DMA and IRQ mode - set user defined value */ + else if ((config->irq_mode.enabled) && (config->dma_mode.enabled)) + { + g_irq_threshold = config->spi.irq_threshold; + } + /* Neither of modes is enabled, return error */ + else + { + return A_ERROR; + } + + /* Prepare driver internal context */ + g_spi_base = config->spi.base; + g_xfer_cs = config->spi.xfer_cs; + g_spi_config = config->spi.config; + + /* Initialize SPI peripheral */ + WIFIDRVS_SPI_InitPeriph(config->spi.base, config->spi.clk_hz, config->spi.xfer_cs, &config->spi.config); + + /* Enable IRQ mode */ + if (config->irq_mode.enabled) + { + WIFIDRVS_SPI_InitIRQMode(config); + } + + /* Enable DMA mode */ + if (config->dma_mode.enabled) + { + WIFIDRVS_SPI_InitDMAMode(config); + } + + return A_OK; +} + +/*! + * @brief Deinitialize SPI driver + */ +A_STATUS WIFIDRVS_SPI_Deinit(WIFIDRVS_SPI_config_t *config) +{ + assert(!(NULL == config)); + if (NULL == config) return A_ERROR; + + if (NULL == config->spi.base) return A_ERROR; + SPI_Deinit(config->spi.base); + + return A_OK; +} + +/*! + * @brief Return default configuration + */ +A_STATUS WIFIDRVS_SPI_GetDefaultConfig(WIFIDRVS_SPI_config_t *config) +{ + assert(!(NULL == config)); + if (NULL == config) return A_ERROR; + + memset(config, 0, sizeof(*config)); + config->dma_mode.dma_rx_chnl = -1; + config->dma_mode.dma_tx_chnl = -1; + + return A_OK; +} + +/*! + * @brief Return default SPI peripheral settings + */ +A_STATUS WIFIDRVS_SPI_GetSPIConfig(spi_master_config_t *user_config, uint32_t baudrate, spi_ssel_t cs) +{ + assert(!(NULL == user_config)); + if (NULL == user_config) return A_ERROR; + + memset(user_config, 0, sizeof(*user_config)); + SPI_MasterGetDefaultConfig(user_config); + + user_config->polarity = kSPI_ClockPolarityActiveLow; + user_config->phase = kSPI_ClockPhaseSecondEdge; + user_config->direction = kSPI_MsbFirst; + user_config->baudRate_Bps = baudrate; + user_config->dataWidth = kSPI_Data8Bits; + user_config->sselNum = cs; + user_config->sselPol = kSPI_SpolActiveAllLow; + + return A_OK; +} + +/*! + * @brief WiFi SPI transfer SPI + */ +A_STATUS WIFIDRVS_SPI_InOutToken(uint32_t OutToken, uint8_t DataSize, uint32_t *pInToken) +{ + A_STATUS result; + spi_transfer_t transfer = {0}; + + transfer.txData = (uint8_t *)&OutToken; + transfer.rxData = (uint8_t *)pInToken; + transfer.dataSize = DataSize; + transfer.configFlags = g_xfer_cs; + + /* Protect transmit by mutex */ + if (pdTRUE != xSemaphoreTake(mutex, portMAX_DELAY)) + { + return A_ERROR; + } + result = WIFIDRVS_SPI_Transfer(&transfer); + xSemaphoreGive(mutex); + return result; +} + +/*! + * @brief WiFi SPI transfer SPI + */ +A_STATUS WIFIDRVS_SPI_InOutBuffer(uint8_t *pBuffer, uint16_t length, uint8_t doRead, boolean sync) +{ + A_STATUS result; + spi_transfer_t transfer = {0}; + + if (doRead) + { + transfer.txData = NULL; + transfer.rxData = pBuffer; + } + else + { + transfer.txData = pBuffer; + transfer.rxData = NULL; + } + transfer.dataSize = length; + transfer.configFlags = g_xfer_cs; + + /* Protect transmit by mutex */ + if (pdTRUE != xSemaphoreTake(mutex, portMAX_DELAY)) + { + return A_ERROR; + } + result = WIFIDRVS_SPI_Transfer(&transfer); + xSemaphoreGive(mutex); + return result; +} + diff --git a/third_party/qca-3.3.5/port/drivers/flexcomm_freertos/wifi_spi.h b/third_party/qca-3.3.5/port/drivers/flexcomm_freertos/wifi_spi.h new file mode 100644 index 00000000..5b2a2595 --- /dev/null +++ b/third_party/qca-3.3.5/port/drivers/flexcomm_freertos/wifi_spi.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2016, NXP Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of NXP Semiconductor, Inc. nor the names of its + * contributors may be used tom endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __WIFI_SPI_H__ +#define __WIFI_SPI_H__ + +#include +#include "fsl_spi.h" +#include "fsl_dma.h" + +/* can be extended in future */ +typedef struct { + struct { + uint32_t enabled; + DMA_Type *dma_base; + int32_t dma_rx_chnl; + dma_priority_t dma_rx_chnl_prio; + int32_t dma_tx_chnl; + dma_priority_t dma_tx_chnl_prio; + uint32_t dma_irq_prio; + } dma_mode; + struct { + uint32_t enabled; + uint32_t spi_irq_prio; + } irq_mode; + struct { + SPI_Type *base; + uint32_t clk_hz; + uint32_t xfer_cs; + uint32_t baudrate; + uint32_t irq_threshold; + spi_master_config_t config; + } spi; +} WIFIDRVS_SPI_config_t; + +/* prototypes */ +A_STATUS WIFIDRVS_SPI_Init(WIFIDRVS_SPI_config_t *config); +A_STATUS WIFIDRVS_SPI_Deinit(WIFIDRVS_SPI_config_t *config); +A_STATUS WIFIDRVS_SPI_InOutToken(uint32_t OutToken, uint8_t DataSize, uint32_t *pInToken); +A_STATUS WIFIDRVS_SPI_InOutBuffer(uint8_t *pBuffer, uint16_t length, uint8_t doRead, boolean sync); +A_STATUS WIFIDRVS_SPI_GetDefaultConfig(WIFIDRVS_SPI_config_t *config); +A_STATUS WIFIDRVS_SPI_GetSPIConfig(spi_master_config_t *user_config, uint32_t baudrate, spi_ssel_t cs); + +#endif

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