-
Notifications
You must be signed in to change notification settings - Fork 8
/
Copy pathMakefile
executable file
·132 lines (109 loc) · 4.49 KB
/
Makefile
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
.PHONY: build generate clean
.PHONY: lint sim build_sim test
GTKWAVE = e:/gtkwave-win32/gtkwave/bin/gtkwave
PYTHON3 = python3
NUM_JOBS = 8
NUM_EMU_THREADS = 8
SRC_DIR = rtl
TESTBENCH_DIR = testbench
PDK_RTL_DIR = pdk-lib/rtl
EM_DIR = em
SRCS = $(foreach x,$(SRC_DIR)/core, $(wildcard $(addprefix ${x}/*,.v) ) )
SRCS += $(foreach x,$(SRC_DIR)/lib, $(wildcard $(addprefix ${x}/*,.v) ) )
SRCS += $(foreach x,$(SRC_DIR)/general, $(wildcard $(addprefix ${x}/*,.v) ) )
SRCS += $(foreach x,$(SRC_DIR)/fabric, $(wildcard $(addprefix ${x}/*,.v) ) )
# SoC - YSYX
YSYX_SRCS += $(foreach x,$(SRC_DIR)/soc/ysyx, $(wildcard $(addprefix ${x}/*,.v) ) )
YSYX_TOPLEVEL = ysyx_210479
YSYX_PREFIX = ysyx_210479_
YSYX_TARGET = build/$(YSYX_TOPLEVEL).v
# Emulator
EM_CXXFLAGS =
EM_CXXFLAGS =
EM_LDFLAGS =
# DRAMsim3
DRAMSIM3_HOME = em/csrc/third-party/DRAMsim3
LIB_DRAMSIM3 = $(DRAMSIM3_HOME)/build/libdramsim3.a
EM_CXXFLAGS += -I../$(DRAMSIM3_HOME)/src
EM_CXXFLAGS += -DWITH_DRAMSIM3 -DDRAMSIM3_CONFIG=\\\"$(DRAMSIM3_HOME)/configs/XiangShan.ini\\\" -DDRAMSIM3_OUTDIR=\\\"$(BUILD_DIR)\\\"
EM_LDFLAGS += ../$(LIB_DRAMSIM3)
# PDK
PDK_SRCS += $(PDK_RTL_DIR)/S011HD1P_X32Y2D128.v \
$(PDK_RTL_DIR)/S011HD1P_X32Y2D128_BW.v
# Simulation (Difftest)
SIM_INCS = -I$(SRC_DIR)/core
SIM_DEFS =
SIM_FLAGS = $(SIM_DEFS) $(SIM_INCS) -Wno-UNUSED
#SIM_FLAGS += --threads $(NUM_EMU_THREADS) -threads-dpi none
CFLAGS = -Wall -Wno-attributes -g -I../em/csrc $(EM_CXXFLAGS)
LDFLAGS = -g $(EM_LDFLAGS)
SIM_FLAGS += +define+IN_VERILATOR_SIM=1+ --exe --trace --assert -LDFLAGS "$(LDFLAGS)" -CFLAGS "$(CFLAGS)" -j $(NUM_JOBS) -Mdir build/ -o emu
SIM_TOPLEVEL = simtop
SIM_SRCS = $(SRCS) $(YSYX_SRCS) $(PDK_SRCS)
SIM_SRCS += $(foreach x,$(EM_DIR)/vsrc, $(wildcard $(addprefix ${x}/*,.v) ) )
SIM_SRCS += $(TESTBENCH_DIR)/simtop.v
# CPU Model
SIM_CPPS = $(EM_DIR)/csrc/main.cc \
$(EM_DIR)/csrc/cpu.cc \
$(EM_DIR)/csrc/cache.cc \
$(EM_DIR)/csrc/memory.cc \
$(EM_DIR)/csrc/mmu.cc \
$(EM_DIR)/csrc/msr.cc \
$(EM_DIR)/csrc/tsc.cc \
$(EM_DIR)/csrc/irqc.cc \
$(EM_DIR)/csrc/pc-queue.cc \
$(EM_DIR)/csrc/ras.cc \
$(EM_DIR)/csrc/symtable.cc \
$(EM_DIR)/csrc/emu.cc \
$(EM_DIR)/csrc/dpi-c.cc
# Peripherals
SIM_CPPS += $(EM_DIR)/csrc/peripheral/device-tree.cc \
$(EM_DIR)/csrc/peripheral/pb-uart.cc \
$(EM_DIR)/csrc/peripheral/flash.cc \
$(EM_DIR)/csrc/peripheral/virt-uart.cc \
$(EM_DIR)/csrc/peripheral/axi4.cc \
$(EM_DIR)/csrc/peripheral/axi4-crossbar.cc
# Lint
LINT_DEFS = +define+SYNTHESIS=1
LINT_INCS = -I$(SRC_DIR)/core
LINT_FLAGS = $(LINT_DEFS) $(LINT_INCS) -Wno-DECLFILENAME
#LINT_SRCS = $(SRCS) $(YSYX_SRCS) $(PDK_SRCS)
LINT_SRCS = $(YSYX_TARGET) $(PDK_SRCS)
# YSYX Information
MYINFO_FILE = myinfo.txt
ID =$(shell sed '/^ID=/!d;s/.*=//' $(MYINFO_FILE))
NAME =$(shell sed '/^Name=/!d;s/.*=//' $(MYINFO_FILE))
build: $(YSYX_TARGET)
$(YSYX_TARGET): $(SRCS) $(YSYX_SRCS)
-@mkdir build
$(PYTHON3) scripts/build.py -d ./ -c $^ -I $(SRC_DIR)/core -t $(YSYX_TOPLEVEL) -p $(YSYX_PREFIX) -o $(YSYX_TARGET)
generate: rtl/general/pmux.v rtl/general/pmux_v.v rtl/general/priority_encoder_gs.v rtl/general/priority_encoder_rev_gs.v
rtl/general/pmux.v rtl/general/pmux_v.v: scripts/gen_pmux.py
$(PYTHON3) scripts/gen_pmux.py $@
rtl/general/priority_encoder_gs.v rtl/general/priority_encoder_rev_gs.v: scripts/gen_priority_encoder.py
$(PYTHON3) scripts/gen_priority_encoder.py $@
build_sim: $(LIB_DRAMSIM3)
verilator --cc -Wall --top-module $(SIM_TOPLEVEL) $(SIM_FLAGS) --build $(SIM_SRCS) $(SIM_CPPS)
# git add . -A --ignore-errors
# (echo $(NAME) && echo $(ID) && hostnamectl && date) | git commit -F - -q --author='tracer-oscpu2021 <[email protected]>' --no-verify --allow-empty 2>&1
sync
sim: build_sim
./build/emu --mode=simulate-only -b ./build/vmlinux.bin --dump-wave=./build/dump.vcd
$(GTKWAVE) ./build/dump.vcd
test: build_sim
./build/emu --mode=difftest -b ./build/coremark.bin --dump-wave=./build/dump.vcd
$(GTKWAVE) ./build/dump.vcd
lint: build/lint.csv
build/lint.csv: $(LINT_SRCS)
-verilator --lint-only -Wall --top-module $(YSYX_TOPLEVEL) $(LINT_FLAGS) $(LINT_SRCS) 2> build/lint.log
$(PYTHON3) scripts/parse_verilator_out.py build/lint.log $@
$(LIB_DRAMSIM3): $(dir $(LIB_DRAMSIM3)) $(dir $(LIB_DRAMSIM3))/Makefile
make -C $< -j$(NUM_JOBS) all
$(dir $(LIB_DRAMSIM3)):
mkdir $@
$(dir $(LIB_DRAMSIM3))/Makefile: $(dir $(LIB_DRAMSIM3))/../CMakeLists.txt
cd $(dir $(LIB_DRAMSIM3)) && cmake .. -DCOSIM=1
clean:
-rm ./build/*.o ./build/*.d ./build/*.cpp ./build/*.h ./build/*.v
-make -C $(dir $(LIB_DRAMSIM3)) clean
-rm $(dir $(LIB_DRAMSIM3))/Makefile