From f2a800231d2ae5a6dae34ec014e015e9f828e912 Mon Sep 17 00:00:00 2001 From: Frank Denis Date: Fri, 6 Dec 2024 23:20:59 +0100 Subject: [PATCH] code size -> size This property can also reduce memory requirements in software implementations, as well as the area size of hardware implementations, so maybe we shouldn't be too specific. --- draft-irtf-cfrg-aegis-aead.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/draft-irtf-cfrg-aegis-aead.md b/draft-irtf-cfrg-aegis-aead.md index 16a97d2..709d5ea 100644 --- a/draft-irtf-cfrg-aegis-aead.md +++ b/draft-irtf-cfrg-aegis-aead.md @@ -1549,7 +1549,7 @@ return tag ## Implementation Considerations -AEGIS-128X and AEGIS-256X with a degree of `1` are identical to AEGIS-128L and AEGIS-256. This property can be used to reduce the code size of a generic implementation. +AEGIS-128X and AEGIS-256X with a degree of `1` are identical to AEGIS-128L and AEGIS-256. This property can be used to reduce the size of a generic implementation. In AEGIS-128X, `V` can be represented as eight 256-bit registers (when `D = 2`) or eight 512-bit registers (when `D = 4`). In AEGIS-256X, `V` can be represented as six 256-bit registers (when `D = 2`) or six 512-bit registers (when `D = 4`). With this representation, loops over `0..D` in the above pseudocode can be replaced by vector instructions.