From b54c2c9c7759e5552a67c65b1cab6fe6cea1d3f3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ryszard=20R=C3=B3=C5=BCak?= <rrozak@antmicro.com>
Date: Wed, 5 Jan 2022 12:26:11 +0100
Subject: [PATCH] Add SelectInAlwaysInFor
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Signed-off-by: Ryszard Różak <rrozak@antmicro.com>
---
 tests/SelectInAlwaysInFor/Makefile.in  |  3 ++
 tests/SelectInAlwaysInFor/main.cpp     | 40 ++++++++++++++++++++++++++
 tests/SelectInAlwaysInFor/top.sv       | 15 ++++++++++
 tests/SelectInAlwaysInFor/top.vlt      |  3 ++
 tests/SelectInAlwaysInFor/yosys_script |  6 ++++
 5 files changed, 67 insertions(+)
 create mode 100644 tests/SelectInAlwaysInFor/Makefile.in
 create mode 100644 tests/SelectInAlwaysInFor/main.cpp
 create mode 100644 tests/SelectInAlwaysInFor/top.sv
 create mode 100644 tests/SelectInAlwaysInFor/top.vlt
 create mode 100644 tests/SelectInAlwaysInFor/yosys_script

diff --git a/tests/SelectInAlwaysInFor/Makefile.in b/tests/SelectInAlwaysInFor/Makefile.in
new file mode 100644
index 00000000..4dbfec67
--- /dev/null
+++ b/tests/SelectInAlwaysInFor/Makefile.in
@@ -0,0 +1,3 @@
+TOP_FILE := $(TEST_DIR)/top.sv
+TOP_MODULE := top
+VERILATOR_FLAGS := $(TEST_DIR)/top.vlt
diff --git a/tests/SelectInAlwaysInFor/main.cpp b/tests/SelectInAlwaysInFor/main.cpp
new file mode 100644
index 00000000..8e0c45f7
--- /dev/null
+++ b/tests/SelectInAlwaysInFor/main.cpp
@@ -0,0 +1,40 @@
+#include <iostream>
+#include <verilated_vcd_c.h>
+
+#define VL_DEBUG
+#include "Vtop.h"
+#include "verilated.h"
+
+static vluint64_t main_time = 0;
+
+double
+sc_time_stamp()
+{
+  return main_time;
+}
+
+int main (int argc, char **argv) {
+  Verilated::commandArgs(argc, argv);
+  Vtop *top = new Vtop();
+
+  Verilated::traceEverOn(true);
+  VerilatedVcdC* tfp = new VerilatedVcdC;
+  top->trace(tfp, 99);
+  tfp->open("dump.vcd");
+
+  while (!Verilated::gotFinish() && (main_time < 100)) {
+    top->eval();
+    tfp->dump(main_time);
+
+    main_time += 1;
+
+    std::cout << "time: " << main_time
+              << " o: " << (int)top->o
+              << std::endl;
+  }
+  top->final();
+  tfp->close();
+  delete top;
+
+  return 0;
+}
diff --git a/tests/SelectInAlwaysInFor/top.sv b/tests/SelectInAlwaysInFor/top.sv
new file mode 100644
index 00000000..cef2d523
--- /dev/null
+++ b/tests/SelectInAlwaysInFor/top.sv
@@ -0,0 +1,15 @@
+module top(output logic [31:0] o);
+   logic [1:0][31:0] data_state;
+
+   assign data_state[0] = 32'hABCD;
+
+   for (genvar r = 0; r < 1; r++) begin : gen_round
+      logic [31:0] data_state_sbox;
+      always_comb begin : p_enc
+         data_state_sbox = data_state[r];
+         data_state[r + 1] = data_state_sbox;
+      end
+   end // gen_round
+
+   assign o = data_state[1];
+endmodule
diff --git a/tests/SelectInAlwaysInFor/top.vlt b/tests/SelectInAlwaysInFor/top.vlt
new file mode 100644
index 00000000..7e793fe4
--- /dev/null
+++ b/tests/SelectInAlwaysInFor/top.vlt
@@ -0,0 +1,3 @@
+`verilator_config
+
+split_var -module "top" -var "data_state"
diff --git a/tests/SelectInAlwaysInFor/yosys_script b/tests/SelectInAlwaysInFor/yosys_script
new file mode 100644
index 00000000..ea782476
--- /dev/null
+++ b/tests/SelectInAlwaysInFor/yosys_script
@@ -0,0 +1,6 @@
+plugin -i uhdm
+read_uhdm -debug top.uhdm
+prep -top \top
+write_verilog
+write_verilog yosys.sv
+sim -rstlen 10 -vcd dump.vcd