[abi] Add rules / hints / conventions for how names are lowered to SystemVerilog

[mmaloney-sf]

It seems like the ABI would be the right place for placing rules on how names for wires, registers, modules, etc are lowered to SystemVerilog.

There was a suggestion as well that we might consider mediating between the Scala/Chisel/FIRRTL convention of snakeCase and the Verilog convention of camel_case.

[jackkoenig]

It seems like the ABI would be the right place for placing rules on how names for wires, registers, modules, etc are lowered to SystemVerilog.

It is defined in the ABI. It could probably use some examples but that does describe the lowering.

It is important that this lowering only applies to public elements. By definition, the ABI defines things that users can rely upon and we do not want people relying on behavior for non-public wires, registers, etc.

There was a suggestion as well that we might consider mediating between the Scala/Chisel/FIRRTL convention of snakeCase and the Verilog convention of camel_case.

I'm sympathetic to optional naming customization to deal with internal lint rules (eg. some users of Chisel have had strict internal rules that disallow names starting with _), but it should be an option to the compiler and not default behavior.