Replies: 6 comments
-
The field you changed is only used to describe the frequency to the SoC. Actual clock generation does not happen in Chisel at all. At SiFive we generally get our clocks from an external oscillator. For simulation, the test-bench provides the clock. If you are using 'emulator/' then the clock comes from csrc/emulator.cc. |
Beta Was this translation helpful? Give feedback.
-
Thanks for your reply. I am not familiar with such modification. |
Beta Was this translation helpful? Give feedback.
-
Just FYI, no one has done what you are trying to do and it's highly unlikely we would merge changes to this effect back into emulator.cc. That said, your best bet is probably to move the tiles into their own clock domain and plumb signals out of the design for them. Shoving the Periphery is something I know @hcook is working to make easier, but AFAIK this work is not completed. |
Beta Was this translation helpful? Give feedback.
-
#1190 adds support for specifying a clock crossing between the system bus and periphery bus, but doesn't actually create a different clock wired to the outside. You could do that manually. The hard part is that then all the slave devices attached to the periphery bus had better be put on its same clock... I think we'll have better support for this in a month or two. |
Beta Was this translation helpful? Give feedback.
-
so am i correct on this that periphery bus means bus supporting only TL-UL type of transactions and not an under-clocked bus for slower peripherals? |
Beta Was this translation helpful? Give feedback.
-
I am aslo confused that how can I generate a clock crossing SOC. In this Soc, system bus running on a fast clock, and periphery bus running on a slow clock. |
Beta Was this translation helpful? Give feedback.
-
Hi,
I have added a simple periphery module on periphery bus and executed c simulation.
I intend to make clock frequency of periphery bus distinguish from system bus.
I try and modify below frequency value to 5000000 for achieving my goal.
https://github.com/freechipsproject/rocket-chip/blob/a48dd575b23aa4b82368f19beaaf19e2d4bf1e3e/src/main/scala/coreplex/PeripheryBus.scala#L18
I have checked the simulation wave form diagram after such modification.
However, periphery bus clock frequency remains same as system bus.
I think that I use wrong approach to achieve my goal.
Can anyone tells me how to set it or the method?
Beta Was this translation helpful? Give feedback.
All reactions